1 /*-
2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <dev/sound/pcm/sound.h>
28 #include <dev/sound/pcm/ac97.h>
29 #include <dev/sound/pci/aureal.h>
30
31 #include <dev/pci/pcireg.h>
32 #include <dev/pci/pcivar.h>
33
34 SND_DECLARE_FILE("$FreeBSD$");
35
36 /* PCI IDs of supported chips */
37 #define AU8820_PCI_ID 0x000112eb
38
39 /* channel interface */
40 static u_int32_t au_playfmt[] = {
41 AFMT_U8,
42 AFMT_STEREO | AFMT_U8,
43 AFMT_S16_LE,
44 AFMT_STEREO | AFMT_S16_LE,
45 0
46 };
47 static struct pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0};
48
49 static u_int32_t au_recfmt[] = {
50 AFMT_U8,
51 AFMT_STEREO | AFMT_U8,
52 AFMT_S16_LE,
53 AFMT_STEREO | AFMT_S16_LE,
54 0
55 };
56 static struct pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0};
57
58 /* -------------------------------------------------------------------- */
59
60 struct au_info;
61
62 struct au_chinfo {
63 struct au_info *parent;
64 struct pcm_channel *channel;
65 struct snd_dbuf *buffer;
66 int dir;
67 };
68
69 struct au_info {
70 int unit;
71
72 bus_space_tag_t st[3];
73 bus_space_handle_t sh[3];
74
75 bus_dma_tag_t parent_dmat;
76 struct mtx *lock;
77
78 u_int32_t x[32], y[128];
79 char z[128];
80 u_int32_t routes[4], interrupts;
81 struct au_chinfo pch;
82 };
83
84 static int au_init(device_t dev, struct au_info *au);
85 static void au_intr(void *);
86
87 /* -------------------------------------------------------------------- */
88
89 static u_int32_t
90 au_rd(struct au_info *au, int mapno, int regno, int size)
91 {
92 switch(size) {
93 case 1:
94 return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
95 case 2:
96 return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
97 case 4:
98 return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
99 default:
100 return 0xffffffff;
101 }
102 }
103
104 static void
105 au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
106 {
107 switch(size) {
108 case 1:
109 bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
110 break;
111 case 2:
112 bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
113 break;
114 case 4:
115 bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
116 break;
117 }
118 }
119
120 /* -------------------------------------------------------------------- */
121
122 static int
123 au_rdcd(kobj_t obj, void *arg, int regno)
124 {
125 struct au_info *au = (struct au_info *)arg;
126 int i=0, j=0;
127
128 regno<<=16;
129 au_wr(au, 0, AU_REG_CODECIO, regno, 4);
130 while (j<50) {
131 i=au_rd(au, 0, AU_REG_CODECIO, 4);
132 if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
133 DELAY(j * 200 + 2000);
134 j++;
135 }
136 if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
137 au->unit, (regno & AU_CDC_REGMASK)>>16, i);
138 return i & AU_CDC_DATAMASK;
139 }
140
141 static int
142 au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data)
143 {
144 struct au_info *au = (struct au_info *)arg;
145 int i, j, tries;
146 i=j=tries=0;
147 do {
148 while (j<50 && (i & AU_CDC_WROK) == 0) {
149 i=au_rd(au, 0, AU_REG_CODECST, 4);
150 DELAY(2000);
151 j++;
152 }
153 if (j==50) printf("codec timeout during write of register %x, data %x\n",
154 regno, data);
155 au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
156 /* DELAY(20000);
157 i=au_rdcd(au, regno);
158 */ tries++;
159 } while (0); /* (i != data && tries < 3); */
160 /*
161 if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
162 */
163
164 return 0;
165 }
166
167 static kobj_method_t au_ac97_methods[] = {
168 KOBJMETHOD(ac97_read, au_rdcd),
169 KOBJMETHOD(ac97_write, au_wrcd),
170 { 0, 0 }
171 };
172 AC97_DECLARE(au_ac97);
173
174 /* -------------------------------------------------------------------- */
175
176 static void
177 au_setbit(u_int32_t *p, char bit, u_int32_t value)
178 {
179 p += bit >> 5;
180 bit &= 0x1f;
181 *p &= ~ (1 << bit);
182 *p |= (value << bit);
183 }
184
185 static void
186 au_addroute(struct au_info *au, int a, int b, int route)
187 {
188 int j = 0x1099c+(a<<2);
189 if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
190
191 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
192 au_wr(au, 0, j, route | (b<<7), 4);
193 au->y[route]=au->x[a];
194 au->x[a]=route;
195 au->z[route]=a & 0x000000ff;
196 au_setbit(au->routes, route, 1);
197 }
198
199 static void
200 au_delroute(struct au_info *au, int route)
201 {
202 int i;
203 int j=au->z[route];
204
205 au_setbit(au->routes, route, 0);
206 au->z[route]=0x1f;
207 i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
208 au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
209 au->y[i & 0x7f]=au->y[route];
210 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
211 if (au->x[j] == route) au->x[j]=au->y[route];
212 au->y[route]=0x7f;
213 }
214
215 static void
216 au_encodec(struct au_info *au, char channel)
217 {
218 au_wr(au, 0, AU_REG_CODECEN,
219 au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
220 }
221
222 static void
223 au_clrfifo(struct au_info *au, u_int32_t c)
224 {
225 u_int32_t i;
226
227 for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
228 }
229
230 static void
231 au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
232 {
233 int x;
234
235 x = au_rd(au, 0, AU_REG_ADB, 4);
236 x &= ~(1 << c);
237 x |= (enable << c);
238 au_wr(au, 0, AU_REG_ADB, x, 4);
239 }
240
241 static void
242 au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
243 {
244 struct au_info *au = ch->parent;
245 int i, stereo = (format & AFMT_STEREO)? 1 : 0;
246 u_int32_t baseaddr = sndbuf_getbufaddr(ch->buffer);
247
248 au_wr(au, 0, 0x1061c, 0, 4);
249 au_wr(au, 0, 0x10620, 0, 4);
250 au_wr(au, 0, 0x10624, 0, 4);
251 switch(format & ~AFMT_STEREO) {
252 case 1:
253 i=0xb000;
254 break;
255 case 2:
256 i=0xf000;
257 break;
258 case 8:
259 i=0x7000;
260 break;
261 case 16:
262 i=0x23000;
263 break;
264 default:
265 i=0x3000;
266 }
267 au_wr(au, 0, 0x10200, baseaddr, 4);
268 au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
269 au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
270 au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
271
272 au_wr(au, 0, 0x10400, 0xdeffffff, 4);
273 au_wr(au, 0, 0x10404, 0xfcffffff, 4);
274
275 au_wr(au, 0, 0x10580, i, 4);
276
277 au_wr(au, 0, 0x10210, baseaddr, 4);
278 au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
279 au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
280 au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
281
282 au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
283 au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
284
285 au_wr(au, 0, 0x10584, i, 4);
286
287 au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
288 au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
289
290 au_addroute(au, 0x11, 0, 0x58);
291 au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
292 }
293
294 /* -------------------------------------------------------------------- */
295 /* channel interface */
296 static void *
297 auchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
298 {
299 struct au_info *au = devinfo;
300 struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
301
302 ch->parent = au;
303 ch->channel = c;
304 ch->buffer = b;
305 ch->dir = dir;
306 if (sndbuf_alloc(ch->buffer, au->parent_dmat, AU_BUFFSIZE) != 0)
307 return NULL;
308 return ch;
309 }
310
311 static int
312 auchan_setformat(kobj_t obj, void *data, u_int32_t format)
313 {
314 struct au_chinfo *ch = data;
315
316 if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
317 return 0;
318 }
319
320 static int
321 auchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
322 {
323 struct au_chinfo *ch = data;
324 if (ch->dir == PCMDIR_PLAY) {
325 } else {
326 }
327 return speed;
328 }
329
330 static int
331 auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
332 {
333 return blocksize;
334 }
335
336 static int
337 auchan_trigger(kobj_t obj, void *data, int go)
338 {
339 struct au_chinfo *ch = data;
340 struct au_info *au = ch->parent;
341
342 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
343 return 0;
344
345 if (ch->dir == PCMDIR_PLAY) {
346 au_setadb(au, 0x11, (go)? 1 : 0);
347 if (!go) {
348 au_wr(au, 0, 0xf800, 0, 4);
349 au_wr(au, 0, 0xf804, 0, 4);
350 au_delroute(au, 0x58);
351 au_delroute(au, 0x59);
352 }
353 } else {
354 }
355 return 0;
356 }
357
358 static int
359 auchan_getptr(kobj_t obj, void *data)
360 {
361 struct au_chinfo *ch = data;
362 struct au_info *au = ch->parent;
363 if (ch->dir == PCMDIR_PLAY) {
364 return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
365 } else {
366 return 0;
367 }
368 }
369
370 static struct pcmchan_caps *
371 auchan_getcaps(kobj_t obj, void *data)
372 {
373 struct au_chinfo *ch = data;
374 return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
375 }
376
377 static kobj_method_t auchan_methods[] = {
378 KOBJMETHOD(channel_init, auchan_init),
379 KOBJMETHOD(channel_setformat, auchan_setformat),
380 KOBJMETHOD(channel_setspeed, auchan_setspeed),
381 KOBJMETHOD(channel_setblocksize, auchan_setblocksize),
382 KOBJMETHOD(channel_trigger, auchan_trigger),
383 KOBJMETHOD(channel_getptr, auchan_getptr),
384 KOBJMETHOD(channel_getcaps, auchan_getcaps),
385 { 0, 0 }
386 };
387 CHANNEL_DECLARE(auchan);
388
389 /* -------------------------------------------------------------------- */
390 /* The interrupt handler */
391 static void
392 au_intr (void *p)
393 {
394 struct au_info *au = p;
395 u_int32_t intsrc, i;
396
397 au->interrupts++;
398 intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
399 printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
400 if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
401 if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
402 if (intsrc & AU_IRQ_UNKNOWN) {
403 (void)au_rd(au, 0, AU_REG_UNK1, 4);
404 au_wr(au, 0, AU_REG_UNK1, 0, 4);
405 au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
406 }
407 if (intsrc & AU_IRQ_PCMOUT) {
408 i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
409 chn_intr(au->pch.channel);
410 (void)au_rd(au, 0, AU_REG_UNK3, 4);
411 (void)au_rd(au, 0, AU_REG_UNK4, 4);
412 (void)au_rd(au, 0, AU_REG_UNK5, 4);
413 }
414 /* don't support midi
415 if (intsrc & AU_IRQ_MIDI) {
416 i=au_rd(au, 0, 0x11004, 4);
417 j=10;
418 while (i & 0xff) {
419 if (j-- <= 0) break;
420 i=au_rd(au, 0, 0x11000, 4);
421 if ((au->midi_stat & 1) && (au->midi_out))
422 au->midi_out(au->midi_devno, i);
423 i=au_rd(au, 0, 0x11004);
424 }
425 }
426 */
427 au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
428 au_rd(au, 0, AU_REG_IRQSRC, 4);
429 }
430
431
432 /* -------------------------------------------------------------------- */
433
434 /* Probe and attach the card */
435
436 static int
437 au_init(device_t dev, struct au_info *au)
438 {
439 u_int32_t i, j;
440
441 au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
442 DELAY(100000);
443
444 /* init codec */
445 /* cold reset */
446 for (i=0; i<32; i++) {
447 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
448 DELAY(10000);
449 }
450 if (1) {
451 au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
452 DELAY(10000);
453 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
454 DELAY(10000);
455 } else {
456 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
457 DELAY(100000);
458 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
459 DELAY(100000);
460 au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
461 DELAY(100000);
462 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
463 DELAY(100000);
464 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
465 DELAY(100000);
466 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
467 DELAY(100000);
468 }
469
470 /* init */
471 for (i=0; i<32; i++) {
472 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
473 DELAY(10000);
474 }
475 au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
476 DELAY(10000);
477 au_wr(au, 0, AU_REG_CODECEN, 0, 4);
478
479 /* setup codec */
480 i=j=0;
481 while (j<100 && (i & AU_CDC_READY)==0) {
482 i=au_rd(au, 0, AU_REG_CODECST, 4);
483 DELAY(1000);
484 j++;
485 }
486 if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
487
488 /* init adb */
489 /*au->x5c=0;*/
490 for (i=0; i<32; i++) au->x[i]=i+0x67;
491 for (i=0; i<128; i++) au->y[i]=0x7f;
492 for (i=0; i<128; i++) au->z[i]=0x1f;
493 au_wr(au, 0, AU_REG_ADB, 0, 4);
494 for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
495
496 /* test */
497 i=au_rd(au, 0, 0x107c0, 4);
498 if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
499
500 /* install mixer */
501 au_wr(au, 0, AU_REG_IRQGLOB,
502 au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
503 /* braindead but it's what the oss/linux driver does
504 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
505 */
506 au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
507 /*au->x1e4=0;*/
508
509 /* attach channel */
510 au_addroute(au, 0x11, 0x48, 0x02);
511 au_addroute(au, 0x11, 0x49, 0x03);
512 au_encodec(au, 0);
513 au_encodec(au, 1);
514
515 for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
516 for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
517 au_wr(au, 0, 0xf8c0, 0x0843, 4);
518 for (i=0; i<4; i++) au_clrfifo(au, i);
519
520 return (0);
521 }
522
523 static int
524 au_testirq(struct au_info *au)
525 {
526 au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
527 au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
528 au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
529 DELAY(1000000);
530 if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
531 /* this apparently generates an irq */
532 return 0;
533 }
534
535 static int
536 au_pci_probe(device_t dev)
537 {
538 if (pci_get_devid(dev) == AU8820_PCI_ID) {
539 device_set_desc(dev, "Aureal Vortex 8820");
540 return 0;
541 }
542
543 return ENXIO;
544 }
545
546 static int
547 au_pci_attach(device_t dev)
548 {
549 u_int32_t data;
550 struct au_info *au;
551 int type[10];
552 int regid[10];
553 struct resource *reg[10];
554 int i, j, mapped = 0;
555 int irqid;
556 struct resource *irq = 0;
557 void *ih = 0;
558 struct ac97_info *codec;
559 char status[SND_STATUSLEN];
560
561 if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
562 device_printf(dev, "cannot allocate softc\n");
563 return ENXIO;
564 }
565
566 au->unit = device_get_unit(dev);
567
568 data = pci_read_config(dev, PCIR_COMMAND, 2);
569 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
570 pci_write_config(dev, PCIR_COMMAND, data, 2);
571 data = pci_read_config(dev, PCIR_COMMAND, 2);
572
573 j=0;
574 /* XXX dfr: is this strictly necessary? */
575 for (i=0; i<PCI_MAXMAPS_0; i++) {
576 #if 0
577 /* Slapped wrist: config_id and map are private structures */
578 if (bootverbose) {
579 printf("pcm%d: map %d - allocating ", unit, i+1);
580 printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
581 printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
582 "io" : "memory");
583 printf("at 0x%x...", config_id->map[i].base);
584 }
585 #endif
586 regid[j] = PCIR_BAR(i);
587 type[j] = SYS_RES_MEMORY;
588 reg[j] = bus_alloc_resource_any(dev, type[j], ®id[j],
589 RF_ACTIVE);
590 if (!reg[j]) {
591 type[j] = SYS_RES_IOPORT;
592 reg[j] = bus_alloc_resource_any(dev, type[j],
593 ®id[j], RF_ACTIVE);
594 }
595 if (reg[j]) {
596 au->st[i] = rman_get_bustag(reg[j]);
597 au->sh[i] = rman_get_bushandle(reg[j]);
598 mapped++;
599 }
600 #if 0
601 if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
602 #endif
603 if (mapped) j++;
604 if (j == 10) {
605 /* XXX */
606 device_printf(dev, "too many resources");
607 goto bad;
608 }
609 }
610
611 #if 0
612 if (j < config_id->nummaps) {
613 printf("pcm%d: unable to map a required resource\n", unit);
614 free(au, M_DEVBUF);
615 return;
616 }
617 #endif
618
619 au_wr(au, 0, AU_REG_IRQEN, 0, 4);
620
621 irqid = 0;
622 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
623 RF_ACTIVE | RF_SHAREABLE);
624 if (!irq || snd_setup_intr(dev, irq, 0, au_intr, au, &ih)) {
625 device_printf(dev, "unable to map interrupt\n");
626 goto bad;
627 }
628
629 if (au_testirq(au)) device_printf(dev, "irq test failed\n");
630
631 if (au_init(dev, au) == -1) {
632 device_printf(dev, "unable to initialize the card\n");
633 goto bad;
634 }
635
636 codec = AC97_CREATE(dev, au, au_ac97);
637 if (codec == NULL) goto bad;
638 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
639
640 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
641 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
642 /*highaddr*/BUS_SPACE_MAXADDR,
643 /*filter*/NULL, /*filterarg*/NULL,
644 /*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
645 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
646 /*lockarg*/&Giant, &au->parent_dmat) != 0) {
647 device_printf(dev, "unable to create dma tag\n");
648 goto bad;
649 }
650
651 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
652 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
653 rman_get_start(reg[0]), rman_get_start(irq),PCM_KLDSTRING(snd_aureal));
654
655 if (pcm_register(dev, au, 1, 1)) goto bad;
656 /* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
657 pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au);
658 pcm_setstatus(dev, status);
659
660 return 0;
661
662 bad:
663 if (au) free(au, M_DEVBUF);
664 for (i = 0; i < j; i++)
665 bus_release_resource(dev, type[i], regid[i], reg[i]);
666 if (ih) bus_teardown_intr(dev, irq, ih);
667 if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
668 return ENXIO;
669 }
670
671 static device_method_t au_methods[] = {
672 /* Device interface */
673 DEVMETHOD(device_probe, au_pci_probe),
674 DEVMETHOD(device_attach, au_pci_attach),
675
676 { 0, 0 }
677 };
678
679 static driver_t au_driver = {
680 "pcm",
681 au_methods,
682 PCM_SOFTC_SIZE,
683 };
684
685 DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0);
686 MODULE_DEPEND(snd_aureal, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
687 MODULE_VERSION(snd_aureal, 1);
Cache object: 84e131e23c69b3d05c4e3523d46d5cc6
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