Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/cmi.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This driver exists largely as a result of other people's efforts. 31 * Much of register handling is based on NetBSD CMI8x38 audio driver 32 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 33 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 34 * registers and the 8738 mixer devices. His Linux driver was also a 35 * useful reference point. 36 * 37 * TODO: MIDI 38 * 39 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 40 * 41 * This card/code does not always manage to sample at 44100 - actual 42 * rate drifts slightly between recordings (usually 0-3%). No 43 * differences visible in register dumps between times that work and 44 * those that don't. 45 */ 46 47 #ifdef HAVE_KERNEL_OPTION_HEADERS 48 #include "opt_snd.h" 49 #endif 50 51 #include <dev/sound/pcm/sound.h> 52 #include <dev/sound/pci/cmireg.h> 53 #include <dev/sound/isa/sb.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 58 #include <sys/sysctl.h> 59 #include <dev/sound/midi/mpu401.h> 60 61 #include "mixer_if.h" 62 #include "mpufoi_if.h" 63 64 SND_DECLARE_FILE("$FreeBSD$"); 65 66 /* Supported chip ID's */ 67 #define CMI8338A_PCI_ID 0x010013f6 68 #define CMI8338B_PCI_ID 0x010113f6 69 #define CMI8738_PCI_ID 0x011113f6 70 #define CMI8738B_PCI_ID 0x011213f6 71 #define CMI120_USB_ID 0x01030d8c 72 73 /* Buffer size max is 64k for permitted DMA boundaries */ 74 #define CMI_DEFAULT_BUFSZ 16384 75 76 /* Interrupts per length of buffer */ 77 #define CMI_INTR_PER_BUFFER 2 78 79 /* Clarify meaning of named defines in cmireg.h */ 80 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 81 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 82 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 83 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 84 85 /* Our indication of custom mixer control */ 86 #define CMPCI_NON_SB16_CONTROL 0xff 87 88 /* Debugging macro's */ 89 #undef DEB 90 #ifndef DEB 91 #define DEB(x) /* x */ 92 #endif /* DEB */ 93 94 #ifndef DEBMIX 95 #define DEBMIX(x) /* x */ 96 #endif /* DEBMIX */ 97 98 /* ------------------------------------------------------------------------- */ 99 /* Structures */ 100 101 struct sc_info; 102 103 struct sc_chinfo { 104 struct sc_info *parent; 105 struct pcm_channel *channel; 106 struct snd_dbuf *buffer; 107 u_int32_t fmt, spd, phys_buf, bps; 108 u_int32_t dma_active:1, dma_was_active:1; 109 int dir; 110 }; 111 112 struct sc_info { 113 device_t dev; 114 115 bus_space_tag_t st; 116 bus_space_handle_t sh; 117 bus_dma_tag_t parent_dmat; 118 struct resource *reg, *irq; 119 int regid, irqid; 120 void *ih; 121 struct mtx *lock; 122 123 int spdif_enabled; 124 unsigned int bufsz; 125 struct sc_chinfo pch, rch; 126 127 struct mpu401 *mpu; 128 mpu401_intr_t *mpu_intr; 129 struct resource *mpu_reg; 130 int mpu_regid; 131 bus_space_tag_t mpu_bt; 132 bus_space_handle_t mpu_bh; 133 }; 134 135 /* Channel caps */ 136 137 static u_int32_t cmi_fmt[] = { 138 SND_FORMAT(AFMT_U8, 1, 0), 139 SND_FORMAT(AFMT_U8, 2, 0), 140 SND_FORMAT(AFMT_S16_LE, 1, 0), 141 SND_FORMAT(AFMT_S16_LE, 2, 0), 142 0 143 }; 144 145 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 146 147 /* ------------------------------------------------------------------------- */ 148 /* Register Utilities */ 149 150 static u_int32_t 151 cmi_rd(struct sc_info *sc, int regno, int size) 152 { 153 switch (size) { 154 case 1: 155 return bus_space_read_1(sc->st, sc->sh, regno); 156 case 2: 157 return bus_space_read_2(sc->st, sc->sh, regno); 158 case 4: 159 return bus_space_read_4(sc->st, sc->sh, regno); 160 default: 161 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 162 return 0xFFFFFFFF; 163 } 164 } 165 166 static void 167 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 168 { 169 switch (size) { 170 case 1: 171 bus_space_write_1(sc->st, sc->sh, regno, data); 172 break; 173 case 2: 174 bus_space_write_2(sc->st, sc->sh, regno, data); 175 break; 176 case 4: 177 bus_space_write_4(sc->st, sc->sh, regno, data); 178 break; 179 } 180 } 181 182 static void 183 cmi_partial_wr4(struct sc_info *sc, 184 int reg, int shift, u_int32_t mask, u_int32_t val) 185 { 186 u_int32_t r; 187 188 r = cmi_rd(sc, reg, 4); 189 r &= ~(mask << shift); 190 r |= val << shift; 191 cmi_wr(sc, reg, r, 4); 192 } 193 194 static void 195 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 196 { 197 u_int32_t r; 198 199 r = cmi_rd(sc, reg, 4); 200 r &= ~mask; 201 cmi_wr(sc, reg, r, 4); 202 } 203 204 static void 205 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 206 { 207 u_int32_t r; 208 209 r = cmi_rd(sc, reg, 4); 210 r |= mask; 211 cmi_wr(sc, reg, r, 4); 212 } 213 214 /* ------------------------------------------------------------------------- */ 215 /* Rate Mapping */ 216 217 static int cmi_rates[] = {5512, 8000, 11025, 16000, 218 22050, 32000, 44100, 48000}; 219 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 220 221 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 222 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 223 224 static u_int32_t 225 cmpci_rate_to_regvalue(int rate) 226 { 227 int i, r; 228 229 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 230 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 231 break; 232 } 233 } 234 235 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 236 237 r = ((i >> 1) | (i << 2)) & 0x07; 238 return r; 239 } 240 241 static int 242 cmpci_regvalue_to_rate(u_int32_t r) 243 { 244 int i; 245 246 i = ((r << 1) | (r >> 2)) & 0x07; 247 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 248 return cmi_rates[i]; 249 } 250 251 /* ------------------------------------------------------------------------- */ 252 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 253 * playback or capture. We use ch0 for playback and ch1 for capture. */ 254 255 static void 256 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 257 { 258 u_int32_t s, i, sz; 259 260 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 261 262 cmi_wr(sc, base, ch->phys_buf, 4); 263 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 264 265 s = sz / ch->bps - 1; 266 cmi_wr(sc, base + 4, s, 2); 267 268 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 269 cmi_wr(sc, base + 6, i, 2); 270 } 271 272 static void 273 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 274 { 275 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 276 277 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 278 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 279 CMPCI_REG_CH0_INTR_ENABLE); 280 281 ch->dma_active = 1; 282 } 283 284 static u_int32_t 285 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 286 { 287 u_int32_t r = ch->dma_active; 288 289 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 290 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 291 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 292 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 293 ch->dma_active = 0; 294 return r; 295 } 296 297 static void 298 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 299 { 300 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 301 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 302 /* Enable Interrupts */ 303 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 304 CMPCI_REG_CH1_INTR_ENABLE); 305 DEB(printf("cmi_ch1_start: dma prog\n")); 306 ch->dma_active = 1; 307 } 308 309 static u_int32_t 310 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 311 { 312 u_int32_t r = ch->dma_active; 313 314 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 315 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 316 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 317 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 318 ch->dma_active = 0; 319 return r; 320 } 321 322 static void 323 cmi_spdif_speed(struct sc_info *sc, int speed) { 324 u_int32_t fcr1, lcr, mcr; 325 326 if (speed >= 44100) { 327 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 328 lcr = CMPCI_REG_XSPDIF_ENABLE; 329 mcr = (speed == 48000) ? 330 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 331 } else { 332 fcr1 = mcr = lcr = 0; 333 } 334 335 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 336 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 337 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 338 CMPCI_REG_SPDIF0_ENABLE, fcr1); 339 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 340 CMPCI_REG_XSPDIF_ENABLE, lcr); 341 } 342 343 /* ------------------------------------------------------------------------- */ 344 /* Channel Interface implementation */ 345 346 static void * 347 cmichan_init(kobj_t obj, void *devinfo, 348 struct snd_dbuf *b, struct pcm_channel *c, int dir) 349 { 350 struct sc_info *sc = devinfo; 351 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 352 353 ch->parent = sc; 354 ch->channel = c; 355 ch->bps = 1; 356 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 357 ch->spd = DSP_DEFAULT_SPEED; 358 ch->buffer = b; 359 ch->dma_active = 0; 360 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 361 DEB(printf("cmichan_init failed\n")); 362 return NULL; 363 } 364 365 ch->dir = dir; 366 snd_mtxlock(sc->lock); 367 if (ch->dir == PCMDIR_PLAY) { 368 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 369 } else { 370 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 371 } 372 snd_mtxunlock(sc->lock); 373 374 return ch; 375 } 376 377 static int 378 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 379 { 380 struct sc_chinfo *ch = data; 381 struct sc_info *sc = ch->parent; 382 u_int32_t f; 383 384 if (format & AFMT_S16_LE) { 385 f = CMPCI_REG_FORMAT_16BIT; 386 ch->bps = 2; 387 } else { 388 f = CMPCI_REG_FORMAT_8BIT; 389 ch->bps = 1; 390 } 391 392 if (AFMT_CHANNEL(format) > 1) { 393 f |= CMPCI_REG_FORMAT_STEREO; 394 ch->bps *= 2; 395 } else { 396 f |= CMPCI_REG_FORMAT_MONO; 397 } 398 399 snd_mtxlock(sc->lock); 400 if (ch->dir == PCMDIR_PLAY) { 401 cmi_partial_wr4(ch->parent, 402 CMPCI_REG_CHANNEL_FORMAT, 403 CMPCI_REG_CH0_FORMAT_SHIFT, 404 CMPCI_REG_CH0_FORMAT_MASK, 405 f); 406 } else { 407 cmi_partial_wr4(ch->parent, 408 CMPCI_REG_CHANNEL_FORMAT, 409 CMPCI_REG_CH1_FORMAT_SHIFT, 410 CMPCI_REG_CH1_FORMAT_MASK, 411 f); 412 } 413 snd_mtxunlock(sc->lock); 414 ch->fmt = format; 415 416 return 0; 417 } 418 419 static u_int32_t 420 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 421 { 422 struct sc_chinfo *ch = data; 423 struct sc_info *sc = ch->parent; 424 u_int32_t r, rsp __unused; 425 426 r = cmpci_rate_to_regvalue(speed); 427 snd_mtxlock(sc->lock); 428 if (ch->dir == PCMDIR_PLAY) { 429 if (speed < 44100) { 430 /* disable if req before rate change */ 431 cmi_spdif_speed(ch->parent, speed); 432 } 433 cmi_partial_wr4(ch->parent, 434 CMPCI_REG_FUNC_1, 435 CMPCI_REG_DAC_FS_SHIFT, 436 CMPCI_REG_DAC_FS_MASK, 437 r); 438 if (speed >= 44100 && ch->parent->spdif_enabled) { 439 /* enable if req after rate change */ 440 cmi_spdif_speed(ch->parent, speed); 441 } 442 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 443 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 444 rsp &= CMPCI_REG_DAC_FS_MASK; 445 } else { 446 cmi_partial_wr4(ch->parent, 447 CMPCI_REG_FUNC_1, 448 CMPCI_REG_ADC_FS_SHIFT, 449 CMPCI_REG_ADC_FS_MASK, 450 r); 451 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 452 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 453 rsp &= CMPCI_REG_ADC_FS_MASK; 454 } 455 snd_mtxunlock(sc->lock); 456 ch->spd = cmpci_regvalue_to_rate(r); 457 458 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 459 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 460 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 461 462 return ch->spd; 463 } 464 465 static u_int32_t 466 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 467 { 468 struct sc_chinfo *ch = data; 469 struct sc_info *sc = ch->parent; 470 471 /* user has requested interrupts every blocksize bytes */ 472 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 473 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 474 } 475 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 476 477 return blocksize; 478 } 479 480 static int 481 cmichan_trigger(kobj_t obj, void *data, int go) 482 { 483 struct sc_chinfo *ch = data; 484 struct sc_info *sc = ch->parent; 485 486 if (!PCMTRIG_COMMON(go)) 487 return 0; 488 489 snd_mtxlock(sc->lock); 490 if (ch->dir == PCMDIR_PLAY) { 491 switch(go) { 492 case PCMTRIG_START: 493 cmi_ch0_start(sc, ch); 494 break; 495 case PCMTRIG_STOP: 496 case PCMTRIG_ABORT: 497 cmi_ch0_stop(sc, ch); 498 break; 499 } 500 } else { 501 switch(go) { 502 case PCMTRIG_START: 503 cmi_ch1_start(sc, ch); 504 break; 505 case PCMTRIG_STOP: 506 case PCMTRIG_ABORT: 507 cmi_ch1_stop(sc, ch); 508 break; 509 } 510 } 511 snd_mtxunlock(sc->lock); 512 return 0; 513 } 514 515 static u_int32_t 516 cmichan_getptr(kobj_t obj, void *data) 517 { 518 struct sc_chinfo *ch = data; 519 struct sc_info *sc = ch->parent; 520 u_int32_t physptr, bufptr, sz; 521 522 snd_mtxlock(sc->lock); 523 if (ch->dir == PCMDIR_PLAY) { 524 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 525 } else { 526 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 527 } 528 snd_mtxunlock(sc->lock); 529 530 sz = sndbuf_getsize(ch->buffer); 531 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 532 533 return bufptr; 534 } 535 536 static void 537 cmi_intr(void *data) 538 { 539 struct sc_info *sc = data; 540 u_int32_t intrstat; 541 u_int32_t toclear; 542 543 snd_mtxlock(sc->lock); 544 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 545 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 546 toclear = 0; 547 if (intrstat & CMPCI_REG_CH0_INTR) { 548 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 549 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 550 } 551 552 if (intrstat & CMPCI_REG_CH1_INTR) { 553 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 554 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 555 } 556 557 if (toclear) { 558 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 559 snd_mtxunlock(sc->lock); 560 561 /* Signal interrupts to channel */ 562 if (intrstat & CMPCI_REG_CH0_INTR) { 563 chn_intr(sc->pch.channel); 564 } 565 566 if (intrstat & CMPCI_REG_CH1_INTR) { 567 chn_intr(sc->rch.channel); 568 } 569 570 snd_mtxlock(sc->lock); 571 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 572 } 573 } 574 if(sc->mpu_intr) { 575 (sc->mpu_intr)(sc->mpu); 576 } 577 snd_mtxunlock(sc->lock); 578 return; 579 } 580 581 static struct pcmchan_caps * 582 cmichan_getcaps(kobj_t obj, void *data) 583 { 584 return &cmi_caps; 585 } 586 587 static kobj_method_t cmichan_methods[] = { 588 KOBJMETHOD(channel_init, cmichan_init), 589 KOBJMETHOD(channel_setformat, cmichan_setformat), 590 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 591 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 592 KOBJMETHOD(channel_trigger, cmichan_trigger), 593 KOBJMETHOD(channel_getptr, cmichan_getptr), 594 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 595 KOBJMETHOD_END 596 }; 597 CHANNEL_DECLARE(cmichan); 598 599 /* ------------------------------------------------------------------------- */ 600 /* Mixer - sb16 with kinks */ 601 602 static void 603 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 604 { 605 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 606 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 607 } 608 609 static u_int8_t 610 cmimix_rd(struct sc_info *sc, u_int8_t port) 611 { 612 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 613 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 614 } 615 616 struct sb16props { 617 u_int8_t rreg; /* right reg chan register */ 618 u_int8_t stereo:1; /* (no explanation needed, honest) */ 619 u_int8_t rec:1; /* recording source */ 620 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 621 u_int8_t oselect; /* output select mask */ 622 u_int8_t iselect; /* right input select mask */ 623 } static const cmt[SOUND_MIXER_NRDEVICES] = { 624 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 625 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 626 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 627 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 628 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 629 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 630 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 631 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 632 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 633 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 634 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 635 /* These controls are not implemented in CMI8738, but maybe at a 636 future date. They are not documented in C-Media documentation, 637 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 638 */ 639 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 640 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 641 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 642 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 643 /* The mic pre-amp is implemented with non-SB16 compatible 644 registers. */ 645 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 646 }; 647 648 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 649 650 static int 651 cmimix_init(struct snd_mixer *m) 652 { 653 struct sc_info *sc = mix_getdevinfo(m); 654 u_int32_t i,v; 655 656 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 657 if (cmt[i].bits) v |= 1 << i; 658 } 659 mix_setdevs(m, v); 660 661 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 662 if (cmt[i].rec) v |= 1 << i; 663 } 664 mix_setrecdevs(m, v); 665 666 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 667 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 668 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 669 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 670 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 671 return 0; 672 } 673 674 static int 675 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 676 { 677 struct sc_info *sc = mix_getdevinfo(m); 678 u_int32_t r, l, max; 679 u_int8_t v; 680 681 max = (1 << cmt[dev].bits) - 1; 682 683 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 684 /* For time being this can only be one thing (mic in 685 * mic/aux reg) */ 686 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 687 l = left * max / 100; 688 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 689 v |= ((l << 1) | (~l >> 3)) & 0x0f; 690 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 691 return 0; 692 } 693 694 l = (left * max / 100) << (8 - cmt[dev].bits); 695 if (cmt[dev].stereo) { 696 r = (right * max / 100) << (8 - cmt[dev].bits); 697 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 698 cmimix_wr(sc, cmt[dev].rreg, r); 699 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 700 "value 0x%02x:0x%02x\n", 701 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 702 } else { 703 r = l; 704 cmimix_wr(sc, cmt[dev].rreg, l); 705 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 706 "value 0x%02x:0x%02x\n", 707 dev, cmt[dev].rreg, l, l)); 708 } 709 710 /* Zero gain does not mute channel from output, but this does... */ 711 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 712 if (l == 0 && r == 0) { 713 v &= ~cmt[dev].oselect; 714 } else { 715 v |= cmt[dev].oselect; 716 } 717 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 718 719 return 0; 720 } 721 722 static u_int32_t 723 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 724 { 725 struct sc_info *sc = mix_getdevinfo(m); 726 u_int32_t i, ml, sl; 727 728 ml = sl = 0; 729 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 730 if ((1<<i) & src) { 731 if (cmt[i].stereo) { 732 sl |= cmt[i].iselect; 733 } else { 734 ml |= cmt[i].iselect; 735 } 736 } 737 } 738 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 739 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 740 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 741 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 742 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 743 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 744 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 745 746 return src; 747 } 748 749 /* Optional SPDIF support. */ 750 751 static int 752 cmi_initsys(struct sc_info* sc) 753 { 754 /* XXX: an user should be able to set this with a control tool, 755 if not done before 7.0-RELEASE, this needs to be converted 756 to a device specific sysctl "dev.pcm.X.yyy" via 757 device_get_sysctl_*() as discussed on multimedia@ in msg-id 758 <861wujij2q.fsf@xps.des.no> */ 759 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 760 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 761 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 762 &sc->spdif_enabled, 0, 763 "enable SPDIF output at 44.1 kHz and above"); 764 765 return 0; 766 } 767 768 /* ------------------------------------------------------------------------- */ 769 static kobj_method_t cmi_mixer_methods[] = { 770 KOBJMETHOD(mixer_init, cmimix_init), 771 KOBJMETHOD(mixer_set, cmimix_set), 772 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 773 KOBJMETHOD_END 774 }; 775 MIXER_DECLARE(cmi_mixer); 776 777 /* 778 * mpu401 functions 779 */ 780 781 static unsigned char 782 cmi_mread(struct mpu401 *arg, void *sc, int reg) 783 { 784 unsigned int d; 785 786 d = bus_space_read_1(0,0, 0x330 + reg); 787 /* printf("cmi_mread: reg %x %x\n",reg, d); 788 */ 789 return d; 790 } 791 792 static void 793 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b) 794 { 795 796 bus_space_write_1(0,0,0x330 + reg , b); 797 } 798 799 static int 800 cmi_muninit(struct mpu401 *arg, void *cookie) 801 { 802 struct sc_info *sc = cookie; 803 804 snd_mtxlock(sc->lock); 805 sc->mpu_intr = NULL; 806 sc->mpu = NULL; 807 snd_mtxunlock(sc->lock); 808 809 return 0; 810 } 811 812 static kobj_method_t cmi_mpu_methods[] = { 813 KOBJMETHOD(mpufoi_read, cmi_mread), 814 KOBJMETHOD(mpufoi_write, cmi_mwrite), 815 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 816 KOBJMETHOD_END 817 }; 818 819 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 820 821 static void 822 cmi_midiattach(struct sc_info *sc) { 823 /* 824 const struct { 825 int port,bits; 826 } *p, ports[] = { 827 {0x330,0}, 828 {0x320,1}, 829 {0x310,2}, 830 {0x300,3}, 831 {0,0} } ; 832 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 833 anyone know how to bus_space tag? 834 */ 835 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 836 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 837 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 838 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 839 0 << CMPCI_REG_VMPUSEL_SHIFT ); 840 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 841 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 842 } 843 844 /* ------------------------------------------------------------------------- */ 845 /* Power and reset */ 846 847 static void 848 cmi_power(struct sc_info *sc, int state) 849 { 850 switch (state) { 851 case 0: /* full power */ 852 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 853 break; 854 default: 855 /* power off */ 856 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 857 break; 858 } 859 } 860 861 static int 862 cmi_init(struct sc_info *sc) 863 { 864 /* Effect reset */ 865 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 866 DELAY(100); 867 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 868 869 /* Disable interrupts and channels */ 870 cmi_clr4(sc, CMPCI_REG_FUNC_0, 871 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 872 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 873 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 874 875 /* Configure DMA channels, ch0 = play, ch1 = capture */ 876 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 877 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 878 879 /* Attempt to enable 4 Channel output */ 880 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 881 882 /* Disable SPDIF1 - not compatible with config */ 883 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 884 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 885 886 return 0; 887 } 888 889 static void 890 cmi_uninit(struct sc_info *sc) 891 { 892 /* Disable interrupts and channels */ 893 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 894 CMPCI_REG_CH0_INTR_ENABLE | 895 CMPCI_REG_CH1_INTR_ENABLE | 896 CMPCI_REG_TDMA_INTR_ENABLE); 897 cmi_clr4(sc, CMPCI_REG_FUNC_0, 898 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 899 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 900 901 if( sc->mpu ) 902 sc->mpu_intr = NULL; 903 } 904 905 /* ------------------------------------------------------------------------- */ 906 /* Bus and device registration */ 907 static int 908 cmi_probe(device_t dev) 909 { 910 switch(pci_get_devid(dev)) { 911 case CMI8338A_PCI_ID: 912 device_set_desc(dev, "CMedia CMI8338A"); 913 return BUS_PROBE_DEFAULT; 914 case CMI8338B_PCI_ID: 915 device_set_desc(dev, "CMedia CMI8338B"); 916 return BUS_PROBE_DEFAULT; 917 case CMI8738_PCI_ID: 918 device_set_desc(dev, "CMedia CMI8738"); 919 return BUS_PROBE_DEFAULT; 920 case CMI8738B_PCI_ID: 921 device_set_desc(dev, "CMedia CMI8738B"); 922 return BUS_PROBE_DEFAULT; 923 case CMI120_USB_ID: 924 device_set_desc(dev, "CMedia CMI120"); 925 return BUS_PROBE_DEFAULT; 926 default: 927 return ENXIO; 928 } 929 } 930 931 static int 932 cmi_attach(device_t dev) 933 { 934 struct sc_info *sc; 935 char status[SND_STATUSLEN]; 936 937 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 938 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc"); 939 pci_enable_busmaster(dev); 940 941 sc->dev = dev; 942 sc->regid = PCIR_BAR(0); 943 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 944 RF_ACTIVE); 945 if (!sc->reg) { 946 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 947 goto bad; 948 } 949 sc->st = rman_get_bustag(sc->reg); 950 sc->sh = rman_get_bushandle(sc->reg); 951 952 if (0) 953 cmi_midiattach(sc); 954 955 sc->irqid = 0; 956 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 957 RF_ACTIVE | RF_SHAREABLE); 958 if (!sc->irq || 959 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 960 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 961 goto bad; 962 } 963 964 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 965 966 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 967 /*boundary*/0, 968 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 969 /*highaddr*/BUS_SPACE_MAXADDR, 970 /*filter*/NULL, /*filterarg*/NULL, 971 /*maxsize*/sc->bufsz, /*nsegments*/1, 972 /*maxsegz*/0x3ffff, /*flags*/0, 973 /*lockfunc*/NULL, 974 /*lockfunc*/NULL, 975 &sc->parent_dmat) != 0) { 976 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 977 goto bad; 978 } 979 980 cmi_power(sc, 0); 981 if (cmi_init(sc)) 982 goto bad; 983 984 if (mixer_init(dev, &cmi_mixer_class, sc)) 985 goto bad; 986 987 if (pcm_register(dev, sc, 1, 1)) 988 goto bad; 989 990 cmi_initsys(sc); 991 992 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 993 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 994 995 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd %s", 996 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 997 pcm_setstatus(dev, status); 998 999 DEB(printf("cmi_attach: succeeded\n")); 1000 return 0; 1001 1002 bad: 1003 if (sc->parent_dmat) 1004 bus_dma_tag_destroy(sc->parent_dmat); 1005 if (sc->ih) 1006 bus_teardown_intr(dev, sc->irq, sc->ih); 1007 if (sc->irq) 1008 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1009 if (sc->reg) 1010 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1011 if (sc->lock) 1012 snd_mtxfree(sc->lock); 1013 if (sc) 1014 free(sc, M_DEVBUF); 1015 1016 return ENXIO; 1017 } 1018 1019 static int 1020 cmi_detach(device_t dev) 1021 { 1022 struct sc_info *sc; 1023 int r; 1024 1025 r = pcm_unregister(dev); 1026 if (r) return r; 1027 1028 sc = pcm_getdevinfo(dev); 1029 cmi_uninit(sc); 1030 cmi_power(sc, 3); 1031 1032 bus_dma_tag_destroy(sc->parent_dmat); 1033 bus_teardown_intr(dev, sc->irq, sc->ih); 1034 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1035 if(sc->mpu) 1036 mpu401_uninit(sc->mpu); 1037 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1038 if (sc->mpu_reg) 1039 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1040 1041 snd_mtxfree(sc->lock); 1042 free(sc, M_DEVBUF); 1043 1044 return 0; 1045 } 1046 1047 static int 1048 cmi_suspend(device_t dev) 1049 { 1050 struct sc_info *sc = pcm_getdevinfo(dev); 1051 1052 snd_mtxlock(sc->lock); 1053 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1054 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1055 cmi_power(sc, 3); 1056 snd_mtxunlock(sc->lock); 1057 return 0; 1058 } 1059 1060 static int 1061 cmi_resume(device_t dev) 1062 { 1063 struct sc_info *sc = pcm_getdevinfo(dev); 1064 1065 snd_mtxlock(sc->lock); 1066 cmi_power(sc, 0); 1067 if (cmi_init(sc) != 0) { 1068 device_printf(dev, "unable to reinitialize the card\n"); 1069 snd_mtxunlock(sc->lock); 1070 return ENXIO; 1071 } 1072 1073 if (mixer_reinit(dev) == -1) { 1074 device_printf(dev, "unable to reinitialize the mixer\n"); 1075 snd_mtxunlock(sc->lock); 1076 return ENXIO; 1077 } 1078 1079 if (sc->pch.dma_was_active) { 1080 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1081 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1082 cmi_ch0_start(sc, &sc->pch); 1083 } 1084 1085 if (sc->rch.dma_was_active) { 1086 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1087 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1088 cmi_ch1_start(sc, &sc->rch); 1089 } 1090 snd_mtxunlock(sc->lock); 1091 return 0; 1092 } 1093 1094 static device_method_t cmi_methods[] = { 1095 DEVMETHOD(device_probe, cmi_probe), 1096 DEVMETHOD(device_attach, cmi_attach), 1097 DEVMETHOD(device_detach, cmi_detach), 1098 DEVMETHOD(device_resume, cmi_resume), 1099 DEVMETHOD(device_suspend, cmi_suspend), 1100 { 0, 0 } 1101 }; 1102 1103 static driver_t cmi_driver = { 1104 "pcm", 1105 cmi_methods, 1106 PCM_SOFTC_SIZE 1107 }; 1108 1109 DRIVER_MODULE(snd_cmi, pci, cmi_driver, 0, 0); 1110 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1111 MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1112 MODULE_VERSION(snd_cmi, 1);
Cache object: f6cb0ad549394dc03e78599598368c67
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