Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/cs4281.c
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1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * The order of pokes in the initiation sequence is based on Linux 27 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom 28 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org) 29 * contributed towards power management. 30 */ 31 32 #include <dev/sound/pcm/sound.h> 33 #include <dev/sound/pcm/ac97.h> 34 35 #include <dev/pci/pcireg.h> 36 #include <dev/pci/pcivar.h> 37 38 #include <dev/sound/pci/cs4281.h> 39 40 SND_DECLARE_FILE("$FreeBSD$"); 41 42 #define CS4281_DEFAULT_BUFSZ 16384 43 44 /* Max fifo size for full duplex is 64 */ 45 #define CS4281_FIFO_SIZE 15 46 47 /* DMA Engine Indices */ 48 #define CS4281_DMA_PLAY 0 49 #define CS4281_DMA_REC 1 50 51 /* Misc */ 52 53 #define inline __inline 54 55 #ifndef DEB 56 #define DEB(x) /* x */ 57 #endif /* DEB */ 58 59 /* ------------------------------------------------------------------------- */ 60 /* Structures */ 61 62 struct sc_info; 63 64 /* channel registers */ 65 struct sc_chinfo { 66 struct sc_info *parent; 67 68 struct snd_dbuf *buffer; 69 struct pcm_channel *channel; 70 71 u_int32_t spd, fmt, bps, blksz; 72 73 int dma_setup, dma_active, dma_chan; 74 }; 75 76 /* device private data */ 77 struct sc_info { 78 device_t dev; 79 u_int32_t type; 80 81 bus_space_tag_t st; 82 bus_space_handle_t sh; 83 bus_dma_tag_t parent_dmat; 84 85 struct resource *reg, *irq, *mem; 86 int regtype, regid, irqid, memid; 87 void *ih; 88 89 int power; 90 unsigned long bufsz; 91 struct sc_chinfo pch; 92 struct sc_chinfo rch; 93 }; 94 95 /* -------------------------------------------------------------------- */ 96 /* prototypes */ 97 98 /* ADC/DAC control */ 99 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go); 100 static void adcdac_prog(struct sc_chinfo *ch); 101 102 /* power management and interrupt control */ 103 static void cs4281_intr(void *); 104 static int cs4281_power(struct sc_info *, int); 105 static int cs4281_init(struct sc_info *); 106 107 /* talk to the card */ 108 static u_int32_t cs4281_rd(struct sc_info *, int); 109 static void cs4281_wr(struct sc_info *, int, u_int32_t); 110 111 /* misc */ 112 static u_int8_t cs4281_rate_to_rv(u_int32_t); 113 static u_int32_t cs4281_format_to_dmr(u_int32_t); 114 static u_int32_t cs4281_format_to_bps(u_int32_t); 115 116 /* -------------------------------------------------------------------- */ 117 /* formats (do not add formats without editing cs_fmt_tab) */ 118 119 static u_int32_t cs4281_fmts[] = { 120 AFMT_U8, 121 AFMT_U8 | AFMT_STEREO, 122 AFMT_S8, 123 AFMT_S8 | AFMT_STEREO, 124 AFMT_S16_LE, 125 AFMT_S16_LE | AFMT_STEREO, 126 AFMT_U16_LE, 127 AFMT_U16_LE | AFMT_STEREO, 128 AFMT_S16_BE, 129 AFMT_S16_BE | AFMT_STEREO, 130 AFMT_U16_BE, 131 AFMT_U16_BE | AFMT_STEREO, 132 0 133 }; 134 135 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0}; 136 137 /* -------------------------------------------------------------------- */ 138 /* Hardware */ 139 140 static inline u_int32_t 141 cs4281_rd(struct sc_info *sc, int regno) 142 { 143 return bus_space_read_4(sc->st, sc->sh, regno); 144 } 145 146 static inline void 147 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data) 148 { 149 bus_space_write_4(sc->st, sc->sh, regno, data); 150 DELAY(100); 151 } 152 153 static inline void 154 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) 155 { 156 u_int32_t r; 157 r = cs4281_rd(sc, regno); 158 cs4281_wr(sc, regno, r & ~mask); 159 } 160 161 static inline void 162 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask) 163 { 164 u_int32_t v; 165 v = cs4281_rd(sc, regno); 166 cs4281_wr(sc, regno, v | mask); 167 } 168 169 static int 170 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries) 171 { 172 u_int32_t v; 173 174 while(tries > 0) { 175 DELAY(100); 176 v = cs4281_rd(sc, regno); 177 if ((v & mask) == mask) break; 178 tries --; 179 } 180 return tries; 181 } 182 183 static int 184 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries) 185 { 186 u_int32_t v; 187 188 while(tries > 0) { 189 DELAY(100); 190 v = ~ cs4281_rd(sc, regno); 191 if (v & mask) break; 192 tries --; 193 } 194 return tries; 195 } 196 197 /* ------------------------------------------------------------------------- */ 198 /* Register value mapping functions */ 199 200 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000}; 201 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0]) 202 203 static u_int8_t 204 cs4281_rate_to_rv(u_int32_t rate) 205 { 206 u_int32_t v; 207 208 for (v = 0; v < CS4281_NUM_RATES; v++) { 209 if (rate == cs4281_rates[v]) return v; 210 } 211 212 v = 1536000 / rate; 213 if (v > 255 || v < 32) v = 5; /* default to 8k */ 214 return v; 215 } 216 217 static u_int32_t 218 cs4281_rv_to_rate(u_int8_t rv) 219 { 220 u_int32_t r; 221 222 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv]; 223 r = 1536000 / rv; 224 return r; 225 } 226 227 static inline u_int32_t 228 cs4281_format_to_dmr(u_int32_t format) 229 { 230 u_int32_t dmr = 0; 231 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8; 232 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO; 233 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND; 234 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN; 235 return dmr; 236 } 237 238 static inline u_int32_t 239 cs4281_format_to_bps(u_int32_t format) 240 { 241 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1); 242 } 243 244 /* -------------------------------------------------------------------- */ 245 /* ac97 codec */ 246 247 static u_int32_t 248 cs4281_rdcd(kobj_t obj, void *devinfo, int regno) 249 { 250 struct sc_info *sc = (struct sc_info *)devinfo; 251 int codecno; 252 253 codecno = regno >> 8; 254 regno &= 0xff; 255 256 /* Remove old state */ 257 cs4281_rd(sc, CS4281PCI_ACSDA); 258 259 /* Fill in AC97 register value request form */ 260 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 261 cs4281_wr(sc, CS4281PCI_ACCDA, 0); 262 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 263 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV | 264 CS4281PCI_ACCTL_CRW); 265 266 /* Wait for read to complete */ 267 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 268 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n"); 269 return 0xffffffff; 270 } 271 272 /* Wait for valid status */ 273 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) { 274 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n"); 275 return 0xffffffff; 276 } 277 278 return cs4281_rd(sc, CS4281PCI_ACSDA); 279 } 280 281 static void 282 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 283 { 284 struct sc_info *sc = (struct sc_info *)devinfo; 285 int codecno; 286 287 codecno = regno >> 8; 288 regno &= 0xff; 289 290 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 291 cs4281_wr(sc, CS4281PCI_ACCDA, data); 292 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 293 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV); 294 295 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 296 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n"); 297 } 298 } 299 300 static kobj_method_t cs4281_ac97_methods[] = { 301 KOBJMETHOD(ac97_read, cs4281_rdcd), 302 KOBJMETHOD(ac97_write, cs4281_wrcd), 303 { 0, 0 } 304 }; 305 AC97_DECLARE(cs4281_ac97); 306 307 /* ------------------------------------------------------------------------- */ 308 /* shared rec/play channel interface */ 309 310 static void * 311 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 312 { 313 struct sc_info *sc = devinfo; 314 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 315 316 ch->buffer = b; 317 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 318 return NULL; 319 } 320 ch->parent = sc; 321 ch->channel = c; 322 323 ch->fmt = AFMT_U8; 324 ch->spd = DSP_DEFAULT_SPEED; 325 ch->bps = 1; 326 ch->blksz = sndbuf_getsize(ch->buffer); 327 328 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC; 329 ch->dma_setup = 0; 330 331 adcdac_go(ch, 0); 332 adcdac_prog(ch); 333 334 return ch; 335 } 336 337 static int 338 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 339 { 340 struct sc_chinfo *ch = data; 341 struct sc_info *sc = ch->parent; 342 u_int32_t go; 343 344 go = adcdac_go(ch, 0); 345 346 /* 2 interrupts are possible and used in buffer (half-empty,empty), 347 * hence factor of 2. */ 348 ch->blksz = MIN(blocksize, sc->bufsz / 2); 349 sndbuf_resize(ch->buffer, 2, ch->blksz); 350 ch->dma_setup = 0; 351 adcdac_prog(ch); 352 adcdac_go(ch, go); 353 354 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz)); 355 356 return ch->blksz; 357 } 358 359 static int 360 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed) 361 { 362 struct sc_chinfo *ch = data; 363 struct sc_info *sc = ch->parent; 364 u_int32_t go, v, r; 365 366 go = adcdac_go(ch, 0); /* pause */ 367 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR; 368 v = cs4281_rate_to_rv(speed); 369 cs4281_wr(sc, r, v); 370 adcdac_go(ch, go); /* unpause */ 371 372 ch->spd = cs4281_rv_to_rate(v); 373 return ch->spd; 374 } 375 376 static int 377 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format) 378 { 379 struct sc_chinfo *ch = data; 380 struct sc_info *sc = ch->parent; 381 u_int32_t v, go; 382 383 go = adcdac_go(ch, 0); /* pause */ 384 385 if (ch->dma_chan == CS4281_DMA_PLAY) 386 v = CS4281PCI_DMR_TR_PLAY; 387 else 388 v = CS4281PCI_DMR_TR_REC; 389 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO; 390 v |= cs4281_format_to_dmr(format); 391 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v); 392 393 adcdac_go(ch, go); /* unpause */ 394 395 ch->fmt = format; 396 ch->bps = cs4281_format_to_bps(format); 397 ch->dma_setup = 0; 398 399 return 0; 400 } 401 402 static int 403 cs4281chan_getptr(kobj_t obj, void *data) 404 { 405 struct sc_chinfo *ch = data; 406 struct sc_info *sc = ch->parent; 407 u_int32_t dba, dca, ptr; 408 int sz; 409 410 sz = sndbuf_getsize(ch->buffer); 411 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan)); 412 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan)); 413 ptr = (dca - dba + sz) % sz; 414 415 return ptr; 416 } 417 418 static int 419 cs4281chan_trigger(kobj_t obj, void *data, int go) 420 { 421 struct sc_chinfo *ch = data; 422 423 switch(go) { 424 case PCMTRIG_START: 425 adcdac_prog(ch); 426 adcdac_go(ch, 1); 427 break; 428 case PCMTRIG_ABORT: 429 adcdac_go(ch, 0); 430 break; 431 default: 432 break; 433 } 434 435 /* return 0 if ok */ 436 return 0; 437 } 438 439 static struct pcmchan_caps * 440 cs4281chan_getcaps(kobj_t obj, void *data) 441 { 442 return &cs4281_caps; 443 } 444 445 static kobj_method_t cs4281chan_methods[] = { 446 KOBJMETHOD(channel_init, cs4281chan_init), 447 KOBJMETHOD(channel_setformat, cs4281chan_setformat), 448 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed), 449 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize), 450 KOBJMETHOD(channel_trigger, cs4281chan_trigger), 451 KOBJMETHOD(channel_getptr, cs4281chan_getptr), 452 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps), 453 { 0, 0 } 454 }; 455 CHANNEL_DECLARE(cs4281chan); 456 457 /* -------------------------------------------------------------------- */ 458 /* ADC/DAC control */ 459 460 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was 461 * active before call */ 462 463 static u_int32_t 464 adcdac_go(struct sc_chinfo *ch, u_int32_t go) 465 { 466 struct sc_info *sc = ch->parent; 467 u_int32_t going; 468 469 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK); 470 471 if (go) 472 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 473 else 474 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 475 476 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 477 478 return going; 479 } 480 481 static void 482 adcdac_prog(struct sc_chinfo *ch) 483 { 484 struct sc_info *sc = ch->parent; 485 u_int32_t go; 486 487 if (!ch->dma_setup) { 488 go = adcdac_go(ch, 0); 489 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan), 490 sndbuf_getbufaddr(ch->buffer)); 491 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan), 492 sndbuf_getsize(ch->buffer) / ch->bps - 1); 493 ch->dma_setup = 1; 494 adcdac_go(ch, go); 495 } 496 } 497 498 /* -------------------------------------------------------------------- */ 499 /* The interrupt handler */ 500 501 static void 502 cs4281_intr(void *p) 503 { 504 struct sc_info *sc = (struct sc_info *)p; 505 u_int32_t hisr; 506 507 hisr = cs4281_rd(sc, CS4281PCI_HISR); 508 509 if (hisr == 0) return; 510 511 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) { 512 chn_intr(sc->pch.channel); 513 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */ 514 } 515 516 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) { 517 chn_intr(sc->rch.channel); 518 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */ 519 } 520 521 /* Signal End-of-Interrupt */ 522 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 523 } 524 525 /* -------------------------------------------------------------------- */ 526 /* power management related */ 527 528 static int 529 cs4281_power(struct sc_info *sc, int state) 530 { 531 532 switch (state) { 533 case 0: 534 /* Permit r/w access to all BA0 registers */ 535 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC); 536 /* Power on */ 537 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 538 break; 539 case 3: 540 /* Power off card and codec */ 541 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 542 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 543 break; 544 } 545 546 DEB(printf("cs4281_power %d -> %d\n", sc->power, state)); 547 sc->power = state; 548 549 return 0; 550 } 551 552 static int 553 cs4281_init(struct sc_info *sc) 554 { 555 u_int32_t i, v; 556 557 /* (0) Blast clock register and serial port */ 558 cs4281_wr(sc, CS4281PCI_CLKCR1, 0); 559 cs4281_wr(sc, CS4281PCI_SERMC, 0); 560 561 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */ 562 cs4281_wr(sc, CS4281PCI_ACCTL, 0); 563 DELAY(50); 564 565 /* (2) Effect Reset */ 566 cs4281_wr(sc, CS4281PCI_SPMC, 0); 567 DELAY(100); 568 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 569 /* Wait 50ms for ABITCLK to become stable */ 570 DELAY(50000); 571 572 /* (3) Enable Sound System Clocks */ 573 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP); 574 DELAY(50000); /* Wait for PLL to stabilize */ 575 cs4281_wr(sc, CS4281PCI_CLKCR1, 576 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE); 577 578 /* (4) Power Up - this combination is essential. */ 579 cs4281_set4(sc, CS4281PCI_SSPM, 580 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN | 581 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN); 582 583 /* (5) Wait for clock stabilization */ 584 if (cs4281_waitset(sc, 585 CS4281PCI_CLKCR1, 586 CS4281PCI_CLKCR1_DLLRDY, 587 250) == 0) { 588 device_printf(sc->dev, "Clock stabilization failed\n"); 589 return -1; 590 } 591 592 /* (6) Enable ASYNC generation. */ 593 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN); 594 595 /* Wait to allow AC97 to start generating clock bit */ 596 DELAY(50000); 597 598 /* Set AC97 timing */ 599 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 600 601 /* (7) Wait for AC97 ready signal */ 602 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) { 603 device_printf(sc->dev, "codec did not avail\n"); 604 return -1; 605 } 606 607 /* (8) Assert valid frame signal to begin sending commands to 608 * AC97 codec */ 609 cs4281_wr(sc, 610 CS4281PCI_ACCTL, 611 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN); 612 613 /* (9) Wait for codec calibration */ 614 for(i = 0 ; i < 1000; i++) { 615 DELAY(10000); 616 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 617 if ((v & 0x0f) == 0x0f) { 618 break; 619 } 620 } 621 if (i == 1000) { 622 device_printf(sc->dev, "codec failed to calibrate\n"); 623 return -1; 624 } 625 626 /* (10) Set AC97 timing */ 627 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 628 629 /* (11) Wait for valid data to arrive */ 630 if (cs4281_waitset(sc, 631 CS4281PCI_ACISV, 632 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4), 633 10000) == 0) { 634 device_printf(sc->dev, "cs4281 never got valid data\n"); 635 return -1; 636 } 637 638 /* (12) Start digital data transfer of audio data to codec */ 639 cs4281_wr(sc, 640 CS4281PCI_ACOSV, 641 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4)); 642 643 /* Set Master and headphone to max */ 644 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0); 645 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0); 646 647 /* Power on the DAC */ 648 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff; 649 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 650 651 /* Wait until DAC state ready */ 652 for(i = 0; i < 320; i++) { 653 DELAY(100); 654 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 655 if (v & 0x02) break; 656 } 657 658 /* Power on the ADC */ 659 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff; 660 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 661 662 /* Wait until ADC state ready */ 663 for(i = 0; i < 320; i++) { 664 DELAY(100); 665 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 666 if (v & 0x01) break; 667 } 668 669 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */ 670 /* Play FIFO */ 671 672 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) | 673 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) | 674 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 675 CS4281PCI_FCR_OF(0); 676 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v); 677 678 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN); 679 680 /* Record FIFO */ 681 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) | 682 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) | 683 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 684 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1); 685 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH); 686 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN); 687 688 /* Match AC97 slots to FIFOs */ 689 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) | 690 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) | 691 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) | 692 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT); 693 cs4281_wr(sc, CS4281PCI_SRCSA, v); 694 695 /* Set Auto-Initialize and set directions */ 696 cs4281_wr(sc, 697 CS4281PCI_DMR(CS4281_DMA_PLAY), 698 CS4281PCI_DMR_DMA | 699 CS4281PCI_DMR_AUTO | 700 CS4281PCI_DMR_TR_PLAY); 701 cs4281_wr(sc, 702 CS4281PCI_DMR(CS4281_DMA_REC), 703 CS4281PCI_DMR_DMA | 704 CS4281PCI_DMR_AUTO | 705 CS4281PCI_DMR_TR_REC); 706 707 /* Enable half and empty buffer interrupts keeping DMA paused */ 708 cs4281_wr(sc, 709 CS4281PCI_DCR(CS4281_DMA_PLAY), 710 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 711 cs4281_wr(sc, 712 CS4281PCI_DCR(CS4281_DMA_REC), 713 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 714 715 /* Enable Interrupts */ 716 cs4281_clr4(sc, 717 CS4281PCI_HIMR, 718 CS4281PCI_HIMR_DMAI | 719 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) | 720 CS4281PCI_HIMR_DMA(CS4281_DMA_REC)); 721 722 /* Set playback volume */ 723 cs4281_wr(sc, CS4281PCI_PPLVC, 7); 724 cs4281_wr(sc, CS4281PCI_PPRVC, 7); 725 726 return 0; 727 } 728 729 /* -------------------------------------------------------------------- */ 730 /* Probe and attach the card */ 731 732 static int 733 cs4281_pci_probe(device_t dev) 734 { 735 char *s = NULL; 736 737 switch (pci_get_devid(dev)) { 738 case CS4281_PCI_ID: 739 s = "Crystal Semiconductor CS4281"; 740 break; 741 } 742 743 if (s) 744 device_set_desc(dev, s); 745 return s ? 0 : ENXIO; 746 } 747 748 static int 749 cs4281_pci_attach(device_t dev) 750 { 751 struct sc_info *sc; 752 struct ac97_info *codec = NULL; 753 u_int32_t data; 754 char status[SND_STATUSLEN]; 755 756 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 757 device_printf(dev, "cannot allocate softc\n"); 758 return ENXIO; 759 } 760 761 sc->dev = dev; 762 sc->type = pci_get_devid(dev); 763 764 data = pci_read_config(dev, PCIR_COMMAND, 2); 765 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 766 pci_write_config(dev, PCIR_COMMAND, data, 2); 767 768 #if __FreeBSD_version > 500000 769 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 770 /* Reset the power state. */ 771 device_printf(dev, "chip is in D%d power mode " 772 "-- setting to D0\n", pci_get_powerstate(dev)); 773 774 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 775 } 776 #else 777 data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4); 778 if (data & CS4281PCI_PMCS_PS_MASK) { 779 /* Reset the power state. */ 780 device_printf(dev, "chip is in D%d power mode " 781 "-- setting to D0\n", 782 data & CS4281PCI_PMCS_PS_MASK); 783 pci_write_config(dev, CS4281PCI_PMCS_OFFSET, 784 data & ~CS4281PCI_PMCS_PS_MASK, 4); 785 } 786 #endif 787 788 sc->regid = PCIR_BAR(0); 789 sc->regtype = SYS_RES_MEMORY; 790 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 791 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 792 if (!sc->reg) { 793 sc->regtype = SYS_RES_IOPORT; 794 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 795 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 796 if (!sc->reg) { 797 device_printf(dev, "unable to allocate register space\n"); 798 goto bad; 799 } 800 } 801 sc->st = rman_get_bustag(sc->reg); 802 sc->sh = rman_get_bushandle(sc->reg); 803 804 sc->memid = PCIR_BAR(1); 805 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0, 806 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE); 807 if (sc->mem == NULL) { 808 device_printf(dev, "unable to allocate fifo space\n"); 809 goto bad; 810 } 811 812 sc->irqid = 0; 813 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 814 RF_ACTIVE | RF_SHAREABLE); 815 if (!sc->irq) { 816 device_printf(dev, "unable to allocate interrupt\n"); 817 goto bad; 818 } 819 820 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) { 821 device_printf(dev, "unable to setup interrupt\n"); 822 goto bad; 823 } 824 825 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536); 826 827 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 828 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 829 /*highaddr*/BUS_SPACE_MAXADDR, 830 /*filter*/NULL, /*filterarg*/NULL, 831 /*maxsize*/sc->bufsz, /*nsegments*/1, 832 /*maxsegz*/0x3ffff, 833 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 834 /*lockarg*/&Giant, &sc->parent_dmat) != 0) { 835 device_printf(dev, "unable to create dma tag\n"); 836 goto bad; 837 } 838 839 /* power up */ 840 cs4281_power(sc, 0); 841 842 /* init chip */ 843 if (cs4281_init(sc) == -1) { 844 device_printf(dev, "unable to initialize the card\n"); 845 goto bad; 846 } 847 848 /* create/init mixer */ 849 codec = AC97_CREATE(dev, sc, cs4281_ac97); 850 if (codec == NULL) 851 goto bad; 852 853 mixer_init(dev, ac97_getmixerclass(), codec); 854 855 if (pcm_register(dev, sc, 1, 1)) 856 goto bad; 857 858 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc); 859 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc); 860 861 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 862 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 863 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281)); 864 pcm_setstatus(dev, status); 865 866 return 0; 867 868 bad: 869 if (codec) 870 ac97_destroy(codec); 871 if (sc->reg) 872 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 873 if (sc->mem) 874 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 875 if (sc->ih) 876 bus_teardown_intr(dev, sc->irq, sc->ih); 877 if (sc->irq) 878 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 879 if (sc->parent_dmat) 880 bus_dma_tag_destroy(sc->parent_dmat); 881 free(sc, M_DEVBUF); 882 883 return ENXIO; 884 } 885 886 static int 887 cs4281_pci_detach(device_t dev) 888 { 889 int r; 890 struct sc_info *sc; 891 892 r = pcm_unregister(dev); 893 if (r) 894 return r; 895 896 sc = pcm_getdevinfo(dev); 897 898 /* power off */ 899 cs4281_power(sc, 3); 900 901 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 902 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 903 bus_teardown_intr(dev, sc->irq, sc->ih); 904 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 905 bus_dma_tag_destroy(sc->parent_dmat); 906 free(sc, M_DEVBUF); 907 908 return 0; 909 } 910 911 static int 912 cs4281_pci_suspend(device_t dev) 913 { 914 struct sc_info *sc; 915 916 sc = pcm_getdevinfo(dev); 917 918 sc->rch.dma_active = adcdac_go(&sc->rch, 0); 919 sc->pch.dma_active = adcdac_go(&sc->pch, 0); 920 921 cs4281_power(sc, 3); 922 923 return 0; 924 } 925 926 static int 927 cs4281_pci_resume(device_t dev) 928 { 929 struct sc_info *sc; 930 931 sc = pcm_getdevinfo(dev); 932 933 /* power up */ 934 cs4281_power(sc, 0); 935 936 /* initialize chip */ 937 if (cs4281_init(sc) == -1) { 938 device_printf(dev, "unable to reinitialize the card\n"); 939 return ENXIO; 940 } 941 942 /* restore mixer state */ 943 if (mixer_reinit(dev) == -1) { 944 device_printf(dev, "unable to reinitialize the mixer\n"); 945 return ENXIO; 946 } 947 948 /* restore chip state */ 949 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd); 950 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz); 951 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt); 952 adcdac_go(&sc->rch, sc->rch.dma_active); 953 954 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd); 955 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz); 956 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt); 957 adcdac_go(&sc->pch, sc->pch.dma_active); 958 959 return 0; 960 } 961 962 static device_method_t cs4281_methods[] = { 963 /* Device interface */ 964 DEVMETHOD(device_probe, cs4281_pci_probe), 965 DEVMETHOD(device_attach, cs4281_pci_attach), 966 DEVMETHOD(device_detach, cs4281_pci_detach), 967 DEVMETHOD(device_suspend, cs4281_pci_suspend), 968 DEVMETHOD(device_resume, cs4281_pci_resume), 969 { 0, 0 } 970 }; 971 972 static driver_t cs4281_driver = { 973 "pcm", 974 cs4281_methods, 975 PCM_SOFTC_SIZE, 976 }; 977 978 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0); 979 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 980 MODULE_VERSION(snd_cs4281, 1);
Cache object: 00c4310cd809cc02bf82c0ea4dded489
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