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sys/dev/sound/pci/csa.c
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1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_intr_t *intr, void *arg, void **cookiep); 86 static int csa_teardown_intr(device_t bus, device_t child, 87 struct resource *irq, void *cookie); 88 static driver_intr_t csa_intr; 89 static int csa_initialize(sc_p scp); 90 static int csa_downloadimage(csa_res *resp); 91 92 static devclass_t csa_devclass; 93 94 static void 95 amp_none(void) 96 { 97 } 98 99 static void 100 amp_voyetra(void) 101 { 102 } 103 104 static int 105 clkrun_hack(int run) 106 { 107 #ifdef __i386__ 108 devclass_t pci_devclass; 109 device_t *pci_devices, *pci_children, *busp, *childp; 110 int pci_count = 0, pci_childcount = 0; 111 int i, j, port; 112 u_int16_t control; 113 bus_space_tag_t btag; 114 115 if ((pci_devclass = devclass_find("pci")) == NULL) { 116 return ENXIO; 117 } 118 119 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 120 121 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 122 pci_childcount = 0; 123 device_get_children(*busp, &pci_children, &pci_childcount); 124 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 125 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 126 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 127 /* XXX */ 128 btag = I386_BUS_SPACE_IO; 129 130 control = bus_space_read_2(btag, 0x0, port); 131 control &= ~0x2000; 132 control |= run? 0 : 0x2000; 133 bus_space_write_2(btag, 0x0, port, control); 134 free(pci_devices, M_TEMP); 135 free(pci_children, M_TEMP); 136 return 0; 137 } 138 } 139 free(pci_children, M_TEMP); 140 } 141 142 free(pci_devices, M_TEMP); 143 return ENXIO; 144 #else 145 return 0; 146 #endif 147 } 148 149 static struct csa_card cards_4610[] = { 150 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 151 }; 152 153 static struct csa_card cards_4614[] = { 154 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 155 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 156 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 157 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 158 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 160 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 161 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 162 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 163 }; 164 165 static struct csa_card cards_4615[] = { 166 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 167 }; 168 169 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 170 171 struct card_type { 172 u_int32_t devid; 173 char *name; 174 struct csa_card *cards; 175 }; 176 177 static struct card_type cards[] = { 178 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 179 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 180 {CS4615_PCI_ID, "CS4615", cards_4615}, 181 {0, NULL, NULL}, 182 }; 183 184 static struct card_type * 185 csa_findcard(device_t dev) 186 { 187 int i; 188 189 i = 0; 190 while (cards[i].devid != 0) { 191 if (pci_get_devid(dev) == cards[i].devid) 192 return &cards[i]; 193 i++; 194 } 195 return NULL; 196 } 197 198 struct csa_card * 199 csa_findsubcard(device_t dev) 200 { 201 int i; 202 struct card_type *card; 203 struct csa_card *subcard; 204 205 card = csa_findcard(dev); 206 if (card == NULL) 207 return &nocard; 208 subcard = card->cards; 209 i = 0; 210 while (subcard[i].subvendor != 0) { 211 if (pci_get_subvendor(dev) == subcard[i].subvendor 212 && pci_get_subdevice(dev) == subcard[i].subdevice) { 213 return &subcard[i]; 214 } 215 i++; 216 } 217 return &subcard[i]; 218 } 219 220 static int 221 csa_probe(device_t dev) 222 { 223 struct card_type *card; 224 225 card = csa_findcard(dev); 226 if (card) { 227 device_set_desc(dev, card->name); 228 return 0; 229 } 230 return ENXIO; 231 } 232 233 static int 234 csa_attach(device_t dev) 235 { 236 u_int32_t stcmd; 237 sc_p scp; 238 csa_res *resp; 239 struct sndcard_func *func; 240 int error = ENXIO; 241 242 scp = device_get_softc(dev); 243 244 /* Fill in the softc. */ 245 bzero(scp, sizeof(*scp)); 246 scp->dev = dev; 247 248 /* Wake up the device. */ 249 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 250 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 251 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 252 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 253 } 254 255 /* Allocate the resources. */ 256 resp = &scp->res; 257 scp->card = csa_findsubcard(dev); 258 scp->binfo.card = scp->card; 259 printf("csa: card is %s\n", scp->card->name); 260 resp->io_rid = PCIR_BAR(0); 261 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 262 &resp->io_rid, RF_ACTIVE); 263 if (resp->io == NULL) 264 return (ENXIO); 265 resp->mem_rid = PCIR_BAR(1); 266 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 267 &resp->mem_rid, RF_ACTIVE); 268 if (resp->mem == NULL) 269 goto err_io; 270 resp->irq_rid = 0; 271 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 272 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 273 if (resp->irq == NULL) 274 goto err_mem; 275 276 /* Enable interrupt. */ 277 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 278 goto err_intr; 279 #if 0 280 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 281 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 282 #endif 283 284 /* Initialize the chip. */ 285 if (csa_initialize(scp)) 286 goto err_teardown; 287 288 /* Reset the Processor. */ 289 csa_resetdsp(resp); 290 291 /* Download the Processor Image to the processor. */ 292 if (csa_downloadimage(resp)) 293 goto err_teardown; 294 295 /* Attach the children. */ 296 297 /* PCM Audio */ 298 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 299 if (func == NULL) { 300 error = ENOMEM; 301 goto err_teardown; 302 } 303 func->varinfo = &scp->binfo; 304 func->func = SCF_PCM; 305 scp->pcm = device_add_child(dev, "pcm", -1); 306 device_set_ivars(scp->pcm, func); 307 308 /* Midi Interface */ 309 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 310 if (func == NULL) { 311 error = ENOMEM; 312 goto err_teardown; 313 } 314 func->varinfo = &scp->binfo; 315 func->func = SCF_MIDI; 316 scp->midi = device_add_child(dev, "midi", -1); 317 device_set_ivars(scp->midi, func); 318 319 bus_generic_attach(dev); 320 321 return (0); 322 323 err_teardown: 324 bus_teardown_intr(dev, resp->irq, scp->ih); 325 err_intr: 326 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 327 err_mem: 328 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 329 err_io: 330 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 331 return (error); 332 } 333 334 static int 335 csa_detach(device_t dev) 336 { 337 csa_res *resp; 338 sc_p scp; 339 int err; 340 341 scp = device_get_softc(dev); 342 resp = &scp->res; 343 344 err = 0; 345 if (scp->midi != NULL) 346 err = device_delete_child(dev, scp->midi); 347 if (err) 348 return err; 349 scp->midi = NULL; 350 351 if (scp->pcm != NULL) 352 err = device_delete_child(dev, scp->pcm); 353 if (err) 354 return err; 355 scp->pcm = NULL; 356 357 bus_teardown_intr(dev, resp->irq, scp->ih); 358 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 359 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 360 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 361 362 return bus_generic_detach(dev); 363 } 364 365 static int 366 csa_resume(device_t dev) 367 { 368 csa_res *resp; 369 sc_p scp; 370 371 scp = device_get_softc(dev); 372 resp = &scp->res; 373 374 /* Initialize the chip. */ 375 if (csa_initialize(scp)) 376 return (ENXIO); 377 378 /* Reset the Processor. */ 379 csa_resetdsp(resp); 380 381 /* Download the Processor Image to the processor. */ 382 if (csa_downloadimage(resp)) 383 return (ENXIO); 384 385 return (bus_generic_resume(dev)); 386 } 387 388 static struct resource * 389 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 390 u_long start, u_long end, u_long count, u_int flags) 391 { 392 sc_p scp; 393 csa_res *resp; 394 struct resource *res; 395 396 scp = device_get_softc(bus); 397 resp = &scp->res; 398 switch (type) { 399 case SYS_RES_IRQ: 400 if (*rid != 0) 401 return (NULL); 402 res = resp->irq; 403 break; 404 case SYS_RES_MEMORY: 405 switch (*rid) { 406 case PCIR_BAR(0): 407 res = resp->io; 408 break; 409 case PCIR_BAR(1): 410 res = resp->mem; 411 break; 412 default: 413 return (NULL); 414 } 415 break; 416 default: 417 return (NULL); 418 } 419 420 return res; 421 } 422 423 static int 424 csa_release_resource(device_t bus, device_t child, int type, int rid, 425 struct resource *r) 426 { 427 return (0); 428 } 429 430 /* 431 * The following three functions deal with interrupt handling. 432 * An interrupt is primarily handled by the bridge driver. 433 * The bridge driver then determines the child devices to pass 434 * the interrupt. Certain information of the device can be read 435 * only once(eg the value of HISR). The bridge driver is responsible 436 * to pass such the information to the children. 437 */ 438 439 static int 440 csa_setup_intr(device_t bus, device_t child, 441 struct resource *irq, int flags, 442 driver_intr_t *intr, void *arg, void **cookiep) 443 { 444 sc_p scp; 445 csa_res *resp; 446 struct sndcard_func *func; 447 448 scp = device_get_softc(bus); 449 resp = &scp->res; 450 451 /* 452 * Look at the function code of the child to determine 453 * the appropriate hander for it. 454 */ 455 func = device_get_ivars(child); 456 if (func == NULL || irq != resp->irq) 457 return (EINVAL); 458 459 switch (func->func) { 460 case SCF_PCM: 461 scp->pcmintr = intr; 462 scp->pcmintr_arg = arg; 463 break; 464 465 case SCF_MIDI: 466 scp->midiintr = intr; 467 scp->midiintr_arg = arg; 468 break; 469 470 default: 471 return (EINVAL); 472 } 473 *cookiep = scp; 474 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 475 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 476 477 return (0); 478 } 479 480 static int 481 csa_teardown_intr(device_t bus, device_t child, 482 struct resource *irq, void *cookie) 483 { 484 sc_p scp; 485 csa_res *resp; 486 struct sndcard_func *func; 487 488 scp = device_get_softc(bus); 489 resp = &scp->res; 490 491 /* 492 * Look at the function code of the child to determine 493 * the appropriate hander for it. 494 */ 495 func = device_get_ivars(child); 496 if (func == NULL || irq != resp->irq || cookie != scp) 497 return (EINVAL); 498 499 switch (func->func) { 500 case SCF_PCM: 501 scp->pcmintr = NULL; 502 scp->pcmintr_arg = NULL; 503 break; 504 505 case SCF_MIDI: 506 scp->midiintr = NULL; 507 scp->midiintr_arg = NULL; 508 break; 509 510 default: 511 return (EINVAL); 512 } 513 514 return (0); 515 } 516 517 /* The interrupt handler */ 518 static void 519 csa_intr(void *arg) 520 { 521 sc_p scp = arg; 522 csa_res *resp; 523 u_int32_t hisr; 524 525 resp = &scp->res; 526 527 /* Is this interrupt for us? */ 528 hisr = csa_readio(resp, BA0_HISR); 529 if ((hisr & 0x7fffffff) == 0) { 530 /* Throw an eoi. */ 531 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 532 return; 533 } 534 535 /* 536 * Pass the value of HISR via struct csa_bridgeinfo. 537 * The children get access through their ivars. 538 */ 539 scp->binfo.hisr = hisr; 540 541 /* Invoke the handlers of the children. */ 542 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 543 scp->pcmintr(scp->pcmintr_arg); 544 hisr &= ~(HISR_VC0 | HISR_VC1); 545 } 546 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 547 scp->midiintr(scp->midiintr_arg); 548 hisr &= ~HISR_MIDI; 549 } 550 551 /* Throw an eoi. */ 552 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 553 } 554 555 static int 556 csa_initialize(sc_p scp) 557 { 558 int i; 559 u_int32_t acsts, acisv; 560 csa_res *resp; 561 562 resp = &scp->res; 563 564 /* 565 * First, blast the clock control register to zero so that the PLL starts 566 * out in a known state, and blast the master serial port control register 567 * to zero so that the serial ports also start out in a known state. 568 */ 569 csa_writeio(resp, BA0_CLKCR1, 0); 570 csa_writeio(resp, BA0_SERMC1, 0); 571 572 /* 573 * If we are in AC97 mode, then we must set the part to a host controlled 574 * AC-link. Otherwise, we won't be able to bring up the link. 575 */ 576 #if 1 577 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 578 #else 579 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 580 #endif /* 1 */ 581 582 /* 583 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 584 * spec) and then drive it high. This is done for non AC97 modes since 585 * there might be logic external to the CS461x that uses the ARST# line 586 * for a reset. 587 */ 588 csa_writeio(resp, BA0_ACCTL, 1); 589 DELAY(50); 590 csa_writeio(resp, BA0_ACCTL, 0); 591 DELAY(50); 592 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 593 594 /* 595 * The first thing we do here is to enable sync generation. As soon 596 * as we start receiving bit clock, we'll start producing the SYNC 597 * signal. 598 */ 599 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 600 601 /* 602 * Now wait for a short while to allow the AC97 part to start 603 * generating bit clock (so we don't try to start the PLL without an 604 * input clock). 605 */ 606 DELAY(50000); 607 608 /* 609 * Set the serial port timing configuration, so that 610 * the clock control circuit gets its clock from the correct place. 611 */ 612 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 613 DELAY(700000); 614 615 /* 616 * Write the selected clock control setup to the hardware. Do not turn on 617 * SWCE yet (if requested), so that the devices clocked by the output of 618 * PLL are not clocked until the PLL is stable. 619 */ 620 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 621 csa_writeio(resp, BA0_PLLM, 0x3a); 622 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 623 624 /* 625 * Power up the PLL. 626 */ 627 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 628 629 /* 630 * Wait until the PLL has stabilized. 631 */ 632 DELAY(5000); 633 634 /* 635 * Turn on clocking of the core so that we can setup the serial ports. 636 */ 637 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 638 639 /* 640 * Fill the serial port FIFOs with silence. 641 */ 642 csa_clearserialfifos(resp); 643 644 /* 645 * Set the serial port FIFO pointer to the first sample in the FIFO. 646 */ 647 #if notdef 648 csa_writeio(resp, BA0_SERBSP, 0); 649 #endif /* notdef */ 650 651 /* 652 * Write the serial port configuration to the part. The master 653 * enable bit is not set until all other values have been written. 654 */ 655 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 656 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 657 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 658 659 /* 660 * Wait for the codec ready signal from the AC97 codec. 661 */ 662 acsts = 0; 663 for (i = 0 ; i < 1000 ; i++) { 664 /* 665 * First, lets wait a short while to let things settle out a bit, 666 * and to prevent retrying the read too quickly. 667 */ 668 DELAY(125); 669 670 /* 671 * Read the AC97 status register to see if we've seen a CODEC READY 672 * signal from the AC97 codec. 673 */ 674 acsts = csa_readio(resp, BA0_ACSTS); 675 if ((acsts & ACSTS_CRDY) != 0) 676 break; 677 } 678 679 /* 680 * Make sure we sampled CODEC READY. 681 */ 682 if ((acsts & ACSTS_CRDY) == 0) 683 return (ENXIO); 684 685 /* 686 * Assert the vaid frame signal so that we can start sending commands 687 * to the AC97 codec. 688 */ 689 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 690 691 /* 692 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 693 * the codec is pumping ADC data across the AC-link. 694 */ 695 acisv = 0; 696 for (i = 0 ; i < 1000 ; i++) { 697 /* 698 * First, lets wait a short while to let things settle out a bit, 699 * and to prevent retrying the read too quickly. 700 */ 701 #if notdef 702 DELAY(10000000L); /* clw */ 703 #else 704 DELAY(1000); 705 #endif /* notdef */ 706 /* 707 * Read the input slot valid register and see if input slots 3 and 708 * 4 are valid yet. 709 */ 710 acisv = csa_readio(resp, BA0_ACISV); 711 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 712 break; 713 } 714 /* 715 * Make sure we sampled valid input slots 3 and 4. If not, then return 716 * an error. 717 */ 718 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 719 return (ENXIO); 720 721 /* 722 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 723 * commense the transfer of digital audio data to the AC97 codec. 724 */ 725 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 726 727 /* 728 * Power down the DAC and ADC. We will power them up (if) when we need 729 * them. 730 */ 731 #if notdef 732 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 733 #endif /* notdef */ 734 735 /* 736 * Turn off the Processor by turning off the software clock enable flag in 737 * the clock control register. 738 */ 739 #if notdef 740 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 741 csa_writeio(resp, BA0_CLKCR1, clkcr1); 742 #endif /* notdef */ 743 744 /* 745 * Enable interrupts on the part. 746 */ 747 #if 0 748 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 749 #endif /* notdef */ 750 751 return (0); 752 } 753 754 void 755 csa_clearserialfifos(csa_res *resp) 756 { 757 int i, j, pwr; 758 u_int8_t clkcr1, serbst; 759 760 /* 761 * See if the devices are powered down. If so, we must power them up first 762 * or they will not respond. 763 */ 764 pwr = 1; 765 clkcr1 = csa_readio(resp, BA0_CLKCR1); 766 if ((clkcr1 & CLKCR1_SWCE) == 0) { 767 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 768 pwr = 0; 769 } 770 771 /* 772 * We want to clear out the serial port FIFOs so we don't end up playing 773 * whatever random garbage happens to be in them. We fill the sample FIFOs 774 * with zero (silence). 775 */ 776 csa_writeio(resp, BA0_SERBWP, 0); 777 778 /* Fill all 256 sample FIFO locations. */ 779 serbst = 0; 780 for (i = 0 ; i < 256 ; i++) { 781 /* Make sure the previous FIFO write operation has completed. */ 782 for (j = 0 ; j < 5 ; j++) { 783 DELAY(100); 784 serbst = csa_readio(resp, BA0_SERBST); 785 if ((serbst & SERBST_WBSY) == 0) 786 break; 787 } 788 if ((serbst & SERBST_WBSY) != 0) { 789 if (!pwr) 790 csa_writeio(resp, BA0_CLKCR1, clkcr1); 791 } 792 /* Write the serial port FIFO index. */ 793 csa_writeio(resp, BA0_SERBAD, i); 794 /* Tell the serial port to load the new value into the FIFO location. */ 795 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 796 } 797 /* 798 * Now, if we powered up the devices, then power them back down again. 799 * This is kinda ugly, but should never happen. 800 */ 801 if (!pwr) 802 csa_writeio(resp, BA0_CLKCR1, clkcr1); 803 } 804 805 void 806 csa_resetdsp(csa_res *resp) 807 { 808 int i; 809 810 /* 811 * Write the reset bit of the SP control register. 812 */ 813 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 814 815 /* 816 * Write the control register. 817 */ 818 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 819 820 /* 821 * Clear the trap registers. 822 */ 823 for (i = 0 ; i < 8 ; i++) { 824 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 825 csa_writemem(resp, BA1_TWPR, 0xffff); 826 } 827 csa_writemem(resp, BA1_DREG, 0); 828 829 /* 830 * Set the frame timer to reflect the number of cycles per frame. 831 */ 832 csa_writemem(resp, BA1_FRMT, 0xadf); 833 } 834 835 static int 836 csa_downloadimage(csa_res *resp) 837 { 838 int i; 839 u_int32_t tmp, src, dst, count, data; 840 841 for (i = 0; i < CLEAR__COUNT; i++) { 842 dst = ClrStat[i].BA1__DestByteOffset; 843 count = ClrStat[i].BA1__SourceSize; 844 for (tmp = 0; tmp < count; tmp += 4) 845 csa_writemem(resp, dst + tmp, 0x00000000); 846 } 847 848 for (i = 0; i < FILL__COUNT; i++) { 849 src = 0; 850 dst = FillStat[i].Offset; 851 count = FillStat[i].Size; 852 for (tmp = 0; tmp < count; tmp += 4) { 853 data = FillStat[i].pFill[src]; 854 csa_writemem(resp, dst + tmp, data); 855 src++; 856 } 857 } 858 859 return (0); 860 } 861 862 int 863 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 864 { 865 int i; 866 u_int32_t acsda, acctl, acsts; 867 868 /* 869 * Make sure that there is not data sitting around from a previous 870 * uncompleted access. ACSDA = Status Data Register = 47Ch 871 */ 872 acsda = csa_readio(resp, BA0_ACSDA); 873 874 /* 875 * Setup the AC97 control registers on the CS461x to send the 876 * appropriate command to the AC97 to perform the read. 877 * ACCAD = Command Address Register = 46Ch 878 * ACCDA = Command Data Register = 470h 879 * ACCTL = Control Register = 460h 880 * set DCV - will clear when process completed 881 * set CRW - Read command 882 * set VFRM - valid frame enabled 883 * set ESYN - ASYNC generation enabled 884 * set RSTN - ARST# inactive, AC97 codec not reset 885 */ 886 887 /* 888 * Get the actual AC97 register from the offset 889 */ 890 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 891 csa_writeio(resp, BA0_ACCDA, 0); 892 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 893 894 /* 895 * Wait for the read to occur. 896 */ 897 acctl = 0; 898 for (i = 0 ; i < 10 ; i++) { 899 /* 900 * First, we want to wait for a short time. 901 */ 902 DELAY(25); 903 904 /* 905 * Now, check to see if the read has completed. 906 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 907 */ 908 acctl = csa_readio(resp, BA0_ACCTL); 909 if ((acctl & ACCTL_DCV) == 0) 910 break; 911 } 912 913 /* 914 * Make sure the read completed. 915 */ 916 if ((acctl & ACCTL_DCV) != 0) 917 return (EAGAIN); 918 919 /* 920 * Wait for the valid status bit to go active. 921 */ 922 acsts = 0; 923 for (i = 0 ; i < 10 ; i++) { 924 /* 925 * Read the AC97 status register. 926 * ACSTS = Status Register = 464h 927 */ 928 acsts = csa_readio(resp, BA0_ACSTS); 929 /* 930 * See if we have valid status. 931 * VSTS - Valid Status 932 */ 933 if ((acsts & ACSTS_VSTS) != 0) 934 break; 935 /* 936 * Wait for a short while. 937 */ 938 DELAY(25); 939 } 940 941 /* 942 * Make sure we got valid status. 943 */ 944 if ((acsts & ACSTS_VSTS) == 0) 945 return (EAGAIN); 946 947 /* 948 * Read the data returned from the AC97 register. 949 * ACSDA = Status Data Register = 474h 950 */ 951 *data = csa_readio(resp, BA0_ACSDA); 952 953 return (0); 954 } 955 956 int 957 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 958 { 959 int i; 960 u_int32_t acctl; 961 962 /* 963 * Setup the AC97 control registers on the CS461x to send the 964 * appropriate command to the AC97 to perform the write. 965 * ACCAD = Command Address Register = 46Ch 966 * ACCDA = Command Data Register = 470h 967 * ACCTL = Control Register = 460h 968 * set DCV - will clear when process completed 969 * set VFRM - valid frame enabled 970 * set ESYN - ASYNC generation enabled 971 * set RSTN - ARST# inactive, AC97 codec not reset 972 */ 973 974 /* 975 * Get the actual AC97 register from the offset 976 */ 977 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 978 csa_writeio(resp, BA0_ACCDA, data); 979 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 980 981 /* 982 * Wait for the write to occur. 983 */ 984 acctl = 0; 985 for (i = 0 ; i < 10 ; i++) { 986 /* 987 * First, we want to wait for a short time. 988 */ 989 DELAY(25); 990 991 /* 992 * Now, check to see if the read has completed. 993 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 994 */ 995 acctl = csa_readio(resp, BA0_ACCTL); 996 if ((acctl & ACCTL_DCV) == 0) 997 break; 998 } 999 1000 /* 1001 * Make sure the write completed. 1002 */ 1003 if ((acctl & ACCTL_DCV) != 0) 1004 return (EAGAIN); 1005 1006 return (0); 1007 } 1008 1009 u_int32_t 1010 csa_readio(csa_res *resp, u_long offset) 1011 { 1012 u_int32_t ul; 1013 1014 if (offset < BA0_AC97_RESET) 1015 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1016 else { 1017 if (csa_readcodec(resp, offset, &ul)) 1018 ul = 0; 1019 return (ul); 1020 } 1021 } 1022 1023 void 1024 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1025 { 1026 if (offset < BA0_AC97_RESET) 1027 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1028 else 1029 csa_writecodec(resp, offset, data); 1030 } 1031 1032 u_int32_t 1033 csa_readmem(csa_res *resp, u_long offset) 1034 { 1035 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1036 } 1037 1038 void 1039 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1040 { 1041 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1042 } 1043 1044 static device_method_t csa_methods[] = { 1045 /* Device interface */ 1046 DEVMETHOD(device_probe, csa_probe), 1047 DEVMETHOD(device_attach, csa_attach), 1048 DEVMETHOD(device_detach, csa_detach), 1049 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1050 DEVMETHOD(device_suspend, bus_generic_suspend), 1051 DEVMETHOD(device_resume, csa_resume), 1052 1053 /* Bus interface */ 1054 DEVMETHOD(bus_print_child, bus_generic_print_child), 1055 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1056 DEVMETHOD(bus_release_resource, csa_release_resource), 1057 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1058 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1059 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1060 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1061 1062 { 0, 0 } 1063 }; 1064 1065 static driver_t csa_driver = { 1066 "csa", 1067 csa_methods, 1068 sizeof(struct csa_softc), 1069 }; 1070 1071 /* 1072 * csa can be attached to a pci bus. 1073 */ 1074 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1075 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1076 MODULE_VERSION(snd_csa, 1);
Cache object: 2a7606af881df0dd488d87c2a36a8a1e
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