Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/csareg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on hwdefs.h in cwcealdr1.zip, the 6 * sample source by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _CSA_REG_H 34 #define _CSA_REG_H 35 36 /* 37 * The following constats are orginally in the sample by Crystal Semiconductor. 38 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 39 */ 40 41 /***************************************************************************** 42 * 43 * The following define the offsets of the registers accessed via base address 44 * register zero on the CS461x part. 45 * 46 *****************************************************************************/ 47 #define BA0_HISR 0x00000000L 48 #define BA0_HSR0 0x00000004L 49 #define BA0_HICR 0x00000008L 50 #define BA0_DMSR 0x00000100L 51 #define BA0_HSAR 0x00000110L 52 #define BA0_HDAR 0x00000114L 53 #define BA0_HDMR 0x00000118L 54 #define BA0_HDCR 0x0000011CL 55 #define BA0_PFMC 0x00000200L 56 #define BA0_PFCV1 0x00000204L 57 #define BA0_PFCV2 0x00000208L 58 #define BA0_PCICFG00 0x00000300L 59 #define BA0_PCICFG04 0x00000304L 60 #define BA0_PCICFG08 0x00000308L 61 #define BA0_PCICFG0C 0x0000030CL 62 #define BA0_PCICFG10 0x00000310L 63 #define BA0_PCICFG14 0x00000314L 64 #define BA0_PCICFG18 0x00000318L 65 #define BA0_PCICFG1C 0x0000031CL 66 #define BA0_PCICFG20 0x00000320L 67 #define BA0_PCICFG24 0x00000324L 68 #define BA0_PCICFG28 0x00000328L 69 #define BA0_PCICFG2C 0x0000032CL 70 #define BA0_PCICFG30 0x00000330L 71 #define BA0_PCICFG34 0x00000334L 72 #define BA0_PCICFG38 0x00000338L 73 #define BA0_PCICFG3C 0x0000033CL 74 #define BA0_CLKCR1 0x00000400L 75 #define BA0_CLKCR2 0x00000404L 76 #define BA0_PLLM 0x00000408L 77 #define BA0_PLLCC 0x0000040CL 78 #define BA0_FRR 0x00000410L 79 #define BA0_CFL1 0x00000414L 80 #define BA0_CFL2 0x00000418L 81 #define BA0_SERMC1 0x00000420L 82 #define BA0_SERMC2 0x00000424L 83 #define BA0_SERC1 0x00000428L 84 #define BA0_SERC2 0x0000042CL 85 #define BA0_SERC3 0x00000430L 86 #define BA0_SERC4 0x00000434L 87 #define BA0_SERC5 0x00000438L 88 #define BA0_SERBSP 0x0000043CL 89 #define BA0_SERBST 0x00000440L 90 #define BA0_SERBCM 0x00000444L 91 #define BA0_SERBAD 0x00000448L 92 #define BA0_SERBCF 0x0000044CL 93 #define BA0_SERBWP 0x00000450L 94 #define BA0_SERBRP 0x00000454L 95 #ifndef NO_CS4612 96 #define BA0_ASER_FADDR 0x00000458L 97 #endif 98 #define BA0_ACCTL 0x00000460L 99 #define BA0_ACSTS 0x00000464L 100 #define BA0_ACOSV 0x00000468L 101 #define BA0_ACCAD 0x0000046CL 102 #define BA0_ACCDA 0x00000470L 103 #define BA0_ACISV 0x00000474L 104 #define BA0_ACSAD 0x00000478L 105 #define BA0_ACSDA 0x0000047CL 106 #define BA0_JSPT 0x00000480L 107 #define BA0_JSCTL 0x00000484L 108 #define BA0_JSC1 0x00000488L 109 #define BA0_JSC2 0x0000048CL 110 #define BA0_MIDCR 0x00000490L 111 #define BA0_MIDSR 0x00000494L 112 #define BA0_MIDWP 0x00000498L 113 #define BA0_MIDRP 0x0000049CL 114 #define BA0_JSIO 0x000004A0L 115 #ifndef NO_CS4612 116 #define BA0_ASER_MASTER 0x000004A4L 117 #endif 118 #define BA0_CFGI 0x000004B0L 119 #define BA0_SSVID 0x000004B4L 120 #define BA0_GPIOR 0x000004B8L 121 #ifndef NO_CS4612 122 #define BA0_EGPIODR 0x000004BCL 123 #define BA0_EGPIOPTR 0x000004C0L 124 #define BA0_EGPIOTR 0x000004C4L 125 #define BA0_EGPIOWR 0x000004C8L 126 #define BA0_EGPIOSR 0x000004CCL 127 #define BA0_SERC6 0x000004D0L 128 #define BA0_SERC7 0x000004D4L 129 #define BA0_SERACC 0x000004D8L 130 #define BA0_ACCTL2 0x000004E0L 131 #define BA0_ACSTS2 0x000004E4L 132 #define BA0_ACOSV2 0x000004E8L 133 #define BA0_ACCAD2 0x000004ECL 134 #define BA0_ACCDA2 0x000004F0L 135 #define BA0_ACISV2 0x000004F4L 136 #define BA0_ACSAD2 0x000004F8L 137 #define BA0_ACSDA2 0x000004FCL 138 #define BA0_IOTAC0 0x00000500L 139 #define BA0_IOTAC1 0x00000504L 140 #define BA0_IOTAC2 0x00000508L 141 #define BA0_IOTAC3 0x0000050CL 142 #define BA0_IOTAC4 0x00000510L 143 #define BA0_IOTAC5 0x00000514L 144 #define BA0_IOTAC6 0x00000518L 145 #define BA0_IOTAC7 0x0000051CL 146 #define BA0_IOTAC8 0x00000520L 147 #define BA0_IOTAC9 0x00000524L 148 #define BA0_IOTAC10 0x00000528L 149 #define BA0_IOTAC11 0x0000052CL 150 #define BA0_IOTFR0 0x00000540L 151 #define BA0_IOTFR1 0x00000544L 152 #define BA0_IOTFR2 0x00000548L 153 #define BA0_IOTFR3 0x0000054CL 154 #define BA0_IOTFR4 0x00000550L 155 #define BA0_IOTFR5 0x00000554L 156 #define BA0_IOTFR6 0x00000558L 157 #define BA0_IOTFR7 0x0000055CL 158 #define BA0_IOTFIFO 0x00000580L 159 #define BA0_IOTRRD 0x00000584L 160 #define BA0_IOTFP 0x00000588L 161 #define BA0_IOTCR 0x0000058CL 162 #define BA0_DPCID 0x00000590L 163 #define BA0_DPCIA 0x00000594L 164 #define BA0_DPCIC 0x00000598L 165 #define BA0_PCPCIR 0x00000600L 166 #define BA0_PCPCIG 0x00000604L 167 #define BA0_PCPCIEN 0x00000608L 168 #define BA0_EPCIPMC 0x00000610L 169 #endif 170 171 /***************************************************************************** 172 * 173 * The following define the offsets of the AC97 shadow registers, which appear 174 * as a virtual extension to the base address register zero memory range. 175 * 176 *****************************************************************************/ 177 #define BA0_AC97_RESET 0x00001000L 178 #define BA0_AC97_MASTER_VOLUME 0x00001002L 179 #define BA0_AC97_HEADPHONE_VOLUME 0x00001004L 180 #define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L 181 #define BA0_AC97_MASTER_TONE 0x00001008L 182 #define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL 183 #define BA0_AC97_PHONE_VOLUME 0x0000100CL 184 #define BA0_AC97_MIC_VOLUME 0x0000100EL 185 #define BA0_AC97_LINE_IN_VOLUME 0x00001010L 186 #define BA0_AC97_CD_VOLUME 0x00001012L 187 #define BA0_AC97_VIDEO_VOLUME 0x00001014L 188 #define BA0_AC97_AUX_VOLUME 0x00001016L 189 #define BA0_AC97_PCM_OUT_VOLUME 0x00001018L 190 #define BA0_AC97_RECORD_SELECT 0x0000101AL 191 #define BA0_AC97_RECORD_GAIN 0x0000101CL 192 #define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL 193 #define BA0_AC97_GENERAL_PURPOSE 0x00001020L 194 #define BA0_AC97_3D_CONTROL 0x00001022L 195 #define BA0_AC97_MODEM_RATE 0x00001024L 196 #define BA0_AC97_POWERDOWN 0x00001026L 197 #define BA0_AC97_RESERVED_28 0x00001028L 198 #define BA0_AC97_RESERVED_2A 0x0000102AL 199 #define BA0_AC97_RESERVED_2C 0x0000102CL 200 #define BA0_AC97_RESERVED_2E 0x0000102EL 201 #define BA0_AC97_RESERVED_30 0x00001030L 202 #define BA0_AC97_RESERVED_32 0x00001032L 203 #define BA0_AC97_RESERVED_34 0x00001034L 204 #define BA0_AC97_RESERVED_36 0x00001036L 205 #define BA0_AC97_RESERVED_38 0x00001038L 206 #define BA0_AC97_RESERVED_3A 0x0000103AL 207 #define BA0_AC97_RESERVED_3C 0x0000103CL 208 #define BA0_AC97_RESERVED_3E 0x0000103EL 209 #define BA0_AC97_RESERVED_40 0x00001040L 210 #define BA0_AC97_RESERVED_42 0x00001042L 211 #define BA0_AC97_RESERVED_44 0x00001044L 212 #define BA0_AC97_RESERVED_46 0x00001046L 213 #define BA0_AC97_RESERVED_48 0x00001048L 214 #define BA0_AC97_RESERVED_4A 0x0000104AL 215 #define BA0_AC97_RESERVED_4C 0x0000104CL 216 #define BA0_AC97_RESERVED_4E 0x0000104EL 217 #define BA0_AC97_RESERVED_50 0x00001050L 218 #define BA0_AC97_RESERVED_52 0x00001052L 219 #define BA0_AC97_RESERVED_54 0x00001054L 220 #define BA0_AC97_RESERVED_56 0x00001056L 221 #define BA0_AC97_RESERVED_58 0x00001058L 222 #define BA0_AC97_VENDOR_RESERVED_5A 0x0000105AL 223 #define BA0_AC97_VENDOR_RESERVED_5C 0x0000105CL 224 #define BA0_AC97_VENDOR_RESERVED_5E 0x0000105EL 225 #define BA0_AC97_VENDOR_RESERVED_60 0x00001060L 226 #define BA0_AC97_VENDOR_RESERVED_62 0x00001062L 227 #define BA0_AC97_VENDOR_RESERVED_64 0x00001064L 228 #define BA0_AC97_VENDOR_RESERVED_66 0x00001066L 229 #define BA0_AC97_VENDOR_RESERVED_68 0x00001068L 230 #define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL 231 #define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL 232 #define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL 233 #define BA0_AC97_VENDOR_RESERVED_70 0x00001070L 234 #define BA0_AC97_VENDOR_RESERVED_72 0x00001072L 235 #define BA0_AC97_VENDOR_RESERVED_74 0x00001074L 236 #define BA0_AC97_VENDOR_RESERVED_76 0x00001076L 237 #define BA0_AC97_VENDOR_RESERVED_78 0x00001078L 238 #define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL 239 #define BA0_AC97_VENDOR_ID1 0x0000107CL 240 #define BA0_AC97_VENDOR_ID2 0x0000107EL 241 242 /***************************************************************************** 243 * 244 * The following define the offsets of the registers and memories accessed via 245 * base address register one on the CS461x part. 246 * 247 *****************************************************************************/ 248 #define BA1_SP_DMEM0 0x00000000L 249 #define BA1_SP_DMEM1 0x00010000L 250 #define BA1_SP_PMEM 0x00020000L 251 #define BA1_SPCR 0x00030000L 252 #define BA1_DREG 0x00030004L 253 #define BA1_DSRWP 0x00030008L 254 #define BA1_TWPR 0x0003000CL 255 #define BA1_SPWR 0x00030010L 256 #define BA1_SPIR 0x00030014L 257 #define BA1_FGR1 0x00030020L 258 #define BA1_SPCS 0x00030028L 259 #define BA1_SDSR 0x0003002CL 260 #define BA1_FRMT 0x00030030L 261 #define BA1_FRCC 0x00030034L 262 #define BA1_FRSC 0x00030038L 263 #define BA1_OMNI_MEM 0x000E0000L 264 265 /***************************************************************************** 266 * 267 * The following defines are for the flags in the PCI interrupt register. 268 * 269 *****************************************************************************/ 270 #define PI_LINE_MASK 0x000000FFL 271 #define PI_PIN_MASK 0x0000FF00L 272 #define PI_MIN_GRANT_MASK 0x00FF0000L 273 #define PI_MAX_LATENCY_MASK 0xFF000000L 274 #define PI_LINE_SHIFT 0L 275 #define PI_PIN_SHIFT 8L 276 #define PI_MIN_GRANT_SHIFT 16L 277 #define PI_MAX_LATENCY_SHIFT 24L 278 279 /***************************************************************************** 280 * 281 * The following defines are for the flags in the host interrupt status 282 * register. 283 * 284 *****************************************************************************/ 285 #define HISR_VC_MASK 0x0000FFFFL 286 #define HISR_VC0 0x00000001L 287 #define HISR_VC1 0x00000002L 288 #define HISR_VC2 0x00000004L 289 #define HISR_VC3 0x00000008L 290 #define HISR_VC4 0x00000010L 291 #define HISR_VC5 0x00000020L 292 #define HISR_VC6 0x00000040L 293 #define HISR_VC7 0x00000080L 294 #define HISR_VC8 0x00000100L 295 #define HISR_VC9 0x00000200L 296 #define HISR_VC10 0x00000400L 297 #define HISR_VC11 0x00000800L 298 #define HISR_VC12 0x00001000L 299 #define HISR_VC13 0x00002000L 300 #define HISR_VC14 0x00004000L 301 #define HISR_VC15 0x00008000L 302 #define HISR_INT0 0x00010000L 303 #define HISR_INT1 0x00020000L 304 #define HISR_DMAI 0x00040000L 305 #define HISR_FROVR 0x00080000L 306 #define HISR_MIDI 0x00100000L 307 #ifdef NO_CS4612 308 #define HISR_RESERVED 0x0FE00000L 309 #else 310 #define HISR_SBINT 0x00200000L 311 #define HISR_RESERVED 0x0FC00000L 312 #endif 313 #define HISR_H0P 0x40000000L 314 #define HISR_INTENA 0x80000000L 315 316 /***************************************************************************** 317 * 318 * The following defines are for the flags in the host signal register 0. 319 * 320 *****************************************************************************/ 321 #define HSR0_VC_MASK 0xFFFFFFFFL 322 #define HSR0_VC16 0x00000001L 323 #define HSR0_VC17 0x00000002L 324 #define HSR0_VC18 0x00000004L 325 #define HSR0_VC19 0x00000008L 326 #define HSR0_VC20 0x00000010L 327 #define HSR0_VC21 0x00000020L 328 #define HSR0_VC22 0x00000040L 329 #define HSR0_VC23 0x00000080L 330 #define HSR0_VC24 0x00000100L 331 #define HSR0_VC25 0x00000200L 332 #define HSR0_VC26 0x00000400L 333 #define HSR0_VC27 0x00000800L 334 #define HSR0_VC28 0x00001000L 335 #define HSR0_VC29 0x00002000L 336 #define HSR0_VC30 0x00004000L 337 #define HSR0_VC31 0x00008000L 338 #define HSR0_VC32 0x00010000L 339 #define HSR0_VC33 0x00020000L 340 #define HSR0_VC34 0x00040000L 341 #define HSR0_VC35 0x00080000L 342 #define HSR0_VC36 0x00100000L 343 #define HSR0_VC37 0x00200000L 344 #define HSR0_VC38 0x00400000L 345 #define HSR0_VC39 0x00800000L 346 #define HSR0_VC40 0x01000000L 347 #define HSR0_VC41 0x02000000L 348 #define HSR0_VC42 0x04000000L 349 #define HSR0_VC43 0x08000000L 350 #define HSR0_VC44 0x10000000L 351 #define HSR0_VC45 0x20000000L 352 #define HSR0_VC46 0x40000000L 353 #define HSR0_VC47 0x80000000L 354 355 /***************************************************************************** 356 * 357 * The following defines are for the flags in the host interrupt control 358 * register. 359 * 360 *****************************************************************************/ 361 #define HICR_IEV 0x00000001L 362 #define HICR_CHGM 0x00000002L 363 364 /***************************************************************************** 365 * 366 * The following defines are for the flags in the DMA status register. 367 * 368 *****************************************************************************/ 369 #define DMSR_HP 0x00000001L 370 #define DMSR_HR 0x00000002L 371 #define DMSR_SP 0x00000004L 372 #define DMSR_SR 0x00000008L 373 374 /***************************************************************************** 375 * 376 * The following defines are for the flags in the host DMA source address 377 * register. 378 * 379 *****************************************************************************/ 380 #define HSAR_HOST_ADDR_MASK 0xFFFFFFFFL 381 #define HSAR_DSP_ADDR_MASK 0x0000FFFFL 382 #define HSAR_MEMID_MASK 0x000F0000L 383 #define HSAR_MEMID_SP_DMEM0 0x00000000L 384 #define HSAR_MEMID_SP_DMEM1 0x00010000L 385 #define HSAR_MEMID_SP_PMEM 0x00020000L 386 #define HSAR_MEMID_SP_DEBUG 0x00030000L 387 #define HSAR_MEMID_OMNI_MEM 0x000E0000L 388 #define HSAR_END 0x40000000L 389 #define HSAR_ERR 0x80000000L 390 391 /***************************************************************************** 392 * 393 * The following defines are for the flags in the host DMA destination address 394 * register. 395 * 396 *****************************************************************************/ 397 #define HDAR_HOST_ADDR_MASK 0xFFFFFFFFL 398 #define HDAR_DSP_ADDR_MASK 0x0000FFFFL 399 #define HDAR_MEMID_MASK 0x000F0000L 400 #define HDAR_MEMID_SP_DMEM0 0x00000000L 401 #define HDAR_MEMID_SP_DMEM1 0x00010000L 402 #define HDAR_MEMID_SP_PMEM 0x00020000L 403 #define HDAR_MEMID_SP_DEBUG 0x00030000L 404 #define HDAR_MEMID_OMNI_MEM 0x000E0000L 405 #define HDAR_END 0x40000000L 406 #define HDAR_ERR 0x80000000L 407 408 /***************************************************************************** 409 * 410 * The following defines are for the flags in the host DMA control register. 411 * 412 *****************************************************************************/ 413 #define HDMR_AC_MASK 0x0000F000L 414 #define HDMR_AC_8_16 0x00001000L 415 #define HDMR_AC_M_S 0x00002000L 416 #define HDMR_AC_B_L 0x00004000L 417 #define HDMR_AC_S_U 0x00008000L 418 419 /***************************************************************************** 420 * 421 * The following defines are for the flags in the host DMA control register. 422 * 423 *****************************************************************************/ 424 #define HDCR_COUNT_MASK 0x000003FFL 425 #define HDCR_DONE 0x00004000L 426 #define HDCR_OPT 0x00008000L 427 #define HDCR_WBD 0x00400000L 428 #define HDCR_WBS 0x00800000L 429 #define HDCR_DMS_MASK 0x07000000L 430 #define HDCR_DMS_LINEAR 0x00000000L 431 #define HDCR_DMS_16_DWORDS 0x01000000L 432 #define HDCR_DMS_32_DWORDS 0x02000000L 433 #define HDCR_DMS_64_DWORDS 0x03000000L 434 #define HDCR_DMS_128_DWORDS 0x04000000L 435 #define HDCR_DMS_256_DWORDS 0x05000000L 436 #define HDCR_DMS_512_DWORDS 0x06000000L 437 #define HDCR_DMS_1024_DWORDS 0x07000000L 438 #define HDCR_DH 0x08000000L 439 #define HDCR_SMS_MASK 0x70000000L 440 #define HDCR_SMS_LINEAR 0x00000000L 441 #define HDCR_SMS_16_DWORDS 0x10000000L 442 #define HDCR_SMS_32_DWORDS 0x20000000L 443 #define HDCR_SMS_64_DWORDS 0x30000000L 444 #define HDCR_SMS_128_DWORDS 0x40000000L 445 #define HDCR_SMS_256_DWORDS 0x50000000L 446 #define HDCR_SMS_512_DWORDS 0x60000000L 447 #define HDCR_SMS_1024_DWORDS 0x70000000L 448 #define HDCR_SH 0x80000000L 449 #define HDCR_COUNT_SHIFT 0L 450 451 /***************************************************************************** 452 * 453 * The following defines are for the flags in the performance monitor control 454 * register. 455 * 456 *****************************************************************************/ 457 #define PFMC_C1SS_MASK 0x0000001FL 458 #define PFMC_C1EV 0x00000020L 459 #define PFMC_C1RS 0x00008000L 460 #define PFMC_C2SS_MASK 0x001F0000L 461 #define PFMC_C2EV 0x00200000L 462 #define PFMC_C2RS 0x80000000L 463 #define PFMC_C1SS_SHIFT 0L 464 #define PFMC_C2SS_SHIFT 16L 465 #define PFMC_BUS_GRANT 0L 466 #define PFMC_GRANT_AFTER_REQ 1L 467 #define PFMC_TRANSACTION 2L 468 #define PFMC_DWORD_TRANSFER 3L 469 #define PFMC_SLAVE_READ 4L 470 #define PFMC_SLAVE_WRITE 5L 471 #define PFMC_PREEMPTION 6L 472 #define PFMC_DISCONNECT_RETRY 7L 473 #define PFMC_INTERRUPT 8L 474 #define PFMC_BUS_OWNERSHIP 9L 475 #define PFMC_TRANSACTION_LAG 10L 476 #define PFMC_PCI_CLOCK 11L 477 #define PFMC_SERIAL_CLOCK 12L 478 #define PFMC_SP_CLOCK 13L 479 480 /***************************************************************************** 481 * 482 * The following defines are for the flags in the performance counter value 1 483 * register. 484 * 485 *****************************************************************************/ 486 #define PFCV1_PC1V_MASK 0xFFFFFFFFL 487 #define PFCV1_PC1V_SHIFT 0L 488 489 /***************************************************************************** 490 * 491 * The following defines are for the flags in the performance counter value 2 492 * register. 493 * 494 *****************************************************************************/ 495 #define PFCV2_PC2V_MASK 0xFFFFFFFFL 496 #define PFCV2_PC2V_SHIFT 0L 497 498 /***************************************************************************** 499 * 500 * The following defines are for the flags in the clock control register 1. 501 * 502 *****************************************************************************/ 503 #define CLKCR1_OSCS 0x00000001L 504 #define CLKCR1_OSCP 0x00000002L 505 #define CLKCR1_PLLSS_MASK 0x0000000CL 506 #define CLKCR1_PLLSS_SERIAL 0x00000000L 507 #define CLKCR1_PLLSS_CRYSTAL 0x00000004L 508 #define CLKCR1_PLLSS_PCI 0x00000008L 509 #define CLKCR1_PLLSS_RESERVED 0x0000000CL 510 #define CLKCR1_PLLP 0x00000010L 511 #define CLKCR1_SWCE 0x00000020L 512 #define CLKCR1_PLLOS 0x00000040L 513 514 /***************************************************************************** 515 * 516 * The following defines are for the flags in the clock control register 2. 517 * 518 *****************************************************************************/ 519 #define CLKCR2_PDIVS_MASK 0x0000000FL 520 #define CLKCR2_PDIVS_1 0x00000001L 521 #define CLKCR2_PDIVS_2 0x00000002L 522 #define CLKCR2_PDIVS_4 0x00000004L 523 #define CLKCR2_PDIVS_7 0x00000007L 524 #define CLKCR2_PDIVS_8 0x00000008L 525 #define CLKCR2_PDIVS_16 0x00000000L 526 527 /***************************************************************************** 528 * 529 * The following defines are for the flags in the PLL multiplier register. 530 * 531 *****************************************************************************/ 532 #define PLLM_MASK 0x000000FFL 533 #define PLLM_SHIFT 0L 534 535 /***************************************************************************** 536 * 537 * The following defines are for the flags in the PLL capacitor coefficient 538 * register. 539 * 540 *****************************************************************************/ 541 #define PLLCC_CDR_MASK 0x00000007L 542 #ifndef NO_CS4610 543 #define PLLCC_CDR_240_350_MHZ 0x00000000L 544 #define PLLCC_CDR_184_265_MHZ 0x00000001L 545 #define PLLCC_CDR_144_205_MHZ 0x00000002L 546 #define PLLCC_CDR_111_160_MHZ 0x00000003L 547 #define PLLCC_CDR_87_123_MHZ 0x00000004L 548 #define PLLCC_CDR_67_96_MHZ 0x00000005L 549 #define PLLCC_CDR_52_74_MHZ 0x00000006L 550 #define PLLCC_CDR_45_58_MHZ 0x00000007L 551 #endif 552 #ifndef NO_CS4612 553 #define PLLCC_CDR_271_398_MHZ 0x00000000L 554 #define PLLCC_CDR_227_330_MHZ 0x00000001L 555 #define PLLCC_CDR_167_239_MHZ 0x00000002L 556 #define PLLCC_CDR_150_215_MHZ 0x00000003L 557 #define PLLCC_CDR_107_154_MHZ 0x00000004L 558 #define PLLCC_CDR_98_140_MHZ 0x00000005L 559 #define PLLCC_CDR_73_104_MHZ 0x00000006L 560 #define PLLCC_CDR_63_90_MHZ 0x00000007L 561 #endif 562 #define PLLCC_LPF_MASK 0x000000F8L 563 #ifndef NO_CS4610 564 #define PLLCC_LPF_23850_60000_KHZ 0x00000000L 565 #define PLLCC_LPF_7960_26290_KHZ 0x00000008L 566 #define PLLCC_LPF_4160_10980_KHZ 0x00000018L 567 #define PLLCC_LPF_1740_4580_KHZ 0x00000038L 568 #define PLLCC_LPF_724_1910_KHZ 0x00000078L 569 #define PLLCC_LPF_317_798_KHZ 0x000000F8L 570 #endif 571 #ifndef NO_CS4612 572 #define PLLCC_LPF_25580_64530_KHZ 0x00000000L 573 #define PLLCC_LPF_14360_37270_KHZ 0x00000008L 574 #define PLLCC_LPF_6100_16020_KHZ 0x00000018L 575 #define PLLCC_LPF_2540_6690_KHZ 0x00000038L 576 #define PLLCC_LPF_1050_2780_KHZ 0x00000078L 577 #define PLLCC_LPF_450_1160_KHZ 0x000000F8L 578 #endif 579 580 /***************************************************************************** 581 * 582 * The following defines are for the flags in the feature reporting register. 583 * 584 *****************************************************************************/ 585 #define FRR_FAB_MASK 0x00000003L 586 #define FRR_MASK_MASK 0x0000001CL 587 #ifdef NO_CS4612 588 #define FRR_CFOP_MASK 0x000000E0L 589 #else 590 #define FRR_CFOP_MASK 0x00000FE0L 591 #endif 592 #define FRR_CFOP_NOT_DVD 0x00000020L 593 #define FRR_CFOP_A3D 0x00000040L 594 #define FRR_CFOP_128_PIN 0x00000080L 595 #ifndef NO_CS4612 596 #define FRR_CFOP_CS4280 0x00000800L 597 #endif 598 #define FRR_FAB_SHIFT 0L 599 #define FRR_MASK_SHIFT 2L 600 #define FRR_CFOP_SHIFT 5L 601 602 /***************************************************************************** 603 * 604 * The following defines are for the flags in the configuration load 1 605 * register. 606 * 607 *****************************************************************************/ 608 #define CFL1_CLOCK_SOURCE_MASK 0x00000003L 609 #define CFL1_CLOCK_SOURCE_CS423X 0x00000000L 610 #define CFL1_CLOCK_SOURCE_AC97 0x00000001L 611 #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002L 612 #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003L 613 #define CFL1_VALID_DATA_MASK 0x000000FFL 614 615 /***************************************************************************** 616 * 617 * The following defines are for the flags in the configuration load 2 618 * register. 619 * 620 *****************************************************************************/ 621 #define CFL2_VALID_DATA_MASK 0x000000FFL 622 623 /***************************************************************************** 624 * 625 * The following defines are for the flags in the serial port master control 626 * register 1. 627 * 628 *****************************************************************************/ 629 #define SERMC1_MSPE 0x00000001L 630 #define SERMC1_PTC_MASK 0x0000000EL 631 #define SERMC1_PTC_CS423X 0x00000000L 632 #define SERMC1_PTC_AC97 0x00000002L 633 #define SERMC1_PTC_DAC 0x00000004L 634 #define SERMC1_PLB 0x00000010L 635 #define SERMC1_XLB 0x00000020L 636 637 /***************************************************************************** 638 * 639 * The following defines are for the flags in the serial port master control 640 * register 2. 641 * 642 *****************************************************************************/ 643 #define SERMC2_LROE 0x00000001L 644 #define SERMC2_MCOE 0x00000002L 645 #define SERMC2_MCDIV 0x00000004L 646 647 /***************************************************************************** 648 * 649 * The following defines are for the flags in the serial port 1 configuration 650 * register. 651 * 652 *****************************************************************************/ 653 #define SERC1_SO1EN 0x00000001L 654 #define SERC1_SO1F_MASK 0x0000000EL 655 #define SERC1_SO1F_CS423X 0x00000000L 656 #define SERC1_SO1F_AC97 0x00000002L 657 #define SERC1_SO1F_DAC 0x00000004L 658 #define SERC1_SO1F_SPDIF 0x00000006L 659 660 /***************************************************************************** 661 * 662 * The following defines are for the flags in the serial port 2 configuration 663 * register. 664 * 665 *****************************************************************************/ 666 #define SERC2_SI1EN 0x00000001L 667 #define SERC2_SI1F_MASK 0x0000000EL 668 #define SERC2_SI1F_CS423X 0x00000000L 669 #define SERC2_SI1F_AC97 0x00000002L 670 #define SERC2_SI1F_ADC 0x00000004L 671 #define SERC2_SI1F_SPDIF 0x00000006L 672 673 /***************************************************************************** 674 * 675 * The following defines are for the flags in the serial port 3 configuration 676 * register. 677 * 678 *****************************************************************************/ 679 #define SERC3_SO2EN 0x00000001L 680 #define SERC3_SO2F_MASK 0x00000006L 681 #define SERC3_SO2F_DAC 0x00000000L 682 #define SERC3_SO2F_SPDIF 0x00000002L 683 684 /***************************************************************************** 685 * 686 * The following defines are for the flags in the serial port 4 configuration 687 * register. 688 * 689 *****************************************************************************/ 690 #define SERC4_SO3EN 0x00000001L 691 #define SERC4_SO3F_MASK 0x00000006L 692 #define SERC4_SO3F_DAC 0x00000000L 693 #define SERC4_SO3F_SPDIF 0x00000002L 694 695 /***************************************************************************** 696 * 697 * The following defines are for the flags in the serial port 5 configuration 698 * register. 699 * 700 *****************************************************************************/ 701 #define SERC5_SI2EN 0x00000001L 702 #define SERC5_SI2F_MASK 0x00000006L 703 #define SERC5_SI2F_ADC 0x00000000L 704 #define SERC5_SI2F_SPDIF 0x00000002L 705 706 /***************************************************************************** 707 * 708 * The following defines are for the flags in the serial port backdoor sample 709 * pointer register. 710 * 711 *****************************************************************************/ 712 #define SERBSP_FSP_MASK 0x0000000FL 713 #define SERBSP_FSP_SHIFT 0L 714 715 /***************************************************************************** 716 * 717 * The following defines are for the flags in the serial port backdoor status 718 * register. 719 * 720 *****************************************************************************/ 721 #define SERBST_RRDY 0x00000001L 722 #define SERBST_WBSY 0x00000002L 723 724 /***************************************************************************** 725 * 726 * The following defines are for the flags in the serial port backdoor command 727 * register. 728 * 729 *****************************************************************************/ 730 #define SERBCM_RDC 0x00000001L 731 #define SERBCM_WRC 0x00000002L 732 733 /***************************************************************************** 734 * 735 * The following defines are for the flags in the serial port backdoor address 736 * register. 737 * 738 *****************************************************************************/ 739 #ifdef NO_CS4612 740 #define SERBAD_FAD_MASK 0x000000FFL 741 #else 742 #define SERBAD_FAD_MASK 0x000001FFL 743 #endif 744 #define SERBAD_FAD_SHIFT 0L 745 746 /***************************************************************************** 747 * 748 * The following defines are for the flags in the serial port backdoor 749 * configuration register. 750 * 751 *****************************************************************************/ 752 #define SERBCF_HBP 0x00000001L 753 754 /***************************************************************************** 755 * 756 * The following defines are for the flags in the serial port backdoor write 757 * port register. 758 * 759 *****************************************************************************/ 760 #define SERBWP_FWD_MASK 0x000FFFFFL 761 #define SERBWP_FWD_SHIFT 0L 762 763 /***************************************************************************** 764 * 765 * The following defines are for the flags in the serial port backdoor read 766 * port register. 767 * 768 *****************************************************************************/ 769 #define SERBRP_FRD_MASK 0x000FFFFFL 770 #define SERBRP_FRD_SHIFT 0L 771 772 /***************************************************************************** 773 * 774 * The following defines are for the flags in the async FIFO address register. 775 * 776 *****************************************************************************/ 777 #ifndef NO_CS4612 778 #define ASER_FADDR_A1_MASK 0x000001FFL 779 #define ASER_FADDR_EN1 0x00008000L 780 #define ASER_FADDR_A2_MASK 0x01FF0000L 781 #define ASER_FADDR_EN2 0x80000000L 782 #define ASER_FADDR_A1_SHIFT 0L 783 #define ASER_FADDR_A2_SHIFT 16L 784 #endif 785 786 /***************************************************************************** 787 * 788 * The following defines are for the flags in the AC97 control register. 789 * 790 *****************************************************************************/ 791 #define ACCTL_RSTN 0x00000001L 792 #define ACCTL_ESYN 0x00000002L 793 #define ACCTL_VFRM 0x00000004L 794 #define ACCTL_DCV 0x00000008L 795 #define ACCTL_CRW 0x00000010L 796 #define ACCTL_ASYN 0x00000020L 797 #ifndef NO_CS4612 798 #define ACCTL_TC 0x00000040L 799 #endif 800 801 /***************************************************************************** 802 * 803 * The following defines are for the flags in the AC97 status register. 804 * 805 *****************************************************************************/ 806 #define ACSTS_CRDY 0x00000001L 807 #define ACSTS_VSTS 0x00000002L 808 #ifndef NO_CS4612 809 #define ACSTS_WKUP 0x00000004L 810 #endif 811 812 /***************************************************************************** 813 * 814 * The following defines are for the flags in the AC97 output slot valid 815 * register. 816 * 817 *****************************************************************************/ 818 #define ACOSV_SLV3 0x00000001L 819 #define ACOSV_SLV4 0x00000002L 820 #define ACOSV_SLV5 0x00000004L 821 #define ACOSV_SLV6 0x00000008L 822 #define ACOSV_SLV7 0x00000010L 823 #define ACOSV_SLV8 0x00000020L 824 #define ACOSV_SLV9 0x00000040L 825 #define ACOSV_SLV10 0x00000080L 826 #define ACOSV_SLV11 0x00000100L 827 #define ACOSV_SLV12 0x00000200L 828 829 /***************************************************************************** 830 * 831 * The following defines are for the flags in the AC97 command address 832 * register. 833 * 834 *****************************************************************************/ 835 #define ACCAD_CI_MASK 0x0000007FL 836 #define ACCAD_CI_SHIFT 0L 837 838 /***************************************************************************** 839 * 840 * The following defines are for the flags in the AC97 command data register. 841 * 842 *****************************************************************************/ 843 #define ACCDA_CD_MASK 0x0000FFFFL 844 #define ACCDA_CD_SHIFT 0L 845 846 /***************************************************************************** 847 * 848 * The following defines are for the flags in the AC97 input slot valid 849 * register. 850 * 851 *****************************************************************************/ 852 #define ACISV_ISV3 0x00000001L 853 #define ACISV_ISV4 0x00000002L 854 #define ACISV_ISV5 0x00000004L 855 #define ACISV_ISV6 0x00000008L 856 #define ACISV_ISV7 0x00000010L 857 #define ACISV_ISV8 0x00000020L 858 #define ACISV_ISV9 0x00000040L 859 #define ACISV_ISV10 0x00000080L 860 #define ACISV_ISV11 0x00000100L 861 #define ACISV_ISV12 0x00000200L 862 863 /***************************************************************************** 864 * 865 * The following defines are for the flags in the AC97 status address 866 * register. 867 * 868 *****************************************************************************/ 869 #define ACSAD_SI_MASK 0x0000007FL 870 #define ACSAD_SI_SHIFT 0L 871 872 /***************************************************************************** 873 * 874 * The following defines are for the flags in the AC97 status data register. 875 * 876 *****************************************************************************/ 877 #define ACSDA_SD_MASK 0x0000FFFFL 878 #define ACSDA_SD_SHIFT 0L 879 880 /***************************************************************************** 881 * 882 * The following defines are for the flags in the joystick poll/trigger 883 * register. 884 * 885 *****************************************************************************/ 886 #define JSPT_CAX 0x00000001L 887 #define JSPT_CAY 0x00000002L 888 #define JSPT_CBX 0x00000004L 889 #define JSPT_CBY 0x00000008L 890 #define JSPT_BA1 0x00000010L 891 #define JSPT_BA2 0x00000020L 892 #define JSPT_BB1 0x00000040L 893 #define JSPT_BB2 0x00000080L 894 895 /***************************************************************************** 896 * 897 * The following defines are for the flags in the joystick control register. 898 * 899 *****************************************************************************/ 900 #define JSCTL_SP_MASK 0x00000003L 901 #define JSCTL_SP_SLOW 0x00000000L 902 #define JSCTL_SP_MEDIUM_SLOW 0x00000001L 903 #define JSCTL_SP_MEDIUM_FAST 0x00000002L 904 #define JSCTL_SP_FAST 0x00000003L 905 #define JSCTL_ARE 0x00000004L 906 907 /***************************************************************************** 908 * 909 * The following defines are for the flags in the joystick coordinate pair 1 910 * readback register. 911 * 912 *****************************************************************************/ 913 #define JSC1_Y1V_MASK 0x0000FFFFL 914 #define JSC1_X1V_MASK 0xFFFF0000L 915 #define JSC1_Y1V_SHIFT 0L 916 #define JSC1_X1V_SHIFT 16L 917 918 /***************************************************************************** 919 * 920 * The following defines are for the flags in the joystick coordinate pair 2 921 * readback register. 922 * 923 *****************************************************************************/ 924 #define JSC2_Y2V_MASK 0x0000FFFFL 925 #define JSC2_X2V_MASK 0xFFFF0000L 926 #define JSC2_Y2V_SHIFT 0L 927 #define JSC2_X2V_SHIFT 16L 928 929 /***************************************************************************** 930 * 931 * The following defines are for the flags in the MIDI control register. 932 * 933 *****************************************************************************/ 934 #define MIDCR_TXE 0x00000001L 935 #define MIDCR_RXE 0x00000002L 936 #define MIDCR_RIE 0x00000004L 937 #define MIDCR_TIE 0x00000008L 938 #define MIDCR_MLB 0x00000010L 939 #define MIDCR_MRST 0x00000020L 940 941 /***************************************************************************** 942 * 943 * The following defines are for the flags in the MIDI status register. 944 * 945 *****************************************************************************/ 946 #define MIDSR_TBF 0x00000001L 947 #define MIDSR_RBE 0x00000002L 948 949 /***************************************************************************** 950 * 951 * The following defines are for the flags in the MIDI write port register. 952 * 953 *****************************************************************************/ 954 #define MIDWP_MWD_MASK 0x000000FFL 955 #define MIDWP_MWD_SHIFT 0L 956 957 /***************************************************************************** 958 * 959 * The following defines are for the flags in the MIDI read port register. 960 * 961 *****************************************************************************/ 962 #define MIDRP_MRD_MASK 0x000000FFL 963 #define MIDRP_MRD_SHIFT 0L 964 965 /***************************************************************************** 966 * 967 * The following defines are for the flags in the joystick GPIO register. 968 * 969 *****************************************************************************/ 970 #define JSIO_DAX 0x00000001L 971 #define JSIO_DAY 0x00000002L 972 #define JSIO_DBX 0x00000004L 973 #define JSIO_DBY 0x00000008L 974 #define JSIO_AXOE 0x00000010L 975 #define JSIO_AYOE 0x00000020L 976 #define JSIO_BXOE 0x00000040L 977 #define JSIO_BYOE 0x00000080L 978 979 /***************************************************************************** 980 * 981 * The following defines are for the flags in the master async/sync serial 982 * port enable register. 983 * 984 *****************************************************************************/ 985 #ifndef NO_CS4612 986 #define ASER_MASTER_ME 0x00000001L 987 #endif 988 989 /***************************************************************************** 990 * 991 * The following defines are for the flags in the configuration interface 992 * register. 993 * 994 *****************************************************************************/ 995 #define CFGI_CLK 0x00000001L 996 #define CFGI_DOUT 0x00000002L 997 #define CFGI_DIN_EEN 0x00000004L 998 #define CFGI_EELD 0x00000008L 999 1000 /***************************************************************************** 1001 * 1002 * The following defines are for the flags in the subsystem ID and vendor ID 1003 * register. 1004 * 1005 *****************************************************************************/ 1006 #define SSVID_VID_MASK 0x0000FFFFL 1007 #define SSVID_SID_MASK 0xFFFF0000L 1008 #define SSVID_VID_SHIFT 0L 1009 #define SSVID_SID_SHIFT 16L 1010 1011 /***************************************************************************** 1012 * 1013 * The following defines are for the flags in the GPIO pin interface register. 1014 * 1015 *****************************************************************************/ 1016 #define GPIOR_VOLDN 0x00000001L 1017 #define GPIOR_VOLUP 0x00000002L 1018 #define GPIOR_SI2D 0x00000004L 1019 #define GPIOR_SI2OE 0x00000008L 1020 1021 /***************************************************************************** 1022 * 1023 * The following defines are for the flags in the extended GPIO pin direction 1024 * register. 1025 * 1026 *****************************************************************************/ 1027 #ifndef NO_CS4612 1028 #define EGPIODR_GPOE0 0x00000001L 1029 #define EGPIODR_GPOE1 0x00000002L 1030 #define EGPIODR_GPOE2 0x00000004L 1031 #define EGPIODR_GPOE3 0x00000008L 1032 #define EGPIODR_GPOE4 0x00000010L 1033 #define EGPIODR_GPOE5 0x00000020L 1034 #define EGPIODR_GPOE6 0x00000040L 1035 #define EGPIODR_GPOE7 0x00000080L 1036 #define EGPIODR_GPOE8 0x00000100L 1037 #endif 1038 1039 /***************************************************************************** 1040 * 1041 * The following defines are for the flags in the extended GPIO pin polarity/ 1042 * type register. 1043 * 1044 *****************************************************************************/ 1045 #ifndef NO_CS4612 1046 #define EGPIOPTR_GPPT0 0x00000001L 1047 #define EGPIOPTR_GPPT1 0x00000002L 1048 #define EGPIOPTR_GPPT2 0x00000004L 1049 #define EGPIOPTR_GPPT3 0x00000008L 1050 #define EGPIOPTR_GPPT4 0x00000010L 1051 #define EGPIOPTR_GPPT5 0x00000020L 1052 #define EGPIOPTR_GPPT6 0x00000040L 1053 #define EGPIOPTR_GPPT7 0x00000080L 1054 #define EGPIOPTR_GPPT8 0x00000100L 1055 #endif 1056 1057 /***************************************************************************** 1058 * 1059 * The following defines are for the flags in the extended GPIO pin sticky 1060 * register. 1061 * 1062 *****************************************************************************/ 1063 #ifndef NO_CS4612 1064 #define EGPIOTR_GPS0 0x00000001L 1065 #define EGPIOTR_GPS1 0x00000002L 1066 #define EGPIOTR_GPS2 0x00000004L 1067 #define EGPIOTR_GPS3 0x00000008L 1068 #define EGPIOTR_GPS4 0x00000010L 1069 #define EGPIOTR_GPS5 0x00000020L 1070 #define EGPIOTR_GPS6 0x00000040L 1071 #define EGPIOTR_GPS7 0x00000080L 1072 #define EGPIOTR_GPS8 0x00000100L 1073 #endif 1074 1075 /***************************************************************************** 1076 * 1077 * The following defines are for the flags in the extended GPIO ping wakeup 1078 * register. 1079 * 1080 *****************************************************************************/ 1081 #ifndef NO_CS4612 1082 #define EGPIOWR_GPW0 0x00000001L 1083 #define EGPIOWR_GPW1 0x00000002L 1084 #define EGPIOWR_GPW2 0x00000004L 1085 #define EGPIOWR_GPW3 0x00000008L 1086 #define EGPIOWR_GPW4 0x00000010L 1087 #define EGPIOWR_GPW5 0x00000020L 1088 #define EGPIOWR_GPW6 0x00000040L 1089 #define EGPIOWR_GPW7 0x00000080L 1090 #define EGPIOWR_GPW8 0x00000100L 1091 #endif 1092 1093 /***************************************************************************** 1094 * 1095 * The following defines are for the flags in the extended GPIO pin status 1096 * register. 1097 * 1098 *****************************************************************************/ 1099 #ifndef NO_CS4612 1100 #define EGPIOSR_GPS0 0x00000001L 1101 #define EGPIOSR_GPS1 0x00000002L 1102 #define EGPIOSR_GPS2 0x00000004L 1103 #define EGPIOSR_GPS3 0x00000008L 1104 #define EGPIOSR_GPS4 0x00000010L 1105 #define EGPIOSR_GPS5 0x00000020L 1106 #define EGPIOSR_GPS6 0x00000040L 1107 #define EGPIOSR_GPS7 0x00000080L 1108 #define EGPIOSR_GPS8 0x00000100L 1109 #endif 1110 1111 /***************************************************************************** 1112 * 1113 * The following defines are for the flags in the serial port 6 configuration 1114 * register. 1115 * 1116 *****************************************************************************/ 1117 #ifndef NO_CS4612 1118 #define SERC6_ASDO2EN 0x00000001L 1119 #endif 1120 1121 /***************************************************************************** 1122 * 1123 * The following defines are for the flags in the serial port 7 configuration 1124 * register. 1125 * 1126 *****************************************************************************/ 1127 #ifndef NO_CS4612 1128 #define SERC7_ASDI2EN 0x00000001L 1129 #define SERC7_POSILB 0x00000002L 1130 #define SERC7_SIPOLB 0x00000004L 1131 #define SERC7_SOSILB 0x00000008L 1132 #define SERC7_SISOLB 0x00000010L 1133 #endif 1134 1135 /***************************************************************************** 1136 * 1137 * The following defines are for the flags in the serial port AC link 1138 * configuration register. 1139 * 1140 *****************************************************************************/ 1141 #ifndef NO_CS4612 1142 #define SERACC_CODEC_TYPE_MASK 0x00000001L 1143 #define SERACC_CODEC_TYPE_1_03 0x00000000L 1144 #define SERACC_CODEC_TYPE_2_0 0x00000001L 1145 #define SERACC_TWO_CODECS 0x00000002L 1146 #define SERACC_MDM 0x00000004L 1147 #define SERACC_HSP 0x00000008L 1148 #endif 1149 1150 /***************************************************************************** 1151 * 1152 * The following defines are for the flags in the AC97 control register 2. 1153 * 1154 *****************************************************************************/ 1155 #ifndef NO_CS4612 1156 #define ACCTL2_RSTN 0x00000001L 1157 #define ACCTL2_ESYN 0x00000002L 1158 #define ACCTL2_VFRM 0x00000004L 1159 #define ACCTL2_DCV 0x00000008L 1160 #define ACCTL2_CRW 0x00000010L 1161 #define ACCTL2_ASYN 0x00000020L 1162 #endif 1163 1164 /***************************************************************************** 1165 * 1166 * The following defines are for the flags in the AC97 status register 2. 1167 * 1168 *****************************************************************************/ 1169 #ifndef NO_CS4612 1170 #define ACSTS2_CRDY 0x00000001L 1171 #define ACSTS2_VSTS 0x00000002L 1172 #endif 1173 1174 /***************************************************************************** 1175 * 1176 * The following defines are for the flags in the AC97 output slot valid 1177 * register 2. 1178 * 1179 *****************************************************************************/ 1180 #ifndef NO_CS4612 1181 #define ACOSV2_SLV3 0x00000001L 1182 #define ACOSV2_SLV4 0x00000002L 1183 #define ACOSV2_SLV5 0x00000004L 1184 #define ACOSV2_SLV6 0x00000008L 1185 #define ACOSV2_SLV7 0x00000010L 1186 #define ACOSV2_SLV8 0x00000020L 1187 #define ACOSV2_SLV9 0x00000040L 1188 #define ACOSV2_SLV10 0x00000080L 1189 #define ACOSV2_SLV11 0x00000100L 1190 #define ACOSV2_SLV12 0x00000200L 1191 #endif 1192 1193 /***************************************************************************** 1194 * 1195 * The following defines are for the flags in the AC97 command address 1196 * register 2. 1197 * 1198 *****************************************************************************/ 1199 #ifndef NO_CS4612 1200 #define ACCAD2_CI_MASK 0x0000007FL 1201 #define ACCAD2_CI_SHIFT 0L 1202 #endif 1203 1204 /***************************************************************************** 1205 * 1206 * The following defines are for the flags in the AC97 command data register 1207 * 2. 1208 * 1209 *****************************************************************************/ 1210 #ifndef NO_CS4612 1211 #define ACCDA2_CD_MASK 0x0000FFFFL 1212 #define ACCDA2_CD_SHIFT 0L 1213 #endif 1214 1215 /***************************************************************************** 1216 * 1217 * The following defines are for the flags in the AC97 input slot valid 1218 * register 2. 1219 * 1220 *****************************************************************************/ 1221 #ifndef NO_CS4612 1222 #define ACISV2_ISV3 0x00000001L 1223 #define ACISV2_ISV4 0x00000002L 1224 #define ACISV2_ISV5 0x00000004L 1225 #define ACISV2_ISV6 0x00000008L 1226 #define ACISV2_ISV7 0x00000010L 1227 #define ACISV2_ISV8 0x00000020L 1228 #define ACISV2_ISV9 0x00000040L 1229 #define ACISV2_ISV10 0x00000080L 1230 #define ACISV2_ISV11 0x00000100L 1231 #define ACISV2_ISV12 0x00000200L 1232 #endif 1233 1234 /***************************************************************************** 1235 * 1236 * The following defines are for the flags in the AC97 status address 1237 * register 2. 1238 * 1239 *****************************************************************************/ 1240 #ifndef NO_CS4612 1241 #define ACSAD2_SI_MASK 0x0000007FL 1242 #define ACSAD2_SI_SHIFT 0L 1243 #endif 1244 1245 /***************************************************************************** 1246 * 1247 * The following defines are for the flags in the AC97 status data register 2. 1248 * 1249 *****************************************************************************/ 1250 #ifndef NO_CS4612 1251 #define ACSDA2_SD_MASK 0x0000FFFFL 1252 #define ACSDA2_SD_SHIFT 0L 1253 #endif 1254 1255 /***************************************************************************** 1256 * 1257 * The following defines are for the flags in the I/O trap address and control 1258 * registers (all 12). 1259 * 1260 *****************************************************************************/ 1261 #ifndef NO_CS4612 1262 #define IOTAC_SA_MASK 0x0000FFFFL 1263 #define IOTAC_MSK_MASK 0x000F0000L 1264 #define IOTAC_IODC_MASK 0x06000000L 1265 #define IOTAC_IODC_16_BIT 0x00000000L 1266 #define IOTAC_IODC_10_BIT 0x02000000L 1267 #define IOTAC_IODC_12_BIT 0x04000000L 1268 #define IOTAC_WSPI 0x08000000L 1269 #define IOTAC_RSPI 0x10000000L 1270 #define IOTAC_WSE 0x20000000L 1271 #define IOTAC_WE 0x40000000L 1272 #define IOTAC_RE 0x80000000L 1273 #define IOTAC_SA_SHIFT 0L 1274 #define IOTAC_MSK_SHIFT 16L 1275 #endif 1276 1277 /***************************************************************************** 1278 * 1279 * The following defines are for the flags in the I/O trap fast read registers 1280 * (all 8). 1281 * 1282 *****************************************************************************/ 1283 #ifndef NO_CS4612 1284 #define IOTFR_D_MASK 0x0000FFFFL 1285 #define IOTFR_A_MASK 0x000F0000L 1286 #define IOTFR_R_MASK 0x0F000000L 1287 #define IOTFR_ALL 0x40000000L 1288 #define IOTFR_VL 0x80000000L 1289 #define IOTFR_D_SHIFT 0L 1290 #define IOTFR_A_SHIFT 16L 1291 #define IOTFR_R_SHIFT 24L 1292 #endif 1293 1294 /***************************************************************************** 1295 * 1296 * The following defines are for the flags in the I/O trap FIFO register. 1297 * 1298 *****************************************************************************/ 1299 #ifndef NO_CS4612 1300 #define IOTFIFO_BA_MASK 0x00003FFFL 1301 #define IOTFIFO_S_MASK 0x00FF0000L 1302 #define IOTFIFO_OF 0x40000000L 1303 #define IOTFIFO_SPIOF 0x80000000L 1304 #define IOTFIFO_BA_SHIFT 0L 1305 #define IOTFIFO_S_SHIFT 16L 1306 #endif 1307 1308 /***************************************************************************** 1309 * 1310 * The following defines are for the flags in the I/O trap retry read data 1311 * register. 1312 * 1313 *****************************************************************************/ 1314 #ifndef NO_CS4612 1315 #define IOTRRD_D_MASK 0x0000FFFFL 1316 #define IOTRRD_RDV 0x80000000L 1317 #define IOTRRD_D_SHIFT 0L 1318 #endif 1319 1320 /***************************************************************************** 1321 * 1322 * The following defines are for the flags in the I/O trap FIFO pointer 1323 * register. 1324 * 1325 *****************************************************************************/ 1326 #ifndef NO_CS4612 1327 #define IOTFP_CA_MASK 0x00003FFFL 1328 #define IOTFP_PA_MASK 0x3FFF0000L 1329 #define IOTFP_CA_SHIFT 0L 1330 #define IOTFP_PA_SHIFT 16L 1331 #endif 1332 1333 /***************************************************************************** 1334 * 1335 * The following defines are for the flags in the I/O trap control register. 1336 * 1337 *****************************************************************************/ 1338 #ifndef NO_CS4612 1339 #define IOTCR_ITD 0x00000001L 1340 #define IOTCR_HRV 0x00000002L 1341 #define IOTCR_SRV 0x00000004L 1342 #define IOTCR_DTI 0x00000008L 1343 #define IOTCR_DFI 0x00000010L 1344 #define IOTCR_DDP 0x00000020L 1345 #define IOTCR_JTE 0x00000040L 1346 #define IOTCR_PPE 0x00000080L 1347 #endif 1348 1349 /***************************************************************************** 1350 * 1351 * The following defines are for the flags in the direct PCI data register. 1352 * 1353 *****************************************************************************/ 1354 #ifndef NO_CS4612 1355 #define DPCID_D_MASK 0xFFFFFFFFL 1356 #define DPCID_D_SHIFT 0L 1357 #endif 1358 1359 /***************************************************************************** 1360 * 1361 * The following defines are for the flags in the direct PCI address register. 1362 * 1363 *****************************************************************************/ 1364 #ifndef NO_CS4612 1365 #define DPCIA_A_MASK 0xFFFFFFFFL 1366 #define DPCIA_A_SHIFT 0L 1367 #endif 1368 1369 /***************************************************************************** 1370 * 1371 * The following defines are for the flags in the direct PCI command register. 1372 * 1373 *****************************************************************************/ 1374 #ifndef NO_CS4612 1375 #define DPCIC_C_MASK 0x0000000FL 1376 #define DPCIC_C_IOREAD 0x00000002L 1377 #define DPCIC_C_IOWRITE 0x00000003L 1378 #define DPCIC_BE_MASK 0x000000F0L 1379 #endif 1380 1381 /***************************************************************************** 1382 * 1383 * The following defines are for the flags in the PC/PCI request register. 1384 * 1385 *****************************************************************************/ 1386 #ifndef NO_CS4612 1387 #define PCPCIR_RDC_MASK 0x00000007L 1388 #define PCPCIR_C_MASK 0x00007000L 1389 #define PCPCIR_REQ 0x00008000L 1390 #define PCPCIR_RDC_SHIFT 0L 1391 #define PCPCIR_C_SHIFT 12L 1392 #endif 1393 1394 /***************************************************************************** 1395 * 1396 * The following defines are for the flags in the PC/PCI grant register. 1397 * 1398 *****************************************************************************/ 1399 #ifndef NO_CS4612 1400 #define PCPCIG_GDC_MASK 0x00000007L 1401 #define PCPCIG_VL 0x00008000L 1402 #define PCPCIG_GDC_SHIFT 0L 1403 #endif 1404 1405 /***************************************************************************** 1406 * 1407 * The following defines are for the flags in the PC/PCI master enable 1408 * register. 1409 * 1410 *****************************************************************************/ 1411 #ifndef NO_CS4612 1412 #define PCPCIEN_EN 0x00000001L 1413 #endif 1414 1415 /***************************************************************************** 1416 * 1417 * The following defines are for the flags in the extended PCI power 1418 * management control register. 1419 * 1420 *****************************************************************************/ 1421 #ifndef NO_CS4612 1422 #define EPCIPMC_GWU 0x00000001L 1423 #define EPCIPMC_FSPC 0x00000002L 1424 #endif 1425 1426 /***************************************************************************** 1427 * 1428 * The following defines are for the flags in the SP control register. 1429 * 1430 *****************************************************************************/ 1431 #define SPCR_RUN 0x00000001L 1432 #define SPCR_STPFR 0x00000002L 1433 #define SPCR_RUNFR 0x00000004L 1434 #define SPCR_TICK 0x00000008L 1435 #define SPCR_DRQEN 0x00000020L 1436 #define SPCR_RSTSP 0x00000040L 1437 #define SPCR_OREN 0x00000080L 1438 #ifndef NO_CS4612 1439 #define SPCR_PCIINT 0x00000100L 1440 #define SPCR_OINTD 0x00000200L 1441 #define SPCR_CRE 0x00008000L 1442 #endif 1443 1444 /***************************************************************************** 1445 * 1446 * The following defines are for the flags in the debug index register. 1447 * 1448 *****************************************************************************/ 1449 #define DREG_REGID_MASK 0x0000007FL 1450 #define DREG_DEBUG 0x00000080L 1451 #define DREG_RGBK_MASK 0x00000700L 1452 #define DREG_TRAP 0x00000800L 1453 #if !defined(NO_CS4612) 1454 #if !defined(NO_CS4615) 1455 #define DREG_TRAPX 0x00001000L 1456 #endif 1457 #endif 1458 #define DREG_REGID_SHIFT 0L 1459 #define DREG_RGBK_SHIFT 8L 1460 #define DREG_RGBK_REGID_MASK 0x0000077FL 1461 #define DREG_REGID_R0 0x00000010L 1462 #define DREG_REGID_R1 0x00000011L 1463 #define DREG_REGID_R2 0x00000012L 1464 #define DREG_REGID_R3 0x00000013L 1465 #define DREG_REGID_R4 0x00000014L 1466 #define DREG_REGID_R5 0x00000015L 1467 #define DREG_REGID_R6 0x00000016L 1468 #define DREG_REGID_R7 0x00000017L 1469 #define DREG_REGID_R8 0x00000018L 1470 #define DREG_REGID_R9 0x00000019L 1471 #define DREG_REGID_RA 0x0000001AL 1472 #define DREG_REGID_RB 0x0000001BL 1473 #define DREG_REGID_RC 0x0000001CL 1474 #define DREG_REGID_RD 0x0000001DL 1475 #define DREG_REGID_RE 0x0000001EL 1476 #define DREG_REGID_RF 0x0000001FL 1477 #define DREG_REGID_RA_BUS_LOW 0x00000020L 1478 #define DREG_REGID_RA_BUS_HIGH 0x00000038L 1479 #define DREG_REGID_YBUS_LOW 0x00000050L 1480 #define DREG_REGID_YBUS_HIGH 0x00000058L 1481 #define DREG_REGID_TRAP_0 0x00000100L 1482 #define DREG_REGID_TRAP_1 0x00000101L 1483 #define DREG_REGID_TRAP_2 0x00000102L 1484 #define DREG_REGID_TRAP_3 0x00000103L 1485 #define DREG_REGID_TRAP_4 0x00000104L 1486 #define DREG_REGID_TRAP_5 0x00000105L 1487 #define DREG_REGID_TRAP_6 0x00000106L 1488 #define DREG_REGID_TRAP_7 0x00000107L 1489 #define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL 1490 #define DREG_REGID_TOP_OF_STACK 0x0000010FL 1491 #if !defined(NO_CS4612) 1492 #if !defined(NO_CS4615) 1493 #define DREG_REGID_TRAP_8 0x00000110L 1494 #define DREG_REGID_TRAP_9 0x00000111L 1495 #define DREG_REGID_TRAP_10 0x00000112L 1496 #define DREG_REGID_TRAP_11 0x00000113L 1497 #define DREG_REGID_TRAP_12 0x00000114L 1498 #define DREG_REGID_TRAP_13 0x00000115L 1499 #define DREG_REGID_TRAP_14 0x00000116L 1500 #define DREG_REGID_TRAP_15 0x00000117L 1501 #define DREG_REGID_TRAP_16 0x00000118L 1502 #define DREG_REGID_TRAP_17 0x00000119L 1503 #define DREG_REGID_TRAP_18 0x0000011AL 1504 #define DREG_REGID_TRAP_19 0x0000011BL 1505 #define DREG_REGID_TRAP_20 0x0000011CL 1506 #define DREG_REGID_TRAP_21 0x0000011DL 1507 #define DREG_REGID_TRAP_22 0x0000011EL 1508 #define DREG_REGID_TRAP_23 0x0000011FL 1509 #endif 1510 #endif 1511 #define DREG_REGID_RSA0_LOW 0x00000200L 1512 #define DREG_REGID_RSA0_HIGH 0x00000201L 1513 #define DREG_REGID_RSA1_LOW 0x00000202L 1514 #define DREG_REGID_RSA1_HIGH 0x00000203L 1515 #define DREG_REGID_RSA2 0x00000204L 1516 #define DREG_REGID_RSA3 0x00000205L 1517 #define DREG_REGID_RSI0_LOW 0x00000206L 1518 #define DREG_REGID_RSI0_HIGH 0x00000207L 1519 #define DREG_REGID_RSI1 0x00000208L 1520 #define DREG_REGID_RSI2 0x00000209L 1521 #define DREG_REGID_SAGUSTATUS 0x0000020AL 1522 #define DREG_REGID_RSCONFIG01_LOW 0x0000020BL 1523 #define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL 1524 #define DREG_REGID_RSCONFIG23_LOW 0x0000020DL 1525 #define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL 1526 #define DREG_REGID_RSDMA01E 0x0000020FL 1527 #define DREG_REGID_RSDMA23E 0x00000210L 1528 #define DREG_REGID_RSD0_LOW 0x00000211L 1529 #define DREG_REGID_RSD0_HIGH 0x00000212L 1530 #define DREG_REGID_RSD1_LOW 0x00000213L 1531 #define DREG_REGID_RSD1_HIGH 0x00000214L 1532 #define DREG_REGID_RSD2_LOW 0x00000215L 1533 #define DREG_REGID_RSD2_HIGH 0x00000216L 1534 #define DREG_REGID_RSD3_LOW 0x00000217L 1535 #define DREG_REGID_RSD3_HIGH 0x00000218L 1536 #define DREG_REGID_SRAR_HIGH 0x0000021AL 1537 #define DREG_REGID_SRAR_LOW 0x0000021BL 1538 #define DREG_REGID_DMA_STATE 0x0000021CL 1539 #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL 1540 #define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL 1541 #define DREG_REGID_CPU_STATUS 0x00000300L 1542 #define DREG_REGID_MAC_MODE 0x00000301L 1543 #define DREG_REGID_STACK_AND_REPEAT 0x00000302L 1544 #define DREG_REGID_INDEX0 0x00000304L 1545 #define DREG_REGID_INDEX1 0x00000305L 1546 #define DREG_REGID_DMA_STATE_0_3 0x00000400L 1547 #define DREG_REGID_DMA_STATE_4_7 0x00000404L 1548 #define DREG_REGID_DMA_STATE_8_11 0x00000408L 1549 #define DREG_REGID_DMA_STATE_12_15 0x0000040CL 1550 #define DREG_REGID_DMA_STATE_16_19 0x00000410L 1551 #define DREG_REGID_DMA_STATE_20_23 0x00000414L 1552 #define DREG_REGID_DMA_STATE_24_27 0x00000418L 1553 #define DREG_REGID_DMA_STATE_28_31 0x0000041CL 1554 #define DREG_REGID_DMA_STATE_32_35 0x00000420L 1555 #define DREG_REGID_DMA_STATE_36_39 0x00000424L 1556 #define DREG_REGID_DMA_STATE_40_43 0x00000428L 1557 #define DREG_REGID_DMA_STATE_44_47 0x0000042CL 1558 #define DREG_REGID_DMA_STATE_48_51 0x00000430L 1559 #define DREG_REGID_DMA_STATE_52_55 0x00000434L 1560 #define DREG_REGID_DMA_STATE_56_59 0x00000438L 1561 #define DREG_REGID_DMA_STATE_60_63 0x0000043CL 1562 #define DREG_REGID_DMA_STATE_64_67 0x00000440L 1563 #define DREG_REGID_DMA_STATE_68_71 0x00000444L 1564 #define DREG_REGID_DMA_STATE_72_75 0x00000448L 1565 #define DREG_REGID_DMA_STATE_76_79 0x0000044CL 1566 #define DREG_REGID_DMA_STATE_80_83 0x00000450L 1567 #define DREG_REGID_DMA_STATE_84_87 0x00000454L 1568 #define DREG_REGID_DMA_STATE_88_91 0x00000458L 1569 #define DREG_REGID_DMA_STATE_92_95 0x0000045CL 1570 #define DREG_REGID_TRAP_SELECT 0x00000500L 1571 #define DREG_REGID_TRAP_WRITE_0 0x00000500L 1572 #define DREG_REGID_TRAP_WRITE_1 0x00000501L 1573 #define DREG_REGID_TRAP_WRITE_2 0x00000502L 1574 #define DREG_REGID_TRAP_WRITE_3 0x00000503L 1575 #define DREG_REGID_TRAP_WRITE_4 0x00000504L 1576 #define DREG_REGID_TRAP_WRITE_5 0x00000505L 1577 #define DREG_REGID_TRAP_WRITE_6 0x00000506L 1578 #define DREG_REGID_TRAP_WRITE_7 0x00000507L 1579 #if !defined(NO_CS4612) 1580 #if !defined(NO_CS4615) 1581 #define DREG_REGID_TRAP_WRITE_8 0x00000510L 1582 #define DREG_REGID_TRAP_WRITE_9 0x00000511L 1583 #define DREG_REGID_TRAP_WRITE_10 0x00000512L 1584 #define DREG_REGID_TRAP_WRITE_11 0x00000513L 1585 #define DREG_REGID_TRAP_WRITE_12 0x00000514L 1586 #define DREG_REGID_TRAP_WRITE_13 0x00000515L 1587 #define DREG_REGID_TRAP_WRITE_14 0x00000516L 1588 #define DREG_REGID_TRAP_WRITE_15 0x00000517L 1589 #define DREG_REGID_TRAP_WRITE_16 0x00000518L 1590 #define DREG_REGID_TRAP_WRITE_17 0x00000519L 1591 #define DREG_REGID_TRAP_WRITE_18 0x0000051AL 1592 #define DREG_REGID_TRAP_WRITE_19 0x0000051BL 1593 #define DREG_REGID_TRAP_WRITE_20 0x0000051CL 1594 #define DREG_REGID_TRAP_WRITE_21 0x0000051DL 1595 #define DREG_REGID_TRAP_WRITE_22 0x0000051EL 1596 #define DREG_REGID_TRAP_WRITE_23 0x0000051FL 1597 #endif 1598 #endif 1599 #define DREG_REGID_MAC0_ACC0_LOW 0x00000600L 1600 #define DREG_REGID_MAC0_ACC1_LOW 0x00000601L 1601 #define DREG_REGID_MAC0_ACC2_LOW 0x00000602L 1602 #define DREG_REGID_MAC0_ACC3_LOW 0x00000603L 1603 #define DREG_REGID_MAC1_ACC0_LOW 0x00000604L 1604 #define DREG_REGID_MAC1_ACC1_LOW 0x00000605L 1605 #define DREG_REGID_MAC1_ACC2_LOW 0x00000606L 1606 #define DREG_REGID_MAC1_ACC3_LOW 0x00000607L 1607 #define DREG_REGID_MAC0_ACC0_MID 0x00000608L 1608 #define DREG_REGID_MAC0_ACC1_MID 0x00000609L 1609 #define DREG_REGID_MAC0_ACC2_MID 0x0000060AL 1610 #define DREG_REGID_MAC0_ACC3_MID 0x0000060BL 1611 #define DREG_REGID_MAC1_ACC0_MID 0x0000060CL 1612 #define DREG_REGID_MAC1_ACC1_MID 0x0000060DL 1613 #define DREG_REGID_MAC1_ACC2_MID 0x0000060EL 1614 #define DREG_REGID_MAC1_ACC3_MID 0x0000060FL 1615 #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L 1616 #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L 1617 #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L 1618 #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L 1619 #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L 1620 #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L 1621 #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L 1622 #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L 1623 #define DREG_REGID_RSHOUT_LOW 0x00000620L 1624 #define DREG_REGID_RSHOUT_MID 0x00000628L 1625 #define DREG_REGID_RSHOUT_HIGH 0x00000630L 1626 1627 /***************************************************************************** 1628 * 1629 * The following defines are for the flags in the DMA stream requestor write 1630 * port register. 1631 * 1632 *****************************************************************************/ 1633 #define DSRWP_DSR_MASK 0x0000000FL 1634 #define DSRWP_DSR_BG_RQ 0x00000001L 1635 #define DSRWP_DSR_PRIORITY_MASK 0x00000006L 1636 #define DSRWP_DSR_PRIORITY_0 0x00000000L 1637 #define DSRWP_DSR_PRIORITY_1 0x00000002L 1638 #define DSRWP_DSR_PRIORITY_2 0x00000004L 1639 #define DSRWP_DSR_PRIORITY_3 0x00000006L 1640 #define DSRWP_DSR_RQ_PENDING 0x00000008L 1641 1642 /***************************************************************************** 1643 * 1644 * The following defines are for the flags in the trap write port register. 1645 * 1646 *****************************************************************************/ 1647 #define TWPR_TW_MASK 0x0000FFFFL 1648 #define TWPR_TW_SHIFT 0L 1649 1650 /***************************************************************************** 1651 * 1652 * The following defines are for the flags in the stack pointer write 1653 * register. 1654 * 1655 *****************************************************************************/ 1656 #define SPWR_STKP_MASK 0x0000000FL 1657 #define SPWR_STKP_SHIFT 0L 1658 1659 /***************************************************************************** 1660 * 1661 * The following defines are for the flags in the SP interrupt register. 1662 * 1663 *****************************************************************************/ 1664 #define SPIR_FRI 0x00000001L 1665 #define SPIR_DOI 0x00000002L 1666 #define SPIR_GPI2 0x00000004L 1667 #define SPIR_GPI3 0x00000008L 1668 #define SPIR_IP0 0x00000010L 1669 #define SPIR_IP1 0x00000020L 1670 #define SPIR_IP2 0x00000040L 1671 #define SPIR_IP3 0x00000080L 1672 1673 /***************************************************************************** 1674 * 1675 * The following defines are for the flags in the functional group 1 register. 1676 * 1677 *****************************************************************************/ 1678 #define FGR1_F1S_MASK 0x0000FFFFL 1679 #define FGR1_F1S_SHIFT 0L 1680 1681 /***************************************************************************** 1682 * 1683 * The following defines are for the flags in the SP clock status register. 1684 * 1685 *****************************************************************************/ 1686 #define SPCS_FRI 0x00000001L 1687 #define SPCS_DOI 0x00000002L 1688 #define SPCS_GPI2 0x00000004L 1689 #define SPCS_GPI3 0x00000008L 1690 #define SPCS_IP0 0x00000010L 1691 #define SPCS_IP1 0x00000020L 1692 #define SPCS_IP2 0x00000040L 1693 #define SPCS_IP3 0x00000080L 1694 #define SPCS_SPRUN 0x00000100L 1695 #define SPCS_SLEEP 0x00000200L 1696 #define SPCS_FG 0x00000400L 1697 #define SPCS_ORUN 0x00000800L 1698 #define SPCS_IRQ 0x00001000L 1699 #define SPCS_FGN_MASK 0x0000E000L 1700 #define SPCS_FGN_SHIFT 13L 1701 1702 /***************************************************************************** 1703 * 1704 * The following defines are for the flags in the SP DMA requestor status 1705 * register. 1706 * 1707 *****************************************************************************/ 1708 #define SDSR_DCS_MASK 0x000000FFL 1709 #define SDSR_DCS_SHIFT 0L 1710 #define SDSR_DCS_NONE 0x00000007L 1711 1712 /***************************************************************************** 1713 * 1714 * The following defines are for the flags in the frame timer register. 1715 * 1716 *****************************************************************************/ 1717 #define FRMT_FTV_MASK 0x0000FFFFL 1718 #define FRMT_FTV_SHIFT 0L 1719 1720 /***************************************************************************** 1721 * 1722 * The following defines are for the flags in the frame timer current count 1723 * register. 1724 * 1725 *****************************************************************************/ 1726 #define FRCC_FCC_MASK 0x0000FFFFL 1727 #define FRCC_FCC_SHIFT 0L 1728 1729 /***************************************************************************** 1730 * 1731 * The following defines are for the flags in the frame timer save count 1732 * register. 1733 * 1734 *****************************************************************************/ 1735 #define FRSC_FCS_MASK 0x0000FFFFL 1736 #define FRSC_FCS_SHIFT 0L 1737 1738 /***************************************************************************** 1739 * 1740 * The following define the various flags stored in the scatter/gather 1741 * descriptors. 1742 * 1743 *****************************************************************************/ 1744 #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8L 1745 #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000L 1746 #define DMA_SG_SAMPLE_END_FLAG 0x10000000L 1747 #define DMA_SG_LOOP_END_FLAG 0x20000000L 1748 #define DMA_SG_SIGNAL_END_FLAG 0x40000000L 1749 #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000L 1750 #define DMA_SG_NEXT_ENTRY_SHIFT 3L 1751 #define DMA_SG_SAMPLE_END_SHIFT 16L 1752 1753 /***************************************************************************** 1754 * 1755 * The following define the offsets of the fields within the on-chip generic 1756 * DMA requestor. 1757 * 1758 *****************************************************************************/ 1759 #define DMA_RQ_CONTROL1 0x00000000L 1760 #define DMA_RQ_CONTROL2 0x00000004L 1761 #define DMA_RQ_SOURCE_ADDR 0x00000008L 1762 #define DMA_RQ_DESTINATION_ADDR 0x0000000CL 1763 #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010L 1764 #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014L 1765 #define DMA_RQ_LOOP_START_ADDR 0x00000018L 1766 #define DMA_RQ_POST_LOOP_ADDR 0x0000001CL 1767 #define DMA_RQ_PAGE_MAP_ADDR 0x00000020L 1768 1769 /***************************************************************************** 1770 * 1771 * The following defines are for the flags in the first control word of the 1772 * on-chip generic DMA requestor. 1773 * 1774 *****************************************************************************/ 1775 #define DMA_RQ_C1_COUNT_MASK 0x000003FFL 1776 #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000L 1777 #define DMA_RQ_C1_SOURCE_GATHER 0x00002000L 1778 #define DMA_RQ_C1_DONE_FLAG 0x00004000L 1779 #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000L 1780 #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000L 1781 #define DMA_RQ_C1_FULL_PAGE 0x00000000L 1782 #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000L 1783 #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000L 1784 #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000L 1785 #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000L 1786 #define DMA_RQ_C1_NOT_LOOP_END 0x00000000L 1787 #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000L 1788 #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000L 1789 #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000L 1790 #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000L 1791 #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000L 1792 #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000L 1793 #define DMA_RQ_C1_PM_RESERVED 0x00200000L 1794 #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000L 1795 #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000L 1796 #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000L 1797 #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000L 1798 #define DMA_RQ_C1_DEST_LINEAR 0x00000000L 1799 #define DMA_RQ_C1_DEST_MOD16 0x01000000L 1800 #define DMA_RQ_C1_DEST_MOD32 0x02000000L 1801 #define DMA_RQ_C1_DEST_MOD64 0x03000000L 1802 #define DMA_RQ_C1_DEST_MOD128 0x04000000L 1803 #define DMA_RQ_C1_DEST_MOD256 0x05000000L 1804 #define DMA_RQ_C1_DEST_MOD512 0x06000000L 1805 #define DMA_RQ_C1_DEST_MOD1024 0x07000000L 1806 #define DMA_RQ_C1_DEST_ON_HOST 0x08000000L 1807 #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000L 1808 #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000L 1809 #define DMA_RQ_C1_SOURCE_MOD16 0x10000000L 1810 #define DMA_RQ_C1_SOURCE_MOD32 0x20000000L 1811 #define DMA_RQ_C1_SOURCE_MOD64 0x30000000L 1812 #define DMA_RQ_C1_SOURCE_MOD128 0x40000000L 1813 #define DMA_RQ_C1_SOURCE_MOD256 0x50000000L 1814 #define DMA_RQ_C1_SOURCE_MOD512 0x60000000L 1815 #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000L 1816 #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000L 1817 #define DMA_RQ_C1_COUNT_SHIFT 0L 1818 1819 /***************************************************************************** 1820 * 1821 * The following defines are for the flags in the second control word of the 1822 * on-chip generic DMA requestor. 1823 * 1824 *****************************************************************************/ 1825 #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003FL 1826 #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300L 1827 #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000L 1828 #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100L 1829 #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200L 1830 #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300L 1831 #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L 1832 #define DMA_RQ_C2_AC_NONE 0x00000000L 1833 #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L 1834 #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L 1835 #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L 1836 #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L 1837 #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000L 1838 #define DMA_RQ_C2_LOOP_MASK 0x30000000L 1839 #define DMA_RQ_C2_NO_LOOP 0x00000000L 1840 #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000L 1841 #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000L 1842 #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000L 1843 #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000L 1844 #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000L 1845 #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0L 1846 #define DMA_RQ_C2_LOOP_END_SHIFT 16L 1847 1848 /***************************************************************************** 1849 * 1850 * The following defines are for the flags in the source and destination words 1851 * of the on-chip generic DMA requestor. 1852 * 1853 *****************************************************************************/ 1854 #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFFL 1855 #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000L 1856 #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000L 1857 #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000L 1858 #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000L 1859 #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000L 1860 #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000L 1861 #define DMA_RQ_SD_END_FLAG 0x40000000L 1862 #define DMA_RQ_SD_ERROR_FLAG 0x80000000L 1863 #define DMA_RQ_SD_ADDRESS_SHIFT 0L 1864 1865 /***************************************************************************** 1866 * 1867 * The following defines are for the flags in the page map address word of the 1868 * on-chip generic DMA requestor. 1869 * 1870 *****************************************************************************/ 1871 #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8L 1872 #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000L 1873 #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3L 1874 #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12L 1875 1876 /***************************************************************************** 1877 * 1878 * The following defines are for the flags in the rsConfig01/23 registers of 1879 * the SP. 1880 * 1881 *****************************************************************************/ 1882 #define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL 1883 #define RSCONFIG_MODULO_16 0x00000001L 1884 #define RSCONFIG_MODULO_32 0x00000002L 1885 #define RSCONFIG_MODULO_64 0x00000003L 1886 #define RSCONFIG_MODULO_128 0x00000004L 1887 #define RSCONFIG_MODULO_256 0x00000005L 1888 #define RSCONFIG_MODULO_512 0x00000006L 1889 #define RSCONFIG_MODULO_1024 0x00000007L 1890 #define RSCONFIG_MODULO_4 0x00000008L 1891 #define RSCONFIG_MODULO_8 0x00000009L 1892 #define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L 1893 #define RSCONFIG_SAMPLE_8MONO 0x00000000L 1894 #define RSCONFIG_SAMPLE_8STEREO 0x00000040L 1895 #define RSCONFIG_SAMPLE_16MONO 0x00000080L 1896 #define RSCONFIG_SAMPLE_16STEREO 0x000000C0L 1897 #define RSCONFIG_UNDERRUN_ZERO 0x00004000L 1898 #define RSCONFIG_DMA_TO_HOST 0x00008000L 1899 #define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L 1900 #define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L 1901 #define RSCONFIG_DMA_ENABLE 0x20000000L 1902 #define RSCONFIG_PRIORITY_MASK 0xC0000000L 1903 #define RSCONFIG_PRIORITY_HIGH 0x00000000L 1904 #define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L 1905 #define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L 1906 #define RSCONFIG_PRIORITY_LOW 0xC0000000L 1907 #define RSCONFIG_STREAM_NUM_SHIFT 16L 1908 #define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L 1909 1910 #define BA1_VARIDEC_BUF_1 0x000 1911 1912 #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */ 1913 #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */ 1914 #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */ 1915 #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */ 1916 #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */ 1917 #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */ 1918 #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */ 1919 1920 #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */ 1921 #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */ 1922 #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */ 1923 #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */ 1924 #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */ 1925 #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */ 1926 #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */ 1927 #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */ 1928 1929 #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */ 1930 #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */ 1931 #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */ 1932 #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */ 1933 1934 /* PM state definitions */ 1935 #define CS461x_AC97_HIGHESTREGTORESTORE 0x26 1936 #define CS461x_AC97_NUMBER_RESTORE_REGS (CS461x_AC97_HIGHESTREGTORESTORE/2-1) 1937 1938 #define CS_POWER_DAC 0x0001 1939 #define CS_POWER_ADC 0x0002 1940 #define CS_POWER_MIXVON 0x0004 1941 #define CS_POWER_MIXVOFF 0x0008 1942 #define CS_AC97_POWER_CONTROL_ON 0xf000 /* always on bits (inverted) */ 1943 #define CS_AC97_POWER_CONTROL_ADC 0x0100 1944 #define CS_AC97_POWER_CONTROL_DAC 0x0200 1945 #define CS_AC97_POWER_CONTROL_MIXVON 0x0400 1946 #define CS_AC97_POWER_CONTROL_MIXVOFF 0x0800 1947 #define CS_AC97_POWER_CONTROL_ADC_ON 0x0001 1948 #define CS_AC97_POWER_CONTROL_DAC_ON 0x0002 1949 #define CS_AC97_POWER_CONTROL_MIXVON_ON 0x0004 1950 #define CS_AC97_POWER_CONTROL_MIXVOFF_ON 0x0008 1951 1952 /* The following struct holds the initialization array. */ 1953 1954 /* 1955 * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 for code since 1956 * each instruction is 40 bits and takes two dwords 1957 */ 1958 #define INKY_BA1_DWORD_SIZE (13 * 1024 + 512) 1959 #define INKY_MEMORY_COUNT 3 1960 1961 struct BA1struct 1962 { 1963 struct 1964 { 1965 u_long ulDestByteOffset, 1966 ulSourceByteSize; 1967 } MemoryStat[INKY_MEMORY_COUNT]; 1968 1969 u_long BA1Array[INKY_BA1_DWORD_SIZE]; 1970 }; 1971 1972 #endif /* _CSA_REG_H */
Cache object: 603d665b55ae861f965ace989e2e4570
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]