Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/ich.c
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1 /*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46 #define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */ 47 #define I6300ESBID 0x25a68086 /* 6300ESB needs to be treated as ICH4 */ 48 #define ICH6ID 0x266e8086 /* ICH6 needs to be treated as ICH4 */ 49 50 /* buffer descriptor */ 51 struct ich_desc { 52 volatile u_int32_t buffer; 53 volatile u_int32_t length; 54 }; 55 56 struct sc_info; 57 58 /* channel registers */ 59 struct sc_chinfo { 60 u_int32_t num:8, run:1, run_save:1; 61 u_int32_t blksz, blkcnt, spd; 62 u_int32_t regbase, spdreg; 63 u_int32_t imask; 64 u_int32_t civ; 65 66 struct snd_dbuf *buffer; 67 struct pcm_channel *channel; 68 struct sc_info *parent; 69 70 struct ich_desc *dtbl; 71 bus_addr_t desc_addr; 72 }; 73 74 /* device private data */ 75 struct sc_info { 76 device_t dev; 77 int hasvra, hasvrm, hasmic; 78 unsigned int chnum, bufsz; 79 int sample_size, swap_reg; 80 81 struct resource *nambar, *nabmbar, *irq; 82 int regtype, nambarid, nabmbarid, irqid; 83 bus_space_tag_t nambart, nabmbart; 84 bus_space_handle_t nambarh, nabmbarh; 85 bus_dma_tag_t dmat; 86 bus_dmamap_t dtmap; 87 void *ih; 88 89 struct ac97_info *codec; 90 struct sc_chinfo ch[3]; 91 int ac97rate; 92 struct ich_desc *dtbl; 93 bus_addr_t desc_addr; 94 struct intr_config_hook intrhook; 95 int use_intrhook; 96 }; 97 98 /* -------------------------------------------------------------------- */ 99 100 static u_int32_t ich_fmt[] = { 101 AFMT_STEREO | AFMT_S16_LE, 102 0 103 }; 104 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 105 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 106 107 /* -------------------------------------------------------------------- */ 108 /* Hardware */ 109 static u_int32_t 110 ich_rd(struct sc_info *sc, int regno, int size) 111 { 112 switch (size) { 113 case 1: 114 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 115 case 2: 116 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 117 case 4: 118 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 119 default: 120 return 0xffffffff; 121 } 122 } 123 124 static void 125 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 126 { 127 switch (size) { 128 case 1: 129 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 130 break; 131 case 2: 132 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 133 break; 134 case 4: 135 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 136 break; 137 } 138 } 139 140 /* ac97 codec */ 141 static int 142 ich_waitcd(void *devinfo) 143 { 144 int i; 145 u_int32_t data; 146 struct sc_info *sc = (struct sc_info *)devinfo; 147 148 for (i = 0; i < ICH_TIMEOUT; i++) { 149 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 150 if ((data & 0x01) == 0) 151 return 0; 152 } 153 device_printf(sc->dev, "CODEC semaphore timeout\n"); 154 return ETIMEDOUT; 155 } 156 157 static int 158 ich_rdcd(kobj_t obj, void *devinfo, int regno) 159 { 160 struct sc_info *sc = (struct sc_info *)devinfo; 161 162 regno &= 0xff; 163 ich_waitcd(sc); 164 165 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 166 } 167 168 static int 169 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 170 { 171 struct sc_info *sc = (struct sc_info *)devinfo; 172 173 regno &= 0xff; 174 ich_waitcd(sc); 175 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 176 177 return 0; 178 } 179 180 static kobj_method_t ich_ac97_methods[] = { 181 KOBJMETHOD(ac97_read, ich_rdcd), 182 KOBJMETHOD(ac97_write, ich_wrcd), 183 { 0, 0 } 184 }; 185 AC97_DECLARE(ich_ac97); 186 187 /* -------------------------------------------------------------------- */ 188 /* common routines */ 189 190 static void 191 ich_filldtbl(struct sc_chinfo *ch) 192 { 193 u_int32_t base; 194 int i; 195 196 base = sndbuf_getbufaddr(ch->buffer); 197 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 198 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 199 ch->blkcnt = 2; 200 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 201 } 202 203 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 204 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 205 ch->dtbl[i].length = ICH_BDC_IOC 206 | (ch->blksz / ch->parent->sample_size); 207 } 208 } 209 210 static int 211 ich_resetchan(struct sc_info *sc, int num) 212 { 213 int i, cr, regbase; 214 215 if (num == 0) 216 regbase = ICH_REG_PO_BASE; 217 else if (num == 1) 218 regbase = ICH_REG_PI_BASE; 219 else if (num == 2) 220 regbase = ICH_REG_MC_BASE; 221 else 222 return ENXIO; 223 224 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 225 DELAY(100); 226 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 227 for (i = 0; i < ICH_TIMEOUT; i++) { 228 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 229 if (cr == 0) 230 return 0; 231 } 232 233 device_printf(sc->dev, "cannot reset channel %d\n", num); 234 return ENXIO; 235 } 236 237 /* -------------------------------------------------------------------- */ 238 /* channel interface */ 239 240 static void * 241 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 242 { 243 struct sc_info *sc = devinfo; 244 struct sc_chinfo *ch; 245 unsigned int num; 246 247 num = sc->chnum++; 248 ch = &sc->ch[num]; 249 ch->num = num; 250 ch->buffer = b; 251 ch->channel = c; 252 ch->parent = sc; 253 ch->run = 0; 254 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 255 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 256 sizeof(struct ich_desc); 257 ch->blkcnt = 2; 258 ch->blksz = sc->bufsz / ch->blkcnt; 259 260 switch(ch->num) { 261 case 0: /* play */ 262 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 263 ch->regbase = ICH_REG_PO_BASE; 264 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 265 ch->imask = ICH_GLOB_STA_POINT; 266 break; 267 268 case 1: /* record */ 269 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 270 ch->regbase = ICH_REG_PI_BASE; 271 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 272 ch->imask = ICH_GLOB_STA_PIINT; 273 break; 274 275 case 2: /* mic */ 276 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 277 ch->regbase = ICH_REG_MC_BASE; 278 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 279 ch->imask = ICH_GLOB_STA_MINT; 280 break; 281 282 default: 283 return NULL; 284 } 285 286 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 287 return NULL; 288 289 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 290 291 return ch; 292 } 293 294 static int 295 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 296 { 297 return 0; 298 } 299 300 static int 301 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 302 { 303 struct sc_chinfo *ch = data; 304 struct sc_info *sc = ch->parent; 305 306 if (ch->spdreg) { 307 int r; 308 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 309 sc->ac97rate = 48000; 310 r = (speed * 48000) / sc->ac97rate; 311 /* 312 * Cast the return value of ac97_setrate() to u_int so that 313 * the math don't overflow into the negative range. 314 */ 315 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 316 sc->ac97rate) / 48000; 317 } else { 318 ch->spd = 48000; 319 } 320 return ch->spd; 321 } 322 323 static int 324 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 325 { 326 struct sc_chinfo *ch = data; 327 struct sc_info *sc = ch->parent; 328 329 ch->blksz = blocksize; 330 ich_filldtbl(ch); 331 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 332 333 return ch->blksz; 334 } 335 336 static int 337 ichchan_trigger(kobj_t obj, void *data, int go) 338 { 339 struct sc_chinfo *ch = data; 340 struct sc_info *sc = ch->parent; 341 342 switch (go) { 343 case PCMTRIG_START: 344 ch->run = 1; 345 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 346 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 347 break; 348 349 case PCMTRIG_ABORT: 350 ich_resetchan(sc, ch->num); 351 ch->run = 0; 352 break; 353 } 354 return 0; 355 } 356 357 static int 358 ichchan_getptr(kobj_t obj, void *data) 359 { 360 struct sc_chinfo *ch = data; 361 struct sc_info *sc = ch->parent; 362 u_int32_t pos; 363 364 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 365 366 pos = ch->civ * ch->blksz; 367 368 return pos; 369 } 370 371 static struct pcmchan_caps * 372 ichchan_getcaps(kobj_t obj, void *data) 373 { 374 struct sc_chinfo *ch = data; 375 376 return ch->spdreg? &ich_vrcaps : &ich_caps; 377 } 378 379 static kobj_method_t ichchan_methods[] = { 380 KOBJMETHOD(channel_init, ichchan_init), 381 KOBJMETHOD(channel_setformat, ichchan_setformat), 382 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 383 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 384 KOBJMETHOD(channel_trigger, ichchan_trigger), 385 KOBJMETHOD(channel_getptr, ichchan_getptr), 386 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 387 { 0, 0 } 388 }; 389 CHANNEL_DECLARE(ichchan); 390 391 /* -------------------------------------------------------------------- */ 392 /* The interrupt handler */ 393 394 static void 395 ich_intr(void *p) 396 { 397 struct sc_info *sc = (struct sc_info *)p; 398 struct sc_chinfo *ch; 399 u_int32_t cbi, lbi, lvi, st, gs; 400 int i; 401 402 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 403 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 404 /* Clear resume interrupt(s) - nothing doing with them */ 405 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 406 } 407 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 408 409 for (i = 0; i < 3; i++) { 410 ch = &sc->ch[i]; 411 if ((ch->imask & gs) == 0) 412 continue; 413 gs &= ~ch->imask; 414 st = ich_rd(sc, ch->regbase + 415 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 416 2); 417 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 418 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 419 /* block complete - update buffer */ 420 if (ch->run) 421 chn_intr(ch->channel); 422 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 423 cbi = ch->civ % ch->blkcnt; 424 if (cbi == 0) 425 cbi = ch->blkcnt - 1; 426 else 427 cbi--; 428 lbi = lvi % ch->blkcnt; 429 if (cbi >= lbi) 430 lvi += cbi - lbi; 431 else 432 lvi += cbi + ch->blkcnt - lbi; 433 lvi %= ICH_DTBL_LENGTH; 434 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 435 436 } 437 /* clear status bit */ 438 ich_wr(sc, ch->regbase + 439 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 440 st, 2); 441 } 442 if (gs != 0) { 443 device_printf(sc->dev, 444 "Unhandled interrupt, gs_intr = %x\n", gs); 445 } 446 } 447 448 /* ------------------------------------------------------------------------- */ 449 /* Sysctl to control ac97 speed (some boards appear to end up using 450 * XTAL_IN rather than BIT_CLK for link timing). 451 */ 452 453 static int 454 ich_initsys(struct sc_info* sc) 455 { 456 #ifdef SND_DYNSYSCTL 457 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 458 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 459 OID_AUTO, "ac97rate", CTLFLAG_RW, 460 &sc->ac97rate, 48000, 461 "AC97 link rate (default = 48000)"); 462 #endif /* SND_DYNSYSCTL */ 463 return 0; 464 } 465 466 /* -------------------------------------------------------------------- */ 467 /* Calibrate card to determine the clock source. The source maybe a 468 * function of the ac97 codec initialization code (to be investigated). 469 */ 470 471 static 472 void ich_calibrate(void *arg) 473 { 474 struct sc_info *sc; 475 struct sc_chinfo *ch; 476 struct timeval t1, t2; 477 u_int8_t ociv, nciv; 478 u_int32_t wait_us, actual_48k_rate, bytes; 479 480 sc = (struct sc_info *)arg; 481 ch = &sc->ch[1]; 482 483 if (sc->use_intrhook) 484 config_intrhook_disestablish(&sc->intrhook); 485 486 /* 487 * Grab audio from input for fixed interval and compare how 488 * much we actually get with what we expect. Interval needs 489 * to be sufficiently short that no interrupts are 490 * generated. 491 */ 492 493 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 494 495 bytes = sndbuf_getsize(ch->buffer) / 2; 496 ichchan_setblocksize(0, ch, bytes); 497 498 /* 499 * our data format is stereo, 16 bit so each sample is 4 bytes. 500 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 501 * we're going to start recording with interrupts disabled and measure 502 * the time taken for one block to complete. we know the block size, 503 * we know the time in microseconds, we calculate the sample rate: 504 * 505 * actual_rate [bps] = bytes / (time [s] * 4) 506 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 507 * actual_rate [Hz] = (bytes * 250000) / time [us] 508 */ 509 510 /* prepare */ 511 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 512 nciv = ociv; 513 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 514 515 /* start */ 516 microtime(&t1); 517 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 518 519 /* wait */ 520 while (nciv == ociv) { 521 microtime(&t2); 522 if (t2.tv_sec - t1.tv_sec > 1) 523 break; 524 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 525 } 526 microtime(&t2); 527 528 /* stop */ 529 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 530 531 /* reset */ 532 DELAY(100); 533 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 534 535 /* turn time delta into us */ 536 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 537 538 if (nciv == ociv) { 539 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 540 return; 541 } 542 543 actual_48k_rate = (bytes * 250000) / wait_us; 544 545 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 546 sc->ac97rate = actual_48k_rate; 547 } else { 548 sc->ac97rate = 48000; 549 } 550 551 if (bootverbose || sc->ac97rate != 48000) { 552 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 553 if (sc->ac97rate != actual_48k_rate) 554 printf(", will use %d Hz", sc->ac97rate); 555 printf("\n"); 556 } 557 558 return; 559 } 560 561 /* -------------------------------------------------------------------- */ 562 /* Probe and attach the card */ 563 564 static void 565 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 566 { 567 struct sc_info *sc = (struct sc_info *)arg; 568 sc->desc_addr = segs->ds_addr; 569 return; 570 } 571 572 static int 573 ich_init(struct sc_info *sc) 574 { 575 u_int32_t stat; 576 int sz; 577 578 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 579 DELAY(600000); 580 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 581 582 if ((stat & ICH_GLOB_STA_PCR) == 0) { 583 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 584 if ((pci_get_devid(sc->dev) != ICH4ID) && 585 (pci_get_devid(sc->dev) != ICH5ID) && 586 (pci_get_devid(sc->dev) != I6300ESBID) && 587 (pci_get_devid(sc->dev) != ICH6ID)) { 588 return ENXIO; 589 } 590 } 591 592 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 593 594 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 595 return ENXIO; 596 if (sc->hasmic && ich_resetchan(sc, 2)) 597 return ENXIO; 598 599 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 600 return ENOSPC; 601 602 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 603 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 604 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 605 return ENOSPC; 606 } 607 608 return 0; 609 } 610 611 static int 612 ich_pci_probe(device_t dev) 613 { 614 switch(pci_get_devid(dev)) { 615 case 0x71958086: 616 device_set_desc(dev, "Intel 443MX"); 617 return 0; 618 619 case 0x24158086: 620 device_set_desc(dev, "Intel ICH (82801AA)"); 621 return 0; 622 623 case 0x24258086: 624 device_set_desc(dev, "Intel ICH (82801AB)"); 625 return 0; 626 627 case 0x24458086: 628 device_set_desc(dev, "Intel ICH2 (82801BA)"); 629 return 0; 630 631 case 0x24858086: 632 device_set_desc(dev, "Intel ICH3 (82801CA)"); 633 return 0; 634 635 case ICH4ID: 636 device_set_desc(dev, "Intel ICH4 (82801DB)"); 637 return -1000; /* allow a better driver to override us */ 638 639 case ICH5ID: 640 device_set_desc(dev, "Intel ICH5 (82801EB)"); 641 return -1000; /* allow a better driver to override us */ 642 643 case I6300ESBID: 644 device_set_desc(dev, "Intel 6300ESB"); 645 return -1000; /* allow a better driver to override us */ 646 647 case ICH6ID: 648 device_set_desc(dev, "Intel ICH6 (82801FB)"); 649 return -1000; /* allow a better driver to override us */ 650 651 case SIS7012ID: 652 device_set_desc(dev, "SiS 7012"); 653 return 0; 654 655 case 0x01b110de: 656 device_set_desc(dev, "nVidia nForce"); 657 return 0; 658 659 case 0x006a10de: 660 device_set_desc(dev, "nVidia nForce2"); 661 return 0; 662 663 case 0x008a10de: 664 device_set_desc(dev, "nVidia nForce2 400"); 665 return 0; 666 667 case 0x00da10de: 668 device_set_desc(dev, "nVidia nForce3"); 669 return 0; 670 671 case 0x00ea10de: 672 device_set_desc(dev, "nVidia nForce3 250"); 673 return 0; 674 675 case 0x005910de: 676 device_set_desc(dev, "nVidia nForce4"); 677 return 0; 678 679 case 0x74451022: 680 device_set_desc(dev, "AMD-768"); 681 return 0; 682 683 case 0x746d1022: 684 device_set_desc(dev, "AMD-8111"); 685 return 0; 686 687 default: 688 return ENXIO; 689 } 690 } 691 692 static int 693 ich_pci_attach(device_t dev) 694 { 695 u_int16_t extcaps; 696 struct sc_info *sc; 697 char status[SND_STATUSLEN]; 698 699 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 700 device_printf(dev, "cannot allocate softc\n"); 701 return ENXIO; 702 } 703 704 bzero(sc, sizeof(*sc)); 705 sc->dev = dev; 706 707 /* 708 * The SiS 7012 register set isn't quite like the standard ich. 709 * There really should be a general "quirks" mechanism. 710 */ 711 if (pci_get_devid(dev) == SIS7012ID) { 712 sc->swap_reg = 1; 713 sc->sample_size = 1; 714 } else { 715 sc->swap_reg = 0; 716 sc->sample_size = 2; 717 } 718 719 /* 720 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 721 * read-only. Need to enable "legacy support", by poking into 722 * pci config space. The driver should use MMBAR and MBBAR, 723 * but doing so will mess things up here. ich4 has enough new 724 * features it warrants it's own driver. 725 */ 726 if (pci_get_devid(dev) == ICH4ID) { 727 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 728 } 729 730 /* 731 * Enable bus master. On ich4/5 this may prevent the detection of 732 * the primary codec becoming ready in ich_init(). 733 */ 734 pci_enable_busmaster(dev); 735 736 if (pci_get_devid(dev) == ICH5ID || 737 pci_get_devid(dev) == I6300ESBID || 738 pci_get_devid(dev) == ICH6ID) { 739 sc->nambarid = PCIR_MMBAR; 740 sc->nabmbarid = PCIR_MBBAR; 741 sc->regtype = SYS_RES_MEMORY; 742 } else { 743 sc->nambarid = PCIR_NAMBAR; 744 sc->nabmbarid = PCIR_NABMBAR; 745 sc->regtype = SYS_RES_IOPORT; 746 } 747 748 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 749 &sc->nambarid, RF_ACTIVE); 750 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 751 &sc->nabmbarid, RF_ACTIVE); 752 753 if (!sc->nambar || !sc->nabmbar) { 754 device_printf(dev, "unable to map IO port space\n"); 755 goto bad; 756 } 757 758 sc->nambart = rman_get_bustag(sc->nambar); 759 sc->nambarh = rman_get_bushandle(sc->nambar); 760 sc->nabmbart = rman_get_bustag(sc->nabmbar); 761 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 762 763 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 764 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 765 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 766 busdma_lock_mutex, &Giant, &sc->dmat) != 0) { 767 device_printf(dev, "unable to create dma tag\n"); 768 goto bad; 769 } 770 771 sc->irqid = 0; 772 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 773 RF_ACTIVE | RF_SHAREABLE); 774 if (!sc->irq || snd_setup_intr(dev, sc->irq, 0, ich_intr, sc, &sc->ih)) { 775 device_printf(dev, "unable to map interrupt\n"); 776 goto bad; 777 } 778 779 if (ich_init(sc)) { 780 device_printf(dev, "unable to initialize the card\n"); 781 goto bad; 782 } 783 784 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 785 if (sc->codec == NULL) 786 goto bad; 787 mixer_init(dev, ac97_getmixerclass(), sc->codec); 788 789 /* check and set VRA function */ 790 extcaps = ac97_getextcaps(sc->codec); 791 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 792 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 793 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 794 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 795 796 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 797 goto bad; 798 799 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 800 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 801 if (sc->hasmic) 802 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 803 804 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 805 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 806 807 pcm_setstatus(dev, status); 808 809 ich_initsys(sc); 810 811 sc->intrhook.ich_func = ich_calibrate; 812 sc->intrhook.ich_arg = sc; 813 sc->use_intrhook = 1; 814 if (config_intrhook_establish(&sc->intrhook) != 0) { 815 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 816 sc->use_intrhook = 0; 817 ich_calibrate(sc); 818 } 819 820 return 0; 821 822 bad: 823 if (sc->codec) 824 ac97_destroy(sc->codec); 825 if (sc->ih) 826 bus_teardown_intr(dev, sc->irq, sc->ih); 827 if (sc->irq) 828 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 829 if (sc->nambar) 830 bus_release_resource(dev, sc->regtype, 831 sc->nambarid, sc->nambar); 832 if (sc->nabmbar) 833 bus_release_resource(dev, sc->regtype, 834 sc->nabmbarid, sc->nabmbar); 835 free(sc, M_DEVBUF); 836 return ENXIO; 837 } 838 839 static int 840 ich_pci_detach(device_t dev) 841 { 842 struct sc_info *sc; 843 int r; 844 845 r = pcm_unregister(dev); 846 if (r) 847 return r; 848 sc = pcm_getdevinfo(dev); 849 850 bus_teardown_intr(dev, sc->irq, sc->ih); 851 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 852 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 853 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 854 bus_dma_tag_destroy(sc->dmat); 855 free(sc, M_DEVBUF); 856 return 0; 857 } 858 859 static void 860 ich_pci_codec_reset(struct sc_info *sc) 861 { 862 int i; 863 uint32_t control; 864 865 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 866 control &= ~(ICH_GLOB_CTL_SHUT); 867 control |= (control & ICH_GLOB_CTL_COLD) ? 868 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 869 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 870 871 for (i = 500000; i; i--) { 872 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 873 break; /* or ICH_SCR? */ 874 DELAY(1); 875 } 876 877 if (i <= 0) 878 printf("%s: time out\n", __func__); 879 } 880 881 static int 882 ich_pci_suspend(device_t dev) 883 { 884 struct sc_info *sc; 885 int i; 886 887 sc = pcm_getdevinfo(dev); 888 for (i = 0 ; i < 3; i++) { 889 sc->ch[i].run_save = sc->ch[i].run; 890 if (sc->ch[i].run) { 891 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 892 } 893 } 894 return 0; 895 } 896 897 static int 898 ich_pci_resume(device_t dev) 899 { 900 struct sc_info *sc; 901 int i; 902 903 sc = pcm_getdevinfo(dev); 904 905 if (sc->regtype == SYS_RES_IOPORT) 906 pci_enable_io(dev, SYS_RES_IOPORT); 907 else 908 pci_enable_io(dev, SYS_RES_MEMORY); 909 pci_enable_busmaster(dev); 910 911 /* Reinit audio device */ 912 if (ich_init(sc) == -1) { 913 device_printf(dev, "unable to reinitialize the card\n"); 914 return ENXIO; 915 } 916 /* Reinit mixer */ 917 ich_pci_codec_reset(sc); 918 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 919 if (mixer_reinit(dev) == -1) { 920 device_printf(dev, "unable to reinitialize the mixer\n"); 921 return ENXIO; 922 } 923 /* Re-start DMA engines */ 924 for (i = 0 ; i < 3; i++) { 925 struct sc_chinfo *ch = &sc->ch[i]; 926 if (sc->ch[i].run_save) { 927 ichchan_setblocksize(0, ch, ch->blksz); 928 ichchan_setspeed(0, ch, ch->spd); 929 ichchan_trigger(0, ch, PCMTRIG_START); 930 } 931 } 932 return 0; 933 } 934 935 static device_method_t ich_methods[] = { 936 /* Device interface */ 937 DEVMETHOD(device_probe, ich_pci_probe), 938 DEVMETHOD(device_attach, ich_pci_attach), 939 DEVMETHOD(device_detach, ich_pci_detach), 940 DEVMETHOD(device_suspend, ich_pci_suspend), 941 DEVMETHOD(device_resume, ich_pci_resume), 942 { 0, 0 } 943 }; 944 945 static driver_t ich_driver = { 946 "pcm", 947 ich_methods, 948 PCM_SOFTC_SIZE, 949 }; 950 951 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 952 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 953 MODULE_VERSION(snd_ich, 1);
Cache object: 695fb3bf782ade01f57f88d78dcf0ea6
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