Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/maestro3.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 Scott Long <scottl@freebsd.org> 5 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Maestro-3/Allegro FreeBSD pcm sound driver 32 * 33 * executive status summary: 34 * (+) /dev/dsp multiple concurrent play channels. 35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit). 36 * (+) /dev/mixer sets left/right volumes. 37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel 38 * (+) apm suspend/resume works, and works properly!. 39 * (-) hardware volme controls don't work =-( 40 * (-) setblocksize() does nothing. 41 * 42 * The real credit goes to: 43 * 44 * Zach Brown for his Linux driver core and helpful technical comments. 45 * <zab@zabbo.net>, http://www.zabbo.net/maestro3 46 * 47 * Cameron Grant created the pcm framework used here nearly verbatim. 48 * <cg@freebsd.org>, https://people.freebsd.org/~cg/template.c 49 * 50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference. 51 * <taku@cent.saitama-u.ac.jp> 52 * 53 * ESS docs explained a few magic registers and numbers. 54 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz 55 */ 56 57 #ifdef HAVE_KERNEL_OPTION_HEADERS 58 #include "opt_snd.h" 59 #endif 60 61 #include <dev/sound/pcm/sound.h> 62 #include <dev/sound/pcm/ac97.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #define M3_MODEL 1 68 69 #include <dev/sound/pci/allegro_reg.h> 70 #include <dev/sound/pci/allegro_code.h> 71 72 SND_DECLARE_FILE("$FreeBSD$"); 73 74 /* -------------------------------------------------------------------- */ 75 76 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1}; 77 #ifndef M3_DEBUG_LEVEL 78 #define M3_DEBUG_LEVEL NONE 79 #endif 80 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}} 81 82 /* -------------------------------------------------------------------- */ 83 enum { 84 ESS_ALLEGRO_1, 85 ESS_MAESTRO3 86 }; 87 88 static struct m3_card_type { 89 u_int32_t pci_id; int which; int delay1; int delay2; char *name; 90 } m3_card_types[] = { 91 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" }, 92 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 93 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, 94 { 0, 0, 0, 0, NULL } 95 }; 96 97 #define M3_BUFSIZE_MIN 4096 98 #define M3_BUFSIZE_MAX 65536 99 #define M3_BUFSIZE_DEFAULT 4096 100 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */ 101 #define M3_RCHANS 1 102 #define M3_MAXADDR ((1 << 27) - 1) 103 #define M3_DEFAULT_VOL 0x6800 104 105 struct sc_info; 106 107 struct sc_pchinfo { 108 u_int32_t spd; 109 u_int32_t fmt; 110 struct snd_dbuf *buffer; 111 struct pcm_channel *channel; 112 struct sc_info *parent; 113 u_int32_t bufsize; 114 u_int32_t dac_data; 115 u_int32_t dac_idx; 116 u_int32_t active; 117 u_int32_t ptr; 118 u_int32_t prevptr; 119 }; 120 121 struct sc_rchinfo { 122 u_int32_t spd; 123 u_int32_t fmt; 124 struct snd_dbuf *buffer; 125 struct pcm_channel *channel; 126 struct sc_info *parent; 127 u_int32_t bufsize; 128 u_int32_t adc_data; 129 u_int32_t adc_idx; 130 u_int32_t active; 131 u_int32_t ptr; 132 u_int32_t prevptr; 133 }; 134 135 struct sc_info { 136 device_t dev; 137 u_int32_t type; 138 int which; 139 int delay1; 140 int delay2; 141 142 bus_space_tag_t st; 143 bus_space_handle_t sh; 144 bus_dma_tag_t parent_dmat; 145 146 struct resource *reg; 147 struct resource *irq; 148 int regtype; 149 int regid; 150 int irqid; 151 void *ih; 152 153 struct sc_pchinfo pch[M3_PCHANS]; 154 struct sc_rchinfo rch[M3_RCHANS]; 155 int pch_cnt; 156 int rch_cnt; 157 int pch_active_cnt; 158 unsigned int bufsz; 159 u_int16_t *savemem; 160 161 struct mtx *sc_lock; 162 }; 163 164 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock) 165 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock) 166 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock) 167 168 /* -------------------------------------------------------------------- */ 169 170 /* play channel interface */ 171 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 172 static int m3_pchan_free(kobj_t, void *); 173 static int m3_pchan_setformat(kobj_t, void *, u_int32_t); 174 static u_int32_t m3_pchan_setspeed(kobj_t, void *, u_int32_t); 175 static u_int32_t m3_pchan_setblocksize(kobj_t, void *, u_int32_t); 176 static int m3_pchan_trigger(kobj_t, void *, int); 177 static int m3_pchan_trigger_locked(kobj_t, void *, int); 178 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *); 179 static u_int32_t m3_pchan_getptr(kobj_t, void *); 180 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *); 181 182 /* record channel interface */ 183 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int); 184 static int m3_rchan_free(kobj_t, void *); 185 static int m3_rchan_setformat(kobj_t, void *, u_int32_t); 186 static u_int32_t m3_rchan_setspeed(kobj_t, void *, u_int32_t); 187 static u_int32_t m3_rchan_setblocksize(kobj_t, void *, u_int32_t); 188 static int m3_rchan_trigger(kobj_t, void *, int); 189 static int m3_rchan_trigger_locked(kobj_t, void *, int); 190 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *); 191 static u_int32_t m3_rchan_getptr(kobj_t, void *); 192 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *); 193 194 static int m3_chan_active(struct sc_info *); 195 196 /* talk to the codec - called from ac97.c */ 197 static u_int32_t m3_initcd(kobj_t, void *); 198 static int m3_rdcd(kobj_t, void *, int); 199 static int m3_wrcd(kobj_t, void *, int, u_int32_t); 200 201 /* stuff */ 202 static void m3_intr(void *); 203 static int m3_power(struct sc_info *, int); 204 static int m3_init(struct sc_info *); 205 static int m3_uninit(struct sc_info *); 206 static u_int8_t m3_assp_halt(struct sc_info *); 207 static void m3_config(struct sc_info *); 208 static void m3_amp_enable(struct sc_info *); 209 static void m3_enable_ints(struct sc_info *); 210 static void m3_codec_reset(struct sc_info *); 211 212 /* -------------------------------------------------------------------- */ 213 /* Codec descriptor */ 214 static kobj_method_t m3_codec_methods[] = { 215 KOBJMETHOD(ac97_init, m3_initcd), 216 KOBJMETHOD(ac97_read, m3_rdcd), 217 KOBJMETHOD(ac97_write, m3_wrcd), 218 KOBJMETHOD_END 219 }; 220 AC97_DECLARE(m3_codec); 221 222 /* -------------------------------------------------------------------- */ 223 /* channel descriptors */ 224 225 static u_int32_t m3_playfmt[] = { 226 SND_FORMAT(AFMT_U8, 1, 0), 227 SND_FORMAT(AFMT_U8, 2, 0), 228 SND_FORMAT(AFMT_S16_LE, 1, 0), 229 SND_FORMAT(AFMT_S16_LE, 2, 0), 230 0 231 }; 232 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0}; 233 234 static kobj_method_t m3_pch_methods[] = { 235 KOBJMETHOD(channel_init, m3_pchan_init), 236 KOBJMETHOD(channel_setformat, m3_pchan_setformat), 237 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed), 238 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize), 239 KOBJMETHOD(channel_trigger, m3_pchan_trigger), 240 KOBJMETHOD(channel_getptr, m3_pchan_getptr), 241 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps), 242 KOBJMETHOD(channel_free, m3_pchan_free), 243 KOBJMETHOD_END 244 }; 245 CHANNEL_DECLARE(m3_pch); 246 247 static u_int32_t m3_recfmt[] = { 248 SND_FORMAT(AFMT_U8, 1, 0), 249 SND_FORMAT(AFMT_U8, 2, 0), 250 SND_FORMAT(AFMT_S16_LE, 1, 0), 251 SND_FORMAT(AFMT_S16_LE, 2, 0), 252 0 253 }; 254 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0}; 255 256 static kobj_method_t m3_rch_methods[] = { 257 KOBJMETHOD(channel_init, m3_rchan_init), 258 KOBJMETHOD(channel_setformat, m3_rchan_setformat), 259 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed), 260 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize), 261 KOBJMETHOD(channel_trigger, m3_rchan_trigger), 262 KOBJMETHOD(channel_getptr, m3_rchan_getptr), 263 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps), 264 KOBJMETHOD(channel_free, m3_rchan_free), 265 KOBJMETHOD_END 266 }; 267 CHANNEL_DECLARE(m3_rch); 268 269 /* -------------------------------------------------------------------- */ 270 /* some i/o convenience functions */ 271 272 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno) 273 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno) 274 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno) 275 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data) 276 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) 277 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data) 278 #define m3_rd_assp_code(sc, index) \ 279 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index) 280 #define m3_wr_assp_code(sc, index, data) \ 281 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data) 282 #define m3_rd_assp_data(sc, index) \ 283 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index) 284 #define m3_wr_assp_data(sc, index, data) \ 285 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data) 286 287 static __inline u_int16_t 288 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index) 289 { 290 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 291 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 292 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA); 293 } 294 295 static __inline void 296 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index, 297 u_int16_t data) 298 { 299 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); 300 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); 301 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); 302 } 303 304 static __inline int 305 m3_wait(struct sc_info *sc) 306 { 307 int i; 308 309 for (i=0 ; i<20 ; i++) { 310 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) { 311 return 0; 312 } 313 DELAY(2); 314 } 315 return -1; 316 } 317 318 /* -------------------------------------------------------------------- */ 319 /* ac97 codec */ 320 321 static u_int32_t 322 m3_initcd(kobj_t kobj, void *devinfo) 323 { 324 struct sc_info *sc = (struct sc_info *)devinfo; 325 u_int32_t data; 326 327 M3_DEBUG(CALL, ("m3_initcd\n")); 328 329 /* init ac-link */ 330 331 data = m3_rd_1(sc, CODEC_COMMAND); 332 return ((data & 0x1) ? 0 : 1); 333 } 334 335 static int 336 m3_rdcd(kobj_t kobj, void *devinfo, int regno) 337 { 338 struct sc_info *sc = (struct sc_info *)devinfo; 339 u_int32_t data; 340 341 if (m3_wait(sc)) { 342 device_printf(sc->dev, "m3_rdcd timed out.\n"); 343 return -1; 344 } 345 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80); 346 DELAY(50); /* ac97 cycle = 20.8 usec */ 347 if (m3_wait(sc)) { 348 device_printf(sc->dev, "m3_rdcd timed out.\n"); 349 return -1; 350 } 351 data = m3_rd_2(sc, CODEC_DATA); 352 return data; 353 } 354 355 static int 356 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data) 357 { 358 struct sc_info *sc = (struct sc_info *)devinfo; 359 if (m3_wait(sc)) { 360 device_printf(sc->dev, "m3_wrcd timed out.\n"); 361 return -1; 362 } 363 m3_wr_2(sc, CODEC_DATA, data); 364 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f); 365 DELAY(50); /* ac97 cycle = 20.8 usec */ 366 return 0; 367 } 368 369 /* -------------------------------------------------------------------- */ 370 /* play channel interface */ 371 372 #define LO(x) (((x) & 0x0000ffff) ) 373 #define HI(x) (((x) & 0xffff0000) >> 16) 374 375 static void * 376 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 377 { 378 struct sc_info *sc = devinfo; 379 struct sc_pchinfo *ch; 380 u_int32_t bus_addr, i; 381 int idx, data_bytes, dac_data; 382 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf; 383 384 struct data_word { 385 u_int16_t addr, val; 386 } pv[] = { 387 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL}, 388 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL}, 389 {SRC3_DIRECTION_OFFSET, 0} , 390 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, 391 {SRC3_DIRECTION_OFFSET + 4, 0}, 392 {SRC3_DIRECTION_OFFSET + 5, 0}, 393 {SRC3_DIRECTION_OFFSET + 6, 0}, 394 {SRC3_DIRECTION_OFFSET + 7, 0}, 395 {SRC3_DIRECTION_OFFSET + 8, 0}, 396 {SRC3_DIRECTION_OFFSET + 9, 0}, 397 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, 398 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, 399 {SRC3_DIRECTION_OFFSET + 13, 0}, 400 {SRC3_DIRECTION_OFFSET + 14, 0}, 401 {SRC3_DIRECTION_OFFSET + 15, 0}, 402 {SRC3_DIRECTION_OFFSET + 16, 8}, 403 {SRC3_DIRECTION_OFFSET + 17, 50*2}, 404 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, 405 {SRC3_DIRECTION_OFFSET + 20, 0}, 406 {SRC3_DIRECTION_OFFSET + 21, 0} 407 }; 408 409 M3_LOCK(sc); 410 idx = sc->pch_cnt; /* dac instance number, no active reuse! */ 411 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx)); 412 413 if (dir != PCMDIR_PLAY) { 414 M3_UNLOCK(sc); 415 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n"); 416 return (NULL); 417 } 418 419 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 420 (MINISRC_IN_BUFFER_SIZE & ~1) + 421 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 422 dac_data = 0x1100 + (data_bytes * idx); 423 424 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 425 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 426 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2); 427 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1; 428 429 ch = &sc->pch[idx]; 430 ch->dac_idx = idx; 431 ch->dac_data = dac_data; 432 if (ch->dac_data + data_bytes/2 >= 0x1c00) { 433 M3_UNLOCK(sc); 434 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n"); 435 return (NULL); 436 } 437 438 ch->buffer = b; 439 ch->parent = sc; 440 ch->channel = c; 441 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 442 ch->spd = DSP_DEFAULT_SPEED; 443 M3_UNLOCK(sc); /* XXX */ 444 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 445 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n"); 446 return (NULL); 447 } 448 M3_LOCK(sc); 449 ch->bufsize = sndbuf_getsize(ch->buffer); 450 451 /* host dma buffer pointers */ 452 bus_addr = sndbuf_getbufaddr(ch->buffer); 453 if (bus_addr & 3) { 454 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n"); 455 bus_addr = (bus_addr + 4) & ~3; 456 } 457 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 458 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 459 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L, 460 LO(bus_addr + ch->bufsize)); 461 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H, 462 HI(bus_addr + ch->bufsize)); 463 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL, 464 LO(bus_addr)); 465 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH, 466 HI(bus_addr)); 467 468 /* dsp buffers */ 469 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 470 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1, 471 dsp_in_buf + dsp_in_size/2); 472 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 473 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 474 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 475 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1, 476 dsp_out_buf + dsp_out_size/2); 477 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 478 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 479 480 /* some per client initializers */ 481 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12, 482 ch->dac_data + 40 + 8); 483 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19, 484 0x400 + MINISRC_COEF_LOC); 485 /* enable or disable low pass filter? (0xff if rate> 45000) */ 486 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0); 487 /* tell it which way dma is going? */ 488 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL, 489 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + 490 DMAC_BLOCKF_SELECTOR); 491 492 /* set an armload of static initializers */ 493 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) { 494 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val); 495 } 496 497 /* put us in the packed task lists */ 498 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 499 (sc->pch_cnt + sc->rch_cnt), 500 ch->dac_data >> DP_SHIFT_COUNT); 501 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 502 ch->dac_data >> DP_SHIFT_COUNT); 503 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt, 504 ch->dac_data >> DP_SHIFT_COUNT); 505 506 /* gotta start before stop */ 507 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START); 508 /* silence noise on load */ 509 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP); 510 511 sc->pch_cnt++; 512 M3_UNLOCK(sc); 513 514 return (ch); 515 } 516 517 static int 518 m3_pchan_free(kobj_t kobj, void *chdata) 519 { 520 struct sc_pchinfo *ch = chdata; 521 struct sc_info *sc = ch->parent; 522 523 M3_LOCK(sc); 524 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx)); 525 526 /* 527 * should remove this exact instance from the packed lists, but all 528 * are released at once (and in a stopped state) so this is ok. 529 */ 530 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 531 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 532 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 533 (sc->pch_cnt - 1) + sc->rch_cnt, 0); 534 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0); 535 sc->pch_cnt--; 536 M3_UNLOCK(sc); 537 538 return (0); 539 } 540 541 static int 542 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 543 { 544 struct sc_pchinfo *ch = chdata; 545 struct sc_info *sc = ch->parent; 546 u_int32_t data; 547 548 M3_LOCK(sc); 549 M3_DEBUG(CHANGE, 550 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 551 ch->dac_idx, format, 552 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 553 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO")); 554 555 /* mono word */ 556 data = (AFMT_CHANNEL(format) > 1)? 0 : 1; 557 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data); 558 559 /* 8bit word */ 560 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 561 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data); 562 563 ch->fmt = format; 564 M3_UNLOCK(sc); 565 566 return (0); 567 } 568 569 static u_int32_t 570 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 571 { 572 struct sc_pchinfo *ch = chdata; 573 struct sc_info *sc = ch->parent; 574 u_int32_t freq; 575 576 M3_LOCK(sc); 577 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n", 578 ch->dac_idx, speed)); 579 580 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 581 freq--; 582 } 583 584 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq); 585 ch->spd = speed; 586 M3_UNLOCK(sc); 587 588 /* return closest possible speed */ 589 return (speed); 590 } 591 592 static u_int32_t 593 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 594 { 595 struct sc_pchinfo *ch = chdata; 596 597 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n", 598 ch->dac_idx, blocksize)); 599 600 return (sndbuf_getblksz(ch->buffer)); 601 } 602 603 static int 604 m3_pchan_trigger(kobj_t kobj, void *chdata, int go) 605 { 606 struct sc_pchinfo *ch = chdata; 607 struct sc_info *sc = ch->parent; 608 int ret; 609 610 if (!PCMTRIG_COMMON(go)) 611 return (0); 612 613 M3_LOCK(sc); 614 ret = m3_pchan_trigger_locked(kobj, chdata, go); 615 M3_UNLOCK(sc); 616 617 return (ret); 618 } 619 620 static int 621 m3_chan_active(struct sc_info *sc) 622 { 623 int i, ret; 624 625 ret = 0; 626 627 for (i = 0; i < sc->pch_cnt; i++) 628 ret += sc->pch[i].active; 629 630 for (i = 0; i < sc->rch_cnt; i++) 631 ret += sc->rch[i].active; 632 633 return (ret); 634 } 635 636 static int 637 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go) 638 { 639 struct sc_pchinfo *ch = chdata; 640 struct sc_info *sc = ch->parent; 641 u_int32_t data; 642 643 M3_LOCK_ASSERT(sc); 644 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 645 go == PCMTRIG_STOP ? CHANGE : 646 go == PCMTRIG_ABORT ? CHANGE : 647 CALL, 648 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go, 649 go == PCMTRIG_START ? "PCMTRIG_START" : 650 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 651 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 652 653 switch(go) { 654 case PCMTRIG_START: 655 if (ch->active) { 656 return 0; 657 } 658 ch->active = 1; 659 ch->ptr = 0; 660 ch->prevptr = 0; 661 sc->pch_active_cnt++; 662 663 /*[[inc_timer_users]]*/ 664 if (m3_chan_active(sc) == 1) { 665 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 666 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 667 data = m3_rd_2(sc, HOST_INT_CTRL); 668 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 669 } 670 671 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1); 672 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 673 sc->pch_active_cnt); 674 break; 675 676 case PCMTRIG_STOP: 677 case PCMTRIG_ABORT: 678 if (ch->active == 0) { 679 return 0; 680 } 681 ch->active = 0; 682 sc->pch_active_cnt--; 683 684 /* XXX should the channel be drained? */ 685 /*[[dec_timer_users]]*/ 686 if (m3_chan_active(sc) == 0) { 687 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 688 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 689 data = m3_rd_2(sc, HOST_INT_CTRL); 690 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 691 } 692 693 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0); 694 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 695 sc->pch_active_cnt); 696 break; 697 698 case PCMTRIG_EMLDMAWR: 699 /* got play irq, transfer next buffer - ignore if using dma */ 700 case PCMTRIG_EMLDMARD: 701 /* got rec irq, transfer next buffer - ignore if using dma */ 702 default: 703 break; 704 } 705 return 0; 706 } 707 708 static u_int32_t 709 m3_pchan_getptr_internal(struct sc_pchinfo *ch) 710 { 711 struct sc_info *sc = ch->parent; 712 u_int32_t hi, lo, bus_base, bus_crnt; 713 714 bus_base = sndbuf_getbufaddr(ch->buffer); 715 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH); 716 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL); 717 bus_crnt = lo | (hi << 16); 718 719 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n", 720 ch->dac_idx, bus_crnt - bus_base)); 721 722 return (bus_crnt - bus_base); /* current byte offset of channel */ 723 } 724 725 static u_int32_t 726 m3_pchan_getptr(kobj_t kobj, void *chdata) 727 { 728 struct sc_pchinfo *ch = chdata; 729 struct sc_info *sc = ch->parent; 730 u_int32_t ptr; 731 732 M3_LOCK(sc); 733 ptr = ch->ptr; 734 M3_UNLOCK(sc); 735 736 return (ptr); 737 } 738 739 static struct pcmchan_caps * 740 m3_pchan_getcaps(kobj_t kobj, void *chdata) 741 { 742 struct sc_pchinfo *ch = chdata; 743 744 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx)); 745 746 return &m3_playcaps; 747 } 748 749 /* -------------------------------------------------------------------- */ 750 /* rec channel interface */ 751 752 static void * 753 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 754 { 755 struct sc_info *sc = devinfo; 756 struct sc_rchinfo *ch; 757 u_int32_t bus_addr, i; 758 759 int idx, data_bytes, adc_data; 760 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf; 761 762 struct data_word { 763 u_int16_t addr, val; 764 } rv[] = { 765 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL}, 766 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL}, 767 {SRC3_DIRECTION_OFFSET, 1}, 768 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, 769 {SRC3_DIRECTION_OFFSET + 4, 0}, 770 {SRC3_DIRECTION_OFFSET + 5, 0}, 771 {SRC3_DIRECTION_OFFSET + 6, 0}, 772 {SRC3_DIRECTION_OFFSET + 7, 0}, 773 {SRC3_DIRECTION_OFFSET + 8, 0}, 774 {SRC3_DIRECTION_OFFSET + 9, 0}, 775 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, 776 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, 777 {SRC3_DIRECTION_OFFSET + 13, 0}, 778 {SRC3_DIRECTION_OFFSET + 14, 0}, 779 {SRC3_DIRECTION_OFFSET + 15, 0}, 780 {SRC3_DIRECTION_OFFSET + 16, 50}, 781 {SRC3_DIRECTION_OFFSET + 17, 8}, 782 {SRC3_DIRECTION_OFFSET + 18, 0}, 783 {SRC3_DIRECTION_OFFSET + 19, 0}, 784 {SRC3_DIRECTION_OFFSET + 20, 0}, 785 {SRC3_DIRECTION_OFFSET + 21, 0}, 786 {SRC3_DIRECTION_OFFSET + 22, 0xff} 787 }; 788 789 M3_LOCK(sc); 790 idx = sc->rch_cnt; /* adc instance number, no active reuse! */ 791 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx)); 792 793 if (dir != PCMDIR_REC) { 794 M3_UNLOCK(sc); 795 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n"); 796 return (NULL); 797 } 798 799 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + 800 (MINISRC_IN_BUFFER_SIZE & ~1) + 801 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; 802 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2; 803 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2); 804 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 805 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2); 806 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1; 807 808 ch = &sc->rch[idx]; 809 ch->adc_idx = idx; 810 ch->adc_data = adc_data; 811 if (ch->adc_data + data_bytes/2 >= 0x1c00) { 812 M3_UNLOCK(sc); 813 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n"); 814 return (NULL); 815 } 816 817 ch->buffer = b; 818 ch->parent = sc; 819 ch->channel = c; 820 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 821 ch->spd = DSP_DEFAULT_SPEED; 822 M3_UNLOCK(sc); /* XXX */ 823 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 824 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n"); 825 return (NULL); 826 } 827 M3_LOCK(sc); 828 ch->bufsize = sndbuf_getsize(ch->buffer); 829 830 /* host dma buffer pointers */ 831 bus_addr = sndbuf_getbufaddr(ch->buffer); 832 if (bus_addr & 3) { 833 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n"); 834 bus_addr = (bus_addr + 4) & ~3; 835 } 836 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); 837 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); 838 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L, 839 LO(bus_addr + ch->bufsize)); 840 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H, 841 HI(bus_addr + ch->bufsize)); 842 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL, 843 LO(bus_addr)); 844 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH, 845 HI(bus_addr)); 846 847 /* dsp buffers */ 848 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); 849 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1, 850 dsp_in_buf + dsp_in_size/2); 851 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf); 852 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf); 853 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); 854 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1, 855 dsp_out_buf + dsp_out_size/2); 856 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); 857 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); 858 859 /* some per client initializers */ 860 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12, 861 ch->adc_data + 40 + 8); 862 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL, 863 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 864 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 865 866 /* set an armload of static initializers */ 867 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) { 868 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val); 869 } 870 871 /* put us in the packed task lists */ 872 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 873 (sc->pch_cnt + sc->rch_cnt), 874 ch->adc_data >> DP_SHIFT_COUNT); 875 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), 876 ch->adc_data >> DP_SHIFT_COUNT); 877 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt, 878 ch->adc_data >> DP_SHIFT_COUNT); 879 880 /* gotta start before stop */ 881 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START); 882 /* stop on init */ 883 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP); 884 885 sc->rch_cnt++; 886 M3_UNLOCK(sc); 887 888 return (ch); 889 } 890 891 static int 892 m3_rchan_free(kobj_t kobj, void *chdata) 893 { 894 struct sc_rchinfo *ch = chdata; 895 struct sc_info *sc = ch->parent; 896 897 M3_LOCK(sc); 898 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx)); 899 900 /* 901 * should remove this exact instance from the packed lists, but all 902 * are released at once (and in a stopped state) so this is ok. 903 */ 904 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + 905 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 906 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + 907 (sc->rch_cnt - 1) + sc->pch_cnt, 0); 908 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0); 909 sc->rch_cnt--; 910 M3_UNLOCK(sc); 911 912 return (0); 913 } 914 915 static int 916 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) 917 { 918 struct sc_rchinfo *ch = chdata; 919 struct sc_info *sc = ch->parent; 920 u_int32_t data; 921 922 M3_LOCK(sc); 923 M3_DEBUG(CHANGE, 924 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n", 925 ch->adc_idx, format, 926 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", 927 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO")); 928 929 /* mono word */ 930 data = (AFMT_CHANNEL(format) > 1) ? 0 : 1; 931 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data); 932 933 /* 8bit word */ 934 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; 935 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data); 936 ch->fmt = format; 937 M3_UNLOCK(sc); 938 939 return (0); 940 } 941 942 static u_int32_t 943 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) 944 { 945 struct sc_rchinfo *ch = chdata; 946 struct sc_info *sc = ch->parent; 947 u_int32_t freq; 948 949 M3_LOCK(sc); 950 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n", 951 ch->adc_idx, speed)); 952 953 if ((freq = ((speed << 15) + 24000) / 48000) != 0) { 954 freq--; 955 } 956 957 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq); 958 ch->spd = speed; 959 M3_UNLOCK(sc); 960 961 /* return closest possible speed */ 962 return (speed); 963 } 964 965 static u_int32_t 966 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) 967 { 968 struct sc_rchinfo *ch = chdata; 969 970 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n", 971 ch->adc_idx, blocksize)); 972 973 return (sndbuf_getblksz(ch->buffer)); 974 } 975 976 static int 977 m3_rchan_trigger(kobj_t kobj, void *chdata, int go) 978 { 979 struct sc_rchinfo *ch = chdata; 980 struct sc_info *sc = ch->parent; 981 int ret; 982 983 if (!PCMTRIG_COMMON(go)) 984 return (0); 985 986 M3_LOCK(sc); 987 ret = m3_rchan_trigger_locked(kobj, chdata, go); 988 M3_UNLOCK(sc); 989 990 return (ret); 991 } 992 993 static int 994 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go) 995 { 996 struct sc_rchinfo *ch = chdata; 997 struct sc_info *sc = ch->parent; 998 u_int32_t data; 999 1000 M3_LOCK_ASSERT(sc); 1001 M3_DEBUG(go == PCMTRIG_START ? CHANGE : 1002 go == PCMTRIG_STOP ? CHANGE : 1003 go == PCMTRIG_ABORT ? CHANGE : 1004 CALL, 1005 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go, 1006 go == PCMTRIG_START ? "PCMTRIG_START" : 1007 go == PCMTRIG_STOP ? "PCMTRIG_STOP" : 1008 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); 1009 1010 switch(go) { 1011 case PCMTRIG_START: 1012 if (ch->active) { 1013 return 0; 1014 } 1015 ch->active = 1; 1016 ch->ptr = 0; 1017 ch->prevptr = 0; 1018 1019 /*[[inc_timer_users]]*/ 1020 if (m3_chan_active(sc) == 1) { 1021 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); 1022 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); 1023 data = m3_rd_2(sc, HOST_INT_CTRL); 1024 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); 1025 } 1026 1027 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1); 1028 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1); 1029 break; 1030 1031 case PCMTRIG_STOP: 1032 case PCMTRIG_ABORT: 1033 if (ch->active == 0) { 1034 return 0; 1035 } 1036 ch->active = 0; 1037 1038 /*[[dec_timer_users]]*/ 1039 if (m3_chan_active(sc) == 0) { 1040 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); 1041 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); 1042 data = m3_rd_2(sc, HOST_INT_CTRL); 1043 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); 1044 } 1045 1046 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0); 1047 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0); 1048 break; 1049 1050 case PCMTRIG_EMLDMAWR: 1051 /* got play irq, transfer next buffer - ignore if using dma */ 1052 case PCMTRIG_EMLDMARD: 1053 /* got rec irq, transfer next buffer - ignore if using dma */ 1054 default: 1055 break; 1056 } 1057 return 0; 1058 } 1059 1060 static u_int32_t 1061 m3_rchan_getptr_internal(struct sc_rchinfo *ch) 1062 { 1063 struct sc_info *sc = ch->parent; 1064 u_int32_t hi, lo, bus_base, bus_crnt; 1065 1066 bus_base = sndbuf_getbufaddr(ch->buffer); 1067 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH); 1068 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL); 1069 bus_crnt = lo | (hi << 16); 1070 1071 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n", 1072 ch->adc_idx, bus_crnt - bus_base)); 1073 1074 return (bus_crnt - bus_base); /* current byte offset of channel */ 1075 } 1076 1077 static u_int32_t 1078 m3_rchan_getptr(kobj_t kobj, void *chdata) 1079 { 1080 struct sc_rchinfo *ch = chdata; 1081 struct sc_info *sc = ch->parent; 1082 u_int32_t ptr; 1083 1084 M3_LOCK(sc); 1085 ptr = ch->ptr; 1086 M3_UNLOCK(sc); 1087 1088 return (ptr); 1089 } 1090 1091 static struct pcmchan_caps * 1092 m3_rchan_getcaps(kobj_t kobj, void *chdata) 1093 { 1094 struct sc_rchinfo *ch = chdata; 1095 1096 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx)); 1097 1098 return &m3_reccaps; 1099 } 1100 1101 /* -------------------------------------------------------------------- */ 1102 /* The interrupt handler */ 1103 1104 static void 1105 m3_intr(void *p) 1106 { 1107 struct sc_info *sc = (struct sc_info *)p; 1108 struct sc_pchinfo *pch; 1109 struct sc_rchinfo *rch; 1110 u_int32_t status, ctl, i, delta; 1111 1112 M3_DEBUG(INTR, ("m3_intr\n")); 1113 1114 M3_LOCK(sc); 1115 status = m3_rd_1(sc, HOST_INT_STATUS); 1116 if (!status) { 1117 M3_UNLOCK(sc); 1118 return; 1119 } 1120 1121 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */ 1122 1123 if (status & HV_INT_PENDING) { 1124 u_int8_t event; 1125 1126 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER); 1127 switch (event) { 1128 case 0x99: 1129 mixer_hwvol_mute(sc->dev); 1130 break; 1131 case 0xaa: 1132 mixer_hwvol_step(sc->dev, 1, 1); 1133 break; 1134 case 0x66: 1135 mixer_hwvol_step(sc->dev, -1, -1); 1136 break; 1137 case 0x88: 1138 break; 1139 default: 1140 device_printf(sc->dev, "Unknown HWVOL event\n"); 1141 } 1142 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88); 1143 } 1144 1145 if (status & ASSP_INT_PENDING) { 1146 ctl = m3_rd_1(sc, ASSP_CONTROL_B); 1147 if (!(ctl & STOP_ASSP_CLOCK)) { 1148 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS); 1149 if (ctl & DSP2HOST_REQ_TIMER) { 1150 m3_wr_1(sc, ASSP_HOST_INT_STATUS, 1151 DSP2HOST_REQ_TIMER); 1152 /*[[ess_update_ptr]]*/ 1153 goto m3_handle_channel_intr; 1154 } 1155 } 1156 } 1157 1158 goto m3_handle_channel_intr_out; 1159 1160 m3_handle_channel_intr: 1161 for (i=0 ; i<sc->pch_cnt ; i++) { 1162 pch = &sc->pch[i]; 1163 if (pch->active) { 1164 pch->ptr = m3_pchan_getptr_internal(pch); 1165 delta = pch->bufsize + pch->ptr - pch->prevptr; 1166 delta %= pch->bufsize; 1167 if (delta < sndbuf_getblksz(pch->buffer)) 1168 continue; 1169 pch->prevptr = pch->ptr; 1170 M3_UNLOCK(sc); 1171 chn_intr(pch->channel); 1172 M3_LOCK(sc); 1173 } 1174 } 1175 for (i=0 ; i<sc->rch_cnt ; i++) { 1176 rch = &sc->rch[i]; 1177 if (rch->active) { 1178 rch->ptr = m3_rchan_getptr_internal(rch); 1179 delta = rch->bufsize + rch->ptr - rch->prevptr; 1180 delta %= rch->bufsize; 1181 if (delta < sndbuf_getblksz(rch->buffer)) 1182 continue; 1183 rch->prevptr = rch->ptr; 1184 M3_UNLOCK(sc); 1185 chn_intr(rch->channel); 1186 M3_LOCK(sc); 1187 } 1188 } 1189 1190 m3_handle_channel_intr_out: 1191 M3_UNLOCK(sc); 1192 } 1193 1194 /* -------------------------------------------------------------------- */ 1195 /* stuff */ 1196 1197 static int 1198 m3_power(struct sc_info *sc, int state) 1199 { 1200 u_int32_t data; 1201 1202 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state)); 1203 M3_LOCK_ASSERT(sc); 1204 1205 data = pci_read_config(sc->dev, 0x34, 1); 1206 if (pci_read_config(sc->dev, data, 1) == 1) { 1207 pci_write_config(sc->dev, data + 4, state, 1); 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int 1214 m3_init(struct sc_info *sc) 1215 { 1216 u_int32_t data, i, size; 1217 u_int8_t reset_state; 1218 1219 M3_LOCK_ASSERT(sc); 1220 M3_DEBUG(CHANGE, ("m3_init\n")); 1221 1222 /* diable legacy emulations. */ 1223 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2); 1224 data |= DISABLE_LEGACY; 1225 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2); 1226 1227 m3_config(sc); 1228 1229 reset_state = m3_assp_halt(sc); 1230 1231 m3_codec_reset(sc); 1232 1233 /* [m3_assp_init] */ 1234 /* zero kernel data */ 1235 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1236 for(i = 0 ; i < size / 2 ; i++) { 1237 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0); 1238 } 1239 /* zero mixer data? */ 1240 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; 1241 for(i = 0 ; i < size / 2 ; i++) { 1242 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0); 1243 } 1244 /* init dma pointer */ 1245 m3_wr_assp_data(sc, KDATA_CURRENT_DMA, 1246 KDATA_DMA_XFER0); 1247 /* write kernel into code memory */ 1248 size = sizeof(gaw_kernel_vect_code); 1249 for(i = 0 ; i < size / 2; i++) { 1250 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i, 1251 gaw_kernel_vect_code[i]); 1252 } 1253 /* 1254 * We only have this one client and we know that 0x400 is free in 1255 * our kernel's mem map, so lets just drop it there. It seems that 1256 * the minisrc doesn't need vectors, so we won't bother with them.. 1257 */ 1258 size = sizeof(gaw_minisrc_code_0400); 1259 for(i = 0 ; i < size / 2; i++) { 1260 m3_wr_assp_code(sc, 0x400 + i, gaw_minisrc_code_0400[i]); 1261 } 1262 /* write the coefficients for the low pass filter? */ 1263 size = sizeof(minisrc_lpf); 1264 for(i = 0; i < size / 2 ; i++) { 1265 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i, 1266 minisrc_lpf[i]); 1267 } 1268 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000); 1269 /* the minisrc is the only thing on our task list */ 1270 m3_wr_assp_data(sc, KDATA_TASK0, 0x400); 1271 /* init the mixer number */ 1272 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0); 1273 /* extreme kernel master volume */ 1274 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, M3_DEFAULT_VOL); 1275 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, M3_DEFAULT_VOL); 1276 1277 m3_amp_enable(sc); 1278 1279 /* [m3_assp_client_init] (only one client at index 0) */ 1280 for (i=0x1100 ; i<0x1c00 ; i++) { 1281 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */ 1282 } 1283 1284 /* [m3_assp_continue] */ 1285 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1286 1287 return 0; 1288 } 1289 1290 static int 1291 m3_uninit(struct sc_info *sc) 1292 { 1293 M3_DEBUG(CHANGE, ("m3_uninit\n")); 1294 return 0; 1295 } 1296 1297 /* -------------------------------------------------------------------- */ 1298 /* Probe and attach the card */ 1299 1300 static int 1301 m3_pci_probe(device_t dev) 1302 { 1303 struct m3_card_type *card; 1304 1305 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev))); 1306 1307 for (card = m3_card_types ; card->pci_id ; card++) { 1308 if (pci_get_devid(dev) == card->pci_id) { 1309 device_set_desc(dev, card->name); 1310 return BUS_PROBE_DEFAULT; 1311 } 1312 } 1313 return ENXIO; 1314 } 1315 1316 static int 1317 m3_pci_attach(device_t dev) 1318 { 1319 struct sc_info *sc; 1320 struct ac97_info *codec = NULL; 1321 char status[SND_STATUSLEN]; 1322 struct m3_card_type *card; 1323 int i, len, dacn, adcn; 1324 1325 M3_DEBUG(CALL, ("m3_pci_attach\n")); 1326 1327 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1328 sc->dev = dev; 1329 sc->type = pci_get_devid(dev); 1330 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev), 1331 "snd_maestro3 softc"); 1332 for (card = m3_card_types ; card->pci_id ; card++) { 1333 if (sc->type == card->pci_id) { 1334 sc->which = card->which; 1335 sc->delay1 = card->delay1; 1336 sc->delay2 = card->delay2; 1337 break; 1338 } 1339 } 1340 1341 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 1342 "dac", &i) == 0) { 1343 if (i < 1) 1344 dacn = 1; 1345 else if (i > M3_PCHANS) 1346 dacn = M3_PCHANS; 1347 else 1348 dacn = i; 1349 } else 1350 dacn = M3_PCHANS; 1351 1352 adcn = M3_RCHANS; 1353 1354 pci_enable_busmaster(dev); 1355 1356 sc->regid = PCIR_BAR(0); 1357 sc->regtype = SYS_RES_MEMORY; 1358 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 1359 RF_ACTIVE); 1360 if (!sc->reg) { 1361 sc->regtype = SYS_RES_IOPORT; 1362 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 1363 RF_ACTIVE); 1364 } 1365 if (!sc->reg) { 1366 device_printf(dev, "unable to allocate register space\n"); 1367 goto bad; 1368 } 1369 sc->st = rman_get_bustag(sc->reg); 1370 sc->sh = rman_get_bushandle(sc->reg); 1371 1372 sc->irqid = 0; 1373 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1374 RF_ACTIVE | RF_SHAREABLE); 1375 if (!sc->irq) { 1376 device_printf(dev, "unable to allocate interrupt\n"); 1377 goto bad; 1378 } 1379 1380 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) { 1381 device_printf(dev, "unable to setup interrupt\n"); 1382 goto bad; 1383 } 1384 1385 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT, 1386 M3_BUFSIZE_MAX); 1387 1388 if (bus_dma_tag_create( 1389 bus_get_dma_tag(dev), /* parent */ 1390 2, 0, /* alignment, boundary */ 1391 M3_MAXADDR, /* lowaddr */ 1392 BUS_SPACE_MAXADDR, /* highaddr */ 1393 NULL, NULL, /* filtfunc, filtfuncarg */ 1394 sc->bufsz, /* maxsize */ 1395 1, /* nsegments */ 1396 0x3ffff, /* maxsegz */ 1397 0, /* flags */ 1398 NULL, /* lockfunc */ 1399 NULL, /* lockfuncarg */ 1400 &sc->parent_dmat) != 0) { 1401 device_printf(dev, "unable to create dma tag\n"); 1402 goto bad; 1403 } 1404 1405 M3_LOCK(sc); 1406 m3_power(sc, 0); /* power up */ 1407 /* init chip */ 1408 i = m3_init(sc); 1409 M3_UNLOCK(sc); 1410 if (i == -1) { 1411 device_printf(dev, "unable to initialize the card\n"); 1412 goto bad; 1413 } 1414 1415 /* create/init mixer */ 1416 codec = AC97_CREATE(dev, sc, m3_codec); 1417 if (codec == NULL) { 1418 device_printf(dev, "ac97_create error\n"); 1419 goto bad; 1420 } 1421 if (mixer_init(dev, ac97_getmixerclass(), codec)) { 1422 device_printf(dev, "mixer_init error\n"); 1423 goto bad; 1424 } 1425 1426 m3_enable_ints(sc); 1427 1428 if (pcm_register(dev, sc, dacn, adcn)) { 1429 device_printf(dev, "pcm_register error\n"); 1430 goto bad; 1431 } 1432 for (i=0 ; i<dacn ; i++) { 1433 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) { 1434 device_printf(dev, "pcm_addchan (play) error\n"); 1435 goto bad; 1436 } 1437 } 1438 for (i=0 ; i<adcn ; i++) { 1439 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) { 1440 device_printf(dev, "pcm_addchan (rec) error\n"); 1441 goto bad; 1442 } 1443 } 1444 snprintf(status, SND_STATUSLEN, "at %s 0x%jx irq %jd %s", 1445 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 1446 rman_get_start(sc->reg), rman_get_start(sc->irq), 1447 PCM_KLDSTRING(snd_maestro3)); 1448 if (pcm_setstatus(dev, status)) { 1449 device_printf(dev, "attach: pcm_setstatus error\n"); 1450 goto bad; 1451 } 1452 1453 mixer_hwvol_init(dev); 1454 1455 /* Create the buffer for saving the card state during suspend */ 1456 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH + 1457 REV_B_DATA_MEMORY_LENGTH); 1458 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1459 1460 return 0; 1461 1462 bad: 1463 if (codec) 1464 ac97_destroy(codec); 1465 if (sc->ih) 1466 bus_teardown_intr(dev, sc->irq, sc->ih); 1467 if (sc->irq) 1468 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1469 if (sc->reg) 1470 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1471 if (sc->parent_dmat) 1472 bus_dma_tag_destroy(sc->parent_dmat); 1473 if (sc->sc_lock) 1474 snd_mtxfree(sc->sc_lock); 1475 free(sc, M_DEVBUF); 1476 return ENXIO; 1477 } 1478 1479 static int 1480 m3_pci_detach(device_t dev) 1481 { 1482 struct sc_info *sc = pcm_getdevinfo(dev); 1483 int r; 1484 1485 M3_DEBUG(CALL, ("m3_pci_detach\n")); 1486 1487 if ((r = pcm_unregister(dev)) != 0) { 1488 return r; 1489 } 1490 1491 M3_LOCK(sc); 1492 m3_uninit(sc); /* shutdown chip */ 1493 m3_power(sc, 3); /* power off */ 1494 M3_UNLOCK(sc); 1495 1496 bus_teardown_intr(dev, sc->irq, sc->ih); 1497 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1498 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1499 bus_dma_tag_destroy(sc->parent_dmat); 1500 1501 free(sc->savemem, M_DEVBUF); 1502 snd_mtxfree(sc->sc_lock); 1503 free(sc, M_DEVBUF); 1504 return 0; 1505 } 1506 1507 static int 1508 m3_pci_suspend(device_t dev) 1509 { 1510 struct sc_info *sc = pcm_getdevinfo(dev); 1511 int i, index = 0; 1512 1513 M3_DEBUG(CHANGE, ("m3_pci_suspend\n")); 1514 1515 M3_LOCK(sc); 1516 for (i=0 ; i<sc->pch_cnt ; i++) { 1517 if (sc->pch[i].active) { 1518 m3_pchan_trigger_locked(NULL, &sc->pch[i], 1519 PCMTRIG_STOP); 1520 } 1521 } 1522 for (i=0 ; i<sc->rch_cnt ; i++) { 1523 if (sc->rch[i].active) { 1524 m3_rchan_trigger_locked(NULL, &sc->rch[i], 1525 PCMTRIG_STOP); 1526 } 1527 } 1528 DELAY(10 * 1000); /* give things a chance to stop */ 1529 1530 /* Disable interrupts */ 1531 m3_wr_2(sc, HOST_INT_CTRL, 0); 1532 m3_wr_1(sc, ASSP_CONTROL_C, 0); 1533 1534 m3_assp_halt(sc); 1535 1536 /* Save the state of the ASSP */ 1537 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1538 sc->savemem[index++] = m3_rd_assp_code(sc, i); 1539 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1540 sc->savemem[index++] = m3_rd_assp_data(sc, i); 1541 1542 /* Power down the card to D3 state */ 1543 m3_power(sc, 3); 1544 M3_UNLOCK(sc); 1545 1546 return 0; 1547 } 1548 1549 static int 1550 m3_pci_resume(device_t dev) 1551 { 1552 struct sc_info *sc = pcm_getdevinfo(dev); 1553 int i, index = 0; 1554 u_int8_t reset_state; 1555 1556 M3_DEBUG(CHANGE, ("m3_pci_resume\n")); 1557 1558 M3_LOCK(sc); 1559 /* Power the card back to D0 */ 1560 m3_power(sc, 0); 1561 1562 m3_config(sc); 1563 1564 reset_state = m3_assp_halt(sc); 1565 1566 m3_codec_reset(sc); 1567 1568 /* Restore the ASSP state */ 1569 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 1570 m3_wr_assp_code(sc, i, sc->savemem[index++]); 1571 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) 1572 m3_wr_assp_data(sc, i, sc->savemem[index++]); 1573 1574 /* Restart the DMA engine */ 1575 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0); 1576 1577 /* [m3_assp_continue] */ 1578 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); 1579 1580 m3_amp_enable(sc); 1581 1582 m3_enable_ints(sc); 1583 1584 M3_UNLOCK(sc); /* XXX */ 1585 if (mixer_reinit(dev) == -1) { 1586 device_printf(dev, "unable to reinitialize the mixer\n"); 1587 return (ENXIO); 1588 } 1589 M3_LOCK(sc); 1590 1591 /* Turn the channels back on */ 1592 for (i=0 ; i<sc->pch_cnt ; i++) { 1593 if (sc->pch[i].active) { 1594 m3_pchan_trigger_locked(NULL, &sc->pch[i], 1595 PCMTRIG_START); 1596 } 1597 } 1598 for (i=0 ; i<sc->rch_cnt ; i++) { 1599 if (sc->rch[i].active) { 1600 m3_rchan_trigger_locked(NULL, &sc->rch[i], 1601 PCMTRIG_START); 1602 } 1603 } 1604 1605 M3_UNLOCK(sc); 1606 return 0; 1607 } 1608 1609 static int 1610 m3_pci_shutdown(device_t dev) 1611 { 1612 struct sc_info *sc = pcm_getdevinfo(dev); 1613 1614 M3_DEBUG(CALL, ("m3_pci_shutdown\n")); 1615 1616 M3_LOCK(sc); 1617 m3_power(sc, 3); /* power off */ 1618 M3_UNLOCK(sc); 1619 1620 return 0; 1621 } 1622 1623 static u_int8_t 1624 m3_assp_halt(struct sc_info *sc) 1625 { 1626 u_int8_t data, reset_state; 1627 1628 M3_LOCK_ASSERT(sc); 1629 1630 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B); 1631 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */ 1632 DELAY(10 * 1000); 1633 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET); 1634 DELAY(10 * 1000); /* necessary? */ 1635 1636 return reset_state; 1637 } 1638 1639 static void 1640 m3_config(struct sc_info *sc) 1641 { 1642 u_int32_t data, hv_cfg; 1643 int hint; 1644 1645 M3_LOCK_ASSERT(sc); 1646 1647 M3_UNLOCK(sc); 1648 /* 1649 * The volume buttons can be wired up via two different sets of pins. 1650 * This presents a problem since we can't tell which way it's 1651 * configured. Allow the user to set a hint in order to twiddle 1652 * the proper bits. 1653 */ 1654 if (resource_int_value(device_get_name(sc->dev), 1655 device_get_unit(sc->dev), 1656 "hwvol_config", &hint) == 0) 1657 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0; 1658 else 1659 hv_cfg = HV_BUTTON_FROM_GD; 1660 M3_LOCK(sc); 1661 1662 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1663 data &= ~HV_BUTTON_FROM_GD; 1664 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg; 1665 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 1666 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1667 1668 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP); 1669 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); 1670 data &= ~INT_CLK_SELECT; 1671 if (sc->which == ESS_MAESTRO3) { 1672 data &= ~INT_CLK_MULT_ENABLE; 1673 data |= INT_CLK_SRC_NOT_PCI; 1674 } 1675 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); 1676 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); 1677 1678 if (sc->which == ESS_ALLEGRO_1) { 1679 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4); 1680 data |= IN_CLK_12MHZ_SELECT; 1681 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4); 1682 } 1683 1684 data = m3_rd_1(sc, ASSP_CONTROL_A); 1685 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 1686 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/ 1687 data |= ASSP_0_WS_ENABLE; 1688 m3_wr_1(sc, ASSP_CONTROL_A, data); 1689 1690 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP); 1691 } 1692 1693 static void 1694 m3_enable_ints(struct sc_info *sc) 1695 { 1696 u_int8_t data; 1697 1698 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); 1699 data = m3_rd_1(sc, ASSP_CONTROL_C); 1700 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE); 1701 } 1702 1703 static void 1704 m3_amp_enable(struct sc_info *sc) 1705 { 1706 u_int32_t gpo, polarity_port, polarity; 1707 u_int16_t data; 1708 1709 M3_LOCK_ASSERT(sc); 1710 1711 switch (sc->which) { 1712 case ESS_ALLEGRO_1: 1713 polarity_port = 0x1800; 1714 break; 1715 case ESS_MAESTRO3: 1716 polarity_port = 0x1100; 1717 break; 1718 default: 1719 panic("bad sc->which"); 1720 } 1721 gpo = (polarity_port >> 8) & 0x0f; 1722 polarity = polarity_port >> 12; 1723 polarity = !polarity; /* enable */ 1724 polarity = polarity << gpo; 1725 gpo = 1 << gpo; 1726 m3_wr_2(sc, GPIO_MASK, ~gpo); 1727 data = m3_rd_2(sc, GPIO_DIRECTION); 1728 m3_wr_2(sc, GPIO_DIRECTION, data | gpo); 1729 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity; 1730 m3_wr_2(sc, GPIO_DATA, data); 1731 m3_wr_2(sc, GPIO_MASK, ~0); 1732 } 1733 1734 static void 1735 m3_codec_reset(struct sc_info *sc) 1736 { 1737 u_int16_t data, dir; 1738 int retry = 0; 1739 1740 M3_LOCK_ASSERT(sc); 1741 do { 1742 data = m3_rd_2(sc, GPIO_DIRECTION); 1743 dir = data | 0x10; /* assuming pci bus master? */ 1744 1745 /* [[remote_codec_config]] */ 1746 data = m3_rd_2(sc, RING_BUS_CTRL_B); 1747 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); 1748 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL); 1749 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); 1750 data = m3_rd_2(sc, SDO_IN_DEST_CTRL); 1751 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); 1752 1753 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); 1754 DELAY(20); 1755 1756 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); 1757 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); 1758 m3_wr_2(sc, GPIO_DATA, 0); 1759 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); 1760 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/ 1761 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); 1762 DELAY(5); 1763 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | 1764 SERIAL_AC_LINK_ENABLE); 1765 m3_wr_2(sc, GPIO_MASK, ~0); 1766 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/ 1767 1768 /* [[try read vendor]] */ 1769 data = m3_rdcd(NULL, sc, 0x7c); 1770 if ((data == 0) || (data == 0xffff)) { 1771 retry++; 1772 if (retry > 3) { 1773 device_printf(sc->dev, "Codec reset failed\n"); 1774 break; 1775 } 1776 device_printf(sc->dev, "Codec reset retry\n"); 1777 } else retry = 0; 1778 } while (retry); 1779 } 1780 1781 static device_method_t m3_methods[] = { 1782 DEVMETHOD(device_probe, m3_pci_probe), 1783 DEVMETHOD(device_attach, m3_pci_attach), 1784 DEVMETHOD(device_detach, m3_pci_detach), 1785 DEVMETHOD(device_suspend, m3_pci_suspend), 1786 DEVMETHOD(device_resume, m3_pci_resume), 1787 DEVMETHOD(device_shutdown, m3_pci_shutdown), 1788 { 0, 0 } 1789 }; 1790 1791 static driver_t m3_driver = { 1792 "pcm", 1793 m3_methods, 1794 PCM_SOFTC_SIZE, 1795 }; 1796 1797 DRIVER_MODULE(snd_maestro3, pci, m3_driver, 0, 0); 1798 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1799 MODULE_VERSION(snd_maestro3, 1);
Cache object: 27430e747fd4f7e6dd5292c7371ef230
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