Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/maestro_reg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 /*- 2 * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: maestro_reg.h,v 1.10 2000/08/29 17:27:29 taku Exp $ 27 * $FreeBSD$ 28 */ 29 30 #ifndef MAESTRO_REG_H_INCLUDED 31 #define MAESTRO_REG_H_INCLUDED 32 33 /* ----------------------------- 34 * PCI config registers 35 */ 36 37 /* Legacy emulation */ 38 #define CONF_LEGACY 0x40 39 40 #define LEGACY_DISABLED 0x8000 41 42 /* Chip configurations */ 43 #define CONF_MAESTRO 0x50 44 #define MAESTRO_CHIBUS 0x00100000 45 #define MAESTRO_POSTEDWRITE 0x00000080 46 #define MAESTRO_DMA_PCITIMING 0x00000040 47 #define MAESTRO_SWAP_LR 0x00000010 48 49 /* ACPI configurations */ 50 #define CONF_ACPI_STOPCLOCK 0x54 51 #define ACPI_PART_2ndC_CLOCK 15 52 #define ACPI_PART_CODEC_CLOCK 14 53 #define ACPI_PART_978 13 /* Docking station or something */ 54 #define ACPI_PART_SPDIF 12 55 #define ACPI_PART_GLUE 11 /* What? */ 56 #define ACPI_PART_DAA 10 57 #define ACPI_PART_PCI_IF 9 58 #define ACPI_PART_HW_VOL 8 59 #define ACPI_PART_GPIO 7 60 #define ACPI_PART_ASSP 6 61 #define ACPI_PART_SB 5 62 #define ACPI_PART_FM 4 63 #define ACPI_PART_RINGBUS 3 64 #define ACPI_PART_MIDI 2 65 #define ACPI_PART_GAME_PORT 1 66 #define ACPI_PART_WP 0 67 68 /* Power management */ 69 #define CONF_PM_PTR 0x34 /* BYTE R */ 70 #define PM_CID 0 /* BYTE R */ 71 #define PPMI_CID 1 72 #define PM_CTRL 4 /* BYTE RW */ 73 #define PPMI_D0 0 /* Full power */ 74 #define PPMI_D1 1 /* Medium power */ 75 #define PPMI_D2 2 /* Low power */ 76 #define PPMI_D3 3 /* Turned off */ 77 78 79 /* ----------------------------- 80 * I/O ports 81 */ 82 83 /* Direct Sound Processor (aka WP) */ 84 #define PORT_DSP_DATA 0x00 /* WORD RW */ 85 #define PORT_DSP_INDEX 0x02 /* WORD RW */ 86 #define PORT_INT_STAT 0x04 /* WORD RW */ 87 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 88 89 /* WaveCache */ 90 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 91 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 92 #define WAVCACHE_PCMBAR 0x1fc 93 #define WAVCACHE_WTBAR 0x1f0 94 #define WAVCACHE_BASEADDR_SHIFT 12 95 96 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 97 #define WAVCACHE_CHCTL_U8 0x0004 98 #define WAVCACHE_CHCTL_STEREO 0x0002 99 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001 100 101 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 102 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200 103 #define WAVCACHE_ENABLED 0x0100 104 #define WAVCACHE_CH_60_ENABLED 0x0080 105 #define WAVCACHE_WTSIZE_MASK 0x0060 106 #define WAVCACHE_WTSIZE_1MB 0x0000 107 #define WAVCACHE_WTSIZE_2MB 0x0020 108 #define WAVCACHE_WTSIZE_4MB 0x0040 109 #define WAVCACHE_WTSIZE_8MB 0x0060 110 #define WAVCACHE_SGC_MASK 0x000c 111 #define WAVCACHE_SGC_DISABLED 0x0000 112 #define WAVCACHE_SGC_40_47 0x0004 113 #define WAVCACHE_SGC_32_47 0x0008 114 #define WAVCACHE_TESTMODE 0x0001 115 116 /* Host Interruption */ 117 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 118 #define HOSTINT_CTRL_SOFT_RESET 0x8000 119 #define HOSTINT_CTRL_DSOUND_RESET 0x4000 120 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 121 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 122 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 123 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 124 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 125 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 126 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 127 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 128 129 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 130 #define HOSTINT_STAT_HWVOL 0x40 131 #define HOSTINT_STAT_ASSP 0x10 132 #define HOSTINT_STAT_ISDN 0x08 133 #define HOSTINT_STAT_DSOUND 0x04 134 #define HOSTINT_STAT_MPU401 0x02 135 #define HOSTINT_STAT_SB 0x01 136 137 /* Hardware volume */ 138 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 139 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 140 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 141 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 142 #define HWVOL_NOP 0x88 143 #define HWVOL_MUTE 0x99 144 #define HWVOL_UP 0xaa 145 #define HWVOL_DOWN 0x66 146 147 /* CODEC */ 148 #define PORT_CODEC_CMD 0x30 /* BYTE W */ 149 #define CODEC_CMD_READ 0x80 150 #define CODEC_CMD_WRITE 0x00 151 #define CODEC_CMD_ADDR_MASK 0x7f 152 153 #define PORT_CODEC_STAT 0x30 /* BYTE R */ 154 #define CODEC_STAT_MASK 0x01 155 #define CODEC_STAT_RW_DONE 0x00 156 #define CODEC_STAT_PROGLESS 0x01 157 158 #define PORT_CODEC_REG 0x32 /* WORD RW */ 159 160 /* Ring bus control */ 161 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 162 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000 163 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 164 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 165 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000 166 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 167 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 168 169 #define RINGBUS_SRC_MIC 20 170 #define RINGBUS_SRC_I2S 16 171 #define RINGBUS_SRC_ADC 12 172 #define RINGBUS_SRC_MODEM 8 173 #define RINGBUS_SRC_DSOUND 4 174 #define RINGBUS_SRC_ASSP 0 175 176 #define RINGBUS_DEST_MONORAL 000 177 #define RINGBUS_DEST_STEREO 010 178 #define RINGBUS_DEST_NONE 0 179 #define RINGBUS_DEST_DAC 1 180 #define RINGBUS_DEST_MODEM_IN 2 181 #define RINGBUS_DEST_RESERVED3 3 182 #define RINGBUS_DEST_DSOUND_IN 4 183 #define RINGBUS_DEST_ASSP_IN 5 184 185 /* General Purpose I/O */ 186 #define PORT_GPIO_DATA 0x60 /* WORD RW */ 187 #define PORT_GPIO_MASK 0x64 /* WORD RW */ 188 #define PORT_GPIO_DIR 0x68 /* WORD RW */ 189 190 /* Application Specific Signal Processor */ 191 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 192 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 193 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 194 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 195 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 196 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 197 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 198 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 199 200 201 /* ----------------------------- 202 * Wave Processor Indexed Data Registers. 203 */ 204 205 #define WPREG_DATA_PORT 0 206 #define WPREG_CRAM_PTR 1 207 #define WPREG_CRAM_DATA 2 208 #define WPREG_WAVE_DATA 3 209 #define WPREG_WAVE_PTR_LOW 4 210 #define WPREG_WAVE_PTR_HIGH 5 211 212 #define WPREG_TIMER_FREQ 6 213 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 214 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5 215 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 216 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0 217 218 #define WPREG_WAVE_ROMRAM 7 219 #define WP_WAVE_VIRTUAL_ENABLED 0x0400 220 #define WP_WAVE_8BITRAM_ENABLED 0x0200 221 #define WP_WAVE_DRAM_ENABLED 0x0100 222 #define WP_WAVE_RAMSPLIT_MASK 0x00ff 223 #define WP_WAVE_RAMSPLIT_SHIFT 0 224 225 #define WPREG_BASE 12 226 #define WP_PARAOUT_BASE_MASK 0xf000 227 #define WP_PARAOUT_BASE_SHIFT 12 228 #define WP_PARAIN_BASE_MASK 0x0f00 229 #define WP_PARAIN_BASE_SHIFT 8 230 #define WP_SERIAL0_BASE_MASK 0x00f0 231 #define WP_SERIAL0_BASE_SHIFT 4 232 #define WP_SERIAL1_BASE_MASK 0x000f 233 #define WP_SERIAL1_BASE_SHIFT 0 234 235 #define WPREG_TIMER_ENABLE 17 236 #define WPREG_TIMER_START 23 237 238 239 /* ----------------------------- 240 * Audio Processing Unit. 241 */ 242 #define APUREG_APUTYPE 0 243 #define APU_DMA_ENABLED 0x4000 244 #define APU_INT_ON_LOOP 0x2000 245 #define APU_ENDCURVE 0x1000 246 #define APU_APUTYPE_MASK 0x00f0 247 #define APU_FILTERTYPE_MASK 0x000c 248 #define APU_FILTERQ_MASK 0x0003 249 250 /* APU types */ 251 #define APU_APUTYPE_SHIFT 4 252 253 #define APUTYPE_INACTIVE 0 254 #define APUTYPE_16BITLINEAR 1 255 #define APUTYPE_16BITSTEREO 2 256 #define APUTYPE_8BITLINEAR 3 257 #define APUTYPE_8BITSTEREO 4 258 #define APUTYPE_8BITDIFF 5 259 #define APUTYPE_DIGITALDELAY 6 260 #define APUTYPE_DUALTAP_READER 7 261 #define APUTYPE_CORRELATOR 8 262 #define APUTYPE_INPUTMIXER 9 263 #define APUTYPE_WAVETABLE 10 264 #define APUTYPE_RATECONV 11 265 #define APUTYPE_16BITPINGPONG 12 266 /* APU type 13 through 15 are reserved. */ 267 268 /* Filter types */ 269 #define APU_FILTERTYPE_SHIFT 2 270 271 #define FILTERTYPE_2POLE_LOPASS 0 272 #define FILTERTYPE_2POLE_BANDPASS 1 273 #define FILTERTYPE_2POLE_HIPASS 2 274 #define FILTERTYPE_1POLE_LOPASS 3 275 #define FILTERTYPE_1POLE_HIPASS 4 276 #define FILTERTYPE_PASSTHROUGH 5 277 278 /* Filter Q */ 279 #define APU_FILTERQ_SHIFT 0 280 281 #define FILTERQ_LESSQ 0 282 #define FILTERQ_MOREQ 3 283 284 /* APU register 2 */ 285 #define APUREG_FREQ_LOBYTE 2 286 #define APU_FREQ_LOBYTE_MASK 0xff00 287 #define APU_plus6dB 0x0010 288 289 /* APU register 3 */ 290 #define APUREG_FREQ_HIWORD 3 291 #define APU_FREQ_HIWORD_MASK 0x0fff 292 293 /* Frequency */ 294 #define APU_FREQ_LOBYTE_SHIFT 8 295 #define APU_FREQ_HIWORD_SHIFT 0 296 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 297 298 /* APU register 4 */ 299 #define APUREG_WAVESPACE 4 300 #define APU_STEREO 0x8000 301 #define APU_USE_SYSMEM 0x4000 302 #define APU_PCMBAR_MASK 0x6000 303 #define APU_64KPAGE_MASK 0xff00 304 305 /* PCM Base Address Register selection */ 306 #define APU_PCMBAR_SHIFT 13 307 308 /* 64KW (==128KB) Page */ 309 #define APU_64KPAGE_SHIFT 8 310 311 /* APU register 5 - 7 */ 312 #define APUREG_CURPTR 5 313 #define APUREG_ENDPTR 6 314 #define APUREG_LOOPLEN 7 315 316 /* APU register 9 */ 317 #define APUREG_AMPLITUDE 9 318 #define APU_AMPLITUDE_NOW_MASK 0xff00 319 #define APU_AMPLITUDE_DEST_MASK 0x00ff 320 321 /* Amplitude now? */ 322 #define APU_AMPLITUDE_NOW_SHIFT 8 323 324 /* APU register 10 */ 325 #define APUREG_POSITION 10 326 #define APU_RADIUS_MASK 0x00c0 327 #define APU_PAN_MASK 0x003f 328 329 /* Radius control. */ 330 #define APU_RADIUS_SHIFT 6 331 #define RADIUS_CENTERCIRCLE 0 332 #define RADIUS_MIDDLE 1 333 #define RADIUS_OUTSIDE 2 334 335 /* Polar pan. */ 336 #define APU_PAN_SHIFT 0 337 #define PAN_RIGHT 0x00 338 #define PAN_FRONT 0x08 339 #define PAN_LEFT 0x10 340 341 342 /* ----------------------------- 343 * Limits. 344 */ 345 #define WPWA_MAX ((1 << 22) - 1) 346 #define WPWA_MAXADDR ((1 << 23) - 1) 347 #define MAESTRO_MAXADDR ((1 << 28) - 1) 348 349 #endif /* MAESTRO_REG_H_INCLUDED */
Cache object: b072fd020e4a9487f9287049da5720e7
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