Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/t4dwave.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifdef HAVE_KERNEL_OPTION_HEADERS 30 #include "opt_snd.h" 31 #endif 32 33 #include <dev/sound/pcm/sound.h> 34 #include <dev/sound/pcm/ac97.h> 35 #include <dev/sound/pci/t4dwave.h> 36 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 SND_DECLARE_FILE("$FreeBSD$"); 41 42 /* -------------------------------------------------------------------- */ 43 44 #define TDX_PCI_ID 0x20001023 45 #define TNX_PCI_ID 0x20011023 46 #define ALI_PCI_ID 0x545110b9 47 #define SPA_PCI_ID 0x70181039 48 49 #define TR_DEFAULT_BUFSZ 0x1000 50 /* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */ 51 #define ALI_BUFSZ 0x10000 52 #define TR_BUFALGN 0x8 53 #define TR_TIMEOUT_CDC 0xffff 54 #define TR_MAXHWCH 64 55 #define ALI_MAXHWCH 32 56 #define TR_MAXPLAYCH 4 57 #define ALI_MAXPLAYCH 1 58 /* 59 * Though, it's not clearly documented in the 4DWAVE datasheet, the 60 * DX and NX chips can't handle DMA addresses located above 1GB as the 61 * LBA (loop begin address) register which holds the DMA base address 62 * is 32-bit, but the two MSBs are used for other purposes. 63 */ 64 #define TR_MAXADDR ((1U << 30) - 1) 65 #define ALI_MAXADDR ((1U << 31) - 1) 66 67 struct tr_info; 68 69 /* channel registers */ 70 struct tr_chinfo { 71 u_int32_t cso, alpha, fms, fmc, ec; 72 u_int32_t lba; 73 u_int32_t eso, delta; 74 u_int32_t rvol, cvol; 75 u_int32_t gvsel, pan, vol, ctrl; 76 u_int32_t active:1, was_active:1; 77 int index, bufhalf; 78 struct snd_dbuf *buffer; 79 struct pcm_channel *channel; 80 struct tr_info *parent; 81 }; 82 83 struct tr_rchinfo { 84 u_int32_t delta; 85 u_int32_t active:1, was_active:1; 86 struct snd_dbuf *buffer; 87 struct pcm_channel *channel; 88 struct tr_info *parent; 89 }; 90 91 /* device private data */ 92 struct tr_info { 93 u_int32_t type; 94 u_int32_t rev; 95 96 bus_space_tag_t st; 97 bus_space_handle_t sh; 98 bus_dma_tag_t parent_dmat; 99 100 struct resource *reg, *irq; 101 int regtype, regid, irqid; 102 void *ih; 103 104 struct mtx *lock; 105 106 u_int32_t hwchns; 107 u_int32_t playchns; 108 unsigned int bufsz; 109 110 struct tr_chinfo chinfo[TR_MAXPLAYCH]; 111 struct tr_rchinfo recchinfo; 112 }; 113 114 /* -------------------------------------------------------------------- */ 115 116 static u_int32_t tr_recfmt[] = { 117 SND_FORMAT(AFMT_U8, 1, 0), 118 SND_FORMAT(AFMT_U8, 2, 0), 119 SND_FORMAT(AFMT_S8, 1, 0), 120 SND_FORMAT(AFMT_S8, 2, 0), 121 SND_FORMAT(AFMT_S16_LE, 1, 0), 122 SND_FORMAT(AFMT_S16_LE, 2, 0), 123 SND_FORMAT(AFMT_U16_LE, 1, 0), 124 SND_FORMAT(AFMT_U16_LE, 2, 0), 125 0 126 }; 127 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0}; 128 129 static u_int32_t tr_playfmt[] = { 130 SND_FORMAT(AFMT_U8, 1, 0), 131 SND_FORMAT(AFMT_U8, 2, 0), 132 SND_FORMAT(AFMT_S8, 1, 0), 133 SND_FORMAT(AFMT_S8, 2, 0), 134 SND_FORMAT(AFMT_S16_LE, 1, 0), 135 SND_FORMAT(AFMT_S16_LE, 2, 0), 136 SND_FORMAT(AFMT_U16_LE, 1, 0), 137 SND_FORMAT(AFMT_U16_LE, 2, 0), 138 0 139 }; 140 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0}; 141 142 /* -------------------------------------------------------------------- */ 143 144 /* Hardware */ 145 146 static u_int32_t 147 tr_rd(struct tr_info *tr, int regno, int size) 148 { 149 switch(size) { 150 case 1: 151 return bus_space_read_1(tr->st, tr->sh, regno); 152 case 2: 153 return bus_space_read_2(tr->st, tr->sh, regno); 154 case 4: 155 return bus_space_read_4(tr->st, tr->sh, regno); 156 default: 157 return 0xffffffff; 158 } 159 } 160 161 static void 162 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size) 163 { 164 switch(size) { 165 case 1: 166 bus_space_write_1(tr->st, tr->sh, regno, data); 167 break; 168 case 2: 169 bus_space_write_2(tr->st, tr->sh, regno, data); 170 break; 171 case 4: 172 bus_space_write_4(tr->st, tr->sh, regno, data); 173 break; 174 } 175 } 176 177 /* -------------------------------------------------------------------- */ 178 /* ac97 codec */ 179 180 static int 181 tr_rdcd(kobj_t obj, void *devinfo, int regno) 182 { 183 struct tr_info *tr = (struct tr_info *)devinfo; 184 int i, j, treg, trw; 185 186 switch (tr->type) { 187 case SPA_PCI_ID: 188 treg=SPA_REG_CODECRD; 189 trw=SPA_CDC_RWSTAT; 190 break; 191 case ALI_PCI_ID: 192 if (tr->rev > 0x01) 193 treg=TDX_REG_CODECWR; 194 else 195 treg=TDX_REG_CODECRD; 196 trw=TDX_CDC_RWSTAT; 197 break; 198 case TDX_PCI_ID: 199 treg=TDX_REG_CODECRD; 200 trw=TDX_CDC_RWSTAT; 201 break; 202 case TNX_PCI_ID: 203 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD; 204 trw=TNX_CDC_RWSTAT; 205 break; 206 default: 207 printf("!!! tr_rdcd defaulted !!!\n"); 208 return -1; 209 } 210 211 i = j = 0; 212 213 regno &= 0x7f; 214 snd_mtxlock(tr->lock); 215 if (tr->type == ALI_PCI_ID) { 216 u_int32_t chk1, chk2; 217 j = trw; 218 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 219 j = tr_rd(tr, treg, 4); 220 if (i > 0) { 221 chk1 = tr_rd(tr, 0xc8, 4); 222 chk2 = tr_rd(tr, 0xc8, 4); 223 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 224 i--) 225 chk2 = tr_rd(tr, 0xc8, 4); 226 } 227 } 228 if (tr->type != ALI_PCI_ID || i > 0) { 229 tr_wr(tr, treg, regno | trw, 4); 230 j=trw; 231 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 232 j=tr_rd(tr, treg, 4); 233 } 234 snd_mtxunlock(tr->lock); 235 if (i == 0) printf("codec timeout during read of register %x\n", regno); 236 return (j >> TR_CDC_DATA) & 0xffff; 237 } 238 239 static int 240 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 241 { 242 struct tr_info *tr = (struct tr_info *)devinfo; 243 int i, j, treg, trw; 244 245 switch (tr->type) { 246 case SPA_PCI_ID: 247 treg=SPA_REG_CODECWR; 248 trw=SPA_CDC_RWSTAT; 249 break; 250 case ALI_PCI_ID: 251 case TDX_PCI_ID: 252 treg=TDX_REG_CODECWR; 253 trw=TDX_CDC_RWSTAT; 254 break; 255 case TNX_PCI_ID: 256 treg=TNX_REG_CODECWR; 257 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0); 258 break; 259 default: 260 printf("!!! tr_wrcd defaulted !!!"); 261 return -1; 262 } 263 264 i = 0; 265 266 regno &= 0x7f; 267 #if 0 268 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno)); 269 #endif 270 j=trw; 271 snd_mtxlock(tr->lock); 272 if (tr->type == ALI_PCI_ID) { 273 j = trw; 274 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 275 j = tr_rd(tr, treg, 4); 276 if (i > 0) { 277 u_int32_t chk1, chk2; 278 chk1 = tr_rd(tr, 0xc8, 4); 279 chk2 = tr_rd(tr, 0xc8, 4); 280 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 281 i--) 282 chk2 = tr_rd(tr, 0xc8, 4); 283 } 284 } 285 if (tr->type != ALI_PCI_ID || i > 0) { 286 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--) 287 j=tr_rd(tr, treg, 4); 288 if (tr->type == ALI_PCI_ID && tr->rev > 0x01) 289 trw |= 0x0100; 290 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4); 291 } 292 #if 0 293 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno)); 294 #endif 295 snd_mtxunlock(tr->lock); 296 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data); 297 return (i > 0)? 0 : -1; 298 } 299 300 static kobj_method_t tr_ac97_methods[] = { 301 KOBJMETHOD(ac97_read, tr_rdcd), 302 KOBJMETHOD(ac97_write, tr_wrcd), 303 KOBJMETHOD_END 304 }; 305 AC97_DECLARE(tr_ac97); 306 307 /* -------------------------------------------------------------------- */ 308 /* playback channel interrupts */ 309 310 #if 0 311 static u_int32_t 312 tr_testint(struct tr_chinfo *ch) 313 { 314 struct tr_info *tr = ch->parent; 315 int bank, chan; 316 317 bank = (ch->index & 0x20) ? 1 : 0; 318 chan = ch->index & 0x1f; 319 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan); 320 } 321 #endif 322 323 static void 324 tr_clrint(struct tr_chinfo *ch) 325 { 326 struct tr_info *tr = ch->parent; 327 int bank, chan; 328 329 bank = (ch->index & 0x20) ? 1 : 0; 330 chan = ch->index & 0x1f; 331 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4); 332 } 333 334 static void 335 tr_enaint(struct tr_chinfo *ch, int enable) 336 { 337 struct tr_info *tr = ch->parent; 338 u_int32_t i, reg; 339 int bank, chan; 340 341 snd_mtxlock(tr->lock); 342 bank = (ch->index & 0x20) ? 1 : 0; 343 chan = ch->index & 0x1f; 344 reg = bank? TR_REG_INTENB : TR_REG_INTENA; 345 346 i = tr_rd(tr, reg, 4); 347 i &= ~(1 << chan); 348 i |= (enable? 1 : 0) << chan; 349 350 tr_clrint(ch); 351 tr_wr(tr, reg, i, 4); 352 snd_mtxunlock(tr->lock); 353 } 354 355 /* playback channels */ 356 357 static void 358 tr_selch(struct tr_chinfo *ch) 359 { 360 struct tr_info *tr = ch->parent; 361 int i; 362 363 i = tr_rd(tr, TR_REG_CIR, 4); 364 i &= ~TR_CIR_MASK; 365 i |= ch->index & 0x3f; 366 tr_wr(tr, TR_REG_CIR, i, 4); 367 } 368 369 static void 370 tr_startch(struct tr_chinfo *ch) 371 { 372 struct tr_info *tr = ch->parent; 373 int bank, chan; 374 375 bank = (ch->index & 0x20) ? 1 : 0; 376 chan = ch->index & 0x1f; 377 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4); 378 } 379 380 static void 381 tr_stopch(struct tr_chinfo *ch) 382 { 383 struct tr_info *tr = ch->parent; 384 int bank, chan; 385 386 bank = (ch->index & 0x20) ? 1 : 0; 387 chan = ch->index & 0x1f; 388 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4); 389 } 390 391 static void 392 tr_wrch(struct tr_chinfo *ch) 393 { 394 struct tr_info *tr = ch->parent; 395 u_int32_t cr[TR_CHN_REGS], i; 396 397 ch->gvsel &= 0x00000001; 398 ch->fmc &= 0x00000003; 399 ch->fms &= 0x0000000f; 400 ch->ctrl &= 0x0000000f; 401 ch->pan &= 0x0000007f; 402 ch->rvol &= 0x0000007f; 403 ch->cvol &= 0x0000007f; 404 ch->vol &= 0x000000ff; 405 ch->ec &= 0x00000fff; 406 ch->alpha &= 0x00000fff; 407 ch->delta &= 0x0000ffff; 408 if (tr->type == ALI_PCI_ID) 409 ch->lba &= ALI_MAXADDR; 410 else 411 ch->lba &= TR_MAXADDR; 412 413 cr[1]=ch->lba; 414 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol); 415 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec); 416 417 switch (tr->type) { 418 case SPA_PCI_ID: 419 case ALI_PCI_ID: 420 case TDX_PCI_ID: 421 ch->cso &= 0x0000ffff; 422 ch->eso &= 0x0000ffff; 423 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms); 424 cr[2]=(ch->eso<<16) | (ch->delta); 425 break; 426 case TNX_PCI_ID: 427 ch->cso &= 0x00ffffff; 428 ch->eso &= 0x00ffffff; 429 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso); 430 cr[2]=((ch->delta>>8)<<24) | (ch->eso); 431 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14); 432 break; 433 } 434 snd_mtxlock(tr->lock); 435 tr_selch(ch); 436 for (i=0; i<TR_CHN_REGS; i++) 437 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4); 438 snd_mtxunlock(tr->lock); 439 } 440 441 static void 442 tr_rdch(struct tr_chinfo *ch) 443 { 444 struct tr_info *tr = ch->parent; 445 u_int32_t cr[5], i; 446 447 snd_mtxlock(tr->lock); 448 tr_selch(ch); 449 for (i=0; i<5; i++) 450 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4); 451 snd_mtxunlock(tr->lock); 452 453 if (tr->type == ALI_PCI_ID) 454 ch->lba=(cr[1] & ALI_MAXADDR); 455 else 456 ch->lba=(cr[1] & TR_MAXADDR); 457 ch->fmc= (cr[3] & 0x0000c000) >> 14; 458 ch->rvol= (cr[3] & 0x00003f80) >> 7; 459 ch->cvol= (cr[3] & 0x0000007f); 460 ch->gvsel= (cr[4] & 0x80000000) >> 31; 461 ch->pan= (cr[4] & 0x7f000000) >> 24; 462 ch->vol= (cr[4] & 0x00ff0000) >> 16; 463 ch->ctrl= (cr[4] & 0x0000f000) >> 12; 464 ch->ec= (cr[4] & 0x00000fff); 465 switch(tr->type) { 466 case SPA_PCI_ID: 467 case ALI_PCI_ID: 468 case TDX_PCI_ID: 469 ch->cso= (cr[0] & 0xffff0000) >> 16; 470 ch->alpha= (cr[0] & 0x0000fff0) >> 4; 471 ch->fms= (cr[0] & 0x0000000f); 472 ch->eso= (cr[2] & 0xffff0000) >> 16; 473 ch->delta= (cr[2] & 0x0000ffff); 474 break; 475 case TNX_PCI_ID: 476 ch->cso= (cr[0] & 0x00ffffff); 477 ch->eso= (cr[2] & 0x00ffffff); 478 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24); 479 ch->alpha= (cr[3] & 0xfff00000) >> 20; 480 ch->fms= (cr[3] & 0x000f0000) >> 16; 481 break; 482 } 483 } 484 485 static u_int32_t 486 tr_fmttobits(u_int32_t fmt) 487 { 488 u_int32_t bits; 489 490 bits = 0; 491 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0; 492 bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0; 493 bits |= (fmt & AFMT_16BIT)? 0x8 : 0; 494 495 return bits; 496 } 497 498 /* -------------------------------------------------------------------- */ 499 /* channel interface */ 500 501 static void * 502 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 503 { 504 struct tr_info *tr = devinfo; 505 struct tr_chinfo *ch; 506 507 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction")); 508 ch = &tr->chinfo[tr->playchns]; 509 ch->index = tr->playchns++; 510 ch->buffer = b; 511 ch->parent = tr; 512 ch->channel = c; 513 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 514 return NULL; 515 516 return ch; 517 } 518 519 static int 520 trpchan_setformat(kobj_t obj, void *data, u_int32_t format) 521 { 522 struct tr_chinfo *ch = data; 523 524 ch->ctrl = tr_fmttobits(format) | 0x01; 525 526 return 0; 527 } 528 529 static u_int32_t 530 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 531 { 532 struct tr_chinfo *ch = data; 533 534 ch->delta = (speed << 12) / 48000; 535 return (ch->delta * 48000) >> 12; 536 } 537 538 static u_int32_t 539 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 540 { 541 struct tr_chinfo *ch = data; 542 543 sndbuf_resize(ch->buffer, 2, blocksize); 544 return blocksize; 545 } 546 547 static int 548 trpchan_trigger(kobj_t obj, void *data, int go) 549 { 550 struct tr_chinfo *ch = data; 551 552 if (!PCMTRIG_COMMON(go)) 553 return 0; 554 555 if (go == PCMTRIG_START) { 556 ch->fmc = 3; 557 ch->fms = 0; 558 ch->ec = 0; 559 ch->alpha = 0; 560 ch->lba = sndbuf_getbufaddr(ch->buffer); 561 ch->cso = 0; 562 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1; 563 ch->rvol = ch->cvol = 0x7f; 564 ch->gvsel = 0; 565 ch->pan = 0; 566 ch->vol = 0; 567 ch->bufhalf = 0; 568 tr_wrch(ch); 569 tr_enaint(ch, 1); 570 tr_startch(ch); 571 ch->active = 1; 572 } else { 573 tr_stopch(ch); 574 ch->active = 0; 575 } 576 577 return 0; 578 } 579 580 static u_int32_t 581 trpchan_getptr(kobj_t obj, void *data) 582 { 583 struct tr_chinfo *ch = data; 584 585 tr_rdch(ch); 586 return ch->cso * sndbuf_getalign(ch->buffer); 587 } 588 589 static struct pcmchan_caps * 590 trpchan_getcaps(kobj_t obj, void *data) 591 { 592 return &tr_playcaps; 593 } 594 595 static kobj_method_t trpchan_methods[] = { 596 KOBJMETHOD(channel_init, trpchan_init), 597 KOBJMETHOD(channel_setformat, trpchan_setformat), 598 KOBJMETHOD(channel_setspeed, trpchan_setspeed), 599 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize), 600 KOBJMETHOD(channel_trigger, trpchan_trigger), 601 KOBJMETHOD(channel_getptr, trpchan_getptr), 602 KOBJMETHOD(channel_getcaps, trpchan_getcaps), 603 KOBJMETHOD_END 604 }; 605 CHANNEL_DECLARE(trpchan); 606 607 /* -------------------------------------------------------------------- */ 608 /* rec channel interface */ 609 610 static void * 611 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 612 { 613 struct tr_info *tr = devinfo; 614 struct tr_rchinfo *ch; 615 616 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction")); 617 ch = &tr->recchinfo; 618 ch->buffer = b; 619 ch->parent = tr; 620 ch->channel = c; 621 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 622 return NULL; 623 624 return ch; 625 } 626 627 static int 628 trrchan_setformat(kobj_t obj, void *data, u_int32_t format) 629 { 630 struct tr_rchinfo *ch = data; 631 struct tr_info *tr = ch->parent; 632 u_int32_t i, bits; 633 634 bits = tr_fmttobits(format); 635 /* set # of samples between interrupts */ 636 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1; 637 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4); 638 /* set sample format */ 639 i = 0x18 | (bits << 4); 640 tr_wr(tr, TR_REG_SBCTRL, i, 1); 641 642 return 0; 643 } 644 645 static u_int32_t 646 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 647 { 648 struct tr_rchinfo *ch = data; 649 struct tr_info *tr = ch->parent; 650 651 /* setup speed */ 652 ch->delta = (48000 << 12) / speed; 653 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2); 654 655 /* return closest possible speed */ 656 return (48000 << 12) / ch->delta; 657 } 658 659 static u_int32_t 660 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 661 { 662 struct tr_rchinfo *ch = data; 663 664 sndbuf_resize(ch->buffer, 2, blocksize); 665 666 return blocksize; 667 } 668 669 static int 670 trrchan_trigger(kobj_t obj, void *data, int go) 671 { 672 struct tr_rchinfo *ch = data; 673 struct tr_info *tr = ch->parent; 674 u_int32_t i; 675 676 if (!PCMTRIG_COMMON(go)) 677 return 0; 678 679 if (go == PCMTRIG_START) { 680 /* set up dma mode regs */ 681 tr_wr(tr, TR_REG_DMAR15, 0, 1); 682 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03; 683 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1); 684 /* set up base address */ 685 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4); 686 /* set up buffer size */ 687 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff; 688 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4); 689 /* start */ 690 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1); 691 ch->active = 1; 692 } else { 693 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1); 694 ch->active = 0; 695 } 696 697 /* return 0 if ok */ 698 return 0; 699 } 700 701 static u_int32_t 702 trrchan_getptr(kobj_t obj, void *data) 703 { 704 struct tr_rchinfo *ch = data; 705 struct tr_info *tr = ch->parent; 706 707 /* return current byte offset of channel */ 708 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer); 709 } 710 711 static struct pcmchan_caps * 712 trrchan_getcaps(kobj_t obj, void *data) 713 { 714 return &tr_reccaps; 715 } 716 717 static kobj_method_t trrchan_methods[] = { 718 KOBJMETHOD(channel_init, trrchan_init), 719 KOBJMETHOD(channel_setformat, trrchan_setformat), 720 KOBJMETHOD(channel_setspeed, trrchan_setspeed), 721 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize), 722 KOBJMETHOD(channel_trigger, trrchan_trigger), 723 KOBJMETHOD(channel_getptr, trrchan_getptr), 724 KOBJMETHOD(channel_getcaps, trrchan_getcaps), 725 KOBJMETHOD_END 726 }; 727 CHANNEL_DECLARE(trrchan); 728 729 /* -------------------------------------------------------------------- */ 730 /* The interrupt handler */ 731 732 static void 733 tr_intr(void *p) 734 { 735 struct tr_info *tr = (struct tr_info *)p; 736 struct tr_chinfo *ch; 737 u_int32_t active, mask, bufhalf, chnum, intsrc; 738 int tmp; 739 740 intsrc = tr_rd(tr, TR_REG_MISCINT, 4); 741 if (intsrc & TR_INT_ADDR) { 742 chnum = 0; 743 while (chnum < tr->hwchns) { 744 mask = 0x00000001; 745 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); 746 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); 747 if (active) { 748 do { 749 if (active & mask) { 750 tmp = (bufhalf & mask)? 1 : 0; 751 if (chnum < tr->playchns) { 752 ch = &tr->chinfo[chnum]; 753 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */ 754 if (ch->bufhalf != tmp) { 755 chn_intr(ch->channel); 756 ch->bufhalf = tmp; 757 } 758 } 759 } 760 chnum++; 761 mask <<= 1; 762 } while (chnum & 31); 763 } else 764 chnum += 32; 765 766 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4); 767 } 768 } 769 if (intsrc & TR_INT_SB) { 770 chn_intr(tr->recchinfo.channel); 771 tr_rd(tr, TR_REG_SBR9, 1); 772 tr_rd(tr, TR_REG_SBR10, 1); 773 } 774 } 775 776 /* -------------------------------------------------------------------- */ 777 778 /* 779 * Probe and attach the card 780 */ 781 782 static int 783 tr_init(struct tr_info *tr) 784 { 785 switch (tr->type) { 786 case SPA_PCI_ID: 787 tr_wr(tr, SPA_REG_GPIO, 0, 4); 788 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); 789 break; 790 case TDX_PCI_ID: 791 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); 792 break; 793 case TNX_PCI_ID: 794 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4); 795 break; 796 } 797 798 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4); 799 return 0; 800 } 801 802 static int 803 tr_pci_probe(device_t dev) 804 { 805 switch (pci_get_devid(dev)) { 806 case SPA_PCI_ID: 807 device_set_desc(dev, "SiS 7018"); 808 return BUS_PROBE_DEFAULT; 809 case ALI_PCI_ID: 810 device_set_desc(dev, "Acer Labs M5451"); 811 return BUS_PROBE_DEFAULT; 812 case TDX_PCI_ID: 813 device_set_desc(dev, "Trident 4DWave DX"); 814 return BUS_PROBE_DEFAULT; 815 case TNX_PCI_ID: 816 device_set_desc(dev, "Trident 4DWave NX"); 817 return BUS_PROBE_DEFAULT; 818 } 819 820 return ENXIO; 821 } 822 823 static int 824 tr_pci_attach(device_t dev) 825 { 826 struct tr_info *tr; 827 struct ac97_info *codec = NULL; 828 bus_addr_t lowaddr; 829 int i, dacn; 830 char status[SND_STATUSLEN]; 831 832 tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO); 833 tr->type = pci_get_devid(dev); 834 tr->rev = pci_get_revid(dev); 835 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc"); 836 837 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 838 "dac", &i) == 0) { 839 if (i < 1) 840 dacn = 1; 841 else if (i > TR_MAXPLAYCH) 842 dacn = TR_MAXPLAYCH; 843 else 844 dacn = i; 845 } else { 846 switch (tr->type) { 847 case ALI_PCI_ID: 848 dacn = ALI_MAXPLAYCH; 849 break; 850 default: 851 dacn = TR_MAXPLAYCH; 852 break; 853 } 854 } 855 856 pci_enable_busmaster(dev); 857 858 tr->regid = PCIR_BAR(0); 859 tr->regtype = SYS_RES_IOPORT; 860 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid, 861 RF_ACTIVE); 862 if (tr->reg) { 863 tr->st = rman_get_bustag(tr->reg); 864 tr->sh = rman_get_bushandle(tr->reg); 865 } else { 866 device_printf(dev, "unable to map register space\n"); 867 goto bad; 868 } 869 870 if (tr_init(tr) == -1) { 871 device_printf(dev, "unable to initialize the card\n"); 872 goto bad; 873 } 874 tr->playchns = 0; 875 876 codec = AC97_CREATE(dev, tr, tr_ac97); 877 if (codec == NULL) goto bad; 878 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 879 880 tr->irqid = 0; 881 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid, 882 RF_ACTIVE | RF_SHAREABLE); 883 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) { 884 device_printf(dev, "unable to map interrupt\n"); 885 goto bad; 886 } 887 888 if (tr->type == ALI_PCI_ID) { 889 /* 890 * The M5451 generates 31 bit of DMA and in order to do 891 * 32-bit DMA, the 31st bit can be set via its accompanying 892 * ISA bridge. Note that we can't predict whether bus_dma(9) 893 * will actually supply us with a 32-bit buffer and even when 894 * using a low address of BUS_SPACE_MAXADDR_32BIT for both 895 * we might end up with the play buffer being in the 32-bit 896 * range while the record buffer isn't or vice versa. So we 897 * don't enabling the 31st bit. 898 */ 899 lowaddr = ALI_MAXADDR; 900 tr->hwchns = ALI_MAXHWCH; 901 tr->bufsz = ALI_BUFSZ; 902 } else { 903 lowaddr = TR_MAXADDR; 904 tr->hwchns = TR_MAXHWCH; 905 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 906 65536); 907 } 908 909 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), 910 /*alignment*/TR_BUFALGN, 911 /*boundary*/0, 912 /*lowaddr*/lowaddr, 913 /*highaddr*/BUS_SPACE_MAXADDR, 914 /*filter*/NULL, /*filterarg*/NULL, 915 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz, 916 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL, 917 &tr->parent_dmat) != 0) { 918 device_printf(dev, "unable to create dma tag\n"); 919 goto bad; 920 } 921 922 snprintf(status, 64, "at io 0x%jx irq %jd %s", 923 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave)); 924 925 if (pcm_register(dev, tr, dacn, 1)) 926 goto bad; 927 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr); 928 for (i = 0; i < dacn; i++) 929 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr); 930 pcm_setstatus(dev, status); 931 932 return 0; 933 934 bad: 935 if (codec) ac97_destroy(codec); 936 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 937 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih); 938 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 939 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat); 940 if (tr->lock) snd_mtxfree(tr->lock); 941 free(tr, M_DEVBUF); 942 return ENXIO; 943 } 944 945 static int 946 tr_pci_detach(device_t dev) 947 { 948 int r; 949 struct tr_info *tr; 950 951 r = pcm_unregister(dev); 952 if (r) 953 return r; 954 955 tr = pcm_getdevinfo(dev); 956 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 957 bus_teardown_intr(dev, tr->irq, tr->ih); 958 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 959 bus_dma_tag_destroy(tr->parent_dmat); 960 snd_mtxfree(tr->lock); 961 free(tr, M_DEVBUF); 962 963 return 0; 964 } 965 966 static int 967 tr_pci_suspend(device_t dev) 968 { 969 int i; 970 struct tr_info *tr; 971 972 tr = pcm_getdevinfo(dev); 973 974 for (i = 0; i < tr->playchns; i++) { 975 tr->chinfo[i].was_active = tr->chinfo[i].active; 976 if (tr->chinfo[i].active) { 977 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP); 978 } 979 } 980 981 tr->recchinfo.was_active = tr->recchinfo.active; 982 if (tr->recchinfo.active) { 983 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP); 984 } 985 986 return 0; 987 } 988 989 static int 990 tr_pci_resume(device_t dev) 991 { 992 int i; 993 struct tr_info *tr; 994 995 tr = pcm_getdevinfo(dev); 996 997 if (tr_init(tr) == -1) { 998 device_printf(dev, "unable to initialize the card\n"); 999 return ENXIO; 1000 } 1001 1002 if (mixer_reinit(dev) == -1) { 1003 device_printf(dev, "unable to initialize the mixer\n"); 1004 return ENXIO; 1005 } 1006 1007 for (i = 0; i < tr->playchns; i++) { 1008 if (tr->chinfo[i].was_active) { 1009 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START); 1010 } 1011 } 1012 1013 if (tr->recchinfo.was_active) { 1014 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START); 1015 } 1016 1017 return 0; 1018 } 1019 1020 static device_method_t tr_methods[] = { 1021 /* Device interface */ 1022 DEVMETHOD(device_probe, tr_pci_probe), 1023 DEVMETHOD(device_attach, tr_pci_attach), 1024 DEVMETHOD(device_detach, tr_pci_detach), 1025 DEVMETHOD(device_suspend, tr_pci_suspend), 1026 DEVMETHOD(device_resume, tr_pci_resume), 1027 { 0, 0 } 1028 }; 1029 1030 static driver_t tr_driver = { 1031 "pcm", 1032 tr_methods, 1033 PCM_SOFTC_SIZE, 1034 }; 1035 1036 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, 0, 0); 1037 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1038 MODULE_VERSION(snd_t4dwave, 1);
Cache object: 1dd52d64f010ff3da5ce46baa52f2aa3
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