Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/vibes.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ------------------------------------------------------------------------- */ 32 /* PCI Configuration Register Offsets */ 33 34 #define SV_PCI_COMPAT 0x10 35 #define SV_PCI_ENHANCED 0x14 36 #define SV_PCI_FMSYNTH 0x18 37 #define SV_PCI_MIDI 0x1c 38 #define SV_PCI_GAMES 0x20 39 #define SV_PCI_DMAA 0x40 40 #define SV_PCI_DMAC 0x48 41 42 #define SV_PCI_DMAA_SIZE 0x10 43 #define SV_PCI_DMAA_ALIGN 0x10 44 #define SV_PCI_DMAC_SIZE 0x10 45 #define SV_PCI_DMAC_ALIGN 0x10 46 47 #define SV_PCI_ENHANCED_SIZE 0x08 48 49 #define SV_PCI_DMA_ENABLE 0x00000001 50 #define SV_PCI_DMA_EXTENDED 0x00000008 51 52 /* ------------------------------------------------------------------------- */ 53 /* DMA Configuration Registers */ 54 55 #define SV_DMA_ADDR 0x00 56 #define SV_DMA_COUNT 0x04 57 58 #define SV_DMA_MODE 0x0B 59 #define SV_DMA_MODE_AUTO 0x10 60 #define SV_DMA_MODE_RD 0x04 61 #define SV_DMA_MODE_WR 0x08 62 63 /* ------------------------------------------------------------------------- */ 64 /* Enhanced Mode Configuration Registers */ 65 66 #define SV_CM_CONTROL 0x00 67 #define SV_CM_CONTROL_ENHANCED 0x01 68 #define SV_CM_CONTROL_TEST 0x02 69 #define SV_CM_CONTROL_REVERB 0x04 70 #define SV_CM_CONTROL_PWS 0x08 71 #define SV_CM_CONTROL_INTA 0x20 72 #define SV_CM_CONTROL_RESET 0x80 73 74 #define SV_CM_IMR 0x01 75 #define SV_CM_IMR_AMSK 0x01 76 #define SV_CM_IMR_CMSK 0x04 77 #define SV_CM_IMR_SMSK 0x08 78 #define SV_CM_IMR_UDM 0x40 79 #define SV_CM_IMR_MIDM 0x80 80 81 #define SV_CM_STATUS 0x02 82 #define SV_CM_STATUS_AINT 0x01 83 #define SV_CM_STATUS_CINT 0x04 84 #define SV_CM_STATUS_SINT 0x08 85 #define SV_CM_STATUS_UDI 0x40 86 #define SV_CM_STATUS_MI 0x80 87 88 #define SV_CM_INDEX 0x04 89 #define SV_CM_INDEX_MASK 0x3f 90 #define SV_CM_INDEX_MCE 0x40 91 #define SV_CM_INDEX_TRD 0x80 92 93 #define SV_CM_DATA 0x05 94 95 /* ------------------------------------------------------------------------- */ 96 /* Indexed Codec/Mixer Registers (left channels were applicable) */ 97 98 #define SV_REG_ADC_INPUT 0x00 99 #define SV_INPUT_GAIN_MASK 0x0f 100 #define SV_INPUT_MICGAIN 0x10 101 #define SV_INPUT_CD 0x20 102 #define SV_INPUT_DAC 0x40 103 #define SV_INPUT_AUX2 0x60 104 #define SV_INPUT_LINE 0x80 105 #define SV_INPUT_AUX1 0xa0 106 #define SV_INPUT_MIC 0xc0 107 #define SV_INPUT_MIXOUT 0xe0 108 109 #define SV_REG_AUX1 0x02 110 #define SV_REG_CD 0x04 111 #define SV_REG_LINE 0x06 112 #define SV_REG_MIC 0x08 113 #define SV_REG_SYNTH 0x0a 114 #define SV_REG_AUX2 0x0c 115 #define SV_REG_MIX 0x0e 116 #define SV_REG_PCM 0x10 117 #define SV_DEFAULT_MAX 0x1f 118 #define SV_ADC_MAX 0x0f 119 #define SV_MIC_MAX 0x0f 120 #define SV_PCM_MAX 0x3f 121 #define SV_MUTE 0x80 122 123 #define SV_REG_FORMAT 0x12 124 #define SV_AFMT_MONO 0x00 125 #define SV_AFMT_STEREO 0x01 126 #define SV_AFMT_S16 0x02 127 #define SV_AFMT_U8 0x00 128 #define SV_AFMT_DMAA(x) (x) 129 #define SV_AFMT_DMAA_MSK 0x03 130 #define SV_AFMT_DMAC(x) ((x) << 4) 131 #define SV_AFMT_DMAC_MSK 0x30 132 133 #define SV_REG_ENABLE 0x13 134 #define SV_PLAY_ENABLE 0x01 135 #define SV_RECORD_ENABLE 0x02 136 #define SV_PLAYBACK_PAUSE 0x04 137 138 #define SV_REG_REVISION 0x15 139 140 #define SV_REG_LOOPBACK 0x16 141 #define SV_LOOPBACK_ENABLE 0x01 142 #define SV_LOOPBACK_MAX 0x3f 143 #define SV_LOOPBACK_LEVEL(x) ((x) << 2) 144 145 #define SV_REG_DMAA_COUNT_HI 0x18 146 #define SV_REG_DMAA_COUNT_LO 0x19 147 #define SV_REG_DMAC_COUNT_HI 0x1c 148 #define SV_REG_DMAC_COUNT_LO 0x1d 149 150 #define SV_REG_PCM_SAMPLING_LO 0x1e 151 #define SV_REG_PCM_SAMPLING_HI 0x1f 152 153 #define SV_REG_SYN_SAMPLING_LO 0x20 154 #define SV_REG_SYN_SAMPLING_HI 0x21 155 156 #define SV_REG_CLOCK_SOURCE 0x22 157 #define SV_CLOCK_ALTERNATE 0x10 158 #define SV_REG_ALT_RATE 0x23 159 160 #define SV_REG_ADC_PLLM 0x24 161 #define SV_REG_ADC_PLLN 0x25 162 #define SV_ADC_PLLN(x) ((x) & 0x1f) 163 #define SV_ADC_PLLR(x) ((x) << 5) 164 165 #define SV_REG_SYNTH_PLLM 0x26 166 #define SV_REG_SYNTH_PLLN 0x27 167 #define SV_SYNTH_PLLN(x) ((x) & 0x1f) 168 #define SV_SYNTH_PLLR(x) ((x) << 5) 169 170 #define SV_REG_SRS_SPACE 0x2c 171 #define SV_SRS_SPACE_100 0x00 172 #define SV_SRS_SPACE_75 0x01 173 #define SV_SRS_SPACE_50 0x02 174 #define SV_SRS_SPACE_25 0x03 175 #define SV_SRS_SPACE_0 0x04 176 #define SV_SRS_DISABLED 0x80 177 178 #define SV_REG_SRS_CENTER 0x2d 179 #define SV_SRS_CENTER_100 0x00 180 #define SV_SRS_CENTER_75 0x01 181 #define SV_SRS_CENTER_50 0x02 182 #define SV_SRS_CENTER_25 0x03 183 #define SV_SRS_CENTER_0 0x04 184 185 #define SV_REG_ANALOG_PWR 0x30 186 #define SV_ANALOG_OFF_DAC 0x01 187 #define SV_ANALOG_OFF_ADC 0x08 188 #define SV_ANALOG_OFF_MIX 0x10 189 #define SV_ANALOG_OFF_SRS 0x20 190 #define SV_ANALOG_OFF_SPLL 0x40 191 #define SV_ANALOG_OFF_APLL 0x80 192 #define SV_ANALOG_OFF 0xf9 193 194 #define SV_REG_DIGITAL_PWR 0x31 195 #define SV_DIGITAL_OFF_SYN 0x01 196 #define SV_DIGITAL_OFF_MU 0x02 197 #define SV_DIGITAL_OFF_GP 0x04 198 #define SV_DIGITAL_OFF_BI 0x08 199 #define SV_DIGITAL_OFF 0x0f 200 201 /* ------------------------------------------------------------------------- */ 202 /* ADC PLL constants */ 203 204 #define SV_F_SCALE 512 205 #define SV_F_REF 24576000
Cache object: 9b9b869b030d2e8b1b91d4787f228fd8
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