Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/sbus/cs4231.h
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1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 1996 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ken Hornstein and John Kohl. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE 29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer 40 * chip, used on Gravis UltraSound MAX cards. 41 * 42 * Block diagram: 43 * +----------------------------------------------------+ 44 * | | 45 * | +----------------------------------------------+ | 46 * | |mixed in +-+ | | 47 * | +------------>--| | | | 48 * | mic in | | | | 49 * Mic --+-->| --------- GAIN ->-| | | | 50 * | | AUX 1 in |M| | | 51 * GF1 --)-->| -------------+-->-|U| | | 52 * | | Line in | |X|---- GAIN ----------+ | | 53 * Line --)-->| ---------+---)-->-| | | | | 54 * | | | | | | | | | 55 * | | | | +-+ ADC | | 56 * | | | | | | | 57 * | | | | | | | 58 * | | | +--- L/M --\ | | | AMP--> 59 * | | | \ | | | | 60 * | | | \ | | | | 61 * | | +---- L/M -------O-->--+--------)-------+-|--+-> line 62 * | | mono in /| | | | 63 * +---|-->------------ L/M -----/ | | | | 64 * | AUX 2 in | | | | 65 * CD --------|-->------------ L/M -------+ L/M | | 66 * | | v | 67 * | | | | 68 * | DAC | | 69 * | | | | 70 * +----------------------------------------------------+ 71 * | | 72 * | | 73 * v v 74 * Pc BUS (DISK) ??? 75 * 76 * Documentation for this chip can be found at: 77 * http://www.cirrus.com/products/overviews/cs4231.html 78 */ 79 80 /* 81 * This file was merged from two header files.(ad1848reg.h and cs4231reg.h) 82 * And the suffix AD1848 and SP was changed to CS4231 and CS respectively. 83 */ 84 /* CS4231 direct registers */ 85 #define CS4231_IADDR 0x00 86 #define CS4231_IDATA 0x01 87 #define CS4231_STATUS 0x02 88 #define CS4231_PIO 0x03 89 90 /* Index address register */ 91 #define CS_IN_INIT 0x80 92 #define MODE_CHANGE_ENABLE 0x40 93 #define TRANSFER_DISABLE 0x20 94 #define ADDRESS_MASK 0xe0 95 96 /* Status bits */ 97 #define INTERRUPT_STATUS 0x01 98 #define PLAYBACK_READY 0x02 99 #define PLAYBACK_LEFT 0x04 100 /* pbright is not left */ 101 #define PLAYBACK_UPPER 0x08 102 /* bplower is not upper */ 103 #define SAMPLE_ERROR 0x10 104 #define CAPTURE_READY 0x20 105 #define CAPTURE_LEFT 0x40 106 /* cpright is not left */ 107 #define CAPTURE_UPPER 0x80 108 /* cplower is not upper */ 109 110 /* CS4231 indirect mapped registers */ 111 #define CS_LEFT_INPUT_CONTROL 0x00 112 #define CS_RIGHT_INPUT_CONTROL 0x01 113 #define CS_LEFT_AUX1_CONTROL 0x02 114 #define CS_RIGHT_AUX1_CONTROL 0x03 115 #define CS_LEFT_AUX2_CONTROL 0x04 116 #define CS_RIGHT_AUX2_CONTROL 0x05 117 #define CS_LEFT_OUTPUT_CONTROL 0x06 118 #define CS_RIGHT_OUTPUT_CONTROL 0x07 119 #define CS_CLOCK_DATA_FORMAT 0x08 120 #define CS_INTERFACE_CONFIG 0x09 121 #define CS_PIN_CONTROL 0x0a 122 #define CS_TEST_AND_INIT 0x0b 123 #define CS_MISC_INFO 0x0c 124 #define CS_DIGITAL_MIX 0x0d 125 #define CS_UPPER_BASE_COUNT 0x0e 126 #define CS_LOWER_BASE_COUNT 0x0f 127 /* CS4231/AD1845 mode2 registers; added to AD1848 registers */ 128 #define CS_ALT_FEATURE1 0x10 129 #define CS_ALT_FEATURE2 0x11 130 #define CS_LEFT_LINE_CONTROL 0x12 131 #define CS_RIGHT_LINE_CONTROL 0x13 132 #define CS_TIMER_LOW 0x14 133 #define CS_TIMER_HIGH 0x15 134 #define CS_UPPER_FREQUENCY_SEL 0x16 135 #define CS_LOWER_FREQUENCY_SEL 0x17 136 #define CS_IRQ_STATUS 0x18 137 #define CS_VERSION_ID 0x19 138 #define CS_MONO_IO_CONTROL 0x1a 139 #define CS_POWERDOWN_CONTROL 0x1b 140 #define CS_REC_FORMAT 0x1c 141 #define CS_XTAL_SELECT 0x1d 142 #define CS_UPPER_REC_CNT 0x1e 143 #define CS_LOWER_REC_CNT 0x1f 144 #define CS_REG_NONE 0xff 145 146 #define CS_IN_MASK 0x2f 147 #define CS_IN_LINE 0x00 148 #define CS_IN_AUX1 0x40 149 #define CS_IN_MIC 0x80 150 #define CS_IN_DAC 0xc0 151 #define CS_MIC_GAIN_ENABLE 0x20 152 #define CS_IN_GAIN_MASK 0xf0 153 154 /* ADC input control - registers I0 (channel 1,left); I1 (channel 1,right) */ 155 #define ADC_INPUT_ATTEN_BITS 0x0f 156 #define ADC_INPUT_GAIN_ENABLE 0x20 157 158 /* Aux input control - registers I2 (channel 1,left); I3 (channel 1,right) 159 I4 (channel 2,left); I5 (channel 2,right) */ 160 #define AUX_INPUT_ATTEN_BITS 0x1f 161 #define AUX_INPUT_ATTEN_MASK 0xe0 162 #define AUX_INPUT_MUTE 0x80 163 164 /* Output bits - registers I6,I7*/ 165 #define OUTPUT_MUTE 0x80 166 #define OUTPUT_ATTEN_BITS 0x3f 167 #define OUTPUT_ATTEN_MASK (~OUTPUT_ATTEN_BITS & 0xff) 168 169 /* Clock and Data format reg bits (some also Capture Data format) - reg I8 */ 170 #define CS_CLOCK_DATA_FORMAT_MASK 0x0f 171 #define CLOCK_XTAL1 0x00 172 #define CLOCK_XTAL2 0x01 173 #define CLOCK_FREQ_MASK 0xf1 174 #define CS_AFMT_STEREO 0x10 175 #define CS_AFMT_U8 0x00 176 #define CS_AFMT_MU_LAW 0x20 177 #define CS_AFMT_S16_LE 0x40 178 #define CS_AFMT_A_LAW 0x60 179 #define CS_AFMT_IMA_ADPCM 0xa0 180 #define CS_AFMT_S16_BE 0xc0 181 182 /* Interface Configuration reg bits - register I9 */ 183 #define PLAYBACK_ENABLE 0x01 184 #define CAPTURE_ENABLE 0x02 185 #define DUAL_DMA 0x00 186 #define SINGLE_DMA 0x04 187 #define AUTO_CAL_ENABLE 0x08 188 #define PLAYBACK_PIO_ENABLE 0x40 189 #define CAPTURE_PIO_ENABLE 0x80 190 191 /* Pin control bits - register I10 */ 192 #define INTERRUPT_ENABLE 0x02 193 #define XCTL0_ENABLE 0x40 194 #define XCTL1_ENABLE 0x80 195 196 /* Test and init reg bits - register I11 (read-only) */ 197 #define OVERRANGE_LEFT_MASK 0xfc 198 #define OVERRANGE_RIGHT_MASK 0xf3 199 #define DATA_REQUEST_STATUS 0x10 200 #define AUTO_CAL_IN_PROG 0x20 201 #define PLAYBACK_UNDERRUN 0x40 202 #define CAPTURE_OVERRUN 0x80 203 204 /* Miscellaneous Control reg bits - register I12 */ 205 #define CS_ID_MASK 0x70 206 #define CS_MODE2 0x40 207 #define CS_CODEC_ID_MASK 0x0f 208 209 /* Digital Mix Control reg bits - register I13 */ 210 #define DIGITAL_MIX1_ENABLE 0x01 211 #define MIX_ATTEN_MASK 0x03 212 213 /* Alternate Feature Enable I - register I16 */ 214 #define CS_DAC_ZERO 0x01 215 #define CS_PMC_ENABLE 0x10 216 #define CS_CMC_ENABLE 0x20 217 #define CS_OUTPUT_LVL 0x80 218 219 /* Alternate Feature Enable II - register I17 */ 220 #define CS_HPF_ENABLE 0x01 221 #define DUAL_XTAL_ENABLE 0x02 222 223 /* alternate feature status(I24) */ 224 #define CS_AFS_TI 0x40 /* timer interrupt */ 225 #define CS_AFS_CI 0x20 /* capture interrupt */ 226 #define CS_AFS_PI 0x10 /* playback interrupt */ 227 #define CS_AFS_CU 0x08 /* capture underrun */ 228 #define CS_AFS_CO 0x04 /* capture overrun */ 229 #define CS_AFS_PO 0x02 /* playback overrun */ 230 #define CS_AFS_PU 0x01 /* playback underrun */ 231 232 /* Version - register I25 */ 233 #define CS_VERSION_NUMBER 0xe0 234 #define CS_VERSION_CHIPID 0x07 235 236 /* Miscellaneous Control reg bits */ 237 #define CS_MODE2 0x40 238 239 #define MONO_INPUT_ATTEN_BITS 0x0f 240 #define MONO_INPUT_ATTEN_MASK 0xf0 241 #define MONO_OUTPUT_MUTE 0x40 242 #define MONO_INPUT_MUTE 0x80 243 #define MONO_INPUT_MUTE_MASK 0x7f 244 245 #define LINE_INPUT_ATTEN_BITS 0x1f 246 #define LINE_INPUT_ATTEN_MASK 0xe0 247 #define LINE_INPUT_MUTE 0x80 248 #define LINE_INPUT_MUTE_MASK 0x7f
Cache object: 94569dee7c50201bea918a4f74743e12
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