Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/sr/if_sr.c
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1 /* 2 * Copyright (c) 1996 - 2001 John Hay. 3 * Copyright (c) 1996 SDL Communications, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: releng/5.0/sys/dev/sr/if_sr.c 106937 2002-11-14 23:54:55Z sam $ 31 */ 32 33 /* 34 * Programming assumptions and other issues. 35 * 36 * Only a 16K window will be used. 37 * 38 * The descriptors of a DMA channel will fit in a 16K memory window. 39 * 40 * The buffers of a transmit DMA channel will fit in a 16K memory window. 41 * 42 * When interface is going up, handshaking is set and it is only cleared 43 * when the interface is down'ed. 44 * 45 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 46 * internal/external clock, etc..... 47 * 48 */ 49 50 #include "opt_netgraph.h" 51 #ifdef NETGRAPH 52 #include <dev/sr/if_sr.h> 53 #endif /* NETGRAPH */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/mbuf.h> 60 #include <sys/sockio.h> 61 #include <sys/socket.h> 62 #include <sys/bus.h> 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <machine/bus_pio.h> 66 #include <machine/bus_memio.h> 67 #include <sys/rman.h> 68 69 #include <net/if.h> 70 #ifdef NETGRAPH 71 #include <sys/syslog.h> 72 #else /* NETGRAPH */ 73 #include <net/if_sppp.h> 74 75 #include <net/bpf.h> 76 #endif /* NETGRAPH */ 77 78 #include <machine/md_var.h> 79 80 #include <dev/ic/hd64570.h> 81 #include <dev/sr/if_srregs.h> 82 83 #ifdef NETGRAPH 84 #include <netgraph/ng_message.h> 85 #include <netgraph/netgraph.h> 86 #endif /* NETGRAPH */ 87 /* #define USE_MODEMCK */ 88 89 #ifndef BUGGY 90 #define BUGGY 0 91 #endif 92 93 #ifndef NETGRAPH 94 #define PPP_HEADER_LEN 4 95 #endif /* NETGRAPH */ 96 97 static int next_sc_unit = 0; 98 #ifndef NETGRAPH 99 #ifdef USE_MODEMCK 100 static int sr_watcher = 0; 101 #endif 102 #endif /* NETGRAPH */ 103 104 /* 105 * Define the software interface for the card... There is one for 106 * every channel (port). 107 */ 108 struct sr_softc { 109 #ifndef NETGRAPH 110 struct sppp ifsppp; /* PPP service w/in system */ 111 #endif /* NETGRAPH */ 112 struct sr_hardc *hc; /* card-level information */ 113 114 int unit; /* With regard to all sr devices */ 115 int subunit; /* With regard to this card */ 116 117 struct buf_block { 118 u_int txdesc; /* DPRAM offset */ 119 u_int txstart;/* DPRAM offset */ 120 u_int txend; /* DPRAM offset */ 121 u_int txtail; /* # of 1st free gran */ 122 u_int txmax; /* # of free grans */ 123 u_int txeda; /* err descr addr */ 124 } block[SR_TX_BLOCKS]; 125 126 char xmit_busy; /* Transmitter is busy */ 127 char txb_inuse; /* # of tx grans in use */ 128 u_int txb_new; /* ndx to new buffer */ 129 u_int txb_next_tx; /* ndx to next gran rdy tx */ 130 131 u_int rxdesc; /* DPRAM offset */ 132 u_int rxstart; /* DPRAM offset */ 133 u_int rxend; /* DPRAM offset */ 134 u_int rxhind; /* ndx to the hd of rx bufrs */ 135 u_int rxmax; /* # of avail grans */ 136 137 u_int clk_cfg; /* Clock configuration */ 138 139 int scachan; /* channel # on card */ 140 #ifdef NETGRAPH 141 int running; /* something is attached so we are running */ 142 int dcd; /* do we have dcd? */ 143 /* ---netgraph bits --- */ 144 char nodename[NG_NODELEN + 1]; /* store our node name */ 145 int datahooks; /* number of data hooks attached */ 146 node_p node; /* netgraph node */ 147 hook_p hook; /* data hook */ 148 hook_p debug_hook; 149 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 150 struct ifqueue xmitq; /* transmit queue */ 151 int flags; /* state */ 152 #define SCF_RUNNING 0x01 /* board is active */ 153 #define SCF_OACTIVE 0x02 /* output is active */ 154 int out_dog; /* watchdog cycles output count-down */ 155 struct callout_handle handle; /* timeout(9) handle */ 156 u_long inbytes, outbytes; /* stats */ 157 u_long lastinbytes, lastoutbytes; /* a second ago */ 158 u_long inrate, outrate; /* highest rate seen */ 159 u_long inlast; /* last input N secs ago */ 160 u_long out_deficit; /* output since last input */ 161 u_long oerrors, ierrors[6]; 162 u_long opackets, ipackets; 163 #endif /* NETGRAPH */ 164 }; 165 166 #ifdef NETGRAPH 167 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 168 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 169 #define LOTS_OF_PACKETS 100 170 #endif /* NETGRAPH */ 171 172 /* 173 * Baud Rate table for Sync Mode. 174 * Each entry consists of 3 elements: 175 * Baud Rate (x100) , TMC, BR 176 * 177 * Baud Rate = FCLK / TMC / 2^BR 178 * Baud table for Crystal freq. of 9.8304 Mhz 179 */ 180 #ifdef N2_TEST_SPEED 181 struct rate_line { 182 int target; /* target rate/100 */ 183 int tmc_reg; /* TMC register value */ 184 int br_reg; /* BR (BaudRateClk) selector */ 185 } n2_rates[] = { 186 /* Baudx100 TMC BR */ 187 { 3, 128, 8 }, 188 { 6, 128, 7 }, 189 { 12, 128, 6 }, 190 { 24, 128, 5 }, 191 { 48, 128, 4 }, 192 { 96, 128, 3 }, 193 { 192, 128, 2 }, 194 { 384, 128, 1 }, 195 { 560, 88, 1 }, 196 { 640, 77, 1 }, 197 { 1280, 38, 1 }, 198 { 2560, 19, 1 }, 199 { 5120, 10, 1 }, 200 { 10000, 5, 1 }, 201 { 15000, 3, 1 }, 202 { 25000, 2, 1 }, 203 { 50000, 1, 1 }, 204 { 0, 0, 0 } 205 }; 206 207 int sr_test_speed[] = { 208 N2_TEST_SPEED, 209 N2_TEST_SPEED 210 }; 211 212 int etc0vals[] = { 213 SR_MCR_ETC0, /* ISA channel 0 */ 214 SR_MCR_ETC1, /* ISA channel 1 */ 215 SR_FECR_ETC0, /* PCI channel 0 */ 216 SR_FECR_ETC1 /* PCI channel 1 */ 217 }; 218 #endif 219 220 devclass_t sr_devclass; 221 #ifndef NETGRAPH 222 MODULE_DEPEND(if_sr, sppp, 1, 1, 1); 223 #else 224 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1); 225 #endif 226 227 static void srintr(void *arg); 228 static void sr_xmit(struct sr_softc *sc); 229 #ifndef NETGRAPH 230 static void srstart(struct ifnet *ifp); 231 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 232 static void srwatchdog(struct ifnet *ifp); 233 #else 234 static void srstart(struct sr_softc *sc); 235 static void srwatchdog(struct sr_softc *sc); 236 #endif /* NETGRAPH */ 237 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat); 238 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len); 239 static void sr_eat_packet(struct sr_softc *sc, int single); 240 static void sr_get_packets(struct sr_softc *sc); 241 242 static void sr_up(struct sr_softc *sc); 243 static void sr_down(struct sr_softc *sc); 244 static void src_init(struct sr_hardc *hc); 245 static void sr_init_sca(struct sr_hardc *hc); 246 static void sr_init_msci(struct sr_softc *sc); 247 static void sr_init_rx_dmac(struct sr_softc *sc); 248 static void sr_init_tx_dmac(struct sr_softc *sc); 249 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr); 250 static void sr_msci_intr(struct sr_hardc *hc, u_char isr); 251 static void sr_timer_intr(struct sr_hardc *hc, u_char isr); 252 #ifndef NETGRAPH 253 #ifdef USE_MODEMCK 254 static void sr_modemck(void *x); 255 #endif 256 #else 257 static void sr_modemck(struct sr_softc *x); 258 #endif /* NETGRAPH */ 259 260 #ifdef NETGRAPH 261 static void ngsr_watchdog_frame(void * arg); 262 static void ngsr_init(void* ignored); 263 264 static ng_constructor_t ngsr_constructor; 265 static ng_rcvmsg_t ngsr_rcvmsg; 266 static ng_shutdown_t ngsr_shutdown; 267 static ng_newhook_t ngsr_newhook; 268 /*static ng_findhook_t ngsr_findhook; */ 269 static ng_connect_t ngsr_connect; 270 static ng_rcvdata_t ngsr_rcvdata; 271 static ng_disconnect_t ngsr_disconnect; 272 273 static struct ng_type typestruct = { 274 NG_ABI_VERSION, 275 NG_SR_NODE_TYPE, 276 NULL, 277 ngsr_constructor, 278 ngsr_rcvmsg, 279 ngsr_shutdown, 280 ngsr_newhook, 281 NULL, 282 ngsr_connect, 283 ngsr_rcvdata, 284 ngsr_disconnect, 285 NULL 286 }; 287 288 static int ngsr_done_init = 0; 289 #endif /* NETGRAPH */ 290 291 /* 292 * Register the ports on the adapter. 293 * Fill in the info for each port. 294 #ifndef NETGRAPH 295 * Attach each port to sppp and bpf. 296 #endif 297 */ 298 int 299 sr_attach(device_t device) 300 { 301 int intf_sw, pndx; 302 u_int32_t flags; 303 u_int fecr, *fecrp; 304 struct sr_hardc *hc; 305 struct sr_softc *sc; 306 #ifndef NETGRAPH 307 struct ifnet *ifp; 308 #endif /* NETGRAPH */ 309 int unit; /* index: channel w/in card */ 310 311 hc = (struct sr_hardc *)device_get_softc(device); 312 MALLOC(sc, struct sr_softc *, 313 hc->numports * sizeof(struct sr_softc), 314 M_DEVBUF, M_WAITOK | M_ZERO); 315 if (sc == NULL) 316 goto errexit; 317 hc->sc = sc; 318 319 /* 320 * Get the TX clock direction and configuration. The default is a 321 * single external clock which is used by RX and TX. 322 */ 323 switch(hc->cardtype) { 324 case SR_CRD_N2: 325 flags = device_get_flags(device); 326 #ifdef N2_TEST_SPEED 327 if (sr_test_speed[0] > 0) 328 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; 329 else 330 #endif 331 if (flags & SR_FLAGS_0_CLK_MSK) 332 hc->sc[0].clk_cfg = 333 (flags & SR_FLAGS_0_CLK_MSK) 334 >> SR_FLAGS_CLK_SHFT; 335 336 if (hc->numports == 2) 337 #ifdef N2_TEST_SPEED 338 if (sr_test_speed[1] > 0) 339 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; 340 else 341 #endif 342 if (flags & SR_FLAGS_1_CLK_MSK) 343 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK) 344 >> (SR_FLAGS_CLK_SHFT + 345 SR_FLAGS_CLK_CHAN_SHFT); 346 break; 347 case SR_CRD_N2PCI: 348 fecrp = (u_int *)(hc->sca_base + SR_FECR); 349 fecr = *fecrp; 350 for (pndx = 0; pndx < hc->numports; pndx++, sc++) { 351 switch (pndx) { 352 case 1: 353 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT; 354 break; 355 case 0: 356 default: 357 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT; 358 } 359 360 #ifdef N2_TEST_SPEED 361 if (sr_test_speed[pndx] > 0) 362 sc->clk_cfg = SR_FLAGS_INT_CLK; 363 else 364 #endif 365 switch (intf_sw) { 366 default: 367 case SR_FE_ID_RS232: 368 case SR_FE_ID_HSSI: 369 case SR_FE_ID_RS422: 370 case SR_FE_ID_TEST: 371 break; 372 373 case SR_FE_ID_V35: 374 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK; 375 break; 376 377 case SR_FE_ID_X21: 378 sc->clk_cfg = SR_FLAGS_EXT_CLK; 379 break; 380 } 381 } 382 sc = hc->sc; 383 break; 384 } 385 386 /* 387 * Report Card configuration information before we start configuring 388 * each channel on the card... 389 */ 390 printf("src%d: %uK RAM (%d mempages) @ %p-%p, %u ports.\n", 391 hc->cunit, hc->memsize / 1024, hc->mempages, 392 hc->mem_start, hc->mem_end, hc->numports); 393 394 src_init(hc); 395 sr_init_sca(hc); 396 397 if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, 398 INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0) 399 goto errexit; 400 401 /* 402 * Now configure each port on the card. 403 */ 404 for (unit = 0; unit < hc->numports; sc++, unit++) { 405 sc->hc = hc; 406 sc->subunit = unit; 407 sc->unit = next_sc_unit; 408 next_sc_unit++; 409 sc->scachan = unit % NCHAN; 410 411 sr_init_rx_dmac(sc); 412 sr_init_tx_dmac(sc); 413 sr_init_msci(sc); 414 415 printf("sr%d: Adapter %d, port %d.\n", 416 sc->unit, hc->cunit, sc->subunit); 417 418 #ifndef NETGRAPH 419 ifp = &sc->ifsppp.pp_if; 420 ifp->if_softc = sc; 421 ifp->if_unit = sc->unit; 422 ifp->if_name = "sr"; 423 ifp->if_mtu = PP_MTU; 424 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 425 ifp->if_ioctl = srioctl; 426 ifp->if_start = srstart; 427 ifp->if_watchdog = srwatchdog; 428 429 sc->ifsppp.pp_flags = PP_KEEPALIVE; 430 sppp_attach((struct ifnet *)&sc->ifsppp); 431 if_attach(ifp); 432 433 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 434 #else /* NETGRAPH */ 435 /* 436 * we have found a node, make sure our 'type' is availabe. 437 */ 438 if (ngsr_done_init == 0) ngsr_init(NULL); 439 if (ng_make_node_common(&typestruct, &sc->node) != 0) 440 goto errexit; 441 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit); 442 if (ng_name_node(sc->node, sc->nodename)) { 443 NG_NODE_UNREF(sc->node); /* make it go away again */ 444 goto errexit; 445 } 446 NG_NODE_SET_PRIVATE(sc->node, sc); 447 callout_handle_init(&sc->handle); 448 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 449 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 450 mtx_init(&sc->xmitq.ifq_mtx, "sr_xmitq", NULL, MTX_DEF); 451 mtx_init(&sc->xmitq_hipri.ifq_mtx, "sr_xmitq_hipri", NULL, 452 MTX_DEF); 453 sc->running = 0; 454 #endif /* NETGRAPH */ 455 } 456 457 if (hc->mempages) 458 SRC_SET_OFF(hc->iobase); 459 460 return (0); 461 462 errexit: 463 sr_deallocate_resources(device); 464 return (ENXIO); 465 } 466 467 int 468 sr_detach(device_t device) 469 { 470 device_t parent = device_get_parent(device); 471 struct sr_hardc *hc = device_get_softc(device); 472 473 if (hc->intr_cookie != NULL) { 474 if (BUS_TEARDOWN_INTR(parent, device, 475 hc->res_irq, hc->intr_cookie) != 0) { 476 printf("intr teardown failed.. continuing\n"); 477 } 478 hc->intr_cookie = NULL; 479 } 480 481 /* XXX Stop the DMA. */ 482 483 /* 484 * deallocate any system resources we may have 485 * allocated on behalf of this driver. 486 */ 487 FREE(hc->sc, M_DEVBUF); 488 hc->sc = NULL; 489 hc->mem_start = NULL; 490 return (sr_deallocate_resources(device)); 491 } 492 493 int 494 sr_allocate_ioport(device_t device, int rid, u_long size) 495 { 496 struct sr_hardc *hc = device_get_softc(device); 497 498 hc->rid_ioport = rid; 499 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, 500 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); 501 if (hc->res_ioport == NULL) { 502 goto errexit; 503 } 504 return (0); 505 506 errexit: 507 sr_deallocate_resources(device); 508 return (ENXIO); 509 } 510 511 int 512 sr_allocate_irq(device_t device, int rid, u_long size) 513 { 514 struct sr_hardc *hc = device_get_softc(device); 515 516 hc->rid_irq = rid; 517 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ, 518 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE); 519 if (hc->res_irq == NULL) { 520 goto errexit; 521 } 522 return (0); 523 524 errexit: 525 sr_deallocate_resources(device); 526 return (ENXIO); 527 } 528 529 int 530 sr_allocate_memory(device_t device, int rid, u_long size) 531 { 532 struct sr_hardc *hc = device_get_softc(device); 533 534 hc->rid_memory = rid; 535 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 536 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); 537 if (hc->res_memory == NULL) { 538 goto errexit; 539 } 540 return (0); 541 542 errexit: 543 sr_deallocate_resources(device); 544 return (ENXIO); 545 } 546 547 int 548 sr_allocate_plx_memory(device_t device, int rid, u_long size) 549 { 550 struct sr_hardc *hc = device_get_softc(device); 551 552 hc->rid_plx_memory = rid; 553 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 554 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); 555 if (hc->res_plx_memory == NULL) { 556 goto errexit; 557 } 558 return (0); 559 560 errexit: 561 sr_deallocate_resources(device); 562 return (ENXIO); 563 } 564 565 int 566 sr_deallocate_resources(device_t device) 567 { 568 struct sr_hardc *hc = device_get_softc(device); 569 570 if (hc->res_irq != 0) { 571 bus_deactivate_resource(device, SYS_RES_IRQ, 572 hc->rid_irq, hc->res_irq); 573 bus_release_resource(device, SYS_RES_IRQ, 574 hc->rid_irq, hc->res_irq); 575 hc->res_irq = 0; 576 } 577 if (hc->res_ioport != 0) { 578 bus_deactivate_resource(device, SYS_RES_IOPORT, 579 hc->rid_ioport, hc->res_ioport); 580 bus_release_resource(device, SYS_RES_IOPORT, 581 hc->rid_ioport, hc->res_ioport); 582 hc->res_ioport = 0; 583 } 584 if (hc->res_memory != 0) { 585 bus_deactivate_resource(device, SYS_RES_MEMORY, 586 hc->rid_memory, hc->res_memory); 587 bus_release_resource(device, SYS_RES_MEMORY, 588 hc->rid_memory, hc->res_memory); 589 hc->res_memory = 0; 590 } 591 if (hc->res_plx_memory != 0) { 592 bus_deactivate_resource(device, SYS_RES_MEMORY, 593 hc->rid_plx_memory, hc->res_plx_memory); 594 bus_release_resource(device, SYS_RES_MEMORY, 595 hc->rid_plx_memory, hc->res_plx_memory); 596 hc->res_plx_memory = 0; 597 } 598 return (0); 599 } 600 601 /* 602 * N2 Interrupt Service Routine 603 * 604 * First figure out which SCA gave the interrupt. 605 * Process it. 606 * See if there is other interrupts pending. 607 * Repeat until there no interrupts remain. 608 */ 609 static void 610 srintr(void *arg) 611 { 612 struct sr_hardc *hc = (struct sr_hardc *)arg; 613 sca_regs *sca = hc->sca; /* MSCI register tree */ 614 u_char isr0, isr1, isr2; /* interrupt statii captured */ 615 616 #if BUGGY > 1 617 printf("sr: srintr_hc(hc=%08x)\n", hc); 618 #endif 619 620 /* 621 * Since multiple interfaces may share this interrupt, we must loop 622 * until no interrupts are still pending service. 623 */ 624 while (1) { 625 /* 626 * Read all three interrupt status registers from the N2 627 * card... 628 */ 629 isr0 = SRC_GET8(hc->sca_base, sca->isr0); 630 isr1 = SRC_GET8(hc->sca_base, sca->isr1); 631 isr2 = SRC_GET8(hc->sca_base, sca->isr2); 632 633 /* 634 * If all three registers returned 0, we've finished 635 * processing interrupts from this device, so we can quit 636 * this loop... 637 */ 638 if ((isr0 | isr1 | isr2) == 0) 639 break; 640 641 #if BUGGY > 2 642 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n", 643 #ifndef NETGRAPH 644 unit, isr0, isr1, isr2); 645 #else 646 hc->cunit, isr0, isr1, isr2); 647 #endif /* NETGRAPH */ 648 #endif 649 650 /* 651 * Now we can dispatch the interrupts. Since we don't expect 652 * either MSCI or timer interrupts, we'll test for DMA 653 * interrupts first... 654 */ 655 if (isr1) /* DMA-initiated interrupt */ 656 sr_dmac_intr(hc, isr1); 657 658 if (isr0) /* serial part IRQ? */ 659 sr_msci_intr(hc, isr0); 660 661 if (isr2) /* timer-initiated interrupt */ 662 sr_timer_intr(hc, isr2); 663 } 664 } 665 666 /* 667 * This will only start the transmitter. It is assumed that the data 668 * is already there. 669 * It is normally called from srstart() or sr_dmac_intr(). 670 */ 671 static void 672 sr_xmit(struct sr_softc *sc) 673 { 674 u_short cda_value; /* starting descriptor */ 675 u_short eda_value; /* ending descriptor */ 676 struct sr_hardc *hc; 677 #ifndef NETGRAPH 678 struct ifnet *ifp; /* O/S Network Services */ 679 #endif /* NETGRAPH */ 680 dmac_channel *dmac; /* DMA channel registers */ 681 682 #if BUGGY > 0 683 printf("sr: sr_xmit( sc=%08x)\n", sc); 684 #endif 685 686 hc = sc->hc; 687 #ifndef NETGRAPH 688 ifp = &sc->ifsppp.pp_if; 689 #endif /* NETGRAPH */ 690 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; 691 692 /* 693 * Get the starting and ending addresses of the chain to be 694 * transmitted and pass these on to the DMA engine on-chip. 695 */ 696 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart; 697 cda_value &= 0x00ffff; 698 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart; 699 eda_value &= 0x00ffff; 700 701 SRC_PUT16(hc->sca_base, dmac->cda, cda_value); 702 SRC_PUT16(hc->sca_base, dmac->eda, eda_value); 703 704 /* 705 * Now we'll let the DMA status register know about this change 706 */ 707 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); 708 709 sc->xmit_busy = 1; /* mark transmitter busy */ 710 711 #if BUGGY > 2 712 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n", 713 sc->unit, cda_value, eda_value, 714 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart); 715 #endif 716 717 sc->txb_next_tx++; /* update next transmit seq# */ 718 719 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */ 720 sc->txb_next_tx = 0; 721 722 #ifndef NETGRAPH 723 /* 724 * Finally, we'll set a timout (which will start srwatchdog()) 725 * within the O/S network services layer... 726 */ 727 ifp->if_timer = 2; /* Value in seconds. */ 728 #else 729 /* 730 * Don't time out for a while. 731 */ 732 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 733 #endif /* NETGRAPH */ 734 } 735 736 /* 737 * This function will be called from the upper level when a user add a 738 * packet to be send, and from the interrupt handler after a finished 739 * transmit. 740 * 741 * NOTE: it should run at spl_imp(). 742 * 743 * This function only place the data in the oncard buffers. It does not 744 * start the transmition. sr_xmit() does that. 745 * 746 * Transmitter idle state is indicated by the IFF_OACTIVE flag. 747 * The function that clears that should ensure that the transmitter 748 * and its DMA is in a "good" idle state. 749 */ 750 #ifndef NETGRAPH 751 static void 752 srstart(struct ifnet *ifp) 753 { 754 struct sr_softc *sc; /* channel control structure */ 755 #else 756 static void 757 srstart(struct sr_softc *sc) 758 { 759 #endif /* NETGRAPH */ 760 struct sr_hardc *hc; /* card control/config block */ 761 int len; /* total length of a packet */ 762 int pkts; /* packets placed in DPRAM */ 763 int tlen; /* working length of pkt */ 764 u_int i; 765 struct mbuf *mtx; /* message buffer from O/S */ 766 u_char *txdata; /* buffer address in DPRAM */ 767 sca_descriptor *txdesc; /* working descriptor pointr */ 768 struct buf_block *blkp; 769 770 #ifndef NETGRAPH 771 #if BUGGY > 0 772 printf("sr: srstart( ifp=%08x)\n", ifp); 773 #endif 774 sc = ifp->if_softc; 775 if ((ifp->if_flags & IFF_RUNNING) == 0) 776 return; 777 #endif /* NETGRAPH */ 778 hc = sc->hc; 779 /* 780 * It is OK to set the memory window outside the loop because all tx 781 * buffers and descriptors are assumed to be in the same 16K window. 782 */ 783 if (hc->mempages) { 784 SRC_SET_ON(hc->iobase); 785 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc); 786 } 787 788 /* 789 * Loop to place packets into DPRAM. 790 * 791 * We stay in this loop until there is nothing in 792 * the TX queue left or the tx buffers are full. 793 */ 794 top_srstart: 795 796 /* 797 * See if we have space for more packets. 798 */ 799 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */ 800 #ifndef NETGRAPH 801 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 802 #else 803 /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ 804 #endif /* NETGRAPH */ 805 806 if (hc->mempages) 807 SRC_SET_OFF(hc->iobase); 808 809 #if BUGGY > 9 810 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n", 811 sc->unit, sc->txb_inuse); 812 #endif 813 return; 814 } 815 /* 816 * OK, the card can take more traffic. Let's see if there's any 817 * pending from the system... 818 * 819 * NOTE: 820 * The architecture of the networking interface doesn't 821 * actually call us like 'write()', providing an address. We get 822 * started, a lot like a disk strategy routine, and we actually call 823 * back out to the system to get traffic to send... 824 * 825 * NOTE: 826 * If we were gonna run through another layer, we would use a 827 * dispatch table to select the service we're getting a packet 828 * from... 829 */ 830 #ifndef NETGRAPH 831 mtx = sppp_dequeue(ifp); 832 #else /* NETGRAPH */ 833 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 834 if (mtx == NULL) { 835 IF_DEQUEUE(&sc->xmitq, mtx); 836 } 837 #endif /* NETGRAPH */ 838 if (!mtx) { 839 if (hc->mempages) 840 SRC_SET_OFF(hc->iobase); 841 return; 842 } 843 /* 844 * OK, we got a packet from the network services of the O/S. Now we 845 * can move it into the DPRAM (under control of the descriptors) and 846 * fire it off... 847 */ 848 pkts = 0; 849 i = 0; /* counts # of granules used */ 850 851 blkp = &sc->block[sc->txb_new]; /* address of free granule */ 852 txdesc = (sca_descriptor *) 853 (hc->mem_start + (blkp->txdesc & hc->winmsk)); 854 855 txdata = (u_char *)(hc->mem_start 856 + (blkp->txstart & hc->winmsk)); 857 858 /* 859 * Now we'll try to install as many packets as possible into the 860 * card's DP RAM buffers. 861 */ 862 for (;;) { /* perform actual copy of packet */ 863 len = mtx->m_pkthdr.len; /* length of message */ 864 865 #if BUGGY > 1 866 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n", 867 sc->unit, mtx, len); 868 #endif 869 870 #ifndef NETGRAPH 871 BPF_MTAP(ifp, mtx); 872 #else /* NETGRAPH */ 873 sc->outbytes += len; 874 #endif /* NETGRAPH */ 875 876 /* 877 * We can perform a straight copy because the tranmit 878 * buffers won't wrap. 879 */ 880 m_copydata(mtx, 0, len, txdata); 881 882 /* 883 * Now we know how big the message is gonna be. We must now 884 * construct the descriptors to drive this message out... 885 */ 886 tlen = len; 887 while (tlen > SR_BUF_SIZ) { /* loop for full granules */ 888 txdesc->stat = 0; /* reset bits */ 889 txdesc->len = SR_BUF_SIZ; /* size of granule */ 890 tlen -= SR_BUF_SIZ; 891 892 txdesc++; /* move to next dscr */ 893 txdata += SR_BUF_SIZ; /* adjust data addr */ 894 i++; 895 } 896 897 /* 898 * This section handles the setting of the final piece of a 899 * message. 900 */ 901 txdesc->stat = SCA_DESC_EOM; 902 txdesc->len = tlen; 903 pkts++; 904 905 /* 906 * prepare for subsequent packets (if any) 907 */ 908 txdesc++; 909 txdata += SR_BUF_SIZ; /* next mem granule */ 910 i++; /* count of granules */ 911 912 /* 913 * OK, we've now placed the message into the DPRAM where it 914 * can be transmitted. We'll now release the message memory 915 * and update the statistics... 916 */ 917 m_freem(mtx); 918 #ifndef NETGRAPH 919 ++sc->ifsppp.pp_if.if_opackets; 920 #else /* NETGRAPH */ 921 sc->opackets++; 922 #endif /* NETGRAPH */ 923 924 /* 925 * Check if we have space for another packet. XXX This is 926 * hardcoded. A packet can't be larger than 3 buffers (3 x 927 * 512). 928 */ 929 if ((i + 3) >= blkp->txmax) { /* enough remains? */ 930 #if BUGGY > 9 931 printf("sr%d.srstart: i=%d (%d pkts); card full.\n", 932 sc->unit, i, pkts); 933 #endif 934 break; 935 } 936 /* 937 * We'll pull the next message to be sent (if any) 938 */ 939 #ifndef NETGRAPH 940 mtx = sppp_dequeue(ifp); 941 #else /* NETGRAPH */ 942 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 943 if (mtx == NULL) { 944 IF_DEQUEUE(&sc->xmitq, mtx); 945 } 946 #endif /* NETGRAPH */ 947 if (!mtx) { /* no message? We're done! */ 948 #if BUGGY > 9 949 printf("sr%d.srstart: pending=0, pkts=%d\n", 950 sc->unit, pkts); 951 #endif 952 break; 953 } 954 } 955 956 blkp->txtail = i; /* record next free granule */ 957 958 /* 959 * Mark the last descriptor, so that the SCA know where to stop. 960 */ 961 txdesc--; /* back up to last descriptor in list */ 962 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */ 963 964 /* 965 * Now we'll reset the transmit granule's descriptor address so we 966 * can record this in the structure and fire it off w/ the DMA 967 * processor of the serial chip... 968 */ 969 txdesc = (sca_descriptor *)(uintptr_t)blkp->txdesc; 970 blkp->txeda = (u_short)((uintptr_t)&txdesc[i]); 971 972 sc->txb_inuse++; /* update inuse status */ 973 sc->txb_new++; /* new traffic wuz added */ 974 975 if (sc->txb_new == SR_TX_BLOCKS) 976 sc->txb_new = 0; 977 978 /* 979 * If the tranmitter wasn't marked as "busy" we will force it to be 980 * started... 981 */ 982 if (sc->xmit_busy == 0) { 983 sr_xmit(sc); 984 #if BUGGY > 9 985 printf("sr%d.srstart: called sr_xmit()\n", sc->unit); 986 #endif 987 } 988 goto top_srstart; 989 } 990 991 #ifndef NETGRAPH 992 /* 993 * Handle ioctl's at the device level, though we *will* call up 994 * a layer... 995 */ 996 #if BUGGY > 2 997 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0}; 998 #endif 999 1000 static int 1001 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1002 { 1003 int s, error, was_up, should_be_up; 1004 struct sr_softc *sc = ifp->if_softc; 1005 1006 #if BUGGY > 0 1007 if_printf(ifp, "srioctl(ifp=%08x, cmd=%08x, data=%08x)\n", 1008 ifp, cmd, data); 1009 #endif 1010 1011 was_up = ifp->if_flags & IFF_RUNNING; 1012 1013 error = sppp_ioctl(ifp, cmd, data); 1014 1015 #if BUGGY > 1 1016 if_printf(ifp, "ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n", 1017 ((struct sppp *)ifp)->pp_flags, ifp->if_flags); 1018 #endif 1019 1020 if (error) 1021 return error; 1022 1023 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) { 1024 #if BUGGY > 2 1025 if (bug_splats[sc->unit]++ < 2) { 1026 printf("sr(%d).if_addrlist = %08x\n", 1027 sc->unit, ifp->if_addrlist); 1028 printf("sr(%d).if_bpf = %08x\n", 1029 sc->unit, ifp->if_bpf); 1030 printf("sr(%d).if_init = %08x\n", 1031 sc->unit, ifp->if_init); 1032 printf("sr(%d).if_output = %08x\n", 1033 sc->unit, ifp->if_output); 1034 printf("sr(%d).if_start = %08x\n", 1035 sc->unit, ifp->if_start); 1036 printf("sr(%d).if_done = %08x\n", 1037 sc->unit, ifp->if_done); 1038 printf("sr(%d).if_ioctl = %08x\n", 1039 sc->unit, ifp->if_ioctl); 1040 printf("sr(%d).if_reset = %08x\n", 1041 sc->unit, ifp->if_reset); 1042 printf("sr(%d).if_watchdog = %08x\n", 1043 sc->unit, ifp->if_watchdog); 1044 } 1045 #endif 1046 return 0; 1047 } 1048 1049 s = splimp(); 1050 should_be_up = ifp->if_flags & IFF_RUNNING; 1051 1052 if (!was_up && should_be_up) { 1053 /* 1054 * Interface should be up -- start it. 1055 */ 1056 sr_up(sc); 1057 srstart(ifp); 1058 1059 /* 1060 * XXX Clear the IFF_UP flag so that the link will only go 1061 * up after sppp lcp and ipcp negotiation. 1062 */ 1063 /* ifp->if_flags &= ~IFF_UP; */ 1064 } else if (was_up && !should_be_up) { 1065 /* 1066 * Interface should be down -- stop it. 1067 */ 1068 sr_down(sc); 1069 sppp_flush(ifp); 1070 } 1071 splx(s); 1072 return 0; 1073 } 1074 #endif /* NETGRAPH */ 1075 1076 /* 1077 * This is to catch lost tx interrupts. 1078 */ 1079 static void 1080 #ifndef NETGRAPH 1081 srwatchdog(struct ifnet *ifp) 1082 #else 1083 srwatchdog(struct sr_softc *sc) 1084 #endif /* NETGRAPH */ 1085 { 1086 int got_st0, got_st1, got_st3, got_dsr; 1087 #ifndef NETGRAPH 1088 struct sr_softc *sc = ifp->if_softc; 1089 #endif /* NETGRAPH */ 1090 struct sr_hardc *hc = sc->hc; 1091 msci_channel *msci = &hc->sca->msci[sc->scachan]; 1092 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan]; 1093 1094 #if BUGGY > 0 1095 #ifndef NETGRAPH 1096 printf("srwatchdog(unit=%d)\n", unit); 1097 #else 1098 printf("srwatchdog(unit=%d)\n", sc->unit); 1099 #endif /* NETGRAPH */ 1100 #endif 1101 1102 #ifndef NETGRAPH 1103 if (!(ifp->if_flags & IFF_RUNNING)) 1104 return; 1105 1106 ifp->if_oerrors++; /* update output error count */ 1107 #else /* NETGRAPH */ 1108 sc->oerrors++; /* update output error count */ 1109 #endif /* NETGRAPH */ 1110 1111 got_st0 = SRC_GET8(hc->sca_base, msci->st0); 1112 got_st1 = SRC_GET8(hc->sca_base, msci->st1); 1113 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 1114 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr); 1115 1116 #ifndef NETGRAPH 1117 #if 0 1118 if (ifp->if_flags & IFF_DEBUG) 1119 #endif 1120 printf("sr%d: transmit failed, " 1121 #else /* NETGRAPH */ 1122 printf("sr%d: transmit failed, " 1123 #endif /* NETGRAPH */ 1124 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n", 1125 sc->unit, 1126 got_st0, got_st1, got_st3, got_dsr); 1127 1128 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) { 1129 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT); 1130 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); 1131 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN); 1132 } 1133 sc->xmit_busy = 0; 1134 #ifndef NETGRAPH 1135 ifp->if_flags &= ~IFF_OACTIVE; 1136 #else 1137 /*ifp->if_flags &= ~IFF_OACTIVE; */ 1138 #endif /* NETGRAPH */ 1139 1140 if (sc->txb_inuse && --sc->txb_inuse) 1141 sr_xmit(sc); 1142 1143 #ifndef NETGRAPH 1144 srstart(ifp); /* restart transmitter */ 1145 #else 1146 srstart(sc); /* restart transmitter */ 1147 #endif /* NETGRAPH */ 1148 } 1149 1150 static void 1151 sr_up(struct sr_softc *sc) 1152 { 1153 u_int *fecrp; 1154 struct sr_hardc *hc = sc->hc; 1155 sca_regs *sca = hc->sca; 1156 msci_channel *msci = &sca->msci[sc->scachan]; 1157 1158 #if BUGGY > 0 1159 printf("sr_up(sc=%08x)\n", sc); 1160 #endif 1161 1162 /* 1163 * Enable transmitter and receiver. Raise DTR and RTS. Enable 1164 * interrupts. 1165 * 1166 * XXX What about using AUTO mode in msci->md0 ??? 1167 */ 1168 SRC_PUT8(hc->sca_base, msci->ctl, 1169 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS); 1170 1171 if (sc->scachan == 0) 1172 switch (hc->cardtype) { 1173 case SR_CRD_N2: 1174 outb(hc->iobase + SR_MCR, 1175 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0)); 1176 break; 1177 case SR_CRD_N2PCI: 1178 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1179 *fecrp &= ~SR_FECR_DTR0; 1180 break; 1181 } 1182 else 1183 switch (hc->cardtype) { 1184 case SR_CRD_N2: 1185 outb(hc->iobase + SR_MCR, 1186 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1)); 1187 break; 1188 case SR_CRD_N2PCI: 1189 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1190 *fecrp &= ~SR_FECR_DTR1; 1191 break; 1192 } 1193 1194 if (sc->scachan == 0) { 1195 SRC_PUT8(hc->sca_base, sca->ier0, 1196 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F); 1197 SRC_PUT8(hc->sca_base, sca->ier1, 1198 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F); 1199 } else { 1200 SRC_PUT8(hc->sca_base, sca->ier0, 1201 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0); 1202 SRC_PUT8(hc->sca_base, sca->ier1, 1203 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0); 1204 } 1205 1206 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE); 1207 inb(hc->iobase); /* XXX slow it down a bit. */ 1208 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); 1209 1210 #ifndef NETGRAPH 1211 #ifdef USE_MODEMCK 1212 if (sr_watcher == 0) 1213 sr_modemck(NULL); 1214 #endif 1215 #else /* NETGRAPH */ 1216 untimeout(ngsr_watchdog_frame, sc, sc->handle); 1217 sc->handle = timeout(ngsr_watchdog_frame, sc, hz); 1218 sc->running = 1; 1219 #endif /* NETGRAPH */ 1220 } 1221 1222 static void 1223 sr_down(struct sr_softc *sc) 1224 { 1225 u_int *fecrp; 1226 struct sr_hardc *hc = sc->hc; 1227 sca_regs *sca = hc->sca; 1228 msci_channel *msci = &sca->msci[sc->scachan]; 1229 1230 #if BUGGY > 0 1231 printf("sr_down(sc=%08x)\n", sc); 1232 #endif 1233 #ifdef NETGRAPH 1234 untimeout(ngsr_watchdog_frame, sc, sc->handle); 1235 sc->running = 0; 1236 #endif /* NETGRAPH */ 1237 1238 /* 1239 * Disable transmitter and receiver. Lower DTR and RTS. Disable 1240 * interrupts. 1241 */ 1242 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE); 1243 inb(hc->iobase); /* XXX slow it down a bit. */ 1244 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE); 1245 1246 SRC_PUT8(hc->sca_base, msci->ctl, 1247 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS); 1248 1249 if (sc->scachan == 0) 1250 switch (hc->cardtype) { 1251 case SR_CRD_N2: 1252 outb(hc->iobase + SR_MCR, 1253 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0)); 1254 break; 1255 case SR_CRD_N2PCI: 1256 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1257 *fecrp |= SR_FECR_DTR0; 1258 break; 1259 } 1260 else 1261 switch (hc->cardtype) { 1262 case SR_CRD_N2: 1263 outb(hc->iobase + SR_MCR, 1264 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1)); 1265 break; 1266 case SR_CRD_N2PCI: 1267 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1268 *fecrp |= SR_FECR_DTR1; 1269 break; 1270 } 1271 1272 if (sc->scachan == 0) { 1273 SRC_PUT8(hc->sca_base, sca->ier0, 1274 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F); 1275 SRC_PUT8(hc->sca_base, sca->ier1, 1276 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F); 1277 } else { 1278 SRC_PUT8(hc->sca_base, sca->ier0, 1279 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0); 1280 SRC_PUT8(hc->sca_base, sca->ier1, 1281 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0); 1282 } 1283 } 1284 1285 /* 1286 * Initialize the card, allocate memory for the sr_softc structures 1287 * and fill in the pointers. 1288 */ 1289 static void 1290 src_init(struct sr_hardc *hc) 1291 { 1292 struct sr_softc *sc = hc->sc; 1293 int x; 1294 u_int chanmem; 1295 u_int bufmem; 1296 u_int next; 1297 u_int descneeded; 1298 1299 #if BUGGY > 0 1300 printf("src_init(hc=%08x)\n", hc); 1301 #endif 1302 1303 chanmem = hc->memsize / hc->numports; 1304 next = 0; 1305 1306 for (x = 0; x < hc->numports; x++, sc++) { 1307 int blk; 1308 1309 for (blk = 0; blk < SR_TX_BLOCKS; blk++) { 1310 sc->block[blk].txdesc = next; 1311 bufmem = (16 * 1024) / SR_TX_BLOCKS; 1312 descneeded = bufmem / SR_BUF_SIZ; 1313 1314 sc->block[blk].txstart = sc->block[blk].txdesc 1315 + ((((descneeded * sizeof(sca_descriptor)) 1316 / SR_BUF_SIZ) + 1) 1317 * SR_BUF_SIZ); 1318 1319 sc->block[blk].txend = next + bufmem; 1320 sc->block[blk].txmax = 1321 (sc->block[blk].txend - sc->block[blk].txstart) 1322 / SR_BUF_SIZ; 1323 next += bufmem; 1324 1325 #if BUGGY > 2 1326 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n", 1327 sc->unit, blk, 1328 sc->block[blk].txdesc, sc->block[blk].txstart); 1329 #endif 1330 } 1331 1332 sc->rxdesc = next; 1333 bufmem = chanmem - (bufmem * SR_TX_BLOCKS); 1334 descneeded = bufmem / SR_BUF_SIZ; 1335 sc->rxstart = sc->rxdesc + 1336 ((((descneeded * sizeof(sca_descriptor)) / 1337 SR_BUF_SIZ) + 1) * SR_BUF_SIZ); 1338 sc->rxend = next + bufmem; 1339 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ; 1340 next += bufmem; 1341 } 1342 } 1343 1344 /* 1345 * The things done here are channel independent. 1346 * 1347 * Configure the sca waitstates. 1348 * Configure the global interrupt registers. 1349 * Enable master dma enable. 1350 */ 1351 static void 1352 sr_init_sca(struct sr_hardc *hc) 1353 { 1354 sca_regs *sca = hc->sca; 1355 1356 #if BUGGY > 0 1357 printf("sr_init_sca(hc=%08x)\n", hc); 1358 #endif 1359 1360 /* 1361 * Do the wait registers. Set everything to 0 wait states. 1362 */ 1363 SRC_PUT8(hc->sca_base, sca->pabr0, 0); 1364 SRC_PUT8(hc->sca_base, sca->pabr1, 0); 1365 SRC_PUT8(hc->sca_base, sca->wcrl, 0); 1366 SRC_PUT8(hc->sca_base, sca->wcrm, 0); 1367 SRC_PUT8(hc->sca_base, sca->wcrh, 0); 1368 1369 /* 1370 * Configure the interrupt registers. Most are cleared until the 1371 * interface is configured. 1372 */ 1373 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */ 1374 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */ 1375 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */ 1376 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr 1377 * ack */ 1378 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */ 1379 SRC_PUT8(hc->sca_base, sca->imvr, 0x40); 1380 1381 /* 1382 * Configure the timers. XXX Later 1383 */ 1384 1385 /* 1386 * Set the DMA channel priority to rotate between all four channels. 1387 * 1388 * Enable all dma channels. 1389 */ 1390 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2); 1391 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN); 1392 } 1393 1394 /* 1395 * Configure the msci 1396 * 1397 * NOTE: The serial port configuration is hardcoded at the moment. 1398 */ 1399 static void 1400 sr_init_msci(struct sr_softc *sc) 1401 { 1402 int portndx; /* on-board port number */ 1403 u_int mcr_v; /* contents of modem control */ 1404 u_int *fecrp; /* pointer for PCI's MCR i/o */ 1405 struct sr_hardc *hc = sc->hc; 1406 msci_channel *msci = &hc->sca->msci[sc->scachan]; 1407 #ifdef N2_TEST_SPEED 1408 int br_v; /* contents for BR divisor */ 1409 int etcndx; /* index into ETC table */ 1410 int fifo_v, gotspeed; /* final tabled speed found */ 1411 int tmc_v; /* timer control register */ 1412 int wanted; /* speed (bitrate) wanted... */ 1413 struct rate_line *rtp; 1414 #endif 1415 1416 portndx = sc->scachan; 1417 1418 #if BUGGY > 0 1419 printf("sr: sr_init_msci( sc=%08x)\n", sc); 1420 #endif 1421 1422 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET); 1423 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 | 1424 SCA_MD0_CRC_CCITT | 1425 SCA_MD0_CRC_ENABLE | 1426 SCA_MD0_MODE_HDLC); 1427 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK); 1428 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ); 1429 1430 /* 1431 * According to the manual I should give a reset after changing the 1432 * mode registers. 1433 */ 1434 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET); 1435 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT | 1436 SCA_CTL_UDRNC | 1437 SCA_CTL_RTS); 1438 1439 /* 1440 * XXX Later we will have to support different clock settings. 1441 */ 1442 switch (sc->clk_cfg) { 1443 default: 1444 #if BUGGY > 0 1445 printf("sr%: clk_cfg=%08x, selected default clock.\n", 1446 portndx, sc->clk_cfg); 1447 #endif 1448 /* FALLTHROUGH */ 1449 case SR_FLAGS_EXT_CLK: 1450 /* 1451 * For now all interfaces are programmed to use the RX clock 1452 * for the TX clock. 1453 */ 1454 1455 #if BUGGY > 0 1456 printf("sr%d: External Clock Selected.\n", portndx); 1457 #endif 1458 1459 SRC_PUT8(hc->sca_base, msci->rxs, 1460 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1); 1461 SRC_PUT8(hc->sca_base, msci->txs, 1462 SCA_TXS_CLK_RX | SCA_TXS_DIV1); 1463 break; 1464 1465 case SR_FLAGS_EXT_SEP_CLK: 1466 #if BUGGY > 0 1467 printf("sr%d: Split Clocking Selected.\n", portndx); 1468 #endif 1469 1470 SRC_PUT8(hc->sca_base, msci->rxs, 1471 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1); 1472 SRC_PUT8(hc->sca_base, msci->txs, 1473 SCA_TXS_CLK_TXC | SCA_TXS_DIV1); 1474 break; 1475 1476 case SR_FLAGS_INT_CLK: 1477 #if BUGGY > 0 1478 printf("sr%d: Internal Clocking selected.\n", portndx); 1479 #endif 1480 1481 /* 1482 * XXX I do need some code to set the baud rate here! 1483 */ 1484 #ifdef N2_TEST_SPEED 1485 switch (hc->cardtype) { 1486 case SR_CRD_N2PCI: 1487 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1488 mcr_v = *fecrp; 1489 etcndx = 2; 1490 break; 1491 case SR_CRD_N2: 1492 default: 1493 mcr_v = inb(hc->iobase + SR_MCR); 1494 etcndx = 0; 1495 } 1496 1497 fifo_v = 0x10; /* stolen from Linux version */ 1498 1499 /* 1500 * search for appropriate speed in table, don't calc it: 1501 */ 1502 wanted = sr_test_speed[portndx]; 1503 rtp = &n2_rates[0]; /* point to first table item */ 1504 1505 while ((rtp->target > 0) /* search table for speed */ 1506 &&(rtp->target != wanted)) 1507 rtp++; 1508 1509 /* 1510 * We've searched the table for a matching speed. If we've 1511 * found the correct rate line, we'll get the pre-calc'd 1512 * values for the TMC and baud rate divisor for subsequent 1513 * use... 1514 */ 1515 if (rtp->target > 0) { /* use table-provided values */ 1516 gotspeed = wanted; 1517 tmc_v = rtp->tmc_reg; 1518 br_v = rtp->br_reg; 1519 } else { /* otherwise assume 1MBit comm rate */ 1520 gotspeed = 10000; 1521 tmc_v = 5; 1522 br_v = 1; 1523 } 1524 1525 /* 1526 * Now we mask in the enable clock output for the MCR: 1527 */ 1528 mcr_v |= etc0vals[etcndx + portndx]; 1529 1530 /* 1531 * Now we'll program the registers with these speed- related 1532 * contents... 1533 */ 1534 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v); 1535 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v); 1536 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v); 1537 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v); 1538 1539 switch (hc->cardtype) { 1540 case SR_CRD_N2PCI: 1541 *fecrp = mcr_v; 1542 break; 1543 case SR_CRD_N2: 1544 default: 1545 outb(hc->iobase + SR_MCR, mcr_v); 1546 } 1547 1548 #if BUGGY > 0 1549 if (wanted != gotspeed) 1550 printf("sr%d: Speed wanted=%d, found=%d\n", 1551 wanted, gotspeed); 1552 1553 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n", 1554 portndx, gotspeed, tmc_v, br_v); 1555 #endif 1556 #else 1557 SRC_PUT8(hc->sca_base, msci->rxs, 1558 SCA_RXS_CLK_INT | SCA_RXS_DIV1); 1559 SRC_PUT8(hc->sca_base, msci->txs, 1560 SCA_TXS_CLK_INT | SCA_TXS_DIV1); 1561 1562 SRC_PUT8(hc->sca_base, msci->tmc, 5); 1563 1564 if (portndx == 0) 1565 switch (hc->cardtype) { 1566 case SR_CRD_N2PCI: 1567 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1568 *fecrp |= SR_FECR_ETC0; 1569 break; 1570 case SR_CRD_N2: 1571 default: 1572 mcr_v = inb(hc->iobase + SR_MCR); 1573 mcr_v |= SR_MCR_ETC0; 1574 outb(hc->iobase + SR_MCR, mcr_v); 1575 } 1576 else 1577 switch (hc->cardtype) { 1578 case SR_CRD_N2: 1579 mcr_v = inb(hc->iobase + SR_MCR); 1580 mcr_v |= SR_MCR_ETC1; 1581 outb(hc->iobase + SR_MCR, mcr_v); 1582 break; 1583 case SR_CRD_N2PCI: 1584 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1585 *fecrp |= SR_FECR_ETC1; 1586 break; 1587 } 1588 #endif 1589 } 1590 1591 /* 1592 * XXX Disable all interrupts for now. I think if you are using the 1593 * dmac you don't use these interrupts. 1594 */ 1595 SRC_PUT8(hc->sca_base, msci->ie0, 0); 1596 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C); 1597 SRC_PUT8(hc->sca_base, msci->ie2, 0); 1598 SRC_PUT8(hc->sca_base, msci->fie, 0); 1599 1600 SRC_PUT8(hc->sca_base, msci->sa0, 0); 1601 SRC_PUT8(hc->sca_base, msci->sa1, 0); 1602 1603 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */ 1604 1605 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E); 1606 SRC_PUT8(hc->sca_base, msci->trc0, 0x10); 1607 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F); 1608 } 1609 1610 /* 1611 * Configure the rx dma controller. 1612 */ 1613 static void 1614 sr_init_rx_dmac(struct sr_softc *sc) 1615 { 1616 struct sr_hardc *hc; 1617 dmac_channel *dmac; 1618 sca_descriptor *rxd; 1619 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d; 1620 1621 #if BUGGY > 0 1622 printf("sr_init_rx_dmac(sc=%08x)\n", sc); 1623 #endif 1624 1625 hc = sc->hc; 1626 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1627 1628 if (hc->mempages) 1629 SRC_SET_MEM(hc->iobase, sc->rxdesc); 1630 1631 /* 1632 * This phase initializes the contents of the descriptor table 1633 * needed to construct a circular buffer... 1634 */ 1635 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk)); 1636 rxda_d = (uintptr_t) hc->mem_start - (sc->rxdesc & ~hc->winmsk); 1637 1638 for (rxbuf = sc->rxstart; 1639 rxbuf < sc->rxend; 1640 rxbuf += SR_BUF_SIZ, rxd++) { 1641 /* 1642 * construct the circular chain... 1643 */ 1644 rxda = (uintptr_t) &rxd[1] - rxda_d + hc->mem_pstart; 1645 rxd->cp = (u_short)(rxda & 0xffff); 1646 1647 /* 1648 * set the on-card buffer address... 1649 */ 1650 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff); 1651 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff); 1652 1653 rxd->len = 0; /* bytes resident w/in granule */ 1654 rxd->stat = 0xff; /* The sca write here when finished */ 1655 } 1656 1657 /* 1658 * heal the chain so that the last entry points to the first... 1659 */ 1660 rxd--; 1661 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); 1662 1663 /* 1664 * reset the reception handler's index... 1665 */ 1666 sc->rxhind = 0; 1667 1668 /* 1669 * We'll now configure the receiver's DMA logic... 1670 */ 1671 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */ 1672 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); 1673 1674 /* XXX maybe also SCA_DMR_CNTE */ 1675 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); 1676 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ); 1677 1678 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); 1679 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff); 1680 1681 SRC_PUT16(hc->sca_base, dmac->cda, cda_v); 1682 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v); 1683 1684 rxd = (sca_descriptor *)(uintptr_t)sc->rxstart; 1685 1686 SRC_PUT16(hc->sca_base, dmac->eda, 1687 (u_short)((uintptr_t) &rxd[sc->rxmax - 1] & 0xffff)); 1688 1689 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0); 1690 1691 1692 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */ 1693 } 1694 1695 /* 1696 * Configure the TX DMA descriptors. 1697 * Initialize the needed values and chain the descriptors. 1698 */ 1699 static void 1700 sr_init_tx_dmac(struct sr_softc *sc) 1701 { 1702 int blk; 1703 u_int txbuf, txda, txda_d; 1704 struct sr_hardc *hc; 1705 sca_descriptor *txd; 1706 dmac_channel *dmac; 1707 struct buf_block *blkp; 1708 u_int x; 1709 u_int sarb_v; 1710 1711 #if BUGGY > 0 1712 printf("sr_init_tx_dmac(sc=%08x)\n", sc); 1713 #endif 1714 1715 hc = sc->hc; 1716 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1717 1718 if (hc->mempages) 1719 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc); 1720 1721 /* 1722 * Initialize the array of descriptors for transmission 1723 */ 1724 for (blk = 0; blk < SR_TX_BLOCKS; blk++) { 1725 blkp = &sc->block[blk]; 1726 txd = (sca_descriptor *)(hc->mem_start 1727 + (blkp->txdesc & hc->winmsk)); 1728 txda_d = (uintptr_t) hc->mem_start 1729 - (blkp->txdesc & ~hc->winmsk); 1730 1731 x = 0; 1732 txbuf = blkp->txstart; 1733 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) { 1734 txda = (uintptr_t) &txd[1] - txda_d + hc->mem_pstart; 1735 txd->cp = (u_short)(txda & 0xffff); 1736 1737 txd->bp = (u_short)((txbuf + hc->mem_pstart) 1738 & 0xffff); 1739 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16) 1740 & 0xff); 1741 txd->len = 0; 1742 txd->stat = 0; 1743 x++; 1744 } 1745 1746 txd--; 1747 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart) 1748 & 0xffff); 1749 1750 blkp->txtail = (uintptr_t)txd - (uintptr_t)hc->mem_start; 1751 } 1752 1753 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */ 1754 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); 1755 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); 1756 SRC_PUT8(hc->sca_base, dmac->dir, 1757 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF); 1758 1759 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16; 1760 sarb_v &= 0x00ff; 1761 1762 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v); 1763 } 1764 1765 /* 1766 * Look through the descriptors to see if there is a complete packet 1767 * available. Stop if we get to where the sca is busy. 1768 * 1769 * Return the length and status of the packet. 1770 * Return nonzero if there is a packet available. 1771 * 1772 * NOTE: 1773 * It seems that we get the interrupt a bit early. The updateing of 1774 * descriptor values is not always completed when this is called. 1775 */ 1776 static int 1777 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat) 1778 { 1779 int granules; /* count of granules in pkt */ 1780 int wki, wko; 1781 struct sr_hardc *hc; 1782 sca_descriptor *rxdesc; /* current descriptor */ 1783 sca_descriptor *endp; /* ending descriptor */ 1784 sca_descriptor *cda; /* starting descriptor */ 1785 1786 hc = sc->hc; /* get card's information */ 1787 1788 /* 1789 * set up starting descriptor by pulling that info from the DMA half 1790 * of the HD chip... 1791 */ 1792 wki = DMAC_RXCH(sc->scachan); 1793 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda); 1794 1795 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk)); 1796 1797 #if BUGGY > 1 1798 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n", 1799 wki, wko, cda); 1800 #endif 1801 1802 /* 1803 * open the appropriate memory window and set our expectations... 1804 */ 1805 if (hc->mempages) { 1806 SRC_SET_MEM(hc->iobase, sc->rxdesc); 1807 SRC_SET_ON(hc->iobase); 1808 } 1809 rxdesc = (sca_descriptor *) 1810 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 1811 endp = rxdesc; 1812 rxdesc = &rxdesc[sc->rxhind]; 1813 endp = &endp[sc->rxmax]; 1814 1815 *len = 0; /* reset result total length */ 1816 granules = 0; /* reset count of granules */ 1817 1818 /* 1819 * This loop will scan descriptors, but it *will* puke up if we wrap 1820 * around to our starting point... 1821 */ 1822 while (rxdesc != cda) { 1823 *len += rxdesc->len; /* increment result length */ 1824 granules++; 1825 1826 /* 1827 * If we hit a valid packet's completion we'll know we've 1828 * got a live one, and that we can deliver the packet. 1829 * Since we're only allowed to report a packet available, 1830 * somebody else does that... 1831 */ 1832 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */ 1833 *rxstat = rxdesc->stat; /* return closing */ 1834 #if BUGGY > 0 1835 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n", 1836 sc->unit, *len, *rxstat, granules); 1837 #endif 1838 return 1; /* indicate success */ 1839 } 1840 /* 1841 * OK, this packet take up multiple granules. Move on to 1842 * the next descriptor so we can consider it... 1843 */ 1844 rxdesc++; 1845 1846 if (rxdesc == endp) /* recognize & act on wrap point */ 1847 rxdesc = (sca_descriptor *) 1848 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 1849 } 1850 1851 /* 1852 * Nothing found in the DPRAM. Let the caller know... 1853 */ 1854 *len = 0; 1855 *rxstat = 0; 1856 1857 return 0; 1858 } 1859 1860 /* 1861 * Copy a packet from the on card memory into a provided mbuf. 1862 * Take into account that buffers wrap and that a packet may 1863 * be larger than a buffer. 1864 */ 1865 static void 1866 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len) 1867 { 1868 struct sr_hardc *hc; 1869 sca_descriptor *rxdesc; 1870 u_int rxdata; 1871 u_int rxmax; 1872 u_int off = 0; 1873 u_int tlen; 1874 1875 #if BUGGY > 0 1876 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n", 1877 m, sc, len); 1878 #endif 1879 1880 hc = sc->hc; 1881 1882 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ); 1883 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ); 1884 1885 rxdesc = (sca_descriptor *) 1886 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 1887 rxdesc = &rxdesc[sc->rxhind]; 1888 1889 /* 1890 * Using the count of bytes in the received packet, we decrement it 1891 * for each granule (controller by an SCA descriptor) to control the 1892 * looping... 1893 */ 1894 while (len) { 1895 /* 1896 * tlen gets the length of *this* granule... ...which is 1897 * then copied to the target buffer. 1898 */ 1899 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ; 1900 1901 if (hc->mempages) 1902 SRC_SET_MEM(hc->iobase, rxdata); 1903 1904 bcopy(hc->mem_start + (rxdata & hc->winmsk), 1905 mtod(m, caddr_t) +off, 1906 tlen); 1907 1908 off += tlen; 1909 len -= tlen; 1910 1911 /* 1912 * now, return to the descriptor's window in DPRAM and reset 1913 * the descriptor we've just suctioned... 1914 */ 1915 if (hc->mempages) 1916 SRC_SET_MEM(hc->iobase, sc->rxdesc); 1917 1918 rxdesc->len = 0; 1919 rxdesc->stat = 0xff; 1920 1921 /* 1922 * Move on to the next granule. If we've any remaining 1923 * bytes to process we'll just continue in our loop... 1924 */ 1925 rxdata += SR_BUF_SIZ; 1926 rxdesc++; 1927 1928 if (rxdata == rxmax) { /* handle the wrap point */ 1929 rxdata = sc->rxstart; 1930 rxdesc = (sca_descriptor *) 1931 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 1932 } 1933 } 1934 } 1935 1936 /* 1937 * If single is set, just eat a packet. Otherwise eat everything up to 1938 * where cda points. Update pointers to point to the next packet. 1939 * 1940 * This handles "flushing" of a packet as received... 1941 * 1942 * If the "single" parameter is zero, all pending reeceive traffic will 1943 * be flushed out of existence. A non-zero value will only drop the 1944 * *next* (currently) pending packet... 1945 */ 1946 static void 1947 sr_eat_packet(struct sr_softc *sc, int single) 1948 { 1949 struct sr_hardc *hc; 1950 sca_descriptor *rxdesc; /* current descriptor being eval'd */ 1951 sca_descriptor *endp; /* last descriptor in chain */ 1952 sca_descriptor *cda; /* current start point */ 1953 u_int loopcnt = 0; /* count of packets flushed ??? */ 1954 u_char stat; /* captured status byte from descr */ 1955 1956 hc = sc->hc; 1957 cda = (sca_descriptor *)(hc->mem_start + 1958 (SRC_GET16(hc->sca_base, 1959 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) & 1960 hc->winmsk)); 1961 1962 /* 1963 * loop until desc->stat == (0xff || EOM) Clear the status and 1964 * length in the descriptor. Increment the descriptor. 1965 */ 1966 if (hc->mempages) 1967 SRC_SET_MEM(hc->iobase, sc->rxdesc); 1968 1969 rxdesc = (sca_descriptor *) 1970 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 1971 endp = rxdesc; 1972 rxdesc = &rxdesc[sc->rxhind]; 1973 endp = &endp[sc->rxmax]; 1974 1975 /* 1976 * allow loop, but abort it if we wrap completely... 1977 */ 1978 while (rxdesc != cda) { 1979 loopcnt++; 1980 1981 if (loopcnt > sc->rxmax) { 1982 printf("sr%d: eat pkt %d loop, cda %p, " 1983 "rxdesc %p, stat %x.\n", 1984 sc->unit, loopcnt, cda, rxdesc, 1985 rxdesc->stat); 1986 break; 1987 } 1988 stat = rxdesc->stat; 1989 1990 rxdesc->len = 0; 1991 rxdesc->stat = 0xff; 1992 1993 rxdesc++; 1994 sc->rxhind++; 1995 1996 if (rxdesc == endp) { 1997 rxdesc = (sca_descriptor *) 1998 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 1999 sc->rxhind = 0; 2000 } 2001 if (single && (stat == SCA_DESC_EOM)) 2002 break; 2003 } 2004 2005 /* 2006 * Update the eda to the previous descriptor. 2007 */ 2008 rxdesc = (sca_descriptor *)(uintptr_t)sc->rxdesc; 2009 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax]; 2010 2011 SRC_PUT16(hc->sca_base, 2012 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, 2013 (u_short)(((uintptr_t)rxdesc + hc->mem_pstart) & 0xffff)); 2014 } 2015 2016 /* 2017 * While there is packets available in the rx buffer, read them out 2018 * into mbufs and ship them off. 2019 */ 2020 static void 2021 sr_get_packets(struct sr_softc *sc) 2022 { 2023 u_char rxstat; /* acquired status byte */ 2024 int i; 2025 int pkts; /* count of packets found */ 2026 int rxndx; /* rcv buffer index */ 2027 int tries; /* settling time counter */ 2028 u_int len; /* length of pending packet */ 2029 struct sr_hardc *hc; /* card-level information */ 2030 sca_descriptor *rxdesc; /* descriptor in memory */ 2031 #ifndef NETGRAPH 2032 struct ifnet *ifp; /* network intf ctl table */ 2033 #else 2034 int error; 2035 #endif /* NETGRAPH */ 2036 struct mbuf *m = NULL; /* message buffer */ 2037 2038 #if BUGGY > 0 2039 printf("sr_get_packets(sc=%08x)\n", sc); 2040 #endif 2041 2042 hc = sc->hc; 2043 #ifndef NETGRAPH 2044 ifp = &sc->ifsppp.pp_if; 2045 #endif /* NETGRAPH */ 2046 2047 if (hc->mempages) { 2048 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2049 SRC_SET_ON(hc->iobase); /* enable shared memory */ 2050 } 2051 pkts = 0; /* reset count of found packets */ 2052 2053 /* 2054 * for each complete packet in the receiving pool, process each 2055 * packet... 2056 */ 2057 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */ 2058 /* 2059 * I have seen situations where we got the interrupt but the 2060 * status value wasn't deposited. This code should allow 2061 * the status byte's value to settle... 2062 */ 2063 2064 tries = 5; 2065 2066 while ((rxstat == 0x00ff) 2067 && --tries) 2068 sr_packet_avail(sc, &len, &rxstat); 2069 2070 #if BUGGY > 1 2071 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n", 2072 len, rxstat); 2073 #endif 2074 2075 pkts++; 2076 #ifdef NETGRAPH 2077 sc->inbytes += len; 2078 sc->inlast = 0; 2079 #endif /* NETGRAPH */ 2080 2081 /* 2082 * OK, we've settled the incoming message status. We can now 2083 * process it... 2084 */ 2085 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 2086 #if BUGGY > 1 2087 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n", 2088 sc->unit, rxstat, len); 2089 #endif 2090 2091 MGETHDR(m, M_DONTWAIT, MT_DATA); 2092 if (m == NULL) { 2093 /* 2094 * eat (flush) packet if get mbuf fail!! 2095 */ 2096 sr_eat_packet(sc, 1); 2097 continue; 2098 } 2099 /* 2100 * construct control information for pass-off 2101 */ 2102 #ifndef NETGRAPH 2103 m->m_pkthdr.rcvif = ifp; 2104 #else 2105 m->m_pkthdr.rcvif = NULL; 2106 #endif /* NETGRAPH */ 2107 m->m_pkthdr.len = m->m_len = len; 2108 if (len > MHLEN) { 2109 MCLGET(m, M_DONTWAIT); 2110 if ((m->m_flags & M_EXT) == 0) { 2111 /* 2112 * We couldn't get a big enough 2113 * message packet, so we'll send the 2114 * packet to /dev/null... 2115 */ 2116 m_freem(m); 2117 sr_eat_packet(sc, 1); 2118 continue; 2119 } 2120 } 2121 /* 2122 * OK, we've got a good message buffer. Now we can 2123 * copy the received message into it 2124 */ 2125 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */ 2126 2127 #ifndef NETGRAPH 2128 BPF_MTAP(ifp, m); 2129 2130 #if BUGGY > 3 2131 { 2132 u_char *bp; 2133 2134 bp = (u_char *)m; 2135 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n", 2136 sc->unit, 2137 bp[0], bp[1], bp[2], 2138 bp[4], bp[5], bp[6]); 2139 } 2140 #endif 2141 sppp_input(ifp, m); 2142 ifp->if_ipackets++; 2143 2144 #else /* NETGRAPH */ 2145 #if BUGGY > 3 2146 { 2147 u_char *bp; 2148 2149 bp = mtod(m,u_char *); 2150 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x", 2151 sc->unit, 2152 bp[0], bp[1], bp[2], 2153 bp[4], bp[5], bp[6]); 2154 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n", 2155 bp[6], bp[7], bp[8], 2156 bp[9], bp[10], bp[11]); 2157 } 2158 #endif 2159 NG_SEND_DATA_ONLY(error, sc->hook, m); 2160 sc->ipackets++; 2161 #endif /* NETGRAPH */ 2162 /* 2163 * Update the eda to the previous descriptor. 2164 */ 2165 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ; 2166 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 2167 2168 rxdesc = (sca_descriptor *)(uintptr_t)sc->rxdesc; 2169 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax; 2170 rxdesc = &rxdesc[rxndx]; 2171 2172 SRC_PUT16(hc->sca_base, 2173 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, 2174 (u_short)(((uintptr_t)rxdesc + hc->mem_pstart) 2175 & 0xffff)); 2176 2177 } else { 2178 int got_st3, got_cda, got_eda; 2179 int tries = 5; 2180 2181 while ((rxstat == 0xff) && --tries) 2182 sr_packet_avail(sc, &len, &rxstat); 2183 2184 /* 2185 * It look like we get an interrupt early 2186 * sometimes and then the status is not 2187 * filled in yet. 2188 */ 2189 if (tries && (tries != 5)) 2190 continue; 2191 2192 /* 2193 * This chunk of code handles the error packets. 2194 * We'll log them for posterity... 2195 */ 2196 sr_eat_packet(sc, 1); 2197 2198 #ifndef NETGRAPH 2199 ifp->if_ierrors++; 2200 #else 2201 sc->ierrors[0]++; 2202 #endif /* NETGRAPH */ 2203 2204 got_st3 = SRC_GET8(hc->sca_base, 2205 hc->sca->msci[sc->scachan].st3); 2206 got_cda = SRC_GET16(hc->sca_base, 2207 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda); 2208 got_eda = SRC_GET16(hc->sca_base, 2209 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda); 2210 2211 #if BUGGY > 0 2212 printf("sr%d: Receive error chan %d, " 2213 "stat %02x, msci st3 %02x," 2214 "rxhind %d, cda %04x, eda %04x.\n", 2215 sc->unit, sc->scachan, rxstat, 2216 got_st3, sc->rxhind, got_cda, got_eda); 2217 #endif 2218 } 2219 } 2220 2221 #if BUGGY > 0 2222 printf("sr%d: sr_get_packets() found %d packet(s)\n", 2223 sc->unit, pkts); 2224 #endif 2225 2226 if (hc->mempages) 2227 SRC_SET_OFF(hc->iobase); 2228 } 2229 2230 /* 2231 * All DMA interrupts come here. 2232 * 2233 * Each channel has two interrupts. 2234 * Interrupt A for errors and Interrupt B for normal stuff like end 2235 * of transmit or receive dmas. 2236 */ 2237 static void 2238 sr_dmac_intr(struct sr_hardc *hc, u_char isr1) 2239 { 2240 u_char dsr; /* contents of DMA Stat Reg */ 2241 u_char dotxstart; /* enables for tranmit part */ 2242 int mch; /* channel being processed */ 2243 struct sr_softc *sc; /* channel's softc structure */ 2244 sca_regs *sca = hc->sca; 2245 dmac_channel *dmac; /* dma structure of chip */ 2246 2247 #if BUGGY > 0 2248 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1); 2249 #endif 2250 2251 mch = 0; /* assume chan0 on card */ 2252 dotxstart = isr1; /* copy for xmitter starts */ 2253 2254 /* 2255 * Shortcut if there is no interrupts for dma channel 0 or 1. 2256 * Skip processing for channel 0 if no incoming hit 2257 */ 2258 if ((isr1 & 0x0F) == 0) { 2259 mch = 1; 2260 isr1 >>= 4; 2261 } 2262 do { 2263 sc = &hc->sc[mch]; 2264 2265 /* 2266 * Transmit channel - DMA Status Register Evaluation 2267 */ 2268 if (isr1 & 0x0C) { 2269 dmac = &sca->dmac[DMAC_TXCH(mch)]; 2270 2271 /* 2272 * get the DMA Status Register contents and write 2273 * back to reset interrupt... 2274 */ 2275 dsr = SRC_GET8(hc->sca_base, dmac->dsr); 2276 SRC_PUT8(hc->sca_base, dmac->dsr, dsr); 2277 2278 /* 2279 * Check for (& process) a Counter overflow 2280 */ 2281 if (dsr & SCA_DSR_COF) { 2282 printf("sr%d: TX DMA Counter overflow, " 2283 "txpacket no %lu.\n", 2284 #ifndef NETGRAPH 2285 sc->unit, sc->ifsppp.pp_if.if_opackets); 2286 sc->ifsppp.pp_if.if_oerrors++; 2287 #else 2288 sc->unit, sc->opackets); 2289 sc->oerrors++; 2290 #endif /* NETGRAPH */ 2291 } 2292 /* 2293 * Check for (& process) a Buffer overflow 2294 */ 2295 if (dsr & SCA_DSR_BOF) { 2296 printf("sr%d: TX DMA Buffer overflow, " 2297 "txpacket no %lu, dsr %02x, " 2298 "cda %04x, eda %04x.\n", 2299 #ifndef NETGRAPH 2300 sc->unit, sc->ifsppp.pp_if.if_opackets, 2301 #else 2302 sc->unit, sc->opackets, 2303 #endif /* NETGRAPH */ 2304 dsr, 2305 SRC_GET16(hc->sca_base, dmac->cda), 2306 SRC_GET16(hc->sca_base, dmac->eda)); 2307 #ifndef NETGRAPH 2308 sc->ifsppp.pp_if.if_oerrors++; 2309 #else 2310 sc->oerrors++; 2311 #endif /* NETGRAPH */ 2312 } 2313 /* 2314 * Check for (& process) an End of Transfer (OK) 2315 */ 2316 if (dsr & SCA_DSR_EOT) { 2317 /* 2318 * This should be the most common case. 2319 * 2320 * Clear the IFF_OACTIVE flag. 2321 * 2322 * Call srstart to start a new transmit if 2323 * there is data to transmit. 2324 */ 2325 #if BUGGY > 0 2326 printf("sr%d: TX Completed OK\n", sc->unit); 2327 #endif 2328 sc->xmit_busy = 0; 2329 #ifndef NETGRAPH 2330 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 2331 sc->ifsppp.pp_if.if_timer = 0; 2332 #else 2333 /* XXX may need to mark tx inactive? */ 2334 sc->out_deficit++; 2335 sc->out_dog = DOG_HOLDOFF; 2336 #endif /* NETGRAPH */ 2337 2338 if (sc->txb_inuse && --sc->txb_inuse) 2339 sr_xmit(sc); 2340 } 2341 } 2342 /* 2343 * Receive channel processing of DMA Status Register 2344 */ 2345 if (isr1 & 0x03) { 2346 dmac = &sca->dmac[DMAC_RXCH(mch)]; 2347 2348 dsr = SRC_GET8(hc->sca_base, dmac->dsr); 2349 SRC_PUT8(hc->sca_base, dmac->dsr, dsr); 2350 2351 /* 2352 * End of frame processing (MSG OK?) 2353 */ 2354 if (dsr & SCA_DSR_EOM) { 2355 #if BUGGY > 0 2356 int tt, ind; 2357 2358 #ifndef NETGRAPH 2359 tt = sc->ifsppp.pp_if.if_ipackets; 2360 #else /* NETGRAPH */ 2361 tt = sc->ipackets; 2362 #endif /* NETGRAPH */ 2363 ind = sc->rxhind; 2364 #endif 2365 2366 sr_get_packets(sc); 2367 #if BUGGY > 0 2368 #ifndef NETGRAPH 2369 if (tt == sc->ifsppp.pp_if.if_ipackets) 2370 #else /* NETGRAPH */ 2371 if (tt == sc->ipackets) 2372 #endif /* NETGRAPH */ 2373 { 2374 sca_descriptor *rxdesc; 2375 int i; 2376 2377 printf("SR: RXINTR isr1 %x, dsr %x, " 2378 "no data %d pkts, orxind %d.\n", 2379 dotxstart, dsr, tt, ind); 2380 printf("SR: rxdesc %x, rxstart %x, " 2381 "rxend %x, rxhind %d, " 2382 "rxmax %d.\n", 2383 sc->rxdesc, sc->rxstart, 2384 sc->rxend, sc->rxhind, 2385 sc->rxmax); 2386 printf("SR: cda %x, eda %x.\n", 2387 SRC_GET16(hc->sca_base, dmac->cda), 2388 SRC_GET16(hc->sca_base, dmac->eda)); 2389 2390 if (hc->mempages) { 2391 SRC_SET_ON(hc->iobase); 2392 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2393 } 2394 rxdesc = (sca_descriptor *) 2395 (hc->mem_start + 2396 (sc->rxdesc & hc->winmsk)); 2397 rxdesc = &rxdesc[sc->rxhind]; 2398 2399 for (i = 0; i < 3; i++, rxdesc++) 2400 printf("SR: rxdesc->stat %x, " 2401 "len %d.\n", 2402 rxdesc->stat, 2403 rxdesc->len); 2404 2405 if (hc->mempages) 2406 SRC_SET_OFF(hc->iobase); 2407 } 2408 #endif /* BUGGY */ 2409 } 2410 /* 2411 * Check for Counter overflow 2412 */ 2413 if (dsr & SCA_DSR_COF) { 2414 printf("sr%d: RX DMA Counter overflow, " 2415 "rxpkts %lu.\n", 2416 #ifndef NETGRAPH 2417 sc->unit, sc->ifsppp.pp_if.if_ipackets); 2418 sc->ifsppp.pp_if.if_ierrors++; 2419 #else /* NETGRAPH */ 2420 sc->unit, sc->ipackets); 2421 sc->ierrors[1]++; 2422 #endif /* NETGRAPH */ 2423 } 2424 /* 2425 * Check for Buffer overflow 2426 */ 2427 if (dsr & SCA_DSR_BOF) { 2428 printf("sr%d: RX DMA Buffer overflow, " 2429 "rxpkts %lu, rxind %d, " 2430 "cda %x, eda %x, dsr %x.\n", 2431 #ifndef NETGRAPH 2432 sc->unit, sc->ifsppp.pp_if.if_ipackets, 2433 #else /* NETGRAPH */ 2434 sc->unit, sc->ipackets, 2435 #endif /* NETGRAPH */ 2436 sc->rxhind, 2437 SRC_GET16(hc->sca_base, dmac->cda), 2438 SRC_GET16(hc->sca_base, dmac->eda), 2439 dsr); 2440 2441 /* 2442 * Make sure we eat as many as possible. 2443 * Then get the system running again. 2444 */ 2445 if (hc->mempages) 2446 SRC_SET_ON(hc->iobase); 2447 2448 sr_eat_packet(sc, 0); 2449 #ifndef NETGRAPH 2450 sc->ifsppp.pp_if.if_ierrors++; 2451 #else /* NETGRAPH */ 2452 sc->ierrors[2]++; 2453 #endif /* NETGRAPH */ 2454 2455 SRC_PUT8(hc->sca_base, 2456 sca->msci[mch].cmd, 2457 SCA_CMD_RXMSGREJ); 2458 2459 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); 2460 2461 #if BUGGY > 0 2462 printf("sr%d: RX DMA Buffer overflow, " 2463 "rxpkts %lu, rxind %d, " 2464 "cda %x, eda %x, dsr %x. After\n", 2465 sc->unit, 2466 #ifndef NETGRAPH 2467 sc->ipackets, 2468 #else /* NETGRAPH */ 2469 sc->ifsppp.pp_if.if_ipackets, 2470 #endif /* NETGRAPH */ 2471 sc->rxhind, 2472 SRC_GET16(hc->sca_base, dmac->cda), 2473 SRC_GET16(hc->sca_base, dmac->eda), 2474 SRC_GET8(hc->sca_base, dmac->dsr)); 2475 #endif 2476 2477 if (hc->mempages) 2478 SRC_SET_OFF(hc->iobase); 2479 } 2480 /* 2481 * End of Transfer 2482 */ 2483 if (dsr & SCA_DSR_EOT) { 2484 /* 2485 * If this happen, it means that we are 2486 * receiving faster than what the processor 2487 * can handle. 2488 * 2489 * XXX We should enable the dma again. 2490 */ 2491 printf("sr%d: RX End of xfer, rxpkts %lu.\n", 2492 sc->unit, 2493 #ifndef NETGRAPH 2494 sc->ifsppp.pp_if.if_ipackets); 2495 sc->ifsppp.pp_if.if_ierrors++; 2496 #else 2497 sc->ipackets); 2498 sc->ierrors[3]++; 2499 #endif /* NETGRAPH */ 2500 } 2501 } 2502 isr1 >>= 4; /* process next half of ISR */ 2503 mch++; /* and move to next channel */ 2504 } while ((mch < NCHAN) && isr1); /* loop for each chn */ 2505 2506 /* 2507 * Now that we have done all the urgent things, see if we can fill 2508 * the transmit buffers. 2509 */ 2510 for (mch = 0; mch < NCHAN; mch++) { 2511 if (dotxstart & 0x0C) { /* TX initiation enabled? */ 2512 sc = &hc->sc[mch]; 2513 #ifndef NETGRAPH 2514 srstart(&sc->ifsppp.pp_if); 2515 #else 2516 srstart(sc); 2517 #endif /* NETGRAPH */ 2518 } 2519 dotxstart >>= 4;/* shift for next channel */ 2520 } 2521 } 2522 #ifndef NETGRAPH 2523 #ifdef USE_MODEMCK 2524 /* 2525 * Perform timeout on an FR channel 2526 * 2527 * Establish a periodic check of open N2 ports; If 2528 * a port is open/active, its DCD state is checked 2529 * and a loss of DCD is recognized (and eventually 2530 * processed). 2531 */ 2532 static void 2533 sr_modemck(void *arg) 2534 { 2535 u_int s; 2536 int card; /* card index in table */ 2537 int cards; /* card list index */ 2538 int mch; /* channel on card */ 2539 u_char dcd_v; /* Data Carrier Detect */ 2540 u_char got_st0; /* contents of ST0 */ 2541 u_char got_st1; /* contents of ST1 */ 2542 u_char got_st2; /* contents of ST2 */ 2543 u_char got_st3; /* contents of ST3 */ 2544 struct sr_hardc *hc; /* card's configuration */ 2545 struct sr_hardc *Card[16];/* up to 16 cards in system */ 2546 struct sr_softc *sc; /* channel's softc structure */ 2547 struct ifnet *ifp; /* interface control table */ 2548 msci_channel *msci; /* regs specific to channel */ 2549 2550 s = splimp(); 2551 2552 #if 0 2553 if (sr_opens == 0) { /* count of "up" channels */ 2554 sr_watcher = 0; /* indicate no watcher */ 2555 splx(s); 2556 return; 2557 } 2558 #endif 2559 2560 sr_watcher = 1; /* mark that we're online */ 2561 2562 /* 2563 * Now we'll need a list of cards to process. Since we can handle 2564 * both ISA and PCI cards (and I didn't think of making this logic 2565 * global YET) we'll generate a single table of card table 2566 * addresses. 2567 */ 2568 cards = 0; 2569 2570 for (card = 0; card < NSR; card++) { 2571 hc = &sr_hardc[card]; 2572 2573 if (hc->sc == (void *)0) 2574 continue; 2575 2576 Card[cards++] = hc; 2577 } 2578 2579 hc = sr_hardc_pci; 2580 2581 while (hc) { 2582 Card[cards++] = hc; 2583 hc = hc->next; 2584 } 2585 2586 /* 2587 * OK, we've got work we can do. Let's do it... (Please note that 2588 * this code _only_ deals w/ ISA cards) 2589 */ 2590 for (card = 0; card < cards; card++) { 2591 hc = Card[card];/* get card table */ 2592 2593 for (mch = 0; mch < hc->numports; mch++) { 2594 sc = &hc->sc[mch]; 2595 2596 ifp = &sc->ifsppp.pp_if; 2597 2598 /* 2599 * if this channel isn't "up", skip it 2600 */ 2601 if ((ifp->if_flags & IFF_UP) == 0) 2602 continue; 2603 2604 /* 2605 * OK, now we can go looking at this channel's 2606 * actual register contents... 2607 */ 2608 msci = &hc->sca->msci[sc->scachan]; 2609 2610 /* 2611 * OK, now we'll look into the actual status of this 2612 * channel... 2613 * 2614 * I suck in more registers than strictly needed 2615 */ 2616 got_st0 = SRC_GET8(hc->sca_base, msci->st0); 2617 got_st1 = SRC_GET8(hc->sca_base, msci->st1); 2618 got_st2 = SRC_GET8(hc->sca_base, msci->st2); 2619 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 2620 2621 /* 2622 * We want to see if the DCD signal is up (DCD is 2623 * true if zero) 2624 */ 2625 dcd_v = (got_st3 & SCA_ST3_DCD) == 0; 2626 2627 if (dcd_v == 0) 2628 printf("sr%d: DCD lost\n", sc->unit); 2629 } 2630 } 2631 2632 /* 2633 * OK, now set up for the next modem signal checking pass... 2634 */ 2635 timeout(sr_modemck, NULL, hz); 2636 2637 splx(s); 2638 } 2639 #endif 2640 #else /* NETGRAPH */ 2641 /* 2642 * If a port is open/active, it's DCD state is checked 2643 * and a loss of DCD is recognized (and eventually processed?). 2644 */ 2645 static void 2646 sr_modemck(struct sr_softc *sc ) 2647 { 2648 u_int s; 2649 u_char got_st3; /* contents of ST3 */ 2650 struct sr_hardc *hc = sc->hc; /* card's configuration */ 2651 msci_channel *msci; /* regs specific to channel */ 2652 2653 s = splimp(); 2654 2655 2656 if (sc->running == 0) 2657 return; 2658 /* 2659 * OK, now we can go looking at this channel's register contents... 2660 */ 2661 msci = &hc->sca->msci[sc->scachan]; 2662 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 2663 2664 /* 2665 * We want to see if the DCD signal is up (DCD is true if zero) 2666 */ 2667 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0; 2668 splx(s); 2669 } 2670 2671 #endif /* NETGRAPH */ 2672 static void 2673 sr_msci_intr(struct sr_hardc *hc, u_char isr0) 2674 { 2675 printf("src%d: SRINTR: MSCI\n", hc->cunit); 2676 } 2677 2678 static void 2679 sr_timer_intr(struct sr_hardc *hc, u_char isr2) 2680 { 2681 printf("src%d: SRINTR: TIMER\n", hc->cunit); 2682 } 2683 2684 #ifdef NETGRAPH 2685 /***************************************** 2686 * Device timeout/watchdog routine. 2687 * called once per second. 2688 * checks to see that if activity was expected, that it hapenned. 2689 * At present we only look to see if expected output was completed. 2690 */ 2691 static void 2692 ngsr_watchdog_frame(void * arg) 2693 { 2694 struct sr_softc * sc = arg; 2695 int s; 2696 int speed; 2697 2698 if (sc->running == 0) 2699 return; /* if we are not running let timeouts die */ 2700 /* 2701 * calculate the apparent throughputs 2702 * XXX a real hack 2703 */ 2704 s = splimp(); 2705 speed = sc->inbytes - sc->lastinbytes; 2706 sc->lastinbytes = sc->inbytes; 2707 if ( sc->inrate < speed ) 2708 sc->inrate = speed; 2709 speed = sc->outbytes - sc->lastoutbytes; 2710 sc->lastoutbytes = sc->outbytes; 2711 if ( sc->outrate < speed ) 2712 sc->outrate = speed; 2713 sc->inlast++; 2714 splx(s); 2715 2716 if ((sc->inlast > QUITE_A_WHILE) 2717 && (sc->out_deficit > LOTS_OF_PACKETS)) { 2718 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit); 2719 s = splimp(); 2720 sr_down(sc); 2721 sr_up(sc); 2722 sc->inlast = sc->out_deficit = 0; 2723 splx(s); 2724 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 2725 if (sc->out_dog == 0) { 2726 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n", 2727 sc->unit); 2728 s = splimp(); 2729 srwatchdog(sc); 2730 #if 0 2731 sr_down(sc); 2732 sr_up(sc); 2733 #endif 2734 splx(s); 2735 sc->inlast = sc->out_deficit = 0; 2736 } else { 2737 sc->out_dog--; 2738 } 2739 } 2740 sr_modemck(sc); /* update the DCD status */ 2741 sc->handle = timeout(ngsr_watchdog_frame, sc, hz); 2742 } 2743 2744 /*********************************************************************** 2745 * This section contains the methods for the Netgraph interface 2746 ***********************************************************************/ 2747 /* 2748 * It is not possible or allowable to create a node of this type. 2749 * If the hardware exists, it will already have created it. 2750 */ 2751 static int 2752 ngsr_constructor(node_p node) 2753 { 2754 return (EINVAL); 2755 } 2756 2757 /* 2758 * give our ok for a hook to be added... 2759 * If we are not running this should kick the device into life. 2760 * The hook's private info points to our stash of info about that 2761 * channel. 2762 */ 2763 static int 2764 ngsr_newhook(node_p node, hook_p hook, const char *name) 2765 { 2766 struct sr_softc * sc = NG_NODE_PRIVATE(node); 2767 2768 /* 2769 * check if it's our friend the debug hook 2770 */ 2771 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) { 2772 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */ 2773 sc->debug_hook = hook; 2774 return (0); 2775 } 2776 2777 /* 2778 * Check for raw mode hook. 2779 */ 2780 if (strcmp(name, NG_SR_HOOK_RAW) != 0) { 2781 return (EINVAL); 2782 } 2783 NG_HOOK_SET_PRIVATE(hook, sc); 2784 sc->hook = hook; 2785 sc->datahooks++; 2786 sr_up(sc); 2787 return (0); 2788 } 2789 2790 /* 2791 * incoming messages. 2792 * Just respond to the generic TEXT_STATUS message 2793 */ 2794 static int 2795 ngsr_rcvmsg(node_p node, item_p item, hook_p lasthook) 2796 { 2797 struct sr_softc * sc; 2798 struct ng_mesg *resp = NULL; 2799 int error = 0; 2800 struct ng_mesg *msg; 2801 2802 NGI_GET_MSG(item,msg); 2803 sc = NG_NODE_PRIVATE(node); 2804 switch (msg->header.typecookie) { 2805 case NG_SR_COOKIE: 2806 error = EINVAL; 2807 break; 2808 case NGM_GENERIC_COOKIE: 2809 switch(msg->header.cmd) { 2810 case NGM_TEXT_STATUS: { 2811 char *arg; 2812 int pos = 0; 2813 2814 int resplen = sizeof(struct ng_mesg) + 512; 2815 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT); 2816 if (resp == NULL) { 2817 error = ENOMEM; 2818 break; 2819 } 2820 arg = (resp)->data; 2821 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 2822 "highest rate seen: %ld B/S in, %ld B/S out\n", 2823 sc->inbytes, sc->outbytes, 2824 sc->inrate, sc->outrate); 2825 pos += sprintf(arg + pos, 2826 "%ld output errors\n", 2827 sc->oerrors); 2828 pos += sprintf(arg + pos, 2829 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n", 2830 sc->ierrors[0], 2831 sc->ierrors[1], 2832 sc->ierrors[2], 2833 sc->ierrors[3], 2834 sc->ierrors[4], 2835 sc->ierrors[5]); 2836 2837 resp->header.arglen = pos + 1; 2838 break; 2839 } 2840 default: 2841 error = EINVAL; 2842 break; 2843 } 2844 break; 2845 default: 2846 error = EINVAL; 2847 break; 2848 } 2849 /* Take care of synchronous response, if any */ 2850 NG_RESPOND_MSG(error, node, item, resp); 2851 NG_FREE_MSG(msg); 2852 return (error); 2853 } 2854 2855 /* 2856 * get data from another node and transmit it to the correct channel 2857 */ 2858 static int 2859 ngsr_rcvdata(hook_p hook, item_p item) 2860 { 2861 int s; 2862 int error = 0; 2863 struct sr_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2864 struct ifqueue *xmitq_p; 2865 struct mbuf *m; 2866 meta_p meta; 2867 2868 NGI_GET_M(item, m); 2869 NGI_GET_META(item, meta); 2870 NG_FREE_ITEM(item); 2871 /* 2872 * data doesn't come in from just anywhere (e.g control hook) 2873 */ 2874 if ( NG_HOOK_PRIVATE(hook) == NULL) { 2875 error = ENETDOWN; 2876 goto bad; 2877 } 2878 2879 /* 2880 * Now queue the data for when it can be sent 2881 */ 2882 if (meta && meta->priority > 0) { 2883 xmitq_p = (&sc->xmitq_hipri); 2884 } else { 2885 xmitq_p = (&sc->xmitq); 2886 } 2887 s = splimp(); 2888 IF_LOCK(xmitq_p); 2889 if (_IF_QFULL(xmitq_p)) { 2890 _IF_DROP(xmitq_p); 2891 IF_UNLOCK(xmitq_p); 2892 splx(s); 2893 error = ENOBUFS; 2894 goto bad; 2895 } 2896 _IF_ENQUEUE(xmitq_p, m); 2897 IF_UNLOCK(xmitq_p); 2898 srstart(sc); 2899 splx(s); 2900 return (0); 2901 2902 bad: 2903 /* 2904 * It was an error case. 2905 * check if we need to free the mbuf, and then return the error 2906 */ 2907 NG_FREE_M(m); 2908 NG_FREE_META(meta); 2909 return (error); 2910 } 2911 2912 /* 2913 * do local shutdown processing.. 2914 * this node will refuse to go away, unless the hardware says to.. 2915 * don't unref the node, or remove our name. just clear our links up. 2916 */ 2917 static int 2918 ngsr_shutdown(node_p node) 2919 { 2920 struct sr_softc * sc = NG_NODE_PRIVATE(node); 2921 2922 sr_down(sc); 2923 NG_NODE_UNREF(node); 2924 /* XXX should drain queues! */ 2925 if (ng_make_node_common(&typestruct, &sc->node) != 0) 2926 return (0); 2927 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit); 2928 if (ng_name_node(sc->node, sc->nodename)) { 2929 printf("node naming failed\n"); 2930 sc->node = NULL; 2931 NG_NODE_UNREF(sc->node); /* drop it again */ 2932 return (0); 2933 } 2934 NG_NODE_SET_PRIVATE(sc->node, sc); 2935 callout_handle_init(&sc->handle); /* should kill timeout */ 2936 sc->running = 0; 2937 return (0); 2938 } 2939 2940 /* already linked */ 2941 static int 2942 ngsr_connect(hook_p hook) 2943 { 2944 /* probably not at splnet, force outward queueing */ 2945 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 2946 /* be really amiable and just say "YUP that's OK by me! " */ 2947 return (0); 2948 } 2949 2950 /* 2951 * notify on hook disconnection (destruction) 2952 * 2953 * Invalidate the private data associated with this dlci. 2954 * For this type, removal of the last link resets tries to destroy the node. 2955 * As the device still exists, the shutdown method will not actually 2956 * destroy the node, but reset the device and leave it 'fresh' :) 2957 * 2958 * The node removal code will remove all references except that owned by the 2959 * driver. 2960 */ 2961 static int 2962 ngsr_disconnect(hook_p hook) 2963 { 2964 struct sr_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2965 int s; 2966 /* 2967 * If it's the data hook, then free resources etc. 2968 */ 2969 if (NG_HOOK_PRIVATE(hook)) { 2970 s = splimp(); 2971 sc->datahooks--; 2972 if (sc->datahooks == 0) 2973 sr_down(sc); 2974 splx(s); 2975 } else { 2976 sc->debug_hook = NULL; 2977 } 2978 return (0); 2979 } 2980 2981 /* 2982 * called during bootup 2983 * or LKM loading to put this type into the list of known modules 2984 */ 2985 static void 2986 ngsr_init(void *ignored) 2987 { 2988 if (ng_newtype(&typestruct)) 2989 printf("ngsr install failed\n"); 2990 ngsr_done_init = 1; 2991 } 2992 #endif /* NETGRAPH */ 2993 2994 /* 2995 ********************************* END ************************************ 2996 */
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