FreeBSD/Linux Kernel Cross Reference
sys/dev/ste/if_ste.c
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 #ifdef HAVE_KERNEL_OPTION_HEADERS
39 #include "opt_device_polling.h"
40 #endif
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/endian.h>
46 #include <sys/kernel.h>
47 #include <sys/lock.h>
48 #include <sys/malloc.h>
49 #include <sys/mbuf.h>
50 #include <sys/module.h>
51 #include <sys/rman.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55
56 #include <net/bpf.h>
57 #include <net/if.h>
58 #include <net/if_var.h>
59 #include <net/if_arp.h>
60 #include <net/ethernet.h>
61 #include <net/if_dl.h>
62 #include <net/if_media.h>
63 #include <net/if_types.h>
64 #include <net/if_vlan_var.h>
65
66 #include <machine/bus.h>
67 #include <machine/resource.h>
68
69 #include <dev/mii/mii.h>
70 #include <dev/mii/mii_bitbang.h>
71 #include <dev/mii/miivar.h>
72
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
75
76 #include <dev/ste/if_stereg.h>
77
78 /* "device miibus" required. See GENERIC if you get errors here. */
79 #include "miibus_if.h"
80
81 MODULE_DEPEND(ste, pci, 1, 1, 1);
82 MODULE_DEPEND(ste, ether, 1, 1, 1);
83 MODULE_DEPEND(ste, miibus, 1, 1, 1);
84
85 /* Define to show Tx error status. */
86 #define STE_SHOW_TXERRORS
87
88 /*
89 * Various supported device vendors/types and their names.
90 */
91 static const struct ste_type ste_devs[] = {
92 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
93 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
94 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
95 { 0, 0, NULL }
96 };
97
98 static int ste_attach(device_t);
99 static int ste_detach(device_t);
100 static int ste_probe(device_t);
101 static int ste_resume(device_t);
102 static int ste_shutdown(device_t);
103 static int ste_suspend(device_t);
104
105 static int ste_dma_alloc(struct ste_softc *);
106 static void ste_dma_free(struct ste_softc *);
107 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
108 static int ste_eeprom_wait(struct ste_softc *);
109 static int ste_encap(struct ste_softc *, struct mbuf **,
110 struct ste_chain *);
111 static int ste_ifmedia_upd(struct ifnet *);
112 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113 static void ste_init(void *);
114 static void ste_init_locked(struct ste_softc *);
115 static int ste_init_rx_list(struct ste_softc *);
116 static void ste_init_tx_list(struct ste_softc *);
117 static void ste_intr(void *);
118 static int ste_ioctl(struct ifnet *, u_long, caddr_t);
119 static uint32_t ste_mii_bitbang_read(device_t);
120 static void ste_mii_bitbang_write(device_t, uint32_t);
121 static int ste_miibus_readreg(device_t, int, int);
122 static void ste_miibus_statchg(device_t);
123 static int ste_miibus_writereg(device_t, int, int, int);
124 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
125 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int);
126 static void ste_reset(struct ste_softc *);
127 static void ste_restart_tx(struct ste_softc *);
128 static int ste_rxeof(struct ste_softc *, int);
129 static void ste_rxfilter(struct ste_softc *);
130 static void ste_setwol(struct ste_softc *);
131 static void ste_start(struct ifnet *);
132 static void ste_start_locked(struct ifnet *);
133 static void ste_stats_clear(struct ste_softc *);
134 static void ste_stats_update(struct ste_softc *);
135 static void ste_stop(struct ste_softc *);
136 static void ste_sysctl_node(struct ste_softc *);
137 static void ste_tick(void *);
138 static void ste_txeoc(struct ste_softc *);
139 static void ste_txeof(struct ste_softc *);
140 static void ste_wait(struct ste_softc *);
141 static void ste_watchdog(struct ste_softc *);
142
143 /*
144 * MII bit-bang glue
145 */
146 static const struct mii_bitbang_ops ste_mii_bitbang_ops = {
147 ste_mii_bitbang_read,
148 ste_mii_bitbang_write,
149 {
150 STE_PHYCTL_MDATA, /* MII_BIT_MDO */
151 STE_PHYCTL_MDATA, /* MII_BIT_MDI */
152 STE_PHYCTL_MCLK, /* MII_BIT_MDC */
153 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */
154 0, /* MII_BIT_DIR_PHY_HOST */
155 }
156 };
157
158 static device_method_t ste_methods[] = {
159 /* Device interface */
160 DEVMETHOD(device_probe, ste_probe),
161 DEVMETHOD(device_attach, ste_attach),
162 DEVMETHOD(device_detach, ste_detach),
163 DEVMETHOD(device_shutdown, ste_shutdown),
164 DEVMETHOD(device_suspend, ste_suspend),
165 DEVMETHOD(device_resume, ste_resume),
166
167 /* MII interface */
168 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
169 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
170 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
171
172 DEVMETHOD_END
173 };
174
175 static driver_t ste_driver = {
176 "ste",
177 ste_methods,
178 sizeof(struct ste_softc)
179 };
180
181 DRIVER_MODULE(ste, pci, ste_driver, 0, 0);
182 DRIVER_MODULE(miibus, ste, miibus_driver, 0, 0);
183
184 #define STE_SETBIT4(sc, reg, x) \
185 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
186
187 #define STE_CLRBIT4(sc, reg, x) \
188 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
189
190 #define STE_SETBIT2(sc, reg, x) \
191 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
192
193 #define STE_CLRBIT2(sc, reg, x) \
194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
195
196 #define STE_SETBIT1(sc, reg, x) \
197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
198
199 #define STE_CLRBIT1(sc, reg, x) \
200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
201
202 /*
203 * Read the MII serial port for the MII bit-bang module.
204 */
205 static uint32_t
206 ste_mii_bitbang_read(device_t dev)
207 {
208 struct ste_softc *sc;
209 uint32_t val;
210
211 sc = device_get_softc(dev);
212
213 val = CSR_READ_1(sc, STE_PHYCTL);
214 CSR_BARRIER(sc, STE_PHYCTL, 1,
215 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
216
217 return (val);
218 }
219
220 /*
221 * Write the MII serial port for the MII bit-bang module.
222 */
223 static void
224 ste_mii_bitbang_write(device_t dev, uint32_t val)
225 {
226 struct ste_softc *sc;
227
228 sc = device_get_softc(dev);
229
230 CSR_WRITE_1(sc, STE_PHYCTL, val);
231 CSR_BARRIER(sc, STE_PHYCTL, 1,
232 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
233 }
234
235 static int
236 ste_miibus_readreg(device_t dev, int phy, int reg)
237 {
238
239 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg));
240 }
241
242 static int
243 ste_miibus_writereg(device_t dev, int phy, int reg, int data)
244 {
245
246 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data);
247
248 return (0);
249 }
250
251 static void
252 ste_miibus_statchg(device_t dev)
253 {
254 struct ste_softc *sc;
255 struct mii_data *mii;
256 struct ifnet *ifp;
257 uint16_t cfg;
258
259 sc = device_get_softc(dev);
260
261 mii = device_get_softc(sc->ste_miibus);
262 ifp = sc->ste_ifp;
263 if (mii == NULL || ifp == NULL ||
264 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
265 return;
266
267 sc->ste_flags &= ~STE_FLAG_LINK;
268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
269 (IFM_ACTIVE | IFM_AVALID)) {
270 switch (IFM_SUBTYPE(mii->mii_media_active)) {
271 case IFM_10_T:
272 case IFM_100_TX:
273 case IFM_100_FX:
274 case IFM_100_T4:
275 sc->ste_flags |= STE_FLAG_LINK;
276 default:
277 break;
278 }
279 }
280
281 /* Program MACs with resolved speed/duplex/flow-control. */
282 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
283 cfg = CSR_READ_2(sc, STE_MACCTL0);
284 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
285 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
286 /*
287 * ST201 data sheet says driver should enable receiving
288 * MAC control frames bit of receive mode register to
289 * receive flow-control frames but the register has no
290 * such bits. In addition the controller has no ability
291 * to send pause frames so it should be handled in
292 * driver. Implementing pause timer handling in driver
293 * layer is not trivial, so don't enable flow-control
294 * here.
295 */
296 cfg |= STE_MACCTL0_FULLDUPLEX;
297 }
298 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
299 }
300 }
301
302 static int
303 ste_ifmedia_upd(struct ifnet *ifp)
304 {
305 struct ste_softc *sc;
306 struct mii_data *mii;
307 struct mii_softc *miisc;
308 int error;
309
310 sc = ifp->if_softc;
311 STE_LOCK(sc);
312 mii = device_get_softc(sc->ste_miibus);
313 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
314 PHY_RESET(miisc);
315 error = mii_mediachg(mii);
316 STE_UNLOCK(sc);
317
318 return (error);
319 }
320
321 static void
322 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
323 {
324 struct ste_softc *sc;
325 struct mii_data *mii;
326
327 sc = ifp->if_softc;
328 mii = device_get_softc(sc->ste_miibus);
329
330 STE_LOCK(sc);
331 if ((ifp->if_flags & IFF_UP) == 0) {
332 STE_UNLOCK(sc);
333 return;
334 }
335 mii_pollstat(mii);
336 ifmr->ifm_active = mii->mii_media_active;
337 ifmr->ifm_status = mii->mii_media_status;
338 STE_UNLOCK(sc);
339 }
340
341 static void
342 ste_wait(struct ste_softc *sc)
343 {
344 int i;
345
346 for (i = 0; i < STE_TIMEOUT; i++) {
347 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
348 break;
349 DELAY(1);
350 }
351
352 if (i == STE_TIMEOUT)
353 device_printf(sc->ste_dev, "command never completed!\n");
354 }
355
356 /*
357 * The EEPROM is slow: give it time to come ready after issuing
358 * it a command.
359 */
360 static int
361 ste_eeprom_wait(struct ste_softc *sc)
362 {
363 int i;
364
365 DELAY(1000);
366
367 for (i = 0; i < 100; i++) {
368 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
369 DELAY(1000);
370 else
371 break;
372 }
373
374 if (i == 100) {
375 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
376 return (1);
377 }
378
379 return (0);
380 }
381
382 /*
383 * Read a sequence of words from the EEPROM. Note that ethernet address
384 * data is stored in the EEPROM in network byte order.
385 */
386 static int
387 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt)
388 {
389 int err = 0, i;
390
391 if (ste_eeprom_wait(sc))
392 return (1);
393
394 for (i = 0; i < cnt; i++) {
395 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
396 err = ste_eeprom_wait(sc);
397 if (err)
398 break;
399 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
400 dest++;
401 }
402
403 return (err ? 1 : 0);
404 }
405
406 static u_int
407 ste_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
408 {
409 uint32_t *hashes = arg;
410 int h;
411
412 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0x3F;
413 if (h < 32)
414 hashes[0] |= (1 << h);
415 else
416 hashes[1] |= (1 << (h - 32));
417
418 return (1);
419 }
420
421 static void
422 ste_rxfilter(struct ste_softc *sc)
423 {
424 struct ifnet *ifp;
425 uint32_t hashes[2] = { 0, 0 };
426 uint8_t rxcfg;
427
428 STE_LOCK_ASSERT(sc);
429
430 ifp = sc->ste_ifp;
431 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
432 rxcfg |= STE_RXMODE_UNICAST;
433 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
434 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
435 if (ifp->if_flags & IFF_BROADCAST)
436 rxcfg |= STE_RXMODE_BROADCAST;
437 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
438 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
439 rxcfg |= STE_RXMODE_ALLMULTI;
440 if ((ifp->if_flags & IFF_PROMISC) != 0)
441 rxcfg |= STE_RXMODE_PROMISC;
442 goto chipit;
443 }
444
445 rxcfg |= STE_RXMODE_MULTIHASH;
446 /* Now program new ones. */
447 if_foreach_llmaddr(ifp, ste_hash_maddr, hashes);
448
449 chipit:
450 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
451 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
452 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
453 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
454 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
455 CSR_READ_1(sc, STE_RX_MODE);
456 }
457
458 #ifdef DEVICE_POLLING
459 static poll_handler_t ste_poll, ste_poll_locked;
460
461 static int
462 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
463 {
464 struct ste_softc *sc = ifp->if_softc;
465 int rx_npkts = 0;
466
467 STE_LOCK(sc);
468 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
469 rx_npkts = ste_poll_locked(ifp, cmd, count);
470 STE_UNLOCK(sc);
471 return (rx_npkts);
472 }
473
474 static int
475 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
476 {
477 struct ste_softc *sc = ifp->if_softc;
478 int rx_npkts;
479
480 STE_LOCK_ASSERT(sc);
481
482 rx_npkts = ste_rxeof(sc, count);
483 ste_txeof(sc);
484 ste_txeoc(sc);
485 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
486 ste_start_locked(ifp);
487
488 if (cmd == POLL_AND_CHECK_STATUS) {
489 uint16_t status;
490
491 status = CSR_READ_2(sc, STE_ISR_ACK);
492
493 if (status & STE_ISR_STATS_OFLOW)
494 ste_stats_update(sc);
495
496 if (status & STE_ISR_HOSTERR) {
497 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
498 ste_init_locked(sc);
499 }
500 }
501 return (rx_npkts);
502 }
503 #endif /* DEVICE_POLLING */
504
505 static void
506 ste_intr(void *xsc)
507 {
508 struct ste_softc *sc;
509 struct ifnet *ifp;
510 uint16_t intrs, status;
511
512 sc = xsc;
513 STE_LOCK(sc);
514 ifp = sc->ste_ifp;
515
516 #ifdef DEVICE_POLLING
517 if (ifp->if_capenable & IFCAP_POLLING) {
518 STE_UNLOCK(sc);
519 return;
520 }
521 #endif
522 /* Reading STE_ISR_ACK clears STE_IMR register. */
523 status = CSR_READ_2(sc, STE_ISR_ACK);
524 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
525 STE_UNLOCK(sc);
526 return;
527 }
528
529 intrs = STE_INTRS;
530 if (status == 0xFFFF || (status & intrs) == 0)
531 goto done;
532
533 if (sc->ste_int_rx_act > 0) {
534 status &= ~STE_ISR_RX_DMADONE;
535 intrs &= ~STE_IMR_RX_DMADONE;
536 }
537
538 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) {
539 ste_rxeof(sc, -1);
540 /*
541 * The controller has no ability to Rx interrupt
542 * moderation feature. Receiving 64 bytes frames
543 * from wire generates too many interrupts which in
544 * turn make system useless to process other useful
545 * things. Fortunately ST201 supports single shot
546 * timer so use the timer to implement Rx interrupt
547 * moderation in driver. This adds more register
548 * access but it greatly reduces number of Rx
549 * interrupts under high network load.
550 */
551 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
552 (sc->ste_int_rx_mod != 0)) {
553 if ((status & STE_ISR_RX_DMADONE) != 0) {
554 CSR_WRITE_2(sc, STE_COUNTDOWN,
555 STE_TIMER_USECS(sc->ste_int_rx_mod));
556 intrs &= ~STE_IMR_RX_DMADONE;
557 sc->ste_int_rx_act = 1;
558 } else {
559 intrs |= STE_IMR_RX_DMADONE;
560 sc->ste_int_rx_act = 0;
561 }
562 }
563 }
564 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
565 if ((status & STE_ISR_TX_DMADONE) != 0)
566 ste_txeof(sc);
567 if ((status & STE_ISR_TX_DONE) != 0)
568 ste_txeoc(sc);
569 if ((status & STE_ISR_STATS_OFLOW) != 0)
570 ste_stats_update(sc);
571 if ((status & STE_ISR_HOSTERR) != 0) {
572 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
573 ste_init_locked(sc);
574 STE_UNLOCK(sc);
575 return;
576 }
577 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
578 ste_start_locked(ifp);
579 done:
580 /* Re-enable interrupts */
581 CSR_WRITE_2(sc, STE_IMR, intrs);
582 }
583 STE_UNLOCK(sc);
584 }
585
586 /*
587 * A frame has been uploaded: pass the resulting mbuf chain up to
588 * the higher level protocols.
589 */
590 static int
591 ste_rxeof(struct ste_softc *sc, int count)
592 {
593 struct mbuf *m;
594 struct ifnet *ifp;
595 struct ste_chain_onefrag *cur_rx;
596 uint32_t rxstat;
597 int total_len, rx_npkts;
598
599 ifp = sc->ste_ifp;
600
601 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
602 sc->ste_cdata.ste_rx_list_map,
603 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
604
605 cur_rx = sc->ste_cdata.ste_rx_head;
606 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
607 cur_rx = cur_rx->ste_next) {
608 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
609 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
610 break;
611 #ifdef DEVICE_POLLING
612 if (ifp->if_capenable & IFCAP_POLLING) {
613 if (count == 0)
614 break;
615 count--;
616 }
617 #endif
618 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
619 break;
620 /*
621 * If an error occurs, update stats, clear the
622 * status word and leave the mbuf cluster in place:
623 * it should simply get re-used next time this descriptor
624 * comes up in the ring.
625 */
626 if (rxstat & STE_RXSTAT_FRAME_ERR) {
627 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
628 cur_rx->ste_ptr->ste_status = 0;
629 continue;
630 }
631
632 /* No errors; receive the packet. */
633 m = cur_rx->ste_mbuf;
634 total_len = STE_RX_BYTES(rxstat);
635
636 /*
637 * Try to conjure up a new mbuf cluster. If that
638 * fails, it means we have an out of memory condition and
639 * should leave the buffer in place and continue. This will
640 * result in a lost packet, but there's little else we
641 * can do in this situation.
642 */
643 if (ste_newbuf(sc, cur_rx) != 0) {
644 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
645 cur_rx->ste_ptr->ste_status = 0;
646 continue;
647 }
648
649 m->m_pkthdr.rcvif = ifp;
650 m->m_pkthdr.len = m->m_len = total_len;
651
652 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
653 STE_UNLOCK(sc);
654 (*ifp->if_input)(ifp, m);
655 STE_LOCK(sc);
656 }
657
658 if (rx_npkts > 0) {
659 sc->ste_cdata.ste_rx_head = cur_rx;
660 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
661 sc->ste_cdata.ste_rx_list_map,
662 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
663 }
664
665 return (rx_npkts);
666 }
667
668 static void
669 ste_txeoc(struct ste_softc *sc)
670 {
671 uint16_t txstat;
672 struct ifnet *ifp;
673
674 STE_LOCK_ASSERT(sc);
675
676 ifp = sc->ste_ifp;
677
678 /*
679 * STE_TX_STATUS register implements a queue of up to 31
680 * transmit status byte. Writing an arbitrary value to the
681 * register will advance the queue to the next transmit
682 * status byte. This means if driver does not read
683 * STE_TX_STATUS register after completing sending more
684 * than 31 frames the controller would be stalled so driver
685 * should re-wake the Tx MAC. This is the most severe
686 * limitation of ST201 based controller.
687 */
688 for (;;) {
689 txstat = CSR_READ_2(sc, STE_TX_STATUS);
690 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
691 break;
692 if ((txstat & (STE_TXSTATUS_UNDERRUN |
693 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
694 STE_TXSTATUS_STATSOFLOW)) != 0) {
695 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
696 #ifdef STE_SHOW_TXERRORS
697 device_printf(sc->ste_dev, "TX error : 0x%b\n",
698 txstat & 0xFF, STE_ERR_BITS);
699 #endif
700 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
701 sc->ste_tx_thresh < STE_PACKET_SIZE) {
702 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
703 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
704 sc->ste_tx_thresh = STE_PACKET_SIZE;
705 device_printf(sc->ste_dev,
706 "TX underrun, increasing TX"
707 " start threshold to %d bytes\n",
708 sc->ste_tx_thresh);
709 /* Make sure to disable active DMA cycles. */
710 STE_SETBIT4(sc, STE_DMACTL,
711 STE_DMACTL_TXDMA_STALL);
712 ste_wait(sc);
713 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
714 ste_init_locked(sc);
715 break;
716 }
717 /* Restart Tx. */
718 ste_restart_tx(sc);
719 }
720 /*
721 * Advance to next status and ACK TxComplete
722 * interrupt. ST201 data sheet was wrong here, to
723 * get next Tx status, we have to write both
724 * STE_TX_STATUS and STE_TX_FRAMEID register.
725 * Otherwise controller returns the same status
726 * as well as not acknowledge Tx completion
727 * interrupt.
728 */
729 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
730 }
731 }
732
733 static void
734 ste_tick(void *arg)
735 {
736 struct ste_softc *sc;
737 struct mii_data *mii;
738
739 sc = (struct ste_softc *)arg;
740
741 STE_LOCK_ASSERT(sc);
742
743 mii = device_get_softc(sc->ste_miibus);
744 mii_tick(mii);
745 /*
746 * ukphy(4) does not seem to generate CB that reports
747 * resolved link state so if we know we lost a link,
748 * explicitly check the link state.
749 */
750 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
751 ste_miibus_statchg(sc->ste_dev);
752 /*
753 * Because we are not generating Tx completion
754 * interrupt for every frame, reclaim transmitted
755 * buffers here.
756 */
757 ste_txeof(sc);
758 ste_txeoc(sc);
759 ste_stats_update(sc);
760 ste_watchdog(sc);
761 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
762 }
763
764 static void
765 ste_txeof(struct ste_softc *sc)
766 {
767 struct ifnet *ifp;
768 struct ste_chain *cur_tx;
769 uint32_t txstat;
770 int idx;
771
772 STE_LOCK_ASSERT(sc);
773
774 ifp = sc->ste_ifp;
775 idx = sc->ste_cdata.ste_tx_cons;
776 if (idx == sc->ste_cdata.ste_tx_prod)
777 return;
778
779 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
780 sc->ste_cdata.ste_tx_list_map,
781 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
782
783 while (idx != sc->ste_cdata.ste_tx_prod) {
784 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
785 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
786 if ((txstat & STE_TXCTL_DMADONE) == 0)
787 break;
788 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
789 BUS_DMASYNC_POSTWRITE);
790 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
791 KASSERT(cur_tx->ste_mbuf != NULL,
792 ("%s: freeing NULL mbuf!\n", __func__));
793 m_freem(cur_tx->ste_mbuf);
794 cur_tx->ste_mbuf = NULL;
795 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
796 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
797 sc->ste_cdata.ste_tx_cnt--;
798 STE_INC(idx, STE_TX_LIST_CNT);
799 }
800
801 sc->ste_cdata.ste_tx_cons = idx;
802 if (sc->ste_cdata.ste_tx_cnt == 0)
803 sc->ste_timer = 0;
804 }
805
806 static void
807 ste_stats_clear(struct ste_softc *sc)
808 {
809
810 STE_LOCK_ASSERT(sc);
811
812 /* Rx stats. */
813 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
814 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
815 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
816 CSR_READ_1(sc, STE_STAT_RX_BCAST);
817 CSR_READ_1(sc, STE_STAT_RX_MCAST);
818 CSR_READ_1(sc, STE_STAT_RX_LOST);
819 /* Tx stats. */
820 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
821 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
822 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
823 CSR_READ_1(sc, STE_STAT_TX_BCAST);
824 CSR_READ_1(sc, STE_STAT_TX_MCAST);
825 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
826 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
827 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
828 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
829 CSR_READ_1(sc, STE_STAT_TX_DEFER);
830 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
831 CSR_READ_1(sc, STE_STAT_TX_ABORT);
832 }
833
834 static void
835 ste_stats_update(struct ste_softc *sc)
836 {
837 struct ifnet *ifp;
838 struct ste_hw_stats *stats;
839 uint32_t val;
840
841 STE_LOCK_ASSERT(sc);
842
843 ifp = sc->ste_ifp;
844 stats = &sc->ste_stats;
845 /* Rx stats. */
846 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
847 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
848 val &= 0x000FFFFF;
849 stats->rx_bytes += val;
850 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
851 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
852 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
853 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
854 /* Tx stats. */
855 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
856 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
857 val &= 0x000FFFFF;
858 stats->tx_bytes += val;
859 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
860 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
861 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
862 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
863 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
864 stats->tx_single_colls += val;
865 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val);
866 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
867 stats->tx_multi_colls += val;
868 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val);
869 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
870 stats->tx_late_colls += val;
871 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val);
872 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
873 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
874 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
875 }
876
877 /*
878 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
879 * IDs against our list and return a device name if we find a match.
880 */
881 static int
882 ste_probe(device_t dev)
883 {
884 const struct ste_type *t;
885
886 t = ste_devs;
887
888 while (t->ste_name != NULL) {
889 if ((pci_get_vendor(dev) == t->ste_vid) &&
890 (pci_get_device(dev) == t->ste_did)) {
891 device_set_desc(dev, t->ste_name);
892 return (BUS_PROBE_DEFAULT);
893 }
894 t++;
895 }
896
897 return (ENXIO);
898 }
899
900 /*
901 * Attach the interface. Allocate softc structures, do ifmedia
902 * setup and ethernet/BPF attach.
903 */
904 static int
905 ste_attach(device_t dev)
906 {
907 struct ste_softc *sc;
908 struct ifnet *ifp;
909 uint16_t eaddr[ETHER_ADDR_LEN / 2];
910 int error = 0, phy, pmc, prefer_iomap, rid;
911
912 sc = device_get_softc(dev);
913 sc->ste_dev = dev;
914
915 /*
916 * Only use one PHY since this chip reports multiple
917 * Note on the DFE-550 the PHY is at 1 on the DFE-580
918 * it is at 0 & 1. It is rev 0x12.
919 */
920 if (pci_get_vendor(dev) == DL_VENDORID &&
921 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
922 pci_get_revid(dev) == 0x12 )
923 sc->ste_flags |= STE_FLAG_ONE_PHY;
924
925 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
926 MTX_DEF);
927 /*
928 * Map control/status registers.
929 */
930 pci_enable_busmaster(dev);
931
932 /*
933 * Prefer memory space register mapping over IO space but use
934 * IO space for a device that is known to have issues on memory
935 * mapping.
936 */
937 prefer_iomap = 0;
938 if (pci_get_device(dev) == ST_DEVICEID_ST201_1)
939 prefer_iomap = 1;
940 else
941 resource_int_value(device_get_name(sc->ste_dev),
942 device_get_unit(sc->ste_dev), "prefer_iomap",
943 &prefer_iomap);
944 if (prefer_iomap == 0) {
945 sc->ste_res_id = PCIR_BAR(1);
946 sc->ste_res_type = SYS_RES_MEMORY;
947 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
948 &sc->ste_res_id, RF_ACTIVE);
949 }
950 if (prefer_iomap || sc->ste_res == NULL) {
951 sc->ste_res_id = PCIR_BAR(0);
952 sc->ste_res_type = SYS_RES_IOPORT;
953 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
954 &sc->ste_res_id, RF_ACTIVE);
955 }
956 if (sc->ste_res == NULL) {
957 device_printf(dev, "couldn't map ports/memory\n");
958 error = ENXIO;
959 goto fail;
960 }
961
962 /* Allocate interrupt */
963 rid = 0;
964 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
965 RF_SHAREABLE | RF_ACTIVE);
966
967 if (sc->ste_irq == NULL) {
968 device_printf(dev, "couldn't map interrupt\n");
969 error = ENXIO;
970 goto fail;
971 }
972
973 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
974
975 /* Reset the adapter. */
976 ste_reset(sc);
977
978 /*
979 * Get station address from the EEPROM.
980 */
981 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) {
982 device_printf(dev, "failed to read station address\n");
983 error = ENXIO;
984 goto fail;
985 }
986 ste_sysctl_node(sc);
987
988 if ((error = ste_dma_alloc(sc)) != 0)
989 goto fail;
990
991 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
992 if (ifp == NULL) {
993 device_printf(dev, "can not if_alloc()\n");
994 error = ENOSPC;
995 goto fail;
996 }
997
998 /* Do MII setup. */
999 phy = MII_PHY_ANY;
1000 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0)
1001 phy = 0;
1002 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd,
1003 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1004 if (error != 0) {
1005 device_printf(dev, "attaching PHYs failed\n");
1006 goto fail;
1007 }
1008
1009 ifp->if_softc = sc;
1010 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1011 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1012 ifp->if_ioctl = ste_ioctl;
1013 ifp->if_start = ste_start;
1014 ifp->if_init = ste_init;
1015 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1016 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1017 IFQ_SET_READY(&ifp->if_snd);
1018
1019 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1020
1021 /*
1022 * Call MI attach routine.
1023 */
1024 ether_ifattach(ifp, (uint8_t *)eaddr);
1025
1026 /*
1027 * Tell the upper layer(s) we support long frames.
1028 */
1029 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1030 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1031 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
1032 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1033 ifp->if_capenable = ifp->if_capabilities;
1034 #ifdef DEVICE_POLLING
1035 ifp->if_capabilities |= IFCAP_POLLING;
1036 #endif
1037
1038 /* Hook interrupt last to avoid having to lock softc */
1039 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1040 NULL, ste_intr, sc, &sc->ste_intrhand);
1041
1042 if (error) {
1043 device_printf(dev, "couldn't set up irq\n");
1044 ether_ifdetach(ifp);
1045 goto fail;
1046 }
1047
1048 fail:
1049 if (error)
1050 ste_detach(dev);
1051
1052 return (error);
1053 }
1054
1055 /*
1056 * Shutdown hardware and free up resources. This can be called any
1057 * time after the mutex has been initialized. It is called in both
1058 * the error case in attach and the normal detach case so it needs
1059 * to be careful about only freeing resources that have actually been
1060 * allocated.
1061 */
1062 static int
1063 ste_detach(device_t dev)
1064 {
1065 struct ste_softc *sc;
1066 struct ifnet *ifp;
1067
1068 sc = device_get_softc(dev);
1069 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1070 ifp = sc->ste_ifp;
1071
1072 #ifdef DEVICE_POLLING
1073 if (ifp->if_capenable & IFCAP_POLLING)
1074 ether_poll_deregister(ifp);
1075 #endif
1076
1077 /* These should only be active if attach succeeded */
1078 if (device_is_attached(dev)) {
1079 ether_ifdetach(ifp);
1080 STE_LOCK(sc);
1081 ste_stop(sc);
1082 STE_UNLOCK(sc);
1083 callout_drain(&sc->ste_callout);
1084 }
1085 if (sc->ste_miibus)
1086 device_delete_child(dev, sc->ste_miibus);
1087 bus_generic_detach(dev);
1088
1089 if (sc->ste_intrhand)
1090 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1091 if (sc->ste_irq)
1092 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1093 if (sc->ste_res)
1094 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1095 sc->ste_res);
1096
1097 if (ifp)
1098 if_free(ifp);
1099
1100 ste_dma_free(sc);
1101 mtx_destroy(&sc->ste_mtx);
1102
1103 return (0);
1104 }
1105
1106 struct ste_dmamap_arg {
1107 bus_addr_t ste_busaddr;
1108 };
1109
1110 static void
1111 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1112 {
1113 struct ste_dmamap_arg *ctx;
1114
1115 if (error != 0)
1116 return;
1117
1118 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1119
1120 ctx = (struct ste_dmamap_arg *)arg;
1121 ctx->ste_busaddr = segs[0].ds_addr;
1122 }
1123
1124 static int
1125 ste_dma_alloc(struct ste_softc *sc)
1126 {
1127 struct ste_chain *txc;
1128 struct ste_chain_onefrag *rxc;
1129 struct ste_dmamap_arg ctx;
1130 int error, i;
1131
1132 /* Create parent DMA tag. */
1133 error = bus_dma_tag_create(
1134 bus_get_dma_tag(sc->ste_dev), /* parent */
1135 1, 0, /* alignment, boundary */
1136 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1137 BUS_SPACE_MAXADDR, /* highaddr */
1138 NULL, NULL, /* filter, filterarg */
1139 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1140 0, /* nsegments */
1141 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1142 0, /* flags */
1143 NULL, NULL, /* lockfunc, lockarg */
1144 &sc->ste_cdata.ste_parent_tag);
1145 if (error != 0) {
1146 device_printf(sc->ste_dev,
1147 "could not create parent DMA tag.\n");
1148 goto fail;
1149 }
1150
1151 /* Create DMA tag for Tx descriptor list. */
1152 error = bus_dma_tag_create(
1153 sc->ste_cdata.ste_parent_tag, /* parent */
1154 STE_DESC_ALIGN, 0, /* alignment, boundary */
1155 BUS_SPACE_MAXADDR, /* lowaddr */
1156 BUS_SPACE_MAXADDR, /* highaddr */
1157 NULL, NULL, /* filter, filterarg */
1158 STE_TX_LIST_SZ, /* maxsize */
1159 1, /* nsegments */
1160 STE_TX_LIST_SZ, /* maxsegsize */
1161 0, /* flags */
1162 NULL, NULL, /* lockfunc, lockarg */
1163 &sc->ste_cdata.ste_tx_list_tag);
1164 if (error != 0) {
1165 device_printf(sc->ste_dev,
1166 "could not create Tx list DMA tag.\n");
1167 goto fail;
1168 }
1169
1170 /* Create DMA tag for Rx descriptor list. */
1171 error = bus_dma_tag_create(
1172 sc->ste_cdata.ste_parent_tag, /* parent */
1173 STE_DESC_ALIGN, 0, /* alignment, boundary */
1174 BUS_SPACE_MAXADDR, /* lowaddr */
1175 BUS_SPACE_MAXADDR, /* highaddr */
1176 NULL, NULL, /* filter, filterarg */
1177 STE_RX_LIST_SZ, /* maxsize */
1178 1, /* nsegments */
1179 STE_RX_LIST_SZ, /* maxsegsize */
1180 0, /* flags */
1181 NULL, NULL, /* lockfunc, lockarg */
1182 &sc->ste_cdata.ste_rx_list_tag);
1183 if (error != 0) {
1184 device_printf(sc->ste_dev,
1185 "could not create Rx list DMA tag.\n");
1186 goto fail;
1187 }
1188
1189 /* Create DMA tag for Tx buffers. */
1190 error = bus_dma_tag_create(
1191 sc->ste_cdata.ste_parent_tag, /* parent */
1192 1, 0, /* alignment, boundary */
1193 BUS_SPACE_MAXADDR, /* lowaddr */
1194 BUS_SPACE_MAXADDR, /* highaddr */
1195 NULL, NULL, /* filter, filterarg */
1196 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1197 STE_MAXFRAGS, /* nsegments */
1198 MCLBYTES, /* maxsegsize */
1199 0, /* flags */
1200 NULL, NULL, /* lockfunc, lockarg */
1201 &sc->ste_cdata.ste_tx_tag);
1202 if (error != 0) {
1203 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1204 goto fail;
1205 }
1206
1207 /* Create DMA tag for Rx buffers. */
1208 error = bus_dma_tag_create(
1209 sc->ste_cdata.ste_parent_tag, /* parent */
1210 1, 0, /* alignment, boundary */
1211 BUS_SPACE_MAXADDR, /* lowaddr */
1212 BUS_SPACE_MAXADDR, /* highaddr */
1213 NULL, NULL, /* filter, filterarg */
1214 MCLBYTES, /* maxsize */
1215 1, /* nsegments */
1216 MCLBYTES, /* maxsegsize */
1217 0, /* flags */
1218 NULL, NULL, /* lockfunc, lockarg */
1219 &sc->ste_cdata.ste_rx_tag);
1220 if (error != 0) {
1221 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1222 goto fail;
1223 }
1224
1225 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1226 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1227 (void **)&sc->ste_ldata.ste_tx_list,
1228 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1229 &sc->ste_cdata.ste_tx_list_map);
1230 if (error != 0) {
1231 device_printf(sc->ste_dev,
1232 "could not allocate DMA'able memory for Tx list.\n");
1233 goto fail;
1234 }
1235 ctx.ste_busaddr = 0;
1236 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1237 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1238 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1239 if (error != 0 || ctx.ste_busaddr == 0) {
1240 device_printf(sc->ste_dev,
1241 "could not load DMA'able memory for Tx list.\n");
1242 goto fail;
1243 }
1244 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1245
1246 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1247 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1248 (void **)&sc->ste_ldata.ste_rx_list,
1249 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1250 &sc->ste_cdata.ste_rx_list_map);
1251 if (error != 0) {
1252 device_printf(sc->ste_dev,
1253 "could not allocate DMA'able memory for Rx list.\n");
1254 goto fail;
1255 }
1256 ctx.ste_busaddr = 0;
1257 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1258 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1259 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1260 if (error != 0 || ctx.ste_busaddr == 0) {
1261 device_printf(sc->ste_dev,
1262 "could not load DMA'able memory for Rx list.\n");
1263 goto fail;
1264 }
1265 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1266
1267 /* Create DMA maps for Tx buffers. */
1268 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1269 txc = &sc->ste_cdata.ste_tx_chain[i];
1270 txc->ste_ptr = NULL;
1271 txc->ste_mbuf = NULL;
1272 txc->ste_next = NULL;
1273 txc->ste_phys = 0;
1274 txc->ste_map = NULL;
1275 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1276 &txc->ste_map);
1277 if (error != 0) {
1278 device_printf(sc->ste_dev,
1279 "could not create Tx dmamap.\n");
1280 goto fail;
1281 }
1282 }
1283 /* Create DMA maps for Rx buffers. */
1284 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1285 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1286 device_printf(sc->ste_dev,
1287 "could not create spare Rx dmamap.\n");
1288 goto fail;
1289 }
1290 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1291 rxc = &sc->ste_cdata.ste_rx_chain[i];
1292 rxc->ste_ptr = NULL;
1293 rxc->ste_mbuf = NULL;
1294 rxc->ste_next = NULL;
1295 rxc->ste_map = NULL;
1296 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1297 &rxc->ste_map);
1298 if (error != 0) {
1299 device_printf(sc->ste_dev,
1300 "could not create Rx dmamap.\n");
1301 goto fail;
1302 }
1303 }
1304
1305 fail:
1306 return (error);
1307 }
1308
1309 static void
1310 ste_dma_free(struct ste_softc *sc)
1311 {
1312 struct ste_chain *txc;
1313 struct ste_chain_onefrag *rxc;
1314 int i;
1315
1316 /* Tx buffers. */
1317 if (sc->ste_cdata.ste_tx_tag != NULL) {
1318 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1319 txc = &sc->ste_cdata.ste_tx_chain[i];
1320 if (txc->ste_map != NULL) {
1321 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1322 txc->ste_map);
1323 txc->ste_map = NULL;
1324 }
1325 }
1326 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1327 sc->ste_cdata.ste_tx_tag = NULL;
1328 }
1329 /* Rx buffers. */
1330 if (sc->ste_cdata.ste_rx_tag != NULL) {
1331 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1332 rxc = &sc->ste_cdata.ste_rx_chain[i];
1333 if (rxc->ste_map != NULL) {
1334 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1335 rxc->ste_map);
1336 rxc->ste_map = NULL;
1337 }
1338 }
1339 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1340 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1341 sc->ste_cdata.ste_rx_sparemap);
1342 sc->ste_cdata.ste_rx_sparemap = NULL;
1343 }
1344 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1345 sc->ste_cdata.ste_rx_tag = NULL;
1346 }
1347 /* Tx descriptor list. */
1348 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1349 if (sc->ste_ldata.ste_tx_list_paddr != 0)
1350 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1351 sc->ste_cdata.ste_tx_list_map);
1352 if (sc->ste_ldata.ste_tx_list != NULL)
1353 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1354 sc->ste_ldata.ste_tx_list,
1355 sc->ste_cdata.ste_tx_list_map);
1356 sc->ste_ldata.ste_tx_list = NULL;
1357 sc->ste_ldata.ste_tx_list_paddr = 0;
1358 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1359 sc->ste_cdata.ste_tx_list_tag = NULL;
1360 }
1361 /* Rx descriptor list. */
1362 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1363 if (sc->ste_ldata.ste_rx_list_paddr != 0)
1364 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1365 sc->ste_cdata.ste_rx_list_map);
1366 if (sc->ste_ldata.ste_rx_list != NULL)
1367 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1368 sc->ste_ldata.ste_rx_list,
1369 sc->ste_cdata.ste_rx_list_map);
1370 sc->ste_ldata.ste_rx_list = NULL;
1371 sc->ste_ldata.ste_rx_list_paddr = 0;
1372 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1373 sc->ste_cdata.ste_rx_list_tag = NULL;
1374 }
1375 if (sc->ste_cdata.ste_parent_tag != NULL) {
1376 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1377 sc->ste_cdata.ste_parent_tag = NULL;
1378 }
1379 }
1380
1381 static int
1382 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1383 {
1384 struct mbuf *m;
1385 bus_dma_segment_t segs[1];
1386 bus_dmamap_t map;
1387 int error, nsegs;
1388
1389 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1390 if (m == NULL)
1391 return (ENOBUFS);
1392 m->m_len = m->m_pkthdr.len = MCLBYTES;
1393 m_adj(m, ETHER_ALIGN);
1394
1395 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1396 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1397 m_freem(m);
1398 return (error);
1399 }
1400 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1401
1402 if (rxc->ste_mbuf != NULL) {
1403 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1404 BUS_DMASYNC_POSTREAD);
1405 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1406 }
1407 map = rxc->ste_map;
1408 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1409 sc->ste_cdata.ste_rx_sparemap = map;
1410 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1411 BUS_DMASYNC_PREREAD);
1412 rxc->ste_mbuf = m;
1413 rxc->ste_ptr->ste_status = 0;
1414 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1415 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1416 STE_FRAG_LAST);
1417 return (0);
1418 }
1419
1420 static int
1421 ste_init_rx_list(struct ste_softc *sc)
1422 {
1423 struct ste_chain_data *cd;
1424 struct ste_list_data *ld;
1425 int error, i;
1426
1427 sc->ste_int_rx_act = 0;
1428 cd = &sc->ste_cdata;
1429 ld = &sc->ste_ldata;
1430 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1431 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1432 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1433 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1434 if (error != 0)
1435 return (error);
1436 if (i == (STE_RX_LIST_CNT - 1)) {
1437 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1438 ld->ste_rx_list[i].ste_next =
1439 htole32(ld->ste_rx_list_paddr +
1440 (sizeof(struct ste_desc_onefrag) * 0));
1441 } else {
1442 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1443 ld->ste_rx_list[i].ste_next =
1444 htole32(ld->ste_rx_list_paddr +
1445 (sizeof(struct ste_desc_onefrag) * (i + 1)));
1446 }
1447 }
1448
1449 cd->ste_rx_head = &cd->ste_rx_chain[0];
1450 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1451 sc->ste_cdata.ste_rx_list_map,
1452 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1453
1454 return (0);
1455 }
1456
1457 static void
1458 ste_init_tx_list(struct ste_softc *sc)
1459 {
1460 struct ste_chain_data *cd;
1461 struct ste_list_data *ld;
1462 int i;
1463
1464 cd = &sc->ste_cdata;
1465 ld = &sc->ste_ldata;
1466 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1467 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1468 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1469 cd->ste_tx_chain[i].ste_mbuf = NULL;
1470 if (i == (STE_TX_LIST_CNT - 1)) {
1471 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1472 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1473 ld->ste_tx_list_paddr +
1474 (sizeof(struct ste_desc) * 0)));
1475 } else {
1476 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1477 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1478 ld->ste_tx_list_paddr +
1479 (sizeof(struct ste_desc) * (i + 1))));
1480 }
1481 }
1482
1483 cd->ste_last_tx = NULL;
1484 cd->ste_tx_prod = 0;
1485 cd->ste_tx_cons = 0;
1486 cd->ste_tx_cnt = 0;
1487
1488 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1489 sc->ste_cdata.ste_tx_list_map,
1490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1491 }
1492
1493 static void
1494 ste_init(void *xsc)
1495 {
1496 struct ste_softc *sc;
1497
1498 sc = xsc;
1499 STE_LOCK(sc);
1500 ste_init_locked(sc);
1501 STE_UNLOCK(sc);
1502 }
1503
1504 static void
1505 ste_init_locked(struct ste_softc *sc)
1506 {
1507 struct ifnet *ifp;
1508 struct mii_data *mii;
1509 uint8_t val;
1510 int i;
1511
1512 STE_LOCK_ASSERT(sc);
1513 ifp = sc->ste_ifp;
1514 mii = device_get_softc(sc->ste_miibus);
1515
1516 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1517 return;
1518
1519 ste_stop(sc);
1520 /* Reset the chip to a known state. */
1521 ste_reset(sc);
1522
1523 /* Init our MAC address */
1524 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1525 CSR_WRITE_2(sc, STE_PAR0 + i,
1526 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1527 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1528 }
1529
1530 /* Init RX list */
1531 if (ste_init_rx_list(sc) != 0) {
1532 device_printf(sc->ste_dev,
1533 "initialization failed: no memory for RX buffers\n");
1534 ste_stop(sc);
1535 return;
1536 }
1537
1538 /* Set RX polling interval */
1539 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1540
1541 /* Init TX descriptors */
1542 ste_init_tx_list(sc);
1543
1544 /* Clear and disable WOL. */
1545 val = CSR_READ_1(sc, STE_WAKE_EVENT);
1546 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
1547 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
1548 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1549
1550 /* Set the TX freethresh value */
1551 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1552
1553 /* Set the TX start threshold for best performance. */
1554 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1555
1556 /* Set the TX reclaim threshold. */
1557 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1558
1559 /* Accept VLAN length packets */
1560 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1561
1562 /* Set up the RX filter. */
1563 ste_rxfilter(sc);
1564
1565 /* Load the address of the RX list. */
1566 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1567 ste_wait(sc);
1568 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1569 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1570 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1571 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1572
1573 /* Set TX polling interval(defer until we TX first packet). */
1574 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1575
1576 /* Load address of the TX list */
1577 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1578 ste_wait(sc);
1579 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1580 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1581 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1582 ste_wait(sc);
1583 /* Select 3.2us timer. */
1584 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED |
1585 STE_DMACTL_COUNTDOWN_MODE);
1586
1587 /* Enable receiver and transmitter */
1588 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1589 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1590 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1591 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1592
1593 /* Enable stats counters. */
1594 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1595 /* Clear stats counters. */
1596 ste_stats_clear(sc);
1597
1598 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1599 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1600 #ifdef DEVICE_POLLING
1601 /* Disable interrupts if we are polling. */
1602 if (ifp->if_capenable & IFCAP_POLLING)
1603 CSR_WRITE_2(sc, STE_IMR, 0);
1604 else
1605 #endif
1606 /* Enable interrupts. */
1607 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1608
1609 sc->ste_flags &= ~STE_FLAG_LINK;
1610 /* Switch to the current media. */
1611 mii_mediachg(mii);
1612
1613 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1614 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1615
1616 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1617 }
1618
1619 static void
1620 ste_stop(struct ste_softc *sc)
1621 {
1622 struct ifnet *ifp;
1623 struct ste_chain_onefrag *cur_rx;
1624 struct ste_chain *cur_tx;
1625 uint32_t val;
1626 int i;
1627
1628 STE_LOCK_ASSERT(sc);
1629 ifp = sc->ste_ifp;
1630
1631 callout_stop(&sc->ste_callout);
1632 sc->ste_timer = 0;
1633 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1634
1635 CSR_WRITE_2(sc, STE_IMR, 0);
1636 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1637 /* Stop pending DMA. */
1638 val = CSR_READ_4(sc, STE_DMACTL);
1639 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1640 CSR_WRITE_4(sc, STE_DMACTL, val);
1641 ste_wait(sc);
1642 /* Disable auto-polling. */
1643 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1644 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1645 /* Nullify DMA address to stop any further DMA. */
1646 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1647 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1648 /* Stop TX/RX MAC. */
1649 val = CSR_READ_2(sc, STE_MACCTL1);
1650 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1651 STE_MACCTL1_STATS_DISABLE;
1652 CSR_WRITE_2(sc, STE_MACCTL1, val);
1653 for (i = 0; i < STE_TIMEOUT; i++) {
1654 DELAY(10);
1655 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1656 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1657 break;
1658 }
1659 if (i == STE_TIMEOUT)
1660 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1661 /* Acknowledge any pending interrupts. */
1662 CSR_READ_2(sc, STE_ISR_ACK);
1663 ste_stats_update(sc);
1664
1665 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1666 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1667 if (cur_rx->ste_mbuf != NULL) {
1668 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1669 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1670 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1671 cur_rx->ste_map);
1672 m_freem(cur_rx->ste_mbuf);
1673 cur_rx->ste_mbuf = NULL;
1674 }
1675 }
1676
1677 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1678 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1679 if (cur_tx->ste_mbuf != NULL) {
1680 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1681 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1682 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1683 cur_tx->ste_map);
1684 m_freem(cur_tx->ste_mbuf);
1685 cur_tx->ste_mbuf = NULL;
1686 }
1687 }
1688 }
1689
1690 static void
1691 ste_reset(struct ste_softc *sc)
1692 {
1693 uint32_t ctl;
1694 int i;
1695
1696 ctl = CSR_READ_4(sc, STE_ASICCTL);
1697 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1698 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1699 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1700 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1701 STE_ASICCTL_EXTRESET_RESET;
1702 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1703 CSR_READ_4(sc, STE_ASICCTL);
1704 /*
1705 * Due to the need of accessing EEPROM controller can take
1706 * up to 1ms to complete the global reset.
1707 */
1708 DELAY(1000);
1709
1710 for (i = 0; i < STE_TIMEOUT; i++) {
1711 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1712 break;
1713 DELAY(10);
1714 }
1715
1716 if (i == STE_TIMEOUT)
1717 device_printf(sc->ste_dev, "global reset never completed\n");
1718 }
1719
1720 static void
1721 ste_restart_tx(struct ste_softc *sc)
1722 {
1723 uint16_t mac;
1724 int i;
1725
1726 for (i = 0; i < STE_TIMEOUT; i++) {
1727 mac = CSR_READ_2(sc, STE_MACCTL1);
1728 mac |= STE_MACCTL1_TX_ENABLE;
1729 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1730 mac = CSR_READ_2(sc, STE_MACCTL1);
1731 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1732 break;
1733 DELAY(10);
1734 }
1735
1736 if (i == STE_TIMEOUT)
1737 device_printf(sc->ste_dev, "starting Tx failed");
1738 }
1739
1740 static int
1741 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1742 {
1743 struct ste_softc *sc;
1744 struct ifreq *ifr;
1745 struct mii_data *mii;
1746 int error = 0, mask;
1747
1748 sc = ifp->if_softc;
1749 ifr = (struct ifreq *)data;
1750
1751 switch (command) {
1752 case SIOCSIFFLAGS:
1753 STE_LOCK(sc);
1754 if ((ifp->if_flags & IFF_UP) != 0) {
1755 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1756 ((ifp->if_flags ^ sc->ste_if_flags) &
1757 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1758 ste_rxfilter(sc);
1759 else
1760 ste_init_locked(sc);
1761 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1762 ste_stop(sc);
1763 sc->ste_if_flags = ifp->if_flags;
1764 STE_UNLOCK(sc);
1765 break;
1766 case SIOCADDMULTI:
1767 case SIOCDELMULTI:
1768 STE_LOCK(sc);
1769 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1770 ste_rxfilter(sc);
1771 STE_UNLOCK(sc);
1772 break;
1773 case SIOCGIFMEDIA:
1774 case SIOCSIFMEDIA:
1775 mii = device_get_softc(sc->ste_miibus);
1776 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1777 break;
1778 case SIOCSIFCAP:
1779 STE_LOCK(sc);
1780 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1781 #ifdef DEVICE_POLLING
1782 if ((mask & IFCAP_POLLING) != 0 &&
1783 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
1784 ifp->if_capenable ^= IFCAP_POLLING;
1785 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
1786 error = ether_poll_register(ste_poll, ifp);
1787 if (error != 0) {
1788 STE_UNLOCK(sc);
1789 break;
1790 }
1791 /* Disable interrupts. */
1792 CSR_WRITE_2(sc, STE_IMR, 0);
1793 } else {
1794 error = ether_poll_deregister(ifp);
1795 /* Enable interrupts. */
1796 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1797 }
1798 }
1799 #endif /* DEVICE_POLLING */
1800 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1801 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1802 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1803 STE_UNLOCK(sc);
1804 break;
1805 default:
1806 error = ether_ioctl(ifp, command, data);
1807 break;
1808 }
1809
1810 return (error);
1811 }
1812
1813 static int
1814 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1815 {
1816 struct ste_frag *frag;
1817 struct mbuf *m;
1818 struct ste_desc *desc;
1819 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1820 int error, i, nsegs;
1821
1822 STE_LOCK_ASSERT(sc);
1823 M_ASSERTPKTHDR((*m_head));
1824
1825 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1826 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1827 if (error == EFBIG) {
1828 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS);
1829 if (m == NULL) {
1830 m_freem(*m_head);
1831 *m_head = NULL;
1832 return (ENOMEM);
1833 }
1834 *m_head = m;
1835 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1836 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1837 if (error != 0) {
1838 m_freem(*m_head);
1839 *m_head = NULL;
1840 return (error);
1841 }
1842 } else if (error != 0)
1843 return (error);
1844 if (nsegs == 0) {
1845 m_freem(*m_head);
1846 *m_head = NULL;
1847 return (EIO);
1848 }
1849 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1850 BUS_DMASYNC_PREWRITE);
1851
1852 desc = txc->ste_ptr;
1853 for (i = 0; i < nsegs; i++) {
1854 frag = &desc->ste_frags[i];
1855 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1856 frag->ste_len = htole32(txsegs[i].ds_len);
1857 }
1858 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1859 /*
1860 * Because we use Tx polling we can't chain multiple
1861 * Tx descriptors here. Otherwise we race with controller.
1862 */
1863 desc->ste_next = 0;
1864 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
1865 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
1866 STE_TXCTL_DMAINTR);
1867 else
1868 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
1869 txc->ste_mbuf = *m_head;
1870 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
1871 sc->ste_cdata.ste_tx_cnt++;
1872
1873 return (0);
1874 }
1875
1876 static void
1877 ste_start(struct ifnet *ifp)
1878 {
1879 struct ste_softc *sc;
1880
1881 sc = ifp->if_softc;
1882 STE_LOCK(sc);
1883 ste_start_locked(ifp);
1884 STE_UNLOCK(sc);
1885 }
1886
1887 static void
1888 ste_start_locked(struct ifnet *ifp)
1889 {
1890 struct ste_softc *sc;
1891 struct ste_chain *cur_tx;
1892 struct mbuf *m_head = NULL;
1893 int enq;
1894
1895 sc = ifp->if_softc;
1896 STE_LOCK_ASSERT(sc);
1897
1898 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1899 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
1900 return;
1901
1902 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
1903 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
1904 /*
1905 * Controller may have cached copy of the last used
1906 * next ptr so we have to reserve one TFD to avoid
1907 * TFD overruns.
1908 */
1909 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1910 break;
1911 }
1912 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1913 if (m_head == NULL)
1914 break;
1915 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
1916 if (ste_encap(sc, &m_head, cur_tx) != 0) {
1917 if (m_head == NULL)
1918 break;
1919 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1920 break;
1921 }
1922 if (sc->ste_cdata.ste_last_tx == NULL) {
1923 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1924 sc->ste_cdata.ste_tx_list_map,
1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1926 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1927 ste_wait(sc);
1928 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1929 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
1930 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1931 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1932 ste_wait(sc);
1933 } else {
1934 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
1935 sc->ste_cdata.ste_last_tx->ste_phys;
1936 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1937 sc->ste_cdata.ste_tx_list_map,
1938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1939 }
1940 sc->ste_cdata.ste_last_tx = cur_tx;
1941
1942 enq++;
1943 /*
1944 * If there's a BPF listener, bounce a copy of this frame
1945 * to him.
1946 */
1947 BPF_MTAP(ifp, m_head);
1948 }
1949
1950 if (enq > 0)
1951 sc->ste_timer = STE_TX_TIMEOUT;
1952 }
1953
1954 static void
1955 ste_watchdog(struct ste_softc *sc)
1956 {
1957 struct ifnet *ifp;
1958
1959 ifp = sc->ste_ifp;
1960 STE_LOCK_ASSERT(sc);
1961
1962 if (sc->ste_timer == 0 || --sc->ste_timer)
1963 return;
1964
1965 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1966 if_printf(ifp, "watchdog timeout\n");
1967
1968 ste_txeof(sc);
1969 ste_txeoc(sc);
1970 ste_rxeof(sc, -1);
1971 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1972 ste_init_locked(sc);
1973
1974 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1975 ste_start_locked(ifp);
1976 }
1977
1978 static int
1979 ste_shutdown(device_t dev)
1980 {
1981
1982 return (ste_suspend(dev));
1983 }
1984
1985 static int
1986 ste_suspend(device_t dev)
1987 {
1988 struct ste_softc *sc;
1989
1990 sc = device_get_softc(dev);
1991
1992 STE_LOCK(sc);
1993 ste_stop(sc);
1994 ste_setwol(sc);
1995 STE_UNLOCK(sc);
1996
1997 return (0);
1998 }
1999
2000 static int
2001 ste_resume(device_t dev)
2002 {
2003 struct ste_softc *sc;
2004 struct ifnet *ifp;
2005 int pmc;
2006 uint16_t pmstat;
2007
2008 sc = device_get_softc(dev);
2009 STE_LOCK(sc);
2010 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
2011 /* Disable PME and clear PME status. */
2012 pmstat = pci_read_config(sc->ste_dev,
2013 pmc + PCIR_POWER_STATUS, 2);
2014 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2015 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2016 pci_write_config(sc->ste_dev,
2017 pmc + PCIR_POWER_STATUS, pmstat, 2);
2018 }
2019 }
2020 ifp = sc->ste_ifp;
2021 if ((ifp->if_flags & IFF_UP) != 0) {
2022 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2023 ste_init_locked(sc);
2024 }
2025 STE_UNLOCK(sc);
2026
2027 return (0);
2028 }
2029
2030 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2031 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2032 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2033 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2034
2035 static void
2036 ste_sysctl_node(struct ste_softc *sc)
2037 {
2038 struct sysctl_ctx_list *ctx;
2039 struct sysctl_oid_list *child, *parent;
2040 struct sysctl_oid *tree;
2041 struct ste_hw_stats *stats;
2042
2043 stats = &sc->ste_stats;
2044 ctx = device_get_sysctl_ctx(sc->ste_dev);
2045 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2046
2047 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod",
2048 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation");
2049 /* Pull in device tunables. */
2050 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT;
2051 resource_int_value(device_get_name(sc->ste_dev),
2052 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod);
2053
2054 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
2055 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "STE statistics");
2056 parent = SYSCTL_CHILDREN(tree);
2057
2058 /* Rx statistics. */
2059 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
2060 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
2061 child = SYSCTL_CHILDREN(tree);
2062 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2063 &stats->rx_bytes, "Good octets");
2064 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2065 &stats->rx_frames, "Good frames");
2066 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2067 &stats->rx_bcast_frames, "Good broadcast frames");
2068 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2069 &stats->rx_mcast_frames, "Good multicast frames");
2070 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2071 &stats->rx_lost_frames, "Lost frames");
2072
2073 /* Tx statistics. */
2074 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
2075 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
2076 child = SYSCTL_CHILDREN(tree);
2077 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2078 &stats->tx_bytes, "Good octets");
2079 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2080 &stats->tx_frames, "Good frames");
2081 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2082 &stats->tx_bcast_frames, "Good broadcast frames");
2083 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2084 &stats->tx_mcast_frames, "Good multicast frames");
2085 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2086 &stats->tx_carrsense_errs, "Carrier sense errors");
2087 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2088 &stats->tx_single_colls, "Single collisions");
2089 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2090 &stats->tx_multi_colls, "Multiple collisions");
2091 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2092 &stats->tx_late_colls, "Late collisions");
2093 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2094 &stats->tx_frames_defered, "Frames with deferrals");
2095 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2096 &stats->tx_excess_defers, "Frames with excessive derferrals");
2097 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2098 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2099 }
2100
2101 #undef STE_SYSCTL_STAT_ADD32
2102 #undef STE_SYSCTL_STAT_ADD64
2103
2104 static void
2105 ste_setwol(struct ste_softc *sc)
2106 {
2107 struct ifnet *ifp;
2108 uint16_t pmstat;
2109 uint8_t val;
2110 int pmc;
2111
2112 STE_LOCK_ASSERT(sc);
2113
2114 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
2115 /* Disable WOL. */
2116 CSR_READ_1(sc, STE_WAKE_EVENT);
2117 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
2118 return;
2119 }
2120
2121 ifp = sc->ste_ifp;
2122 val = CSR_READ_1(sc, STE_WAKE_EVENT);
2123 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
2124 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
2125 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2126 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB;
2127 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
2128 /* Request PME. */
2129 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2);
2130 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2131 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2132 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2133 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2134 }
Cache object: e69e7760dbe96f3de6804af9858ee05d
|