FreeBSD/Linux Kernel Cross Reference
sys/dev/ste/if_ste.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
38 #endif
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/bus.h>
43 #include <sys/endian.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/malloc.h>
47 #include <sys/mbuf.h>
48 #include <sys/module.h>
49 #include <sys/rman.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53
54 #include <net/bpf.h>
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_arp.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
63
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66
67 #include <dev/mii/mii.h>
68 #include <dev/mii/mii_bitbang.h>
69 #include <dev/mii/miivar.h>
70
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
73
74 #include <dev/ste/if_stereg.h>
75
76 /* "device miibus" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
78
79 MODULE_DEPEND(ste, pci, 1, 1, 1);
80 MODULE_DEPEND(ste, ether, 1, 1, 1);
81 MODULE_DEPEND(ste, miibus, 1, 1, 1);
82
83 /* Define to show Tx error status. */
84 #define STE_SHOW_TXERRORS
85
86 /*
87 * Various supported device vendors/types and their names.
88 */
89 static const struct ste_type ste_devs[] = {
90 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
91 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
92 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
93 { 0, 0, NULL }
94 };
95
96 static int ste_attach(device_t);
97 static int ste_detach(device_t);
98 static int ste_probe(device_t);
99 static int ste_resume(device_t);
100 static int ste_shutdown(device_t);
101 static int ste_suspend(device_t);
102
103 static int ste_dma_alloc(struct ste_softc *);
104 static void ste_dma_free(struct ste_softc *);
105 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
106 static int ste_eeprom_wait(struct ste_softc *);
107 static int ste_encap(struct ste_softc *, struct mbuf **,
108 struct ste_chain *);
109 static int ste_ifmedia_upd(struct ifnet *);
110 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
111 static void ste_init(void *);
112 static void ste_init_locked(struct ste_softc *);
113 static int ste_init_rx_list(struct ste_softc *);
114 static void ste_init_tx_list(struct ste_softc *);
115 static void ste_intr(void *);
116 static int ste_ioctl(struct ifnet *, u_long, caddr_t);
117 static uint32_t ste_mii_bitbang_read(device_t);
118 static void ste_mii_bitbang_write(device_t, uint32_t);
119 static int ste_miibus_readreg(device_t, int, int);
120 static void ste_miibus_statchg(device_t);
121 static int ste_miibus_writereg(device_t, int, int, int);
122 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
123 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int);
124 static void ste_reset(struct ste_softc *);
125 static void ste_restart_tx(struct ste_softc *);
126 static int ste_rxeof(struct ste_softc *, int);
127 static void ste_rxfilter(struct ste_softc *);
128 static void ste_setwol(struct ste_softc *);
129 static void ste_start(struct ifnet *);
130 static void ste_start_locked(struct ifnet *);
131 static void ste_stats_clear(struct ste_softc *);
132 static void ste_stats_update(struct ste_softc *);
133 static void ste_stop(struct ste_softc *);
134 static void ste_sysctl_node(struct ste_softc *);
135 static void ste_tick(void *);
136 static void ste_txeoc(struct ste_softc *);
137 static void ste_txeof(struct ste_softc *);
138 static void ste_wait(struct ste_softc *);
139 static void ste_watchdog(struct ste_softc *);
140
141 /*
142 * MII bit-bang glue
143 */
144 static const struct mii_bitbang_ops ste_mii_bitbang_ops = {
145 ste_mii_bitbang_read,
146 ste_mii_bitbang_write,
147 {
148 STE_PHYCTL_MDATA, /* MII_BIT_MDO */
149 STE_PHYCTL_MDATA, /* MII_BIT_MDI */
150 STE_PHYCTL_MCLK, /* MII_BIT_MDC */
151 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */
152 0, /* MII_BIT_DIR_PHY_HOST */
153 }
154 };
155
156 static device_method_t ste_methods[] = {
157 /* Device interface */
158 DEVMETHOD(device_probe, ste_probe),
159 DEVMETHOD(device_attach, ste_attach),
160 DEVMETHOD(device_detach, ste_detach),
161 DEVMETHOD(device_shutdown, ste_shutdown),
162 DEVMETHOD(device_suspend, ste_suspend),
163 DEVMETHOD(device_resume, ste_resume),
164
165 /* MII interface */
166 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
167 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
168 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
169
170 DEVMETHOD_END
171 };
172
173 static driver_t ste_driver = {
174 "ste",
175 ste_methods,
176 sizeof(struct ste_softc)
177 };
178
179 static devclass_t ste_devclass;
180
181 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
182 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
183
184 #define STE_SETBIT4(sc, reg, x) \
185 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
186
187 #define STE_CLRBIT4(sc, reg, x) \
188 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
189
190 #define STE_SETBIT2(sc, reg, x) \
191 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
192
193 #define STE_CLRBIT2(sc, reg, x) \
194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
195
196 #define STE_SETBIT1(sc, reg, x) \
197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
198
199 #define STE_CLRBIT1(sc, reg, x) \
200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
201
202 /*
203 * Read the MII serial port for the MII bit-bang module.
204 */
205 static uint32_t
206 ste_mii_bitbang_read(device_t dev)
207 {
208 struct ste_softc *sc;
209 uint32_t val;
210
211 sc = device_get_softc(dev);
212
213 val = CSR_READ_1(sc, STE_PHYCTL);
214 CSR_BARRIER(sc, STE_PHYCTL, 1,
215 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
216
217 return (val);
218 }
219
220 /*
221 * Write the MII serial port for the MII bit-bang module.
222 */
223 static void
224 ste_mii_bitbang_write(device_t dev, uint32_t val)
225 {
226 struct ste_softc *sc;
227
228 sc = device_get_softc(dev);
229
230 CSR_WRITE_1(sc, STE_PHYCTL, val);
231 CSR_BARRIER(sc, STE_PHYCTL, 1,
232 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
233 }
234
235 static int
236 ste_miibus_readreg(device_t dev, int phy, int reg)
237 {
238
239 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg));
240 }
241
242 static int
243 ste_miibus_writereg(device_t dev, int phy, int reg, int data)
244 {
245
246 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data);
247
248 return (0);
249 }
250
251 static void
252 ste_miibus_statchg(device_t dev)
253 {
254 struct ste_softc *sc;
255 struct mii_data *mii;
256 struct ifnet *ifp;
257 uint16_t cfg;
258
259 sc = device_get_softc(dev);
260
261 mii = device_get_softc(sc->ste_miibus);
262 ifp = sc->ste_ifp;
263 if (mii == NULL || ifp == NULL ||
264 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
265 return;
266
267 sc->ste_flags &= ~STE_FLAG_LINK;
268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
269 (IFM_ACTIVE | IFM_AVALID)) {
270 switch (IFM_SUBTYPE(mii->mii_media_active)) {
271 case IFM_10_T:
272 case IFM_100_TX:
273 case IFM_100_FX:
274 case IFM_100_T4:
275 sc->ste_flags |= STE_FLAG_LINK;
276 default:
277 break;
278 }
279 }
280
281 /* Program MACs with resolved speed/duplex/flow-control. */
282 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
283 cfg = CSR_READ_2(sc, STE_MACCTL0);
284 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
285 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
286 /*
287 * ST201 data sheet says driver should enable receiving
288 * MAC control frames bit of receive mode register to
289 * receive flow-control frames but the register has no
290 * such bits. In addition the controller has no ability
291 * to send pause frames so it should be handled in
292 * driver. Implementing pause timer handling in driver
293 * layer is not trivial, so don't enable flow-control
294 * here.
295 */
296 cfg |= STE_MACCTL0_FULLDUPLEX;
297 }
298 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
299 }
300 }
301
302 static int
303 ste_ifmedia_upd(struct ifnet *ifp)
304 {
305 struct ste_softc *sc;
306 struct mii_data *mii;
307 struct mii_softc *miisc;
308 int error;
309
310 sc = ifp->if_softc;
311 STE_LOCK(sc);
312 mii = device_get_softc(sc->ste_miibus);
313 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
314 PHY_RESET(miisc);
315 error = mii_mediachg(mii);
316 STE_UNLOCK(sc);
317
318 return (error);
319 }
320
321 static void
322 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
323 {
324 struct ste_softc *sc;
325 struct mii_data *mii;
326
327 sc = ifp->if_softc;
328 mii = device_get_softc(sc->ste_miibus);
329
330 STE_LOCK(sc);
331 if ((ifp->if_flags & IFF_UP) == 0) {
332 STE_UNLOCK(sc);
333 return;
334 }
335 mii_pollstat(mii);
336 ifmr->ifm_active = mii->mii_media_active;
337 ifmr->ifm_status = mii->mii_media_status;
338 STE_UNLOCK(sc);
339 }
340
341 static void
342 ste_wait(struct ste_softc *sc)
343 {
344 int i;
345
346 for (i = 0; i < STE_TIMEOUT; i++) {
347 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
348 break;
349 DELAY(1);
350 }
351
352 if (i == STE_TIMEOUT)
353 device_printf(sc->ste_dev, "command never completed!\n");
354 }
355
356 /*
357 * The EEPROM is slow: give it time to come ready after issuing
358 * it a command.
359 */
360 static int
361 ste_eeprom_wait(struct ste_softc *sc)
362 {
363 int i;
364
365 DELAY(1000);
366
367 for (i = 0; i < 100; i++) {
368 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
369 DELAY(1000);
370 else
371 break;
372 }
373
374 if (i == 100) {
375 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
376 return (1);
377 }
378
379 return (0);
380 }
381
382 /*
383 * Read a sequence of words from the EEPROM. Note that ethernet address
384 * data is stored in the EEPROM in network byte order.
385 */
386 static int
387 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt)
388 {
389 int err = 0, i;
390
391 if (ste_eeprom_wait(sc))
392 return (1);
393
394 for (i = 0; i < cnt; i++) {
395 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
396 err = ste_eeprom_wait(sc);
397 if (err)
398 break;
399 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
400 dest++;
401 }
402
403 return (err ? 1 : 0);
404 }
405
406 static void
407 ste_rxfilter(struct ste_softc *sc)
408 {
409 struct ifnet *ifp;
410 struct ifmultiaddr *ifma;
411 uint32_t hashes[2] = { 0, 0 };
412 uint8_t rxcfg;
413 int h;
414
415 STE_LOCK_ASSERT(sc);
416
417 ifp = sc->ste_ifp;
418 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
419 rxcfg |= STE_RXMODE_UNICAST;
420 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
421 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
422 if (ifp->if_flags & IFF_BROADCAST)
423 rxcfg |= STE_RXMODE_BROADCAST;
424 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
425 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
426 rxcfg |= STE_RXMODE_ALLMULTI;
427 if ((ifp->if_flags & IFF_PROMISC) != 0)
428 rxcfg |= STE_RXMODE_PROMISC;
429 goto chipit;
430 }
431
432 rxcfg |= STE_RXMODE_MULTIHASH;
433 /* Now program new ones. */
434 if_maddr_rlock(ifp);
435 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
436 if (ifma->ifma_addr->sa_family != AF_LINK)
437 continue;
438 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
439 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
440 if (h < 32)
441 hashes[0] |= (1 << h);
442 else
443 hashes[1] |= (1 << (h - 32));
444 }
445 if_maddr_runlock(ifp);
446
447 chipit:
448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
452 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
453 CSR_READ_1(sc, STE_RX_MODE);
454 }
455
456 #ifdef DEVICE_POLLING
457 static poll_handler_t ste_poll, ste_poll_locked;
458
459 static int
460 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
461 {
462 struct ste_softc *sc = ifp->if_softc;
463 int rx_npkts = 0;
464
465 STE_LOCK(sc);
466 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
467 rx_npkts = ste_poll_locked(ifp, cmd, count);
468 STE_UNLOCK(sc);
469 return (rx_npkts);
470 }
471
472 static int
473 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
474 {
475 struct ste_softc *sc = ifp->if_softc;
476 int rx_npkts;
477
478 STE_LOCK_ASSERT(sc);
479
480 rx_npkts = ste_rxeof(sc, count);
481 ste_txeof(sc);
482 ste_txeoc(sc);
483 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
484 ste_start_locked(ifp);
485
486 if (cmd == POLL_AND_CHECK_STATUS) {
487 uint16_t status;
488
489 status = CSR_READ_2(sc, STE_ISR_ACK);
490
491 if (status & STE_ISR_STATS_OFLOW)
492 ste_stats_update(sc);
493
494 if (status & STE_ISR_HOSTERR) {
495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
496 ste_init_locked(sc);
497 }
498 }
499 return (rx_npkts);
500 }
501 #endif /* DEVICE_POLLING */
502
503 static void
504 ste_intr(void *xsc)
505 {
506 struct ste_softc *sc;
507 struct ifnet *ifp;
508 uint16_t intrs, status;
509
510 sc = xsc;
511 STE_LOCK(sc);
512 ifp = sc->ste_ifp;
513
514 #ifdef DEVICE_POLLING
515 if (ifp->if_capenable & IFCAP_POLLING) {
516 STE_UNLOCK(sc);
517 return;
518 }
519 #endif
520 /* Reading STE_ISR_ACK clears STE_IMR register. */
521 status = CSR_READ_2(sc, STE_ISR_ACK);
522 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
523 STE_UNLOCK(sc);
524 return;
525 }
526
527 intrs = STE_INTRS;
528 if (status == 0xFFFF || (status & intrs) == 0)
529 goto done;
530
531 if (sc->ste_int_rx_act > 0) {
532 status &= ~STE_ISR_RX_DMADONE;
533 intrs &= ~STE_IMR_RX_DMADONE;
534 }
535
536 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) {
537 ste_rxeof(sc, -1);
538 /*
539 * The controller has no ability to Rx interrupt
540 * moderation feature. Receiving 64 bytes frames
541 * from wire generates too many interrupts which in
542 * turn make system useless to process other useful
543 * things. Fortunately ST201 supports single shot
544 * timer so use the timer to implement Rx interrupt
545 * moderation in driver. This adds more register
546 * access but it greatly reduces number of Rx
547 * interrupts under high network load.
548 */
549 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
550 (sc->ste_int_rx_mod != 0)) {
551 if ((status & STE_ISR_RX_DMADONE) != 0) {
552 CSR_WRITE_2(sc, STE_COUNTDOWN,
553 STE_TIMER_USECS(sc->ste_int_rx_mod));
554 intrs &= ~STE_IMR_RX_DMADONE;
555 sc->ste_int_rx_act = 1;
556 } else {
557 intrs |= STE_IMR_RX_DMADONE;
558 sc->ste_int_rx_act = 0;
559 }
560 }
561 }
562 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
563 if ((status & STE_ISR_TX_DMADONE) != 0)
564 ste_txeof(sc);
565 if ((status & STE_ISR_TX_DONE) != 0)
566 ste_txeoc(sc);
567 if ((status & STE_ISR_STATS_OFLOW) != 0)
568 ste_stats_update(sc);
569 if ((status & STE_ISR_HOSTERR) != 0) {
570 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
571 ste_init_locked(sc);
572 STE_UNLOCK(sc);
573 return;
574 }
575 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
576 ste_start_locked(ifp);
577 done:
578 /* Re-enable interrupts */
579 CSR_WRITE_2(sc, STE_IMR, intrs);
580 }
581 STE_UNLOCK(sc);
582 }
583
584 /*
585 * A frame has been uploaded: pass the resulting mbuf chain up to
586 * the higher level protocols.
587 */
588 static int
589 ste_rxeof(struct ste_softc *sc, int count)
590 {
591 struct mbuf *m;
592 struct ifnet *ifp;
593 struct ste_chain_onefrag *cur_rx;
594 uint32_t rxstat;
595 int total_len, rx_npkts;
596
597 ifp = sc->ste_ifp;
598
599 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
600 sc->ste_cdata.ste_rx_list_map,
601 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
602
603 cur_rx = sc->ste_cdata.ste_rx_head;
604 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
605 cur_rx = cur_rx->ste_next) {
606 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
607 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
608 break;
609 #ifdef DEVICE_POLLING
610 if (ifp->if_capenable & IFCAP_POLLING) {
611 if (count == 0)
612 break;
613 count--;
614 }
615 #endif
616 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
617 break;
618 /*
619 * If an error occurs, update stats, clear the
620 * status word and leave the mbuf cluster in place:
621 * it should simply get re-used next time this descriptor
622 * comes up in the ring.
623 */
624 if (rxstat & STE_RXSTAT_FRAME_ERR) {
625 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
626 cur_rx->ste_ptr->ste_status = 0;
627 continue;
628 }
629
630 /* No errors; receive the packet. */
631 m = cur_rx->ste_mbuf;
632 total_len = STE_RX_BYTES(rxstat);
633
634 /*
635 * Try to conjure up a new mbuf cluster. If that
636 * fails, it means we have an out of memory condition and
637 * should leave the buffer in place and continue. This will
638 * result in a lost packet, but there's little else we
639 * can do in this situation.
640 */
641 if (ste_newbuf(sc, cur_rx) != 0) {
642 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
643 cur_rx->ste_ptr->ste_status = 0;
644 continue;
645 }
646
647 m->m_pkthdr.rcvif = ifp;
648 m->m_pkthdr.len = m->m_len = total_len;
649
650 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
651 STE_UNLOCK(sc);
652 (*ifp->if_input)(ifp, m);
653 STE_LOCK(sc);
654 }
655
656 if (rx_npkts > 0) {
657 sc->ste_cdata.ste_rx_head = cur_rx;
658 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
659 sc->ste_cdata.ste_rx_list_map,
660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
661 }
662
663 return (rx_npkts);
664 }
665
666 static void
667 ste_txeoc(struct ste_softc *sc)
668 {
669 uint16_t txstat;
670 struct ifnet *ifp;
671
672 STE_LOCK_ASSERT(sc);
673
674 ifp = sc->ste_ifp;
675
676 /*
677 * STE_TX_STATUS register implements a queue of up to 31
678 * transmit status byte. Writing an arbitrary value to the
679 * register will advance the queue to the next transmit
680 * status byte. This means if driver does not read
681 * STE_TX_STATUS register after completing sending more
682 * than 31 frames the controller would be stalled so driver
683 * should re-wake the Tx MAC. This is the most severe
684 * limitation of ST201 based controller.
685 */
686 for (;;) {
687 txstat = CSR_READ_2(sc, STE_TX_STATUS);
688 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
689 break;
690 if ((txstat & (STE_TXSTATUS_UNDERRUN |
691 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
692 STE_TXSTATUS_STATSOFLOW)) != 0) {
693 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
694 #ifdef STE_SHOW_TXERRORS
695 device_printf(sc->ste_dev, "TX error : 0x%b\n",
696 txstat & 0xFF, STE_ERR_BITS);
697 #endif
698 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
699 sc->ste_tx_thresh < STE_PACKET_SIZE) {
700 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
701 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
702 sc->ste_tx_thresh = STE_PACKET_SIZE;
703 device_printf(sc->ste_dev,
704 "TX underrun, increasing TX"
705 " start threshold to %d bytes\n",
706 sc->ste_tx_thresh);
707 /* Make sure to disable active DMA cycles. */
708 STE_SETBIT4(sc, STE_DMACTL,
709 STE_DMACTL_TXDMA_STALL);
710 ste_wait(sc);
711 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
712 ste_init_locked(sc);
713 break;
714 }
715 /* Restart Tx. */
716 ste_restart_tx(sc);
717 }
718 /*
719 * Advance to next status and ACK TxComplete
720 * interrupt. ST201 data sheet was wrong here, to
721 * get next Tx status, we have to write both
722 * STE_TX_STATUS and STE_TX_FRAMEID register.
723 * Otherwise controller returns the same status
724 * as well as not acknowledge Tx completion
725 * interrupt.
726 */
727 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
728 }
729 }
730
731 static void
732 ste_tick(void *arg)
733 {
734 struct ste_softc *sc;
735 struct mii_data *mii;
736
737 sc = (struct ste_softc *)arg;
738
739 STE_LOCK_ASSERT(sc);
740
741 mii = device_get_softc(sc->ste_miibus);
742 mii_tick(mii);
743 /*
744 * ukphy(4) does not seem to generate CB that reports
745 * resolved link state so if we know we lost a link,
746 * explicitly check the link state.
747 */
748 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
749 ste_miibus_statchg(sc->ste_dev);
750 /*
751 * Because we are not generating Tx completion
752 * interrupt for every frame, reclaim transmitted
753 * buffers here.
754 */
755 ste_txeof(sc);
756 ste_txeoc(sc);
757 ste_stats_update(sc);
758 ste_watchdog(sc);
759 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
760 }
761
762 static void
763 ste_txeof(struct ste_softc *sc)
764 {
765 struct ifnet *ifp;
766 struct ste_chain *cur_tx;
767 uint32_t txstat;
768 int idx;
769
770 STE_LOCK_ASSERT(sc);
771
772 ifp = sc->ste_ifp;
773 idx = sc->ste_cdata.ste_tx_cons;
774 if (idx == sc->ste_cdata.ste_tx_prod)
775 return;
776
777 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
778 sc->ste_cdata.ste_tx_list_map,
779 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
780
781 while (idx != sc->ste_cdata.ste_tx_prod) {
782 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
783 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
784 if ((txstat & STE_TXCTL_DMADONE) == 0)
785 break;
786 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
787 BUS_DMASYNC_POSTWRITE);
788 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
789 KASSERT(cur_tx->ste_mbuf != NULL,
790 ("%s: freeing NULL mbuf!\n", __func__));
791 m_freem(cur_tx->ste_mbuf);
792 cur_tx->ste_mbuf = NULL;
793 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
794 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
795 sc->ste_cdata.ste_tx_cnt--;
796 STE_INC(idx, STE_TX_LIST_CNT);
797 }
798
799 sc->ste_cdata.ste_tx_cons = idx;
800 if (sc->ste_cdata.ste_tx_cnt == 0)
801 sc->ste_timer = 0;
802 }
803
804 static void
805 ste_stats_clear(struct ste_softc *sc)
806 {
807
808 STE_LOCK_ASSERT(sc);
809
810 /* Rx stats. */
811 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
812 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
813 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
814 CSR_READ_1(sc, STE_STAT_RX_BCAST);
815 CSR_READ_1(sc, STE_STAT_RX_MCAST);
816 CSR_READ_1(sc, STE_STAT_RX_LOST);
817 /* Tx stats. */
818 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
819 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
820 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
821 CSR_READ_1(sc, STE_STAT_TX_BCAST);
822 CSR_READ_1(sc, STE_STAT_TX_MCAST);
823 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
824 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
825 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
826 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
827 CSR_READ_1(sc, STE_STAT_TX_DEFER);
828 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
829 CSR_READ_1(sc, STE_STAT_TX_ABORT);
830 }
831
832 static void
833 ste_stats_update(struct ste_softc *sc)
834 {
835 struct ifnet *ifp;
836 struct ste_hw_stats *stats;
837 uint32_t val;
838
839 STE_LOCK_ASSERT(sc);
840
841 ifp = sc->ste_ifp;
842 stats = &sc->ste_stats;
843 /* Rx stats. */
844 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
845 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
846 val &= 0x000FFFFF;
847 stats->rx_bytes += val;
848 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
849 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
850 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
851 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
852 /* Tx stats. */
853 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
854 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
855 val &= 0x000FFFFF;
856 stats->tx_bytes += val;
857 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
858 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
859 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
860 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
861 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
862 stats->tx_single_colls += val;
863 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val);
864 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
865 stats->tx_multi_colls += val;
866 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val);
867 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
868 stats->tx_late_colls += val;
869 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val);
870 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
871 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
872 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
873 }
874
875 /*
876 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
877 * IDs against our list and return a device name if we find a match.
878 */
879 static int
880 ste_probe(device_t dev)
881 {
882 const struct ste_type *t;
883
884 t = ste_devs;
885
886 while (t->ste_name != NULL) {
887 if ((pci_get_vendor(dev) == t->ste_vid) &&
888 (pci_get_device(dev) == t->ste_did)) {
889 device_set_desc(dev, t->ste_name);
890 return (BUS_PROBE_DEFAULT);
891 }
892 t++;
893 }
894
895 return (ENXIO);
896 }
897
898 /*
899 * Attach the interface. Allocate softc structures, do ifmedia
900 * setup and ethernet/BPF attach.
901 */
902 static int
903 ste_attach(device_t dev)
904 {
905 struct ste_softc *sc;
906 struct ifnet *ifp;
907 uint16_t eaddr[ETHER_ADDR_LEN / 2];
908 int error = 0, phy, pmc, prefer_iomap, rid;
909
910 sc = device_get_softc(dev);
911 sc->ste_dev = dev;
912
913 /*
914 * Only use one PHY since this chip reports multiple
915 * Note on the DFE-550 the PHY is at 1 on the DFE-580
916 * it is at 0 & 1. It is rev 0x12.
917 */
918 if (pci_get_vendor(dev) == DL_VENDORID &&
919 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
920 pci_get_revid(dev) == 0x12 )
921 sc->ste_flags |= STE_FLAG_ONE_PHY;
922
923 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
924 MTX_DEF);
925 /*
926 * Map control/status registers.
927 */
928 pci_enable_busmaster(dev);
929
930 /*
931 * Prefer memory space register mapping over IO space but use
932 * IO space for a device that is known to have issues on memory
933 * mapping.
934 */
935 prefer_iomap = 0;
936 if (pci_get_device(dev) == ST_DEVICEID_ST201_1)
937 prefer_iomap = 1;
938 else
939 resource_int_value(device_get_name(sc->ste_dev),
940 device_get_unit(sc->ste_dev), "prefer_iomap",
941 &prefer_iomap);
942 if (prefer_iomap == 0) {
943 sc->ste_res_id = PCIR_BAR(1);
944 sc->ste_res_type = SYS_RES_MEMORY;
945 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
946 &sc->ste_res_id, RF_ACTIVE);
947 }
948 if (prefer_iomap || sc->ste_res == NULL) {
949 sc->ste_res_id = PCIR_BAR(0);
950 sc->ste_res_type = SYS_RES_IOPORT;
951 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
952 &sc->ste_res_id, RF_ACTIVE);
953 }
954 if (sc->ste_res == NULL) {
955 device_printf(dev, "couldn't map ports/memory\n");
956 error = ENXIO;
957 goto fail;
958 }
959
960 /* Allocate interrupt */
961 rid = 0;
962 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
963 RF_SHAREABLE | RF_ACTIVE);
964
965 if (sc->ste_irq == NULL) {
966 device_printf(dev, "couldn't map interrupt\n");
967 error = ENXIO;
968 goto fail;
969 }
970
971 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
972
973 /* Reset the adapter. */
974 ste_reset(sc);
975
976 /*
977 * Get station address from the EEPROM.
978 */
979 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) {
980 device_printf(dev, "failed to read station address\n");
981 error = ENXIO;
982 goto fail;
983 }
984 ste_sysctl_node(sc);
985
986 if ((error = ste_dma_alloc(sc)) != 0)
987 goto fail;
988
989 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
990 if (ifp == NULL) {
991 device_printf(dev, "can not if_alloc()\n");
992 error = ENOSPC;
993 goto fail;
994 }
995
996 /* Do MII setup. */
997 phy = MII_PHY_ANY;
998 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0)
999 phy = 0;
1000 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd,
1001 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1002 if (error != 0) {
1003 device_printf(dev, "attaching PHYs failed\n");
1004 goto fail;
1005 }
1006
1007 ifp->if_softc = sc;
1008 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1009 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1010 ifp->if_ioctl = ste_ioctl;
1011 ifp->if_start = ste_start;
1012 ifp->if_init = ste_init;
1013 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1014 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1015 IFQ_SET_READY(&ifp->if_snd);
1016
1017 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1018
1019 /*
1020 * Call MI attach routine.
1021 */
1022 ether_ifattach(ifp, (uint8_t *)eaddr);
1023
1024 /*
1025 * Tell the upper layer(s) we support long frames.
1026 */
1027 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1028 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1029 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
1030 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1031 ifp->if_capenable = ifp->if_capabilities;
1032 #ifdef DEVICE_POLLING
1033 ifp->if_capabilities |= IFCAP_POLLING;
1034 #endif
1035
1036 /* Hook interrupt last to avoid having to lock softc */
1037 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1038 NULL, ste_intr, sc, &sc->ste_intrhand);
1039
1040 if (error) {
1041 device_printf(dev, "couldn't set up irq\n");
1042 ether_ifdetach(ifp);
1043 goto fail;
1044 }
1045
1046 fail:
1047 if (error)
1048 ste_detach(dev);
1049
1050 return (error);
1051 }
1052
1053 /*
1054 * Shutdown hardware and free up resources. This can be called any
1055 * time after the mutex has been initialized. It is called in both
1056 * the error case in attach and the normal detach case so it needs
1057 * to be careful about only freeing resources that have actually been
1058 * allocated.
1059 */
1060 static int
1061 ste_detach(device_t dev)
1062 {
1063 struct ste_softc *sc;
1064 struct ifnet *ifp;
1065
1066 sc = device_get_softc(dev);
1067 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1068 ifp = sc->ste_ifp;
1069
1070 #ifdef DEVICE_POLLING
1071 if (ifp->if_capenable & IFCAP_POLLING)
1072 ether_poll_deregister(ifp);
1073 #endif
1074
1075 /* These should only be active if attach succeeded */
1076 if (device_is_attached(dev)) {
1077 ether_ifdetach(ifp);
1078 STE_LOCK(sc);
1079 ste_stop(sc);
1080 STE_UNLOCK(sc);
1081 callout_drain(&sc->ste_callout);
1082 }
1083 if (sc->ste_miibus)
1084 device_delete_child(dev, sc->ste_miibus);
1085 bus_generic_detach(dev);
1086
1087 if (sc->ste_intrhand)
1088 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1089 if (sc->ste_irq)
1090 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1091 if (sc->ste_res)
1092 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1093 sc->ste_res);
1094
1095 if (ifp)
1096 if_free(ifp);
1097
1098 ste_dma_free(sc);
1099 mtx_destroy(&sc->ste_mtx);
1100
1101 return (0);
1102 }
1103
1104 struct ste_dmamap_arg {
1105 bus_addr_t ste_busaddr;
1106 };
1107
1108 static void
1109 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1110 {
1111 struct ste_dmamap_arg *ctx;
1112
1113 if (error != 0)
1114 return;
1115
1116 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1117
1118 ctx = (struct ste_dmamap_arg *)arg;
1119 ctx->ste_busaddr = segs[0].ds_addr;
1120 }
1121
1122 static int
1123 ste_dma_alloc(struct ste_softc *sc)
1124 {
1125 struct ste_chain *txc;
1126 struct ste_chain_onefrag *rxc;
1127 struct ste_dmamap_arg ctx;
1128 int error, i;
1129
1130 /* Create parent DMA tag. */
1131 error = bus_dma_tag_create(
1132 bus_get_dma_tag(sc->ste_dev), /* parent */
1133 1, 0, /* alignment, boundary */
1134 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1135 BUS_SPACE_MAXADDR, /* highaddr */
1136 NULL, NULL, /* filter, filterarg */
1137 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1138 0, /* nsegments */
1139 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1140 0, /* flags */
1141 NULL, NULL, /* lockfunc, lockarg */
1142 &sc->ste_cdata.ste_parent_tag);
1143 if (error != 0) {
1144 device_printf(sc->ste_dev,
1145 "could not create parent DMA tag.\n");
1146 goto fail;
1147 }
1148
1149 /* Create DMA tag for Tx descriptor list. */
1150 error = bus_dma_tag_create(
1151 sc->ste_cdata.ste_parent_tag, /* parent */
1152 STE_DESC_ALIGN, 0, /* alignment, boundary */
1153 BUS_SPACE_MAXADDR, /* lowaddr */
1154 BUS_SPACE_MAXADDR, /* highaddr */
1155 NULL, NULL, /* filter, filterarg */
1156 STE_TX_LIST_SZ, /* maxsize */
1157 1, /* nsegments */
1158 STE_TX_LIST_SZ, /* maxsegsize */
1159 0, /* flags */
1160 NULL, NULL, /* lockfunc, lockarg */
1161 &sc->ste_cdata.ste_tx_list_tag);
1162 if (error != 0) {
1163 device_printf(sc->ste_dev,
1164 "could not create Tx list DMA tag.\n");
1165 goto fail;
1166 }
1167
1168 /* Create DMA tag for Rx descriptor list. */
1169 error = bus_dma_tag_create(
1170 sc->ste_cdata.ste_parent_tag, /* parent */
1171 STE_DESC_ALIGN, 0, /* alignment, boundary */
1172 BUS_SPACE_MAXADDR, /* lowaddr */
1173 BUS_SPACE_MAXADDR, /* highaddr */
1174 NULL, NULL, /* filter, filterarg */
1175 STE_RX_LIST_SZ, /* maxsize */
1176 1, /* nsegments */
1177 STE_RX_LIST_SZ, /* maxsegsize */
1178 0, /* flags */
1179 NULL, NULL, /* lockfunc, lockarg */
1180 &sc->ste_cdata.ste_rx_list_tag);
1181 if (error != 0) {
1182 device_printf(sc->ste_dev,
1183 "could not create Rx list DMA tag.\n");
1184 goto fail;
1185 }
1186
1187 /* Create DMA tag for Tx buffers. */
1188 error = bus_dma_tag_create(
1189 sc->ste_cdata.ste_parent_tag, /* parent */
1190 1, 0, /* alignment, boundary */
1191 BUS_SPACE_MAXADDR, /* lowaddr */
1192 BUS_SPACE_MAXADDR, /* highaddr */
1193 NULL, NULL, /* filter, filterarg */
1194 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1195 STE_MAXFRAGS, /* nsegments */
1196 MCLBYTES, /* maxsegsize */
1197 0, /* flags */
1198 NULL, NULL, /* lockfunc, lockarg */
1199 &sc->ste_cdata.ste_tx_tag);
1200 if (error != 0) {
1201 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1202 goto fail;
1203 }
1204
1205 /* Create DMA tag for Rx buffers. */
1206 error = bus_dma_tag_create(
1207 sc->ste_cdata.ste_parent_tag, /* parent */
1208 1, 0, /* alignment, boundary */
1209 BUS_SPACE_MAXADDR, /* lowaddr */
1210 BUS_SPACE_MAXADDR, /* highaddr */
1211 NULL, NULL, /* filter, filterarg */
1212 MCLBYTES, /* maxsize */
1213 1, /* nsegments */
1214 MCLBYTES, /* maxsegsize */
1215 0, /* flags */
1216 NULL, NULL, /* lockfunc, lockarg */
1217 &sc->ste_cdata.ste_rx_tag);
1218 if (error != 0) {
1219 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1220 goto fail;
1221 }
1222
1223 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1224 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1225 (void **)&sc->ste_ldata.ste_tx_list,
1226 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1227 &sc->ste_cdata.ste_tx_list_map);
1228 if (error != 0) {
1229 device_printf(sc->ste_dev,
1230 "could not allocate DMA'able memory for Tx list.\n");
1231 goto fail;
1232 }
1233 ctx.ste_busaddr = 0;
1234 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1235 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1236 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1237 if (error != 0 || ctx.ste_busaddr == 0) {
1238 device_printf(sc->ste_dev,
1239 "could not load DMA'able memory for Tx list.\n");
1240 goto fail;
1241 }
1242 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1243
1244 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1245 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1246 (void **)&sc->ste_ldata.ste_rx_list,
1247 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1248 &sc->ste_cdata.ste_rx_list_map);
1249 if (error != 0) {
1250 device_printf(sc->ste_dev,
1251 "could not allocate DMA'able memory for Rx list.\n");
1252 goto fail;
1253 }
1254 ctx.ste_busaddr = 0;
1255 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1256 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1257 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1258 if (error != 0 || ctx.ste_busaddr == 0) {
1259 device_printf(sc->ste_dev,
1260 "could not load DMA'able memory for Rx list.\n");
1261 goto fail;
1262 }
1263 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1264
1265 /* Create DMA maps for Tx buffers. */
1266 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1267 txc = &sc->ste_cdata.ste_tx_chain[i];
1268 txc->ste_ptr = NULL;
1269 txc->ste_mbuf = NULL;
1270 txc->ste_next = NULL;
1271 txc->ste_phys = 0;
1272 txc->ste_map = NULL;
1273 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1274 &txc->ste_map);
1275 if (error != 0) {
1276 device_printf(sc->ste_dev,
1277 "could not create Tx dmamap.\n");
1278 goto fail;
1279 }
1280 }
1281 /* Create DMA maps for Rx buffers. */
1282 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1283 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1284 device_printf(sc->ste_dev,
1285 "could not create spare Rx dmamap.\n");
1286 goto fail;
1287 }
1288 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1289 rxc = &sc->ste_cdata.ste_rx_chain[i];
1290 rxc->ste_ptr = NULL;
1291 rxc->ste_mbuf = NULL;
1292 rxc->ste_next = NULL;
1293 rxc->ste_map = NULL;
1294 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1295 &rxc->ste_map);
1296 if (error != 0) {
1297 device_printf(sc->ste_dev,
1298 "could not create Rx dmamap.\n");
1299 goto fail;
1300 }
1301 }
1302
1303 fail:
1304 return (error);
1305 }
1306
1307 static void
1308 ste_dma_free(struct ste_softc *sc)
1309 {
1310 struct ste_chain *txc;
1311 struct ste_chain_onefrag *rxc;
1312 int i;
1313
1314 /* Tx buffers. */
1315 if (sc->ste_cdata.ste_tx_tag != NULL) {
1316 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1317 txc = &sc->ste_cdata.ste_tx_chain[i];
1318 if (txc->ste_map != NULL) {
1319 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1320 txc->ste_map);
1321 txc->ste_map = NULL;
1322 }
1323 }
1324 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1325 sc->ste_cdata.ste_tx_tag = NULL;
1326 }
1327 /* Rx buffers. */
1328 if (sc->ste_cdata.ste_rx_tag != NULL) {
1329 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1330 rxc = &sc->ste_cdata.ste_rx_chain[i];
1331 if (rxc->ste_map != NULL) {
1332 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1333 rxc->ste_map);
1334 rxc->ste_map = NULL;
1335 }
1336 }
1337 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1338 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1339 sc->ste_cdata.ste_rx_sparemap);
1340 sc->ste_cdata.ste_rx_sparemap = NULL;
1341 }
1342 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1343 sc->ste_cdata.ste_rx_tag = NULL;
1344 }
1345 /* Tx descriptor list. */
1346 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1347 if (sc->ste_ldata.ste_tx_list_paddr != 0)
1348 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1349 sc->ste_cdata.ste_tx_list_map);
1350 if (sc->ste_ldata.ste_tx_list != NULL)
1351 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1352 sc->ste_ldata.ste_tx_list,
1353 sc->ste_cdata.ste_tx_list_map);
1354 sc->ste_ldata.ste_tx_list = NULL;
1355 sc->ste_ldata.ste_tx_list_paddr = 0;
1356 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1357 sc->ste_cdata.ste_tx_list_tag = NULL;
1358 }
1359 /* Rx descriptor list. */
1360 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1361 if (sc->ste_ldata.ste_rx_list_paddr != 0)
1362 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1363 sc->ste_cdata.ste_rx_list_map);
1364 if (sc->ste_ldata.ste_rx_list != NULL)
1365 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1366 sc->ste_ldata.ste_rx_list,
1367 sc->ste_cdata.ste_rx_list_map);
1368 sc->ste_ldata.ste_rx_list = NULL;
1369 sc->ste_ldata.ste_rx_list_paddr = 0;
1370 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1371 sc->ste_cdata.ste_rx_list_tag = NULL;
1372 }
1373 if (sc->ste_cdata.ste_parent_tag != NULL) {
1374 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1375 sc->ste_cdata.ste_parent_tag = NULL;
1376 }
1377 }
1378
1379 static int
1380 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1381 {
1382 struct mbuf *m;
1383 bus_dma_segment_t segs[1];
1384 bus_dmamap_t map;
1385 int error, nsegs;
1386
1387 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1388 if (m == NULL)
1389 return (ENOBUFS);
1390 m->m_len = m->m_pkthdr.len = MCLBYTES;
1391 m_adj(m, ETHER_ALIGN);
1392
1393 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1394 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1395 m_freem(m);
1396 return (error);
1397 }
1398 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1399
1400 if (rxc->ste_mbuf != NULL) {
1401 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1402 BUS_DMASYNC_POSTREAD);
1403 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1404 }
1405 map = rxc->ste_map;
1406 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1407 sc->ste_cdata.ste_rx_sparemap = map;
1408 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1409 BUS_DMASYNC_PREREAD);
1410 rxc->ste_mbuf = m;
1411 rxc->ste_ptr->ste_status = 0;
1412 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1413 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1414 STE_FRAG_LAST);
1415 return (0);
1416 }
1417
1418 static int
1419 ste_init_rx_list(struct ste_softc *sc)
1420 {
1421 struct ste_chain_data *cd;
1422 struct ste_list_data *ld;
1423 int error, i;
1424
1425 sc->ste_int_rx_act = 0;
1426 cd = &sc->ste_cdata;
1427 ld = &sc->ste_ldata;
1428 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1429 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1430 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1431 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1432 if (error != 0)
1433 return (error);
1434 if (i == (STE_RX_LIST_CNT - 1)) {
1435 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1436 ld->ste_rx_list[i].ste_next =
1437 htole32(ld->ste_rx_list_paddr +
1438 (sizeof(struct ste_desc_onefrag) * 0));
1439 } else {
1440 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1441 ld->ste_rx_list[i].ste_next =
1442 htole32(ld->ste_rx_list_paddr +
1443 (sizeof(struct ste_desc_onefrag) * (i + 1)));
1444 }
1445 }
1446
1447 cd->ste_rx_head = &cd->ste_rx_chain[0];
1448 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1449 sc->ste_cdata.ste_rx_list_map,
1450 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1451
1452 return (0);
1453 }
1454
1455 static void
1456 ste_init_tx_list(struct ste_softc *sc)
1457 {
1458 struct ste_chain_data *cd;
1459 struct ste_list_data *ld;
1460 int i;
1461
1462 cd = &sc->ste_cdata;
1463 ld = &sc->ste_ldata;
1464 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1465 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1466 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1467 cd->ste_tx_chain[i].ste_mbuf = NULL;
1468 if (i == (STE_TX_LIST_CNT - 1)) {
1469 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1470 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1471 ld->ste_tx_list_paddr +
1472 (sizeof(struct ste_desc) * 0)));
1473 } else {
1474 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1475 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1476 ld->ste_tx_list_paddr +
1477 (sizeof(struct ste_desc) * (i + 1))));
1478 }
1479 }
1480
1481 cd->ste_last_tx = NULL;
1482 cd->ste_tx_prod = 0;
1483 cd->ste_tx_cons = 0;
1484 cd->ste_tx_cnt = 0;
1485
1486 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1487 sc->ste_cdata.ste_tx_list_map,
1488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1489 }
1490
1491 static void
1492 ste_init(void *xsc)
1493 {
1494 struct ste_softc *sc;
1495
1496 sc = xsc;
1497 STE_LOCK(sc);
1498 ste_init_locked(sc);
1499 STE_UNLOCK(sc);
1500 }
1501
1502 static void
1503 ste_init_locked(struct ste_softc *sc)
1504 {
1505 struct ifnet *ifp;
1506 struct mii_data *mii;
1507 uint8_t val;
1508 int i;
1509
1510 STE_LOCK_ASSERT(sc);
1511 ifp = sc->ste_ifp;
1512 mii = device_get_softc(sc->ste_miibus);
1513
1514 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1515 return;
1516
1517 ste_stop(sc);
1518 /* Reset the chip to a known state. */
1519 ste_reset(sc);
1520
1521 /* Init our MAC address */
1522 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1523 CSR_WRITE_2(sc, STE_PAR0 + i,
1524 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1525 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1526 }
1527
1528 /* Init RX list */
1529 if (ste_init_rx_list(sc) != 0) {
1530 device_printf(sc->ste_dev,
1531 "initialization failed: no memory for RX buffers\n");
1532 ste_stop(sc);
1533 return;
1534 }
1535
1536 /* Set RX polling interval */
1537 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1538
1539 /* Init TX descriptors */
1540 ste_init_tx_list(sc);
1541
1542 /* Clear and disable WOL. */
1543 val = CSR_READ_1(sc, STE_WAKE_EVENT);
1544 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
1545 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
1546 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1547
1548 /* Set the TX freethresh value */
1549 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1550
1551 /* Set the TX start threshold for best performance. */
1552 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1553
1554 /* Set the TX reclaim threshold. */
1555 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1556
1557 /* Accept VLAN length packets */
1558 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1559
1560 /* Set up the RX filter. */
1561 ste_rxfilter(sc);
1562
1563 /* Load the address of the RX list. */
1564 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1565 ste_wait(sc);
1566 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1567 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1568 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1569 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1570
1571 /* Set TX polling interval(defer until we TX first packet). */
1572 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1573
1574 /* Load address of the TX list */
1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1576 ste_wait(sc);
1577 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1578 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1579 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1580 ste_wait(sc);
1581 /* Select 3.2us timer. */
1582 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED |
1583 STE_DMACTL_COUNTDOWN_MODE);
1584
1585 /* Enable receiver and transmitter */
1586 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1587 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1588 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1589 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1590
1591 /* Enable stats counters. */
1592 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1593 /* Clear stats counters. */
1594 ste_stats_clear(sc);
1595
1596 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1597 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1598 #ifdef DEVICE_POLLING
1599 /* Disable interrupts if we are polling. */
1600 if (ifp->if_capenable & IFCAP_POLLING)
1601 CSR_WRITE_2(sc, STE_IMR, 0);
1602 else
1603 #endif
1604 /* Enable interrupts. */
1605 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1606
1607 sc->ste_flags &= ~STE_FLAG_LINK;
1608 /* Switch to the current media. */
1609 mii_mediachg(mii);
1610
1611 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1612 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1613
1614 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1615 }
1616
1617 static void
1618 ste_stop(struct ste_softc *sc)
1619 {
1620 struct ifnet *ifp;
1621 struct ste_chain_onefrag *cur_rx;
1622 struct ste_chain *cur_tx;
1623 uint32_t val;
1624 int i;
1625
1626 STE_LOCK_ASSERT(sc);
1627 ifp = sc->ste_ifp;
1628
1629 callout_stop(&sc->ste_callout);
1630 sc->ste_timer = 0;
1631 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1632
1633 CSR_WRITE_2(sc, STE_IMR, 0);
1634 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1635 /* Stop pending DMA. */
1636 val = CSR_READ_4(sc, STE_DMACTL);
1637 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1638 CSR_WRITE_4(sc, STE_DMACTL, val);
1639 ste_wait(sc);
1640 /* Disable auto-polling. */
1641 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1642 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1643 /* Nullify DMA address to stop any further DMA. */
1644 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1645 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1646 /* Stop TX/RX MAC. */
1647 val = CSR_READ_2(sc, STE_MACCTL1);
1648 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1649 STE_MACCTL1_STATS_DISABLE;
1650 CSR_WRITE_2(sc, STE_MACCTL1, val);
1651 for (i = 0; i < STE_TIMEOUT; i++) {
1652 DELAY(10);
1653 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1654 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1655 break;
1656 }
1657 if (i == STE_TIMEOUT)
1658 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1659 /* Acknowledge any pending interrupts. */
1660 CSR_READ_2(sc, STE_ISR_ACK);
1661 ste_stats_update(sc);
1662
1663 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1664 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1665 if (cur_rx->ste_mbuf != NULL) {
1666 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1667 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1668 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1669 cur_rx->ste_map);
1670 m_freem(cur_rx->ste_mbuf);
1671 cur_rx->ste_mbuf = NULL;
1672 }
1673 }
1674
1675 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1676 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1677 if (cur_tx->ste_mbuf != NULL) {
1678 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1679 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1680 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1681 cur_tx->ste_map);
1682 m_freem(cur_tx->ste_mbuf);
1683 cur_tx->ste_mbuf = NULL;
1684 }
1685 }
1686 }
1687
1688 static void
1689 ste_reset(struct ste_softc *sc)
1690 {
1691 uint32_t ctl;
1692 int i;
1693
1694 ctl = CSR_READ_4(sc, STE_ASICCTL);
1695 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1696 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1697 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1698 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1699 STE_ASICCTL_EXTRESET_RESET;
1700 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1701 CSR_READ_4(sc, STE_ASICCTL);
1702 /*
1703 * Due to the need of accessing EEPROM controller can take
1704 * up to 1ms to complete the global reset.
1705 */
1706 DELAY(1000);
1707
1708 for (i = 0; i < STE_TIMEOUT; i++) {
1709 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1710 break;
1711 DELAY(10);
1712 }
1713
1714 if (i == STE_TIMEOUT)
1715 device_printf(sc->ste_dev, "global reset never completed\n");
1716 }
1717
1718 static void
1719 ste_restart_tx(struct ste_softc *sc)
1720 {
1721 uint16_t mac;
1722 int i;
1723
1724 for (i = 0; i < STE_TIMEOUT; i++) {
1725 mac = CSR_READ_2(sc, STE_MACCTL1);
1726 mac |= STE_MACCTL1_TX_ENABLE;
1727 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1728 mac = CSR_READ_2(sc, STE_MACCTL1);
1729 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1730 break;
1731 DELAY(10);
1732 }
1733
1734 if (i == STE_TIMEOUT)
1735 device_printf(sc->ste_dev, "starting Tx failed");
1736 }
1737
1738 static int
1739 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1740 {
1741 struct ste_softc *sc;
1742 struct ifreq *ifr;
1743 struct mii_data *mii;
1744 int error = 0, mask;
1745
1746 sc = ifp->if_softc;
1747 ifr = (struct ifreq *)data;
1748
1749 switch (command) {
1750 case SIOCSIFFLAGS:
1751 STE_LOCK(sc);
1752 if ((ifp->if_flags & IFF_UP) != 0) {
1753 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1754 ((ifp->if_flags ^ sc->ste_if_flags) &
1755 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1756 ste_rxfilter(sc);
1757 else
1758 ste_init_locked(sc);
1759 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1760 ste_stop(sc);
1761 sc->ste_if_flags = ifp->if_flags;
1762 STE_UNLOCK(sc);
1763 break;
1764 case SIOCADDMULTI:
1765 case SIOCDELMULTI:
1766 STE_LOCK(sc);
1767 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1768 ste_rxfilter(sc);
1769 STE_UNLOCK(sc);
1770 break;
1771 case SIOCGIFMEDIA:
1772 case SIOCSIFMEDIA:
1773 mii = device_get_softc(sc->ste_miibus);
1774 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1775 break;
1776 case SIOCSIFCAP:
1777 STE_LOCK(sc);
1778 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1779 #ifdef DEVICE_POLLING
1780 if ((mask & IFCAP_POLLING) != 0 &&
1781 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
1782 ifp->if_capenable ^= IFCAP_POLLING;
1783 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
1784 error = ether_poll_register(ste_poll, ifp);
1785 if (error != 0) {
1786 STE_UNLOCK(sc);
1787 break;
1788 }
1789 /* Disable interrupts. */
1790 CSR_WRITE_2(sc, STE_IMR, 0);
1791 } else {
1792 error = ether_poll_deregister(ifp);
1793 /* Enable interrupts. */
1794 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1795 }
1796 }
1797 #endif /* DEVICE_POLLING */
1798 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1799 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1800 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1801 STE_UNLOCK(sc);
1802 break;
1803 default:
1804 error = ether_ioctl(ifp, command, data);
1805 break;
1806 }
1807
1808 return (error);
1809 }
1810
1811 static int
1812 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1813 {
1814 struct ste_frag *frag;
1815 struct mbuf *m;
1816 struct ste_desc *desc;
1817 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1818 int error, i, nsegs;
1819
1820 STE_LOCK_ASSERT(sc);
1821 M_ASSERTPKTHDR((*m_head));
1822
1823 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1824 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1825 if (error == EFBIG) {
1826 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS);
1827 if (m == NULL) {
1828 m_freem(*m_head);
1829 *m_head = NULL;
1830 return (ENOMEM);
1831 }
1832 *m_head = m;
1833 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1834 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1835 if (error != 0) {
1836 m_freem(*m_head);
1837 *m_head = NULL;
1838 return (error);
1839 }
1840 } else if (error != 0)
1841 return (error);
1842 if (nsegs == 0) {
1843 m_freem(*m_head);
1844 *m_head = NULL;
1845 return (EIO);
1846 }
1847 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1848 BUS_DMASYNC_PREWRITE);
1849
1850 desc = txc->ste_ptr;
1851 for (i = 0; i < nsegs; i++) {
1852 frag = &desc->ste_frags[i];
1853 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1854 frag->ste_len = htole32(txsegs[i].ds_len);
1855 }
1856 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1857 /*
1858 * Because we use Tx polling we can't chain multiple
1859 * Tx descriptors here. Otherwise we race with controller.
1860 */
1861 desc->ste_next = 0;
1862 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
1863 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
1864 STE_TXCTL_DMAINTR);
1865 else
1866 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
1867 txc->ste_mbuf = *m_head;
1868 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
1869 sc->ste_cdata.ste_tx_cnt++;
1870
1871 return (0);
1872 }
1873
1874 static void
1875 ste_start(struct ifnet *ifp)
1876 {
1877 struct ste_softc *sc;
1878
1879 sc = ifp->if_softc;
1880 STE_LOCK(sc);
1881 ste_start_locked(ifp);
1882 STE_UNLOCK(sc);
1883 }
1884
1885 static void
1886 ste_start_locked(struct ifnet *ifp)
1887 {
1888 struct ste_softc *sc;
1889 struct ste_chain *cur_tx;
1890 struct mbuf *m_head = NULL;
1891 int enq;
1892
1893 sc = ifp->if_softc;
1894 STE_LOCK_ASSERT(sc);
1895
1896 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1897 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
1898 return;
1899
1900 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
1901 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
1902 /*
1903 * Controller may have cached copy of the last used
1904 * next ptr so we have to reserve one TFD to avoid
1905 * TFD overruns.
1906 */
1907 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1908 break;
1909 }
1910 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1911 if (m_head == NULL)
1912 break;
1913 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
1914 if (ste_encap(sc, &m_head, cur_tx) != 0) {
1915 if (m_head == NULL)
1916 break;
1917 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1918 break;
1919 }
1920 if (sc->ste_cdata.ste_last_tx == NULL) {
1921 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1922 sc->ste_cdata.ste_tx_list_map,
1923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1924 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1925 ste_wait(sc);
1926 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1927 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
1928 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1929 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1930 ste_wait(sc);
1931 } else {
1932 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
1933 sc->ste_cdata.ste_last_tx->ste_phys;
1934 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1935 sc->ste_cdata.ste_tx_list_map,
1936 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1937 }
1938 sc->ste_cdata.ste_last_tx = cur_tx;
1939
1940 enq++;
1941 /*
1942 * If there's a BPF listener, bounce a copy of this frame
1943 * to him.
1944 */
1945 BPF_MTAP(ifp, m_head);
1946 }
1947
1948 if (enq > 0)
1949 sc->ste_timer = STE_TX_TIMEOUT;
1950 }
1951
1952 static void
1953 ste_watchdog(struct ste_softc *sc)
1954 {
1955 struct ifnet *ifp;
1956
1957 ifp = sc->ste_ifp;
1958 STE_LOCK_ASSERT(sc);
1959
1960 if (sc->ste_timer == 0 || --sc->ste_timer)
1961 return;
1962
1963 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1964 if_printf(ifp, "watchdog timeout\n");
1965
1966 ste_txeof(sc);
1967 ste_txeoc(sc);
1968 ste_rxeof(sc, -1);
1969 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1970 ste_init_locked(sc);
1971
1972 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1973 ste_start_locked(ifp);
1974 }
1975
1976 static int
1977 ste_shutdown(device_t dev)
1978 {
1979
1980 return (ste_suspend(dev));
1981 }
1982
1983 static int
1984 ste_suspend(device_t dev)
1985 {
1986 struct ste_softc *sc;
1987
1988 sc = device_get_softc(dev);
1989
1990 STE_LOCK(sc);
1991 ste_stop(sc);
1992 ste_setwol(sc);
1993 STE_UNLOCK(sc);
1994
1995 return (0);
1996 }
1997
1998 static int
1999 ste_resume(device_t dev)
2000 {
2001 struct ste_softc *sc;
2002 struct ifnet *ifp;
2003 int pmc;
2004 uint16_t pmstat;
2005
2006 sc = device_get_softc(dev);
2007 STE_LOCK(sc);
2008 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
2009 /* Disable PME and clear PME status. */
2010 pmstat = pci_read_config(sc->ste_dev,
2011 pmc + PCIR_POWER_STATUS, 2);
2012 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2013 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2014 pci_write_config(sc->ste_dev,
2015 pmc + PCIR_POWER_STATUS, pmstat, 2);
2016 }
2017 }
2018 ifp = sc->ste_ifp;
2019 if ((ifp->if_flags & IFF_UP) != 0) {
2020 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2021 ste_init_locked(sc);
2022 }
2023 STE_UNLOCK(sc);
2024
2025 return (0);
2026 }
2027
2028 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2029 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2030 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2031 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2032
2033 static void
2034 ste_sysctl_node(struct ste_softc *sc)
2035 {
2036 struct sysctl_ctx_list *ctx;
2037 struct sysctl_oid_list *child, *parent;
2038 struct sysctl_oid *tree;
2039 struct ste_hw_stats *stats;
2040
2041 stats = &sc->ste_stats;
2042 ctx = device_get_sysctl_ctx(sc->ste_dev);
2043 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2044
2045 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod",
2046 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation");
2047 /* Pull in device tunables. */
2048 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT;
2049 resource_int_value(device_get_name(sc->ste_dev),
2050 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod);
2051
2052 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2053 NULL, "STE statistics");
2054 parent = SYSCTL_CHILDREN(tree);
2055
2056 /* Rx statistics. */
2057 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2058 NULL, "Rx MAC statistics");
2059 child = SYSCTL_CHILDREN(tree);
2060 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2061 &stats->rx_bytes, "Good octets");
2062 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2063 &stats->rx_frames, "Good frames");
2064 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2065 &stats->rx_bcast_frames, "Good broadcast frames");
2066 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2067 &stats->rx_mcast_frames, "Good multicast frames");
2068 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2069 &stats->rx_lost_frames, "Lost frames");
2070
2071 /* Tx statistics. */
2072 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2073 NULL, "Tx MAC statistics");
2074 child = SYSCTL_CHILDREN(tree);
2075 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2076 &stats->tx_bytes, "Good octets");
2077 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2078 &stats->tx_frames, "Good frames");
2079 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2080 &stats->tx_bcast_frames, "Good broadcast frames");
2081 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2082 &stats->tx_mcast_frames, "Good multicast frames");
2083 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2084 &stats->tx_carrsense_errs, "Carrier sense errors");
2085 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2086 &stats->tx_single_colls, "Single collisions");
2087 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2088 &stats->tx_multi_colls, "Multiple collisions");
2089 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2090 &stats->tx_late_colls, "Late collisions");
2091 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2092 &stats->tx_frames_defered, "Frames with deferrals");
2093 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2094 &stats->tx_excess_defers, "Frames with excessive derferrals");
2095 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2096 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2097 }
2098
2099 #undef STE_SYSCTL_STAT_ADD32
2100 #undef STE_SYSCTL_STAT_ADD64
2101
2102 static void
2103 ste_setwol(struct ste_softc *sc)
2104 {
2105 struct ifnet *ifp;
2106 uint16_t pmstat;
2107 uint8_t val;
2108 int pmc;
2109
2110 STE_LOCK_ASSERT(sc);
2111
2112 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
2113 /* Disable WOL. */
2114 CSR_READ_1(sc, STE_WAKE_EVENT);
2115 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
2116 return;
2117 }
2118
2119 ifp = sc->ste_ifp;
2120 val = CSR_READ_1(sc, STE_WAKE_EVENT);
2121 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
2122 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
2123 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2124 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB;
2125 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
2126 /* Request PME. */
2127 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2);
2128 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2129 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2130 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2131 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2132 }
Cache object: fa8b86a76c8b0fd7ef9fd2bb2802bada
|