FreeBSD/Linux Kernel Cross Reference
sys/dev/ste/if_ste.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/7.3/sys/dev/ste/if_ste.c 202319 2010-01-14 22:29:29Z yongari $");
35
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
38 #endif
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/bus.h>
43 #include <sys/endian.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/malloc.h>
47 #include <sys/mbuf.h>
48 #include <sys/module.h>
49 #include <sys/rman.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53
54 #include <net/bpf.h>
55 #include <net/if.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
61 #include <net/if_vlan_var.h>
62
63 #include <machine/bus.h>
64 #include <machine/resource.h>
65
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
68
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
71
72 #include <dev/ste/if_stereg.h>
73
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
76
77 MODULE_DEPEND(ste, pci, 1, 1, 1);
78 MODULE_DEPEND(ste, ether, 1, 1, 1);
79 MODULE_DEPEND(ste, miibus, 1, 1, 1);
80
81 /* Define to show Tx error status. */
82 #define STE_SHOW_TXERRORS
83
84 /*
85 * Various supported device vendors/types and their names.
86 */
87 static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
91 { 0, 0, NULL }
92 };
93
94 static int ste_attach(device_t);
95 static int ste_detach(device_t);
96 static int ste_probe(device_t);
97 static int ste_resume(device_t);
98 static int ste_shutdown(device_t);
99 static int ste_suspend(device_t);
100
101 static int ste_dma_alloc(struct ste_softc *);
102 static void ste_dma_free(struct ste_softc *);
103 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
104 static int ste_eeprom_wait(struct ste_softc *);
105 static int ste_encap(struct ste_softc *, struct mbuf **,
106 struct ste_chain *);
107 static int ste_ifmedia_upd(struct ifnet *);
108 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
109 static void ste_init(void *);
110 static void ste_init_locked(struct ste_softc *);
111 static int ste_init_rx_list(struct ste_softc *);
112 static void ste_init_tx_list(struct ste_softc *);
113 static void ste_intr(void *);
114 static int ste_ioctl(struct ifnet *, u_long, caddr_t);
115 static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
116 static void ste_mii_send(struct ste_softc *, uint32_t, int);
117 static void ste_mii_sync(struct ste_softc *);
118 static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
119 static int ste_miibus_readreg(device_t, int, int);
120 static void ste_miibus_statchg(device_t);
121 static int ste_miibus_writereg(device_t, int, int, int);
122 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
123 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int);
124 static void ste_reset(struct ste_softc *);
125 static void ste_restart_tx(struct ste_softc *);
126 static void ste_rxeof(struct ste_softc *, int);
127 static void ste_rxfilter(struct ste_softc *);
128 static void ste_setwol(struct ste_softc *);
129 static void ste_start(struct ifnet *);
130 static void ste_start_locked(struct ifnet *);
131 static void ste_stats_clear(struct ste_softc *);
132 static void ste_stats_update(struct ste_softc *);
133 static void ste_stop(struct ste_softc *);
134 static void ste_sysctl_node(struct ste_softc *);
135 static void ste_tick(void *);
136 static void ste_txeoc(struct ste_softc *);
137 static void ste_txeof(struct ste_softc *);
138 static void ste_wait(struct ste_softc *);
139 static void ste_watchdog(struct ste_softc *);
140
141 static device_method_t ste_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, ste_probe),
144 DEVMETHOD(device_attach, ste_attach),
145 DEVMETHOD(device_detach, ste_detach),
146 DEVMETHOD(device_shutdown, ste_shutdown),
147 DEVMETHOD(device_suspend, ste_suspend),
148 DEVMETHOD(device_resume, ste_resume),
149
150 /* bus interface */
151 DEVMETHOD(bus_print_child, bus_generic_print_child),
152 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
153
154 /* MII interface */
155 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
156 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
157 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
158
159 { 0, 0 }
160 };
161
162 static driver_t ste_driver = {
163 "ste",
164 ste_methods,
165 sizeof(struct ste_softc)
166 };
167
168 static devclass_t ste_devclass;
169
170 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
171 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
172
173 #define STE_SETBIT4(sc, reg, x) \
174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
175
176 #define STE_CLRBIT4(sc, reg, x) \
177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
178
179 #define STE_SETBIT2(sc, reg, x) \
180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
181
182 #define STE_CLRBIT2(sc, reg, x) \
183 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
184
185 #define STE_SETBIT1(sc, reg, x) \
186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
187
188 #define STE_CLRBIT1(sc, reg, x) \
189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
190
191
192 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
193 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
194
195 /*
196 * Sync the PHYs by setting data bit and strobing the clock 32 times.
197 */
198 static void
199 ste_mii_sync(struct ste_softc *sc)
200 {
201 int i;
202
203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
204
205 for (i = 0; i < 32; i++) {
206 MII_SET(STE_PHYCTL_MCLK);
207 DELAY(1);
208 MII_CLR(STE_PHYCTL_MCLK);
209 DELAY(1);
210 }
211 }
212
213 /*
214 * Clock a series of bits through the MII.
215 */
216 static void
217 ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt)
218 {
219 int i;
220
221 MII_CLR(STE_PHYCTL_MCLK);
222
223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
224 if (bits & i) {
225 MII_SET(STE_PHYCTL_MDATA);
226 } else {
227 MII_CLR(STE_PHYCTL_MDATA);
228 }
229 DELAY(1);
230 MII_CLR(STE_PHYCTL_MCLK);
231 DELAY(1);
232 MII_SET(STE_PHYCTL_MCLK);
233 }
234 }
235
236 /*
237 * Read an PHY register through the MII.
238 */
239 static int
240 ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame)
241 {
242 int i, ack;
243
244 /*
245 * Set up frame for RX.
246 */
247 frame->mii_stdelim = STE_MII_STARTDELIM;
248 frame->mii_opcode = STE_MII_READOP;
249 frame->mii_turnaround = 0;
250 frame->mii_data = 0;
251
252 CSR_WRITE_2(sc, STE_PHYCTL, 0);
253 /*
254 * Turn on data xmit.
255 */
256 MII_SET(STE_PHYCTL_MDIR);
257
258 ste_mii_sync(sc);
259
260 /*
261 * Send command/address info.
262 */
263 ste_mii_send(sc, frame->mii_stdelim, 2);
264 ste_mii_send(sc, frame->mii_opcode, 2);
265 ste_mii_send(sc, frame->mii_phyaddr, 5);
266 ste_mii_send(sc, frame->mii_regaddr, 5);
267
268 /* Turn off xmit. */
269 MII_CLR(STE_PHYCTL_MDIR);
270
271 /* Idle bit */
272 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
273 DELAY(1);
274 MII_SET(STE_PHYCTL_MCLK);
275 DELAY(1);
276
277 /* Check for ack */
278 MII_CLR(STE_PHYCTL_MCLK);
279 DELAY(1);
280 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
281 MII_SET(STE_PHYCTL_MCLK);
282 DELAY(1);
283
284 /*
285 * Now try reading data bits. If the ack failed, we still
286 * need to clock through 16 cycles to keep the PHY(s) in sync.
287 */
288 if (ack) {
289 for (i = 0; i < 16; i++) {
290 MII_CLR(STE_PHYCTL_MCLK);
291 DELAY(1);
292 MII_SET(STE_PHYCTL_MCLK);
293 DELAY(1);
294 }
295 goto fail;
296 }
297
298 for (i = 0x8000; i; i >>= 1) {
299 MII_CLR(STE_PHYCTL_MCLK);
300 DELAY(1);
301 if (!ack) {
302 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
303 frame->mii_data |= i;
304 DELAY(1);
305 }
306 MII_SET(STE_PHYCTL_MCLK);
307 DELAY(1);
308 }
309
310 fail:
311
312 MII_CLR(STE_PHYCTL_MCLK);
313 DELAY(1);
314 MII_SET(STE_PHYCTL_MCLK);
315 DELAY(1);
316
317 if (ack)
318 return (1);
319 return (0);
320 }
321
322 /*
323 * Write to a PHY register through the MII.
324 */
325 static int
326 ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame)
327 {
328
329 /*
330 * Set up frame for TX.
331 */
332
333 frame->mii_stdelim = STE_MII_STARTDELIM;
334 frame->mii_opcode = STE_MII_WRITEOP;
335 frame->mii_turnaround = STE_MII_TURNAROUND;
336
337 /*
338 * Turn on data output.
339 */
340 MII_SET(STE_PHYCTL_MDIR);
341
342 ste_mii_sync(sc);
343
344 ste_mii_send(sc, frame->mii_stdelim, 2);
345 ste_mii_send(sc, frame->mii_opcode, 2);
346 ste_mii_send(sc, frame->mii_phyaddr, 5);
347 ste_mii_send(sc, frame->mii_regaddr, 5);
348 ste_mii_send(sc, frame->mii_turnaround, 2);
349 ste_mii_send(sc, frame->mii_data, 16);
350
351 /* Idle bit. */
352 MII_SET(STE_PHYCTL_MCLK);
353 DELAY(1);
354 MII_CLR(STE_PHYCTL_MCLK);
355 DELAY(1);
356
357 /*
358 * Turn off xmit.
359 */
360 MII_CLR(STE_PHYCTL_MDIR);
361
362 return (0);
363 }
364
365 static int
366 ste_miibus_readreg(device_t dev, int phy, int reg)
367 {
368 struct ste_softc *sc;
369 struct ste_mii_frame frame;
370
371 sc = device_get_softc(dev);
372
373 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0)
374 return (0);
375
376 bzero((char *)&frame, sizeof(frame));
377
378 frame.mii_phyaddr = phy;
379 frame.mii_regaddr = reg;
380 ste_mii_readreg(sc, &frame);
381
382 return (frame.mii_data);
383 }
384
385 static int
386 ste_miibus_writereg(device_t dev, int phy, int reg, int data)
387 {
388 struct ste_softc *sc;
389 struct ste_mii_frame frame;
390
391 sc = device_get_softc(dev);
392 bzero((char *)&frame, sizeof(frame));
393
394 frame.mii_phyaddr = phy;
395 frame.mii_regaddr = reg;
396 frame.mii_data = data;
397
398 ste_mii_writereg(sc, &frame);
399
400 return (0);
401 }
402
403 static void
404 ste_miibus_statchg(device_t dev)
405 {
406 struct ste_softc *sc;
407 struct mii_data *mii;
408 struct ifnet *ifp;
409 uint16_t cfg;
410
411 sc = device_get_softc(dev);
412
413 mii = device_get_softc(sc->ste_miibus);
414 ifp = sc->ste_ifp;
415 if (mii == NULL || ifp == NULL ||
416 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
417 return;
418
419 sc->ste_flags &= ~STE_FLAG_LINK;
420 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
421 (IFM_ACTIVE | IFM_AVALID)) {
422 switch (IFM_SUBTYPE(mii->mii_media_active)) {
423 case IFM_10_T:
424 case IFM_100_TX:
425 case IFM_100_FX:
426 case IFM_100_T4:
427 sc->ste_flags |= STE_FLAG_LINK;
428 default:
429 break;
430 }
431 }
432
433 /* Program MACs with resolved speed/duplex/flow-control. */
434 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
435 cfg = CSR_READ_2(sc, STE_MACCTL0);
436 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
437 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
438 /*
439 * ST201 data sheet says driver should enable receiving
440 * MAC control frames bit of receive mode register to
441 * receive flow-control frames but the register has no
442 * such bits. In addition the controller has no ability
443 * to send pause frames so it should be handled in
444 * driver. Implementing pause timer handling in driver
445 * layer is not trivial, so don't enable flow-control
446 * here.
447 */
448 cfg |= STE_MACCTL0_FULLDUPLEX;
449 }
450 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
451 }
452 }
453
454 static int
455 ste_ifmedia_upd(struct ifnet *ifp)
456 {
457 struct ste_softc *sc;
458 struct mii_data *mii;
459 struct mii_softc *miisc;
460 int error;
461
462 sc = ifp->if_softc;
463 STE_LOCK(sc);
464 mii = device_get_softc(sc->ste_miibus);
465 if (mii->mii_instance) {
466 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
467 mii_phy_reset(miisc);
468 }
469 error = mii_mediachg(mii);
470 STE_UNLOCK(sc);
471
472 return (error);
473 }
474
475 static void
476 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
477 {
478 struct ste_softc *sc;
479 struct mii_data *mii;
480
481 sc = ifp->if_softc;
482 mii = device_get_softc(sc->ste_miibus);
483
484 STE_LOCK(sc);
485 if ((ifp->if_flags & IFF_UP) == 0) {
486 STE_UNLOCK(sc);
487 return;
488 }
489 mii_pollstat(mii);
490 ifmr->ifm_active = mii->mii_media_active;
491 ifmr->ifm_status = mii->mii_media_status;
492 STE_UNLOCK(sc);
493 }
494
495 static void
496 ste_wait(struct ste_softc *sc)
497 {
498 int i;
499
500 for (i = 0; i < STE_TIMEOUT; i++) {
501 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
502 break;
503 DELAY(1);
504 }
505
506 if (i == STE_TIMEOUT)
507 device_printf(sc->ste_dev, "command never completed!\n");
508 }
509
510 /*
511 * The EEPROM is slow: give it time to come ready after issuing
512 * it a command.
513 */
514 static int
515 ste_eeprom_wait(struct ste_softc *sc)
516 {
517 int i;
518
519 DELAY(1000);
520
521 for (i = 0; i < 100; i++) {
522 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
523 DELAY(1000);
524 else
525 break;
526 }
527
528 if (i == 100) {
529 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
530 return (1);
531 }
532
533 return (0);
534 }
535
536 /*
537 * Read a sequence of words from the EEPROM. Note that ethernet address
538 * data is stored in the EEPROM in network byte order.
539 */
540 static int
541 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt)
542 {
543 int err = 0, i;
544
545 if (ste_eeprom_wait(sc))
546 return (1);
547
548 for (i = 0; i < cnt; i++) {
549 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
550 err = ste_eeprom_wait(sc);
551 if (err)
552 break;
553 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
554 dest++;
555 }
556
557 return (err ? 1 : 0);
558 }
559
560 static void
561 ste_rxfilter(struct ste_softc *sc)
562 {
563 struct ifnet *ifp;
564 struct ifmultiaddr *ifma;
565 uint32_t hashes[2] = { 0, 0 };
566 uint8_t rxcfg;
567 int h;
568
569 STE_LOCK_ASSERT(sc);
570
571 ifp = sc->ste_ifp;
572 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
573 rxcfg |= STE_RXMODE_UNICAST;
574 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
575 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
576 if (ifp->if_flags & IFF_BROADCAST)
577 rxcfg |= STE_RXMODE_BROADCAST;
578 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
579 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
580 rxcfg |= STE_RXMODE_ALLMULTI;
581 if ((ifp->if_flags & IFF_PROMISC) != 0)
582 rxcfg |= STE_RXMODE_PROMISC;
583 goto chipit;
584 }
585
586 rxcfg |= STE_RXMODE_MULTIHASH;
587 /* Now program new ones. */
588 IF_ADDR_LOCK(ifp);
589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
590 if (ifma->ifma_addr->sa_family != AF_LINK)
591 continue;
592 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
593 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
594 if (h < 32)
595 hashes[0] |= (1 << h);
596 else
597 hashes[1] |= (1 << (h - 32));
598 }
599 IF_ADDR_UNLOCK(ifp);
600
601 chipit:
602 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
603 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
604 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
605 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
606 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
607 CSR_READ_1(sc, STE_RX_MODE);
608 }
609
610 #ifdef DEVICE_POLLING
611 static poll_handler_t ste_poll, ste_poll_locked;
612
613 static void
614 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
615 {
616 struct ste_softc *sc = ifp->if_softc;
617
618 STE_LOCK(sc);
619 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
620 ste_poll_locked(ifp, cmd, count);
621 STE_UNLOCK(sc);
622 }
623
624 static void
625 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
626 {
627 struct ste_softc *sc = ifp->if_softc;
628
629 STE_LOCK_ASSERT(sc);
630
631 ste_rxeof(sc, count);
632 ste_txeof(sc);
633 ste_txeoc(sc);
634 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
635 ste_start_locked(ifp);
636
637 if (cmd == POLL_AND_CHECK_STATUS) {
638 uint16_t status;
639
640 status = CSR_READ_2(sc, STE_ISR_ACK);
641
642 if (status & STE_ISR_STATS_OFLOW)
643 ste_stats_update(sc);
644
645 if (status & STE_ISR_HOSTERR) {
646 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
647 ste_init_locked(sc);
648 }
649 }
650 }
651 #endif /* DEVICE_POLLING */
652
653 static void
654 ste_intr(void *xsc)
655 {
656 struct ste_softc *sc;
657 struct ifnet *ifp;
658 uint16_t intrs, status;
659
660 sc = xsc;
661 STE_LOCK(sc);
662 ifp = sc->ste_ifp;
663
664 #ifdef DEVICE_POLLING
665 if (ifp->if_capenable & IFCAP_POLLING) {
666 STE_UNLOCK(sc);
667 return;
668 }
669 #endif
670 /* Reading STE_ISR_ACK clears STE_IMR register. */
671 status = CSR_READ_2(sc, STE_ISR_ACK);
672 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
673 STE_UNLOCK(sc);
674 return;
675 }
676
677 intrs = STE_INTRS;
678 if (status == 0xFFFF || (status & intrs) == 0)
679 goto done;
680
681 if (sc->ste_int_rx_act > 0) {
682 status &= ~STE_ISR_RX_DMADONE;
683 intrs &= ~STE_IMR_RX_DMADONE;
684 }
685
686 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) {
687 ste_rxeof(sc, -1);
688 /*
689 * The controller has no ability to Rx interrupt
690 * moderation feature. Receiving 64 bytes frames
691 * from wire generates too many interrupts which in
692 * turn make system useless to process other useful
693 * things. Fortunately ST201 supports single shot
694 * timer so use the timer to implement Rx interrupt
695 * moderation in driver. This adds more register
696 * access but it greatly reduces number of Rx
697 * interrupts under high network load.
698 */
699 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
700 (sc->ste_int_rx_mod != 0)) {
701 if ((status & STE_ISR_RX_DMADONE) != 0) {
702 CSR_WRITE_2(sc, STE_COUNTDOWN,
703 STE_TIMER_USECS(sc->ste_int_rx_mod));
704 intrs &= ~STE_IMR_RX_DMADONE;
705 sc->ste_int_rx_act = 1;
706 } else {
707 intrs |= STE_IMR_RX_DMADONE;
708 sc->ste_int_rx_act = 0;
709 }
710 }
711 }
712 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
713 if ((status & STE_ISR_TX_DMADONE) != 0)
714 ste_txeof(sc);
715 if ((status & STE_ISR_TX_DONE) != 0)
716 ste_txeoc(sc);
717 if ((status & STE_ISR_STATS_OFLOW) != 0)
718 ste_stats_update(sc);
719 if ((status & STE_ISR_HOSTERR) != 0) {
720 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
721 ste_init_locked(sc);
722 STE_UNLOCK(sc);
723 return;
724 }
725 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
726 ste_start_locked(ifp);
727 done:
728 /* Re-enable interrupts */
729 CSR_WRITE_2(sc, STE_IMR, intrs);
730 }
731 STE_UNLOCK(sc);
732 }
733
734 /*
735 * A frame has been uploaded: pass the resulting mbuf chain up to
736 * the higher level protocols.
737 */
738 static void
739 ste_rxeof(struct ste_softc *sc, int count)
740 {
741 struct mbuf *m;
742 struct ifnet *ifp;
743 struct ste_chain_onefrag *cur_rx;
744 uint32_t rxstat;
745 int total_len, rx_npkts;
746
747 ifp = sc->ste_ifp;
748
749 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
750 sc->ste_cdata.ste_rx_list_map,
751 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
752
753 cur_rx = sc->ste_cdata.ste_rx_head;
754 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
755 cur_rx = cur_rx->ste_next) {
756 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
757 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
758 break;
759 #ifdef DEVICE_POLLING
760 if (ifp->if_capenable & IFCAP_POLLING) {
761 if (count == 0)
762 break;
763 count--;
764 }
765 #endif
766 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
767 break;
768 /*
769 * If an error occurs, update stats, clear the
770 * status word and leave the mbuf cluster in place:
771 * it should simply get re-used next time this descriptor
772 * comes up in the ring.
773 */
774 if (rxstat & STE_RXSTAT_FRAME_ERR) {
775 ifp->if_ierrors++;
776 cur_rx->ste_ptr->ste_status = 0;
777 continue;
778 }
779
780 /* No errors; receive the packet. */
781 m = cur_rx->ste_mbuf;
782 total_len = STE_RX_BYTES(rxstat);
783
784 /*
785 * Try to conjure up a new mbuf cluster. If that
786 * fails, it means we have an out of memory condition and
787 * should leave the buffer in place and continue. This will
788 * result in a lost packet, but there's little else we
789 * can do in this situation.
790 */
791 if (ste_newbuf(sc, cur_rx) != 0) {
792 ifp->if_iqdrops++;
793 cur_rx->ste_ptr->ste_status = 0;
794 continue;
795 }
796
797 m->m_pkthdr.rcvif = ifp;
798 m->m_pkthdr.len = m->m_len = total_len;
799
800 ifp->if_ipackets++;
801 STE_UNLOCK(sc);
802 (*ifp->if_input)(ifp, m);
803 STE_LOCK(sc);
804 }
805
806 if (rx_npkts > 0) {
807 sc->ste_cdata.ste_rx_head = cur_rx;
808 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
809 sc->ste_cdata.ste_rx_list_map,
810 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
811 }
812 }
813
814 static void
815 ste_txeoc(struct ste_softc *sc)
816 {
817 uint16_t txstat;
818 struct ifnet *ifp;
819
820 STE_LOCK_ASSERT(sc);
821
822 ifp = sc->ste_ifp;
823
824 /*
825 * STE_TX_STATUS register implements a queue of up to 31
826 * transmit status byte. Writing an arbitrary value to the
827 * register will advance the queue to the next transmit
828 * status byte. This means if driver does not read
829 * STE_TX_STATUS register after completing sending more
830 * than 31 frames the controller would be stalled so driver
831 * should re-wake the Tx MAC. This is the most severe
832 * limitation of ST201 based controller.
833 */
834 for (;;) {
835 txstat = CSR_READ_2(sc, STE_TX_STATUS);
836 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
837 break;
838 if ((txstat & (STE_TXSTATUS_UNDERRUN |
839 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
840 STE_TXSTATUS_STATSOFLOW)) != 0) {
841 ifp->if_oerrors++;
842 #ifdef STE_SHOW_TXERRORS
843 device_printf(sc->ste_dev, "TX error : 0x%b\n",
844 txstat & 0xFF, STE_ERR_BITS);
845 #endif
846 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
847 sc->ste_tx_thresh < STE_PACKET_SIZE) {
848 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
849 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
850 sc->ste_tx_thresh = STE_PACKET_SIZE;
851 device_printf(sc->ste_dev,
852 "TX underrun, increasing TX"
853 " start threshold to %d bytes\n",
854 sc->ste_tx_thresh);
855 /* Make sure to disable active DMA cycles. */
856 STE_SETBIT4(sc, STE_DMACTL,
857 STE_DMACTL_TXDMA_STALL);
858 ste_wait(sc);
859 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
860 ste_init_locked(sc);
861 break;
862 }
863 /* Restart Tx. */
864 ste_restart_tx(sc);
865 }
866 /*
867 * Advance to next status and ACK TxComplete
868 * interrupt. ST201 data sheet was wrong here, to
869 * get next Tx status, we have to write both
870 * STE_TX_STATUS and STE_TX_FRAMEID register.
871 * Otherwise controller returns the same status
872 * as well as not acknowledge Tx completion
873 * interrupt.
874 */
875 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
876 }
877 }
878
879 static void
880 ste_tick(void *arg)
881 {
882 struct ste_softc *sc;
883 struct mii_data *mii;
884
885 sc = (struct ste_softc *)arg;
886
887 STE_LOCK_ASSERT(sc);
888
889 mii = device_get_softc(sc->ste_miibus);
890 mii_tick(mii);
891 /*
892 * ukphy(4) does not seem to generate CB that reports
893 * resolved link state so if we know we lost a link,
894 * explicitly check the link state.
895 */
896 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
897 ste_miibus_statchg(sc->ste_dev);
898 /*
899 * Because we are not generating Tx completion
900 * interrupt for every frame, reclaim transmitted
901 * buffers here.
902 */
903 ste_txeof(sc);
904 ste_txeoc(sc);
905 ste_stats_update(sc);
906 ste_watchdog(sc);
907 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
908 }
909
910 static void
911 ste_txeof(struct ste_softc *sc)
912 {
913 struct ifnet *ifp;
914 struct ste_chain *cur_tx;
915 uint32_t txstat;
916 int idx;
917
918 STE_LOCK_ASSERT(sc);
919
920 ifp = sc->ste_ifp;
921 idx = sc->ste_cdata.ste_tx_cons;
922 if (idx == sc->ste_cdata.ste_tx_prod)
923 return;
924
925 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
926 sc->ste_cdata.ste_tx_list_map,
927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
928
929 while (idx != sc->ste_cdata.ste_tx_prod) {
930 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
931 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
932 if ((txstat & STE_TXCTL_DMADONE) == 0)
933 break;
934 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
935 BUS_DMASYNC_POSTWRITE);
936 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
937 KASSERT(cur_tx->ste_mbuf != NULL,
938 ("%s: freeing NULL mbuf!\n", __func__));
939 m_freem(cur_tx->ste_mbuf);
940 cur_tx->ste_mbuf = NULL;
941 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
942 ifp->if_opackets++;
943 sc->ste_cdata.ste_tx_cnt--;
944 STE_INC(idx, STE_TX_LIST_CNT);
945 }
946
947 sc->ste_cdata.ste_tx_cons = idx;
948 if (sc->ste_cdata.ste_tx_cnt == 0)
949 sc->ste_timer = 0;
950 }
951
952 static void
953 ste_stats_clear(struct ste_softc *sc)
954 {
955
956 STE_LOCK_ASSERT(sc);
957
958 /* Rx stats. */
959 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
960 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
961 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
962 CSR_READ_1(sc, STE_STAT_RX_BCAST);
963 CSR_READ_1(sc, STE_STAT_RX_MCAST);
964 CSR_READ_1(sc, STE_STAT_RX_LOST);
965 /* Tx stats. */
966 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
967 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
968 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
969 CSR_READ_1(sc, STE_STAT_TX_BCAST);
970 CSR_READ_1(sc, STE_STAT_TX_MCAST);
971 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
972 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
973 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
974 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
975 CSR_READ_1(sc, STE_STAT_TX_DEFER);
976 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
977 CSR_READ_1(sc, STE_STAT_TX_ABORT);
978 }
979
980 static void
981 ste_stats_update(struct ste_softc *sc)
982 {
983 struct ifnet *ifp;
984 struct ste_hw_stats *stats;
985 uint32_t val;
986
987 STE_LOCK_ASSERT(sc);
988
989 ifp = sc->ste_ifp;
990 stats = &sc->ste_stats;
991 /* Rx stats. */
992 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
993 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
994 val &= 0x000FFFFF;
995 stats->rx_bytes += val;
996 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
997 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
998 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
999 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
1000 /* Tx stats. */
1001 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
1002 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
1003 val &= 0x000FFFFF;
1004 stats->tx_bytes += val;
1005 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
1006 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
1007 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
1008 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
1009 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
1010 stats->tx_single_colls += val;
1011 ifp->if_collisions += val;
1012 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
1013 stats->tx_multi_colls += val;
1014 ifp->if_collisions += val;
1015 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
1016 stats->tx_late_colls += val;
1017 ifp->if_collisions += val;
1018 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
1019 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
1020 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
1021 }
1022
1023 /*
1024 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
1025 * IDs against our list and return a device name if we find a match.
1026 */
1027 static int
1028 ste_probe(device_t dev)
1029 {
1030 struct ste_type *t;
1031
1032 t = ste_devs;
1033
1034 while (t->ste_name != NULL) {
1035 if ((pci_get_vendor(dev) == t->ste_vid) &&
1036 (pci_get_device(dev) == t->ste_did)) {
1037 device_set_desc(dev, t->ste_name);
1038 return (BUS_PROBE_DEFAULT);
1039 }
1040 t++;
1041 }
1042
1043 return (ENXIO);
1044 }
1045
1046 /*
1047 * Attach the interface. Allocate softc structures, do ifmedia
1048 * setup and ethernet/BPF attach.
1049 */
1050 static int
1051 ste_attach(device_t dev)
1052 {
1053 struct ste_softc *sc;
1054 struct ifnet *ifp;
1055 uint16_t eaddr[ETHER_ADDR_LEN / 2];
1056 int error = 0, pmc, rid;
1057
1058 sc = device_get_softc(dev);
1059 sc->ste_dev = dev;
1060
1061 /*
1062 * Only use one PHY since this chip reports multiple
1063 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1064 * it is at 0 & 1. It is rev 0x12.
1065 */
1066 if (pci_get_vendor(dev) == DL_VENDORID &&
1067 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1068 pci_get_revid(dev) == 0x12 )
1069 sc->ste_flags |= STE_FLAG_ONE_PHY;
1070
1071 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1072 MTX_DEF);
1073 /*
1074 * Map control/status registers.
1075 */
1076 pci_enable_busmaster(dev);
1077
1078 /* Prefer memory space register mapping over IO space. */
1079 sc->ste_res_id = PCIR_BAR(1);
1080 sc->ste_res_type = SYS_RES_MEMORY;
1081 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1082 &sc->ste_res_id, RF_ACTIVE);
1083 if (sc->ste_res == NULL) {
1084 sc->ste_res_id = PCIR_BAR(0);
1085 sc->ste_res_type = SYS_RES_IOPORT;
1086 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1087 &sc->ste_res_id, RF_ACTIVE);
1088 }
1089 if (sc->ste_res == NULL) {
1090 device_printf(dev, "couldn't map ports/memory\n");
1091 error = ENXIO;
1092 goto fail;
1093 }
1094
1095 /* Allocate interrupt */
1096 rid = 0;
1097 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1098 RF_SHAREABLE | RF_ACTIVE);
1099
1100 if (sc->ste_irq == NULL) {
1101 device_printf(dev, "couldn't map interrupt\n");
1102 error = ENXIO;
1103 goto fail;
1104 }
1105
1106 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
1107
1108 /* Reset the adapter. */
1109 ste_reset(sc);
1110
1111 /*
1112 * Get station address from the EEPROM.
1113 */
1114 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) {
1115 device_printf(dev, "failed to read station address\n");
1116 error = ENXIO;;
1117 goto fail;
1118 }
1119 ste_sysctl_node(sc);
1120
1121 if ((error = ste_dma_alloc(sc)) != 0)
1122 goto fail;
1123
1124 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1125 if (ifp == NULL) {
1126 device_printf(dev, "can not if_alloc()\n");
1127 error = ENOSPC;
1128 goto fail;
1129 }
1130
1131 /* Do MII setup. */
1132 if (mii_phy_probe(dev, &sc->ste_miibus,
1133 ste_ifmedia_upd, ste_ifmedia_sts)) {
1134 device_printf(dev, "MII without any phy!\n");
1135 error = ENXIO;
1136 goto fail;
1137 }
1138
1139 ifp->if_softc = sc;
1140 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1141 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1142 ifp->if_ioctl = ste_ioctl;
1143 ifp->if_start = ste_start;
1144 ifp->if_init = ste_init;
1145 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1146 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1147 IFQ_SET_READY(&ifp->if_snd);
1148
1149 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1150
1151 /*
1152 * Call MI attach routine.
1153 */
1154 ether_ifattach(ifp, (uint8_t *)eaddr);
1155
1156 /*
1157 * Tell the upper layer(s) we support long frames.
1158 */
1159 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1160 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1161 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
1162 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1163 ifp->if_capenable = ifp->if_capabilities;
1164 #ifdef DEVICE_POLLING
1165 ifp->if_capabilities |= IFCAP_POLLING;
1166 #endif
1167
1168 /* Hook interrupt last to avoid having to lock softc */
1169 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1170 NULL, ste_intr, sc, &sc->ste_intrhand);
1171
1172 if (error) {
1173 device_printf(dev, "couldn't set up irq\n");
1174 ether_ifdetach(ifp);
1175 goto fail;
1176 }
1177
1178 fail:
1179 if (error)
1180 ste_detach(dev);
1181
1182 return (error);
1183 }
1184
1185 /*
1186 * Shutdown hardware and free up resources. This can be called any
1187 * time after the mutex has been initialized. It is called in both
1188 * the error case in attach and the normal detach case so it needs
1189 * to be careful about only freeing resources that have actually been
1190 * allocated.
1191 */
1192 static int
1193 ste_detach(device_t dev)
1194 {
1195 struct ste_softc *sc;
1196 struct ifnet *ifp;
1197
1198 sc = device_get_softc(dev);
1199 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1200 ifp = sc->ste_ifp;
1201
1202 #ifdef DEVICE_POLLING
1203 if (ifp->if_capenable & IFCAP_POLLING)
1204 ether_poll_deregister(ifp);
1205 #endif
1206
1207 /* These should only be active if attach succeeded */
1208 if (device_is_attached(dev)) {
1209 ether_ifdetach(ifp);
1210 STE_LOCK(sc);
1211 ste_stop(sc);
1212 STE_UNLOCK(sc);
1213 callout_drain(&sc->ste_callout);
1214 }
1215 if (sc->ste_miibus)
1216 device_delete_child(dev, sc->ste_miibus);
1217 bus_generic_detach(dev);
1218
1219 if (sc->ste_intrhand)
1220 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1221 if (sc->ste_irq)
1222 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1223 if (sc->ste_res)
1224 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1225 sc->ste_res);
1226
1227 if (ifp)
1228 if_free(ifp);
1229
1230 ste_dma_free(sc);
1231 mtx_destroy(&sc->ste_mtx);
1232
1233 return (0);
1234 }
1235
1236 struct ste_dmamap_arg {
1237 bus_addr_t ste_busaddr;
1238 };
1239
1240 static void
1241 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1242 {
1243 struct ste_dmamap_arg *ctx;
1244
1245 if (error != 0)
1246 return;
1247
1248 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1249
1250 ctx = (struct ste_dmamap_arg *)arg;
1251 ctx->ste_busaddr = segs[0].ds_addr;
1252 }
1253
1254 static int
1255 ste_dma_alloc(struct ste_softc *sc)
1256 {
1257 struct ste_chain *txc;
1258 struct ste_chain_onefrag *rxc;
1259 struct ste_dmamap_arg ctx;
1260 int error, i;
1261
1262 /* Create parent DMA tag. */
1263 error = bus_dma_tag_create(
1264 bus_get_dma_tag(sc->ste_dev), /* parent */
1265 1, 0, /* alignment, boundary */
1266 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1267 BUS_SPACE_MAXADDR, /* highaddr */
1268 NULL, NULL, /* filter, filterarg */
1269 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1270 0, /* nsegments */
1271 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1272 0, /* flags */
1273 NULL, NULL, /* lockfunc, lockarg */
1274 &sc->ste_cdata.ste_parent_tag);
1275 if (error != 0) {
1276 device_printf(sc->ste_dev,
1277 "could not create parent DMA tag.\n");
1278 goto fail;
1279 }
1280
1281 /* Create DMA tag for Tx descriptor list. */
1282 error = bus_dma_tag_create(
1283 sc->ste_cdata.ste_parent_tag, /* parent */
1284 STE_DESC_ALIGN, 0, /* alignment, boundary */
1285 BUS_SPACE_MAXADDR, /* lowaddr */
1286 BUS_SPACE_MAXADDR, /* highaddr */
1287 NULL, NULL, /* filter, filterarg */
1288 STE_TX_LIST_SZ, /* maxsize */
1289 1, /* nsegments */
1290 STE_TX_LIST_SZ, /* maxsegsize */
1291 0, /* flags */
1292 NULL, NULL, /* lockfunc, lockarg */
1293 &sc->ste_cdata.ste_tx_list_tag);
1294 if (error != 0) {
1295 device_printf(sc->ste_dev,
1296 "could not create Tx list DMA tag.\n");
1297 goto fail;
1298 }
1299
1300 /* Create DMA tag for Rx descriptor list. */
1301 error = bus_dma_tag_create(
1302 sc->ste_cdata.ste_parent_tag, /* parent */
1303 STE_DESC_ALIGN, 0, /* alignment, boundary */
1304 BUS_SPACE_MAXADDR, /* lowaddr */
1305 BUS_SPACE_MAXADDR, /* highaddr */
1306 NULL, NULL, /* filter, filterarg */
1307 STE_RX_LIST_SZ, /* maxsize */
1308 1, /* nsegments */
1309 STE_RX_LIST_SZ, /* maxsegsize */
1310 0, /* flags */
1311 NULL, NULL, /* lockfunc, lockarg */
1312 &sc->ste_cdata.ste_rx_list_tag);
1313 if (error != 0) {
1314 device_printf(sc->ste_dev,
1315 "could not create Rx list DMA tag.\n");
1316 goto fail;
1317 }
1318
1319 /* Create DMA tag for Tx buffers. */
1320 error = bus_dma_tag_create(
1321 sc->ste_cdata.ste_parent_tag, /* parent */
1322 1, 0, /* alignment, boundary */
1323 BUS_SPACE_MAXADDR, /* lowaddr */
1324 BUS_SPACE_MAXADDR, /* highaddr */
1325 NULL, NULL, /* filter, filterarg */
1326 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1327 STE_MAXFRAGS, /* nsegments */
1328 MCLBYTES, /* maxsegsize */
1329 0, /* flags */
1330 NULL, NULL, /* lockfunc, lockarg */
1331 &sc->ste_cdata.ste_tx_tag);
1332 if (error != 0) {
1333 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1334 goto fail;
1335 }
1336
1337 /* Create DMA tag for Rx buffers. */
1338 error = bus_dma_tag_create(
1339 sc->ste_cdata.ste_parent_tag, /* parent */
1340 1, 0, /* alignment, boundary */
1341 BUS_SPACE_MAXADDR, /* lowaddr */
1342 BUS_SPACE_MAXADDR, /* highaddr */
1343 NULL, NULL, /* filter, filterarg */
1344 MCLBYTES, /* maxsize */
1345 1, /* nsegments */
1346 MCLBYTES, /* maxsegsize */
1347 0, /* flags */
1348 NULL, NULL, /* lockfunc, lockarg */
1349 &sc->ste_cdata.ste_rx_tag);
1350 if (error != 0) {
1351 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1352 goto fail;
1353 }
1354
1355 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1356 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1357 (void **)&sc->ste_ldata.ste_tx_list,
1358 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1359 &sc->ste_cdata.ste_tx_list_map);
1360 if (error != 0) {
1361 device_printf(sc->ste_dev,
1362 "could not allocate DMA'able memory for Tx list.\n");
1363 goto fail;
1364 }
1365 ctx.ste_busaddr = 0;
1366 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1367 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1368 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1369 if (error != 0 || ctx.ste_busaddr == 0) {
1370 device_printf(sc->ste_dev,
1371 "could not load DMA'able memory for Tx list.\n");
1372 goto fail;
1373 }
1374 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1375
1376 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1377 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1378 (void **)&sc->ste_ldata.ste_rx_list,
1379 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1380 &sc->ste_cdata.ste_rx_list_map);
1381 if (error != 0) {
1382 device_printf(sc->ste_dev,
1383 "could not allocate DMA'able memory for Rx list.\n");
1384 goto fail;
1385 }
1386 ctx.ste_busaddr = 0;
1387 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1388 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1389 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1390 if (error != 0 || ctx.ste_busaddr == 0) {
1391 device_printf(sc->ste_dev,
1392 "could not load DMA'able memory for Rx list.\n");
1393 goto fail;
1394 }
1395 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1396
1397 /* Create DMA maps for Tx buffers. */
1398 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1399 txc = &sc->ste_cdata.ste_tx_chain[i];
1400 txc->ste_ptr = NULL;
1401 txc->ste_mbuf = NULL;
1402 txc->ste_next = NULL;
1403 txc->ste_phys = 0;
1404 txc->ste_map = NULL;
1405 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1406 &txc->ste_map);
1407 if (error != 0) {
1408 device_printf(sc->ste_dev,
1409 "could not create Tx dmamap.\n");
1410 goto fail;
1411 }
1412 }
1413 /* Create DMA maps for Rx buffers. */
1414 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1415 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1416 device_printf(sc->ste_dev,
1417 "could not create spare Rx dmamap.\n");
1418 goto fail;
1419 }
1420 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1421 rxc = &sc->ste_cdata.ste_rx_chain[i];
1422 rxc->ste_ptr = NULL;
1423 rxc->ste_mbuf = NULL;
1424 rxc->ste_next = NULL;
1425 rxc->ste_map = NULL;
1426 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1427 &rxc->ste_map);
1428 if (error != 0) {
1429 device_printf(sc->ste_dev,
1430 "could not create Rx dmamap.\n");
1431 goto fail;
1432 }
1433 }
1434
1435 fail:
1436 return (error);
1437 }
1438
1439 static void
1440 ste_dma_free(struct ste_softc *sc)
1441 {
1442 struct ste_chain *txc;
1443 struct ste_chain_onefrag *rxc;
1444 int i;
1445
1446 /* Tx buffers. */
1447 if (sc->ste_cdata.ste_tx_tag != NULL) {
1448 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1449 txc = &sc->ste_cdata.ste_tx_chain[i];
1450 if (txc->ste_map != NULL) {
1451 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1452 txc->ste_map);
1453 txc->ste_map = NULL;
1454 }
1455 }
1456 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1457 sc->ste_cdata.ste_tx_tag = NULL;
1458 }
1459 /* Rx buffers. */
1460 if (sc->ste_cdata.ste_rx_tag != NULL) {
1461 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1462 rxc = &sc->ste_cdata.ste_rx_chain[i];
1463 if (rxc->ste_map != NULL) {
1464 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1465 rxc->ste_map);
1466 rxc->ste_map = NULL;
1467 }
1468 }
1469 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1470 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1471 sc->ste_cdata.ste_rx_sparemap);
1472 sc->ste_cdata.ste_rx_sparemap = NULL;
1473 }
1474 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1475 sc->ste_cdata.ste_rx_tag = NULL;
1476 }
1477 /* Tx descriptor list. */
1478 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1479 if (sc->ste_cdata.ste_tx_list_map != NULL)
1480 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1481 sc->ste_cdata.ste_tx_list_map);
1482 if (sc->ste_cdata.ste_tx_list_map != NULL &&
1483 sc->ste_ldata.ste_tx_list != NULL)
1484 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1485 sc->ste_ldata.ste_tx_list,
1486 sc->ste_cdata.ste_tx_list_map);
1487 sc->ste_ldata.ste_tx_list = NULL;
1488 sc->ste_cdata.ste_tx_list_map = NULL;
1489 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1490 sc->ste_cdata.ste_tx_list_tag = NULL;
1491 }
1492 /* Rx descriptor list. */
1493 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1494 if (sc->ste_cdata.ste_rx_list_map != NULL)
1495 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1496 sc->ste_cdata.ste_rx_list_map);
1497 if (sc->ste_cdata.ste_rx_list_map != NULL &&
1498 sc->ste_ldata.ste_rx_list != NULL)
1499 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1500 sc->ste_ldata.ste_rx_list,
1501 sc->ste_cdata.ste_rx_list_map);
1502 sc->ste_ldata.ste_rx_list = NULL;
1503 sc->ste_cdata.ste_rx_list_map = NULL;
1504 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1505 sc->ste_cdata.ste_rx_list_tag = NULL;
1506 }
1507 if (sc->ste_cdata.ste_parent_tag != NULL) {
1508 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1509 sc->ste_cdata.ste_parent_tag = NULL;
1510 }
1511 }
1512
1513 static int
1514 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1515 {
1516 struct mbuf *m;
1517 bus_dma_segment_t segs[1];
1518 bus_dmamap_t map;
1519 int error, nsegs;
1520
1521 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1522 if (m == NULL)
1523 return (ENOBUFS);
1524 m->m_len = m->m_pkthdr.len = MCLBYTES;
1525 m_adj(m, ETHER_ALIGN);
1526
1527 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1528 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1529 m_freem(m);
1530 return (error);
1531 }
1532 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1533
1534 if (rxc->ste_mbuf != NULL) {
1535 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1536 BUS_DMASYNC_POSTREAD);
1537 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1538 }
1539 map = rxc->ste_map;
1540 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1541 sc->ste_cdata.ste_rx_sparemap = map;
1542 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1543 BUS_DMASYNC_PREREAD);
1544 rxc->ste_mbuf = m;
1545 rxc->ste_ptr->ste_status = 0;
1546 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1547 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1548 STE_FRAG_LAST);
1549 return (0);
1550 }
1551
1552 static int
1553 ste_init_rx_list(struct ste_softc *sc)
1554 {
1555 struct ste_chain_data *cd;
1556 struct ste_list_data *ld;
1557 int error, i;
1558
1559 sc->ste_int_rx_act = 0;
1560 cd = &sc->ste_cdata;
1561 ld = &sc->ste_ldata;
1562 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1563 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1564 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1565 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1566 if (error != 0)
1567 return (error);
1568 if (i == (STE_RX_LIST_CNT - 1)) {
1569 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1570 ld->ste_rx_list[i].ste_next =
1571 htole32(ld->ste_rx_list_paddr +
1572 (sizeof(struct ste_desc_onefrag) * 0));
1573 } else {
1574 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1575 ld->ste_rx_list[i].ste_next =
1576 htole32(ld->ste_rx_list_paddr +
1577 (sizeof(struct ste_desc_onefrag) * (i + 1)));
1578 }
1579 }
1580
1581 cd->ste_rx_head = &cd->ste_rx_chain[0];
1582 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1583 sc->ste_cdata.ste_rx_list_map,
1584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1585
1586 return (0);
1587 }
1588
1589 static void
1590 ste_init_tx_list(struct ste_softc *sc)
1591 {
1592 struct ste_chain_data *cd;
1593 struct ste_list_data *ld;
1594 int i;
1595
1596 cd = &sc->ste_cdata;
1597 ld = &sc->ste_ldata;
1598 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1599 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1600 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1601 cd->ste_tx_chain[i].ste_mbuf = NULL;
1602 if (i == (STE_TX_LIST_CNT - 1)) {
1603 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1604 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1605 ld->ste_tx_list_paddr +
1606 (sizeof(struct ste_desc) * 0)));
1607 } else {
1608 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1609 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1610 ld->ste_tx_list_paddr +
1611 (sizeof(struct ste_desc) * (i + 1))));
1612 }
1613 }
1614
1615 cd->ste_last_tx = NULL;
1616 cd->ste_tx_prod = 0;
1617 cd->ste_tx_cons = 0;
1618 cd->ste_tx_cnt = 0;
1619
1620 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1621 sc->ste_cdata.ste_tx_list_map,
1622 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1623 }
1624
1625 static void
1626 ste_init(void *xsc)
1627 {
1628 struct ste_softc *sc;
1629
1630 sc = xsc;
1631 STE_LOCK(sc);
1632 ste_init_locked(sc);
1633 STE_UNLOCK(sc);
1634 }
1635
1636 static void
1637 ste_init_locked(struct ste_softc *sc)
1638 {
1639 struct ifnet *ifp;
1640 struct mii_data *mii;
1641 uint8_t val;
1642 int i;
1643
1644 STE_LOCK_ASSERT(sc);
1645 ifp = sc->ste_ifp;
1646 mii = device_get_softc(sc->ste_miibus);
1647
1648 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1649 return;
1650
1651 ste_stop(sc);
1652 /* Reset the chip to a known state. */
1653 ste_reset(sc);
1654
1655 /* Init our MAC address */
1656 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1657 CSR_WRITE_2(sc, STE_PAR0 + i,
1658 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1659 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1660 }
1661
1662 /* Init RX list */
1663 if (ste_init_rx_list(sc) != 0) {
1664 device_printf(sc->ste_dev,
1665 "initialization failed: no memory for RX buffers\n");
1666 ste_stop(sc);
1667 return;
1668 }
1669
1670 /* Set RX polling interval */
1671 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1672
1673 /* Init TX descriptors */
1674 ste_init_tx_list(sc);
1675
1676 /* Clear and disable WOL. */
1677 val = CSR_READ_1(sc, STE_WAKE_EVENT);
1678 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
1679 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
1680 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1681
1682 /* Set the TX freethresh value */
1683 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1684
1685 /* Set the TX start threshold for best performance. */
1686 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1687
1688 /* Set the TX reclaim threshold. */
1689 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1690
1691 /* Accept VLAN length packets */
1692 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1693
1694 /* Set up the RX filter. */
1695 ste_rxfilter(sc);
1696
1697 /* Load the address of the RX list. */
1698 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1699 ste_wait(sc);
1700 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1701 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1702 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1703 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1704
1705 /* Set TX polling interval(defer until we TX first packet). */
1706 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1707
1708 /* Load address of the TX list */
1709 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1710 ste_wait(sc);
1711 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1712 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1713 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1714 ste_wait(sc);
1715 /* Select 3.2us timer. */
1716 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED |
1717 STE_DMACTL_COUNTDOWN_MODE);
1718
1719 /* Enable receiver and transmitter */
1720 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1721 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1722 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1723 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1724
1725 /* Enable stats counters. */
1726 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1727 /* Clear stats counters. */
1728 ste_stats_clear(sc);
1729
1730 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1731 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1732 #ifdef DEVICE_POLLING
1733 /* Disable interrupts if we are polling. */
1734 if (ifp->if_capenable & IFCAP_POLLING)
1735 CSR_WRITE_2(sc, STE_IMR, 0);
1736 else
1737 #endif
1738 /* Enable interrupts. */
1739 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1740
1741 sc->ste_flags &= ~STE_FLAG_LINK;
1742 /* Switch to the current media. */
1743 mii_mediachg(mii);
1744
1745 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1746 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1747
1748 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1749 }
1750
1751 static void
1752 ste_stop(struct ste_softc *sc)
1753 {
1754 struct ifnet *ifp;
1755 struct ste_chain_onefrag *cur_rx;
1756 struct ste_chain *cur_tx;
1757 uint32_t val;
1758 int i;
1759
1760 STE_LOCK_ASSERT(sc);
1761 ifp = sc->ste_ifp;
1762
1763 callout_stop(&sc->ste_callout);
1764 sc->ste_timer = 0;
1765 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1766
1767 CSR_WRITE_2(sc, STE_IMR, 0);
1768 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1769 /* Stop pending DMA. */
1770 val = CSR_READ_4(sc, STE_DMACTL);
1771 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1772 CSR_WRITE_4(sc, STE_DMACTL, val);
1773 ste_wait(sc);
1774 /* Disable auto-polling. */
1775 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1776 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1777 /* Nullify DMA address to stop any further DMA. */
1778 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1779 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1780 /* Stop TX/RX MAC. */
1781 val = CSR_READ_2(sc, STE_MACCTL1);
1782 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1783 STE_MACCTL1_STATS_DISABLE;
1784 CSR_WRITE_2(sc, STE_MACCTL1, val);
1785 for (i = 0; i < STE_TIMEOUT; i++) {
1786 DELAY(10);
1787 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1788 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1789 break;
1790 }
1791 if (i == STE_TIMEOUT)
1792 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1793 /* Acknowledge any pending interrupts. */
1794 CSR_READ_2(sc, STE_ISR_ACK);
1795 ste_stats_update(sc);
1796
1797 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1798 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1799 if (cur_rx->ste_mbuf != NULL) {
1800 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1801 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1802 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1803 cur_rx->ste_map);
1804 m_freem(cur_rx->ste_mbuf);
1805 cur_rx->ste_mbuf = NULL;
1806 }
1807 }
1808
1809 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1810 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1811 if (cur_tx->ste_mbuf != NULL) {
1812 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1813 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1814 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1815 cur_tx->ste_map);
1816 m_freem(cur_tx->ste_mbuf);
1817 cur_tx->ste_mbuf = NULL;
1818 }
1819 }
1820 }
1821
1822 static void
1823 ste_reset(struct ste_softc *sc)
1824 {
1825 uint32_t ctl;
1826 int i;
1827
1828 ctl = CSR_READ_4(sc, STE_ASICCTL);
1829 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1830 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1831 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1832 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1833 STE_ASICCTL_EXTRESET_RESET;
1834 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1835 CSR_READ_4(sc, STE_ASICCTL);
1836 /*
1837 * Due to the need of accessing EEPROM controller can take
1838 * up to 1ms to complete the global reset.
1839 */
1840 DELAY(1000);
1841
1842 for (i = 0; i < STE_TIMEOUT; i++) {
1843 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1844 break;
1845 DELAY(10);
1846 }
1847
1848 if (i == STE_TIMEOUT)
1849 device_printf(sc->ste_dev, "global reset never completed\n");
1850 }
1851
1852 static void
1853 ste_restart_tx(struct ste_softc *sc)
1854 {
1855 uint16_t mac;
1856 int i;
1857
1858 for (i = 0; i < STE_TIMEOUT; i++) {
1859 mac = CSR_READ_2(sc, STE_MACCTL1);
1860 mac |= STE_MACCTL1_TX_ENABLE;
1861 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1862 mac = CSR_READ_2(sc, STE_MACCTL1);
1863 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1864 break;
1865 DELAY(10);
1866 }
1867
1868 if (i == STE_TIMEOUT)
1869 device_printf(sc->ste_dev, "starting Tx failed");
1870 }
1871
1872 static int
1873 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1874 {
1875 struct ste_softc *sc;
1876 struct ifreq *ifr;
1877 struct mii_data *mii;
1878 int error = 0, mask;
1879
1880 sc = ifp->if_softc;
1881 ifr = (struct ifreq *)data;
1882
1883 switch (command) {
1884 case SIOCSIFFLAGS:
1885 STE_LOCK(sc);
1886 if ((ifp->if_flags & IFF_UP) != 0) {
1887 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1888 ((ifp->if_flags ^ sc->ste_if_flags) &
1889 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1890 ste_rxfilter(sc);
1891 else
1892 ste_init_locked(sc);
1893 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1894 ste_stop(sc);
1895 sc->ste_if_flags = ifp->if_flags;
1896 STE_UNLOCK(sc);
1897 break;
1898 case SIOCADDMULTI:
1899 case SIOCDELMULTI:
1900 STE_LOCK(sc);
1901 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1902 ste_rxfilter(sc);
1903 STE_UNLOCK(sc);
1904 break;
1905 case SIOCGIFMEDIA:
1906 case SIOCSIFMEDIA:
1907 mii = device_get_softc(sc->ste_miibus);
1908 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1909 break;
1910 case SIOCSIFCAP:
1911 STE_LOCK(sc);
1912 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1913 #ifdef DEVICE_POLLING
1914 if ((mask & IFCAP_POLLING) != 0 &&
1915 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
1916 ifp->if_capenable ^= IFCAP_POLLING;
1917 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
1918 error = ether_poll_register(ste_poll, ifp);
1919 if (error != 0) {
1920 STE_UNLOCK(sc);
1921 break;
1922 }
1923 /* Disable interrupts. */
1924 CSR_WRITE_2(sc, STE_IMR, 0);
1925 } else {
1926 error = ether_poll_deregister(ifp);
1927 /* Enable interrupts. */
1928 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1929 }
1930 }
1931 #endif /* DEVICE_POLLING */
1932 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1933 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1934 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1935 STE_UNLOCK(sc);
1936 break;
1937 default:
1938 error = ether_ioctl(ifp, command, data);
1939 break;
1940 }
1941
1942 return (error);
1943 }
1944
1945 static int
1946 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1947 {
1948 struct ste_frag *frag;
1949 struct mbuf *m;
1950 struct ste_desc *desc;
1951 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1952 int error, i, nsegs;
1953
1954 STE_LOCK_ASSERT(sc);
1955 M_ASSERTPKTHDR((*m_head));
1956
1957 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1958 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1959 if (error == EFBIG) {
1960 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS);
1961 if (m == NULL) {
1962 m_freem(*m_head);
1963 *m_head = NULL;
1964 return (ENOMEM);
1965 }
1966 *m_head = m;
1967 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1968 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1969 if (error != 0) {
1970 m_freem(*m_head);
1971 *m_head = NULL;
1972 return (error);
1973 }
1974 } else if (error != 0)
1975 return (error);
1976 if (nsegs == 0) {
1977 m_freem(*m_head);
1978 *m_head = NULL;
1979 return (EIO);
1980 }
1981 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1982 BUS_DMASYNC_PREWRITE);
1983
1984 desc = txc->ste_ptr;
1985 for (i = 0; i < nsegs; i++) {
1986 frag = &desc->ste_frags[i];
1987 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1988 frag->ste_len = htole32(txsegs[i].ds_len);
1989 }
1990 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1991 /*
1992 * Because we use Tx polling we can't chain multiple
1993 * Tx descriptors here. Otherwise we race with controller.
1994 */
1995 desc->ste_next = 0;
1996 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
1997 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
1998 STE_TXCTL_DMAINTR);
1999 else
2000 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
2001 txc->ste_mbuf = *m_head;
2002 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
2003 sc->ste_cdata.ste_tx_cnt++;
2004
2005 return (0);
2006 }
2007
2008 static void
2009 ste_start(struct ifnet *ifp)
2010 {
2011 struct ste_softc *sc;
2012
2013 sc = ifp->if_softc;
2014 STE_LOCK(sc);
2015 ste_start_locked(ifp);
2016 STE_UNLOCK(sc);
2017 }
2018
2019 static void
2020 ste_start_locked(struct ifnet *ifp)
2021 {
2022 struct ste_softc *sc;
2023 struct ste_chain *cur_tx;
2024 struct mbuf *m_head = NULL;
2025 int enq;
2026
2027 sc = ifp->if_softc;
2028 STE_LOCK_ASSERT(sc);
2029
2030 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2031 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
2032 return;
2033
2034 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
2035 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
2036 /*
2037 * Controller may have cached copy of the last used
2038 * next ptr so we have to reserve one TFD to avoid
2039 * TFD overruns.
2040 */
2041 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2042 break;
2043 }
2044 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2045 if (m_head == NULL)
2046 break;
2047 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
2048 if (ste_encap(sc, &m_head, cur_tx) != 0) {
2049 if (m_head == NULL)
2050 break;
2051 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2052 break;
2053 }
2054 if (sc->ste_cdata.ste_last_tx == NULL) {
2055 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2056 sc->ste_cdata.ste_tx_list_map,
2057 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2058 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
2059 ste_wait(sc);
2060 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
2061 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
2062 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
2063 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
2064 ste_wait(sc);
2065 } else {
2066 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
2067 sc->ste_cdata.ste_last_tx->ste_phys;
2068 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2069 sc->ste_cdata.ste_tx_list_map,
2070 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2071 }
2072 sc->ste_cdata.ste_last_tx = cur_tx;
2073
2074 enq++;
2075 /*
2076 * If there's a BPF listener, bounce a copy of this frame
2077 * to him.
2078 */
2079 BPF_MTAP(ifp, m_head);
2080 }
2081
2082 if (enq > 0)
2083 sc->ste_timer = STE_TX_TIMEOUT;
2084 }
2085
2086 static void
2087 ste_watchdog(struct ste_softc *sc)
2088 {
2089 struct ifnet *ifp;
2090
2091 ifp = sc->ste_ifp;
2092 STE_LOCK_ASSERT(sc);
2093
2094 if (sc->ste_timer == 0 || --sc->ste_timer)
2095 return;
2096
2097 ifp->if_oerrors++;
2098 if_printf(ifp, "watchdog timeout\n");
2099
2100 ste_txeof(sc);
2101 ste_txeoc(sc);
2102 ste_rxeof(sc, -1);
2103 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2104 ste_init_locked(sc);
2105
2106 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2107 ste_start_locked(ifp);
2108 }
2109
2110 static int
2111 ste_shutdown(device_t dev)
2112 {
2113
2114 return (ste_suspend(dev));
2115 }
2116
2117 static int
2118 ste_suspend(device_t dev)
2119 {
2120 struct ste_softc *sc;
2121
2122 sc = device_get_softc(dev);
2123
2124 STE_LOCK(sc);
2125 ste_stop(sc);
2126 ste_setwol(sc);
2127 STE_UNLOCK(sc);
2128
2129 return (0);
2130 }
2131
2132 static int
2133 ste_resume(device_t dev)
2134 {
2135 struct ste_softc *sc;
2136 struct ifnet *ifp;
2137 int pmc;
2138 uint16_t pmstat;
2139
2140 sc = device_get_softc(dev);
2141 STE_LOCK(sc);
2142 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
2143 /* Disable PME and clear PME status. */
2144 pmstat = pci_read_config(sc->ste_dev,
2145 pmc + PCIR_POWER_STATUS, 2);
2146 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2147 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2148 pci_write_config(sc->ste_dev,
2149 pmc + PCIR_POWER_STATUS, pmstat, 2);
2150 }
2151 }
2152 ifp = sc->ste_ifp;
2153 if ((ifp->if_flags & IFF_UP) != 0) {
2154 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2155 ste_init_locked(sc);
2156 }
2157 STE_UNLOCK(sc);
2158
2159 return (0);
2160 }
2161
2162 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2163 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2164 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2165 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2166
2167 static void
2168 ste_sysctl_node(struct ste_softc *sc)
2169 {
2170 struct sysctl_ctx_list *ctx;
2171 struct sysctl_oid_list *child, *parent;
2172 struct sysctl_oid *tree;
2173 struct ste_hw_stats *stats;
2174
2175 stats = &sc->ste_stats;
2176 ctx = device_get_sysctl_ctx(sc->ste_dev);
2177 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2178
2179 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod",
2180 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation");
2181 /* Pull in device tunables. */
2182 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT;
2183 resource_int_value(device_get_name(sc->ste_dev),
2184 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod);
2185
2186 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2187 NULL, "STE statistics");
2188 parent = SYSCTL_CHILDREN(tree);
2189
2190 /* Rx statistics. */
2191 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2192 NULL, "Rx MAC statistics");
2193 child = SYSCTL_CHILDREN(tree);
2194 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2195 &stats->rx_bytes, "Good octets");
2196 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2197 &stats->rx_frames, "Good frames");
2198 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2199 &stats->rx_bcast_frames, "Good broadcast frames");
2200 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2201 &stats->rx_mcast_frames, "Good multicast frames");
2202 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2203 &stats->rx_lost_frames, "Lost frames");
2204
2205 /* Tx statistics. */
2206 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2207 NULL, "Tx MAC statistics");
2208 child = SYSCTL_CHILDREN(tree);
2209 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2210 &stats->tx_bytes, "Good octets");
2211 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2212 &stats->tx_frames, "Good frames");
2213 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2214 &stats->tx_bcast_frames, "Good broadcast frames");
2215 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2216 &stats->tx_mcast_frames, "Good multicast frames");
2217 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2218 &stats->tx_carrsense_errs, "Carrier sense errors");
2219 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2220 &stats->tx_single_colls, "Single collisions");
2221 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2222 &stats->tx_multi_colls, "Multiple collisions");
2223 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2224 &stats->tx_late_colls, "Late collisions");
2225 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2226 &stats->tx_frames_defered, "Frames with deferrals");
2227 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2228 &stats->tx_excess_defers, "Frames with excessive derferrals");
2229 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2230 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2231 }
2232
2233 #undef STE_SYSCTL_STAT_ADD32
2234 #undef STE_SYSCTL_STAT_ADD64
2235
2236 static void
2237 ste_setwol(struct ste_softc *sc)
2238 {
2239 struct ifnet *ifp;
2240 uint16_t pmstat;
2241 uint8_t val;
2242 int pmc;
2243
2244 STE_LOCK_ASSERT(sc);
2245
2246 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
2247 /* Disable WOL. */
2248 CSR_READ_1(sc, STE_WAKE_EVENT);
2249 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
2250 return;
2251 }
2252
2253 ifp = sc->ste_ifp;
2254 val = CSR_READ_1(sc, STE_WAKE_EVENT);
2255 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
2256 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
2257 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2258 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB;
2259 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
2260 /* Request PME. */
2261 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2);
2262 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2263 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2264 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2265 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2266 }
Cache object: 7fbdedb99944d170b48466f8a0dae53e
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