Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ste/if_ste.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 54 #include <net/bpf.h> 55 #include <net/if.h> 56 #include <net/if_arp.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 #include <net/if_vlan_var.h> 62 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/mii_bitbang.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 73 #include <dev/ste/if_stereg.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 MODULE_DEPEND(ste, pci, 1, 1, 1); 79 MODULE_DEPEND(ste, ether, 1, 1, 1); 80 MODULE_DEPEND(ste, miibus, 1, 1, 1); 81 82 /* Define to show Tx error status. */ 83 #define STE_SHOW_TXERRORS 84 85 /* 86 * Various supported device vendors/types and their names. 87 */ 88 static const struct ste_type const ste_devs[] = { 89 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 90 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 91 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 92 { 0, 0, NULL } 93 }; 94 95 static int ste_attach(device_t); 96 static int ste_detach(device_t); 97 static int ste_probe(device_t); 98 static int ste_resume(device_t); 99 static int ste_shutdown(device_t); 100 static int ste_suspend(device_t); 101 102 static int ste_dma_alloc(struct ste_softc *); 103 static void ste_dma_free(struct ste_softc *); 104 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 105 static int ste_eeprom_wait(struct ste_softc *); 106 static int ste_encap(struct ste_softc *, struct mbuf **, 107 struct ste_chain *); 108 static int ste_ifmedia_upd(struct ifnet *); 109 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 110 static void ste_init(void *); 111 static void ste_init_locked(struct ste_softc *); 112 static int ste_init_rx_list(struct ste_softc *); 113 static void ste_init_tx_list(struct ste_softc *); 114 static void ste_intr(void *); 115 static int ste_ioctl(struct ifnet *, u_long, caddr_t); 116 static uint32_t ste_mii_bitbang_read(device_t); 117 static void ste_mii_bitbang_write(device_t, uint32_t); 118 static int ste_miibus_readreg(device_t, int, int); 119 static void ste_miibus_statchg(device_t); 120 static int ste_miibus_writereg(device_t, int, int, int); 121 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 122 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int); 123 static void ste_reset(struct ste_softc *); 124 static void ste_restart_tx(struct ste_softc *); 125 static void ste_rxeof(struct ste_softc *, int); 126 static void ste_rxfilter(struct ste_softc *); 127 static void ste_setwol(struct ste_softc *); 128 static void ste_start(struct ifnet *); 129 static void ste_start_locked(struct ifnet *); 130 static void ste_stats_clear(struct ste_softc *); 131 static void ste_stats_update(struct ste_softc *); 132 static void ste_stop(struct ste_softc *); 133 static void ste_sysctl_node(struct ste_softc *); 134 static void ste_tick(void *); 135 static void ste_txeoc(struct ste_softc *); 136 static void ste_txeof(struct ste_softc *); 137 static void ste_wait(struct ste_softc *); 138 static void ste_watchdog(struct ste_softc *); 139 140 /* 141 * MII bit-bang glue 142 */ 143 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 144 ste_mii_bitbang_read, 145 ste_mii_bitbang_write, 146 { 147 STE_PHYCTL_MDATA, /* MII_BIT_MDO */ 148 STE_PHYCTL_MDATA, /* MII_BIT_MDI */ 149 STE_PHYCTL_MCLK, /* MII_BIT_MDC */ 150 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */ 151 0, /* MII_BIT_DIR_PHY_HOST */ 152 } 153 }; 154 155 static device_method_t ste_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, ste_probe), 158 DEVMETHOD(device_attach, ste_attach), 159 DEVMETHOD(device_detach, ste_detach), 160 DEVMETHOD(device_shutdown, ste_shutdown), 161 DEVMETHOD(device_suspend, ste_suspend), 162 DEVMETHOD(device_resume, ste_resume), 163 164 /* bus interface */ 165 DEVMETHOD(bus_print_child, bus_generic_print_child), 166 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 167 168 /* MII interface */ 169 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 170 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 171 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 172 173 { 0, 0 } 174 }; 175 176 static driver_t ste_driver = { 177 "ste", 178 ste_methods, 179 sizeof(struct ste_softc) 180 }; 181 182 static devclass_t ste_devclass; 183 184 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 185 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 186 187 #define STE_SETBIT4(sc, reg, x) \ 188 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 189 190 #define STE_CLRBIT4(sc, reg, x) \ 191 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 192 193 #define STE_SETBIT2(sc, reg, x) \ 194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 195 196 #define STE_CLRBIT2(sc, reg, x) \ 197 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 198 199 #define STE_SETBIT1(sc, reg, x) \ 200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 201 202 #define STE_CLRBIT1(sc, reg, x) \ 203 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 204 205 /* 206 * Read the MII serial port for the MII bit-bang module. 207 */ 208 static uint32_t 209 ste_mii_bitbang_read(device_t dev) 210 { 211 struct ste_softc *sc; 212 uint32_t val; 213 214 sc = device_get_softc(dev); 215 216 val = CSR_READ_1(sc, STE_PHYCTL); 217 CSR_BARRIER(sc, STE_PHYCTL, 1, 218 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 219 220 return (val); 221 } 222 223 /* 224 * Write the MII serial port for the MII bit-bang module. 225 */ 226 static void 227 ste_mii_bitbang_write(device_t dev, uint32_t val) 228 { 229 struct ste_softc *sc; 230 231 sc = device_get_softc(dev); 232 233 CSR_WRITE_1(sc, STE_PHYCTL, val); 234 CSR_BARRIER(sc, STE_PHYCTL, 1, 235 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 236 } 237 238 static int 239 ste_miibus_readreg(device_t dev, int phy, int reg) 240 { 241 242 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg)); 243 } 244 245 static int 246 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 247 { 248 249 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data); 250 251 return (0); 252 } 253 254 static void 255 ste_miibus_statchg(device_t dev) 256 { 257 struct ste_softc *sc; 258 struct mii_data *mii; 259 struct ifnet *ifp; 260 uint16_t cfg; 261 262 sc = device_get_softc(dev); 263 264 mii = device_get_softc(sc->ste_miibus); 265 ifp = sc->ste_ifp; 266 if (mii == NULL || ifp == NULL || 267 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 268 return; 269 270 sc->ste_flags &= ~STE_FLAG_LINK; 271 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 272 (IFM_ACTIVE | IFM_AVALID)) { 273 switch (IFM_SUBTYPE(mii->mii_media_active)) { 274 case IFM_10_T: 275 case IFM_100_TX: 276 case IFM_100_FX: 277 case IFM_100_T4: 278 sc->ste_flags |= STE_FLAG_LINK; 279 default: 280 break; 281 } 282 } 283 284 /* Program MACs with resolved speed/duplex/flow-control. */ 285 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 286 cfg = CSR_READ_2(sc, STE_MACCTL0); 287 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 288 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 289 /* 290 * ST201 data sheet says driver should enable receiving 291 * MAC control frames bit of receive mode register to 292 * receive flow-control frames but the register has no 293 * such bits. In addition the controller has no ability 294 * to send pause frames so it should be handled in 295 * driver. Implementing pause timer handling in driver 296 * layer is not trivial, so don't enable flow-control 297 * here. 298 */ 299 cfg |= STE_MACCTL0_FULLDUPLEX; 300 } 301 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 302 } 303 } 304 305 static int 306 ste_ifmedia_upd(struct ifnet *ifp) 307 { 308 struct ste_softc *sc; 309 struct mii_data *mii; 310 struct mii_softc *miisc; 311 int error; 312 313 sc = ifp->if_softc; 314 STE_LOCK(sc); 315 mii = device_get_softc(sc->ste_miibus); 316 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 317 mii_phy_reset(miisc); 318 error = mii_mediachg(mii); 319 STE_UNLOCK(sc); 320 321 return (error); 322 } 323 324 static void 325 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 326 { 327 struct ste_softc *sc; 328 struct mii_data *mii; 329 330 sc = ifp->if_softc; 331 mii = device_get_softc(sc->ste_miibus); 332 333 STE_LOCK(sc); 334 if ((ifp->if_flags & IFF_UP) == 0) { 335 STE_UNLOCK(sc); 336 return; 337 } 338 mii_pollstat(mii); 339 ifmr->ifm_active = mii->mii_media_active; 340 ifmr->ifm_status = mii->mii_media_status; 341 STE_UNLOCK(sc); 342 } 343 344 static void 345 ste_wait(struct ste_softc *sc) 346 { 347 int i; 348 349 for (i = 0; i < STE_TIMEOUT; i++) { 350 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 351 break; 352 DELAY(1); 353 } 354 355 if (i == STE_TIMEOUT) 356 device_printf(sc->ste_dev, "command never completed!\n"); 357 } 358 359 /* 360 * The EEPROM is slow: give it time to come ready after issuing 361 * it a command. 362 */ 363 static int 364 ste_eeprom_wait(struct ste_softc *sc) 365 { 366 int i; 367 368 DELAY(1000); 369 370 for (i = 0; i < 100; i++) { 371 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 372 DELAY(1000); 373 else 374 break; 375 } 376 377 if (i == 100) { 378 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 379 return (1); 380 } 381 382 return (0); 383 } 384 385 /* 386 * Read a sequence of words from the EEPROM. Note that ethernet address 387 * data is stored in the EEPROM in network byte order. 388 */ 389 static int 390 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt) 391 { 392 int err = 0, i; 393 394 if (ste_eeprom_wait(sc)) 395 return (1); 396 397 for (i = 0; i < cnt; i++) { 398 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 399 err = ste_eeprom_wait(sc); 400 if (err) 401 break; 402 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); 403 dest++; 404 } 405 406 return (err ? 1 : 0); 407 } 408 409 static void 410 ste_rxfilter(struct ste_softc *sc) 411 { 412 struct ifnet *ifp; 413 struct ifmultiaddr *ifma; 414 uint32_t hashes[2] = { 0, 0 }; 415 uint8_t rxcfg; 416 int h; 417 418 STE_LOCK_ASSERT(sc); 419 420 ifp = sc->ste_ifp; 421 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 422 rxcfg |= STE_RXMODE_UNICAST; 423 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 424 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 425 if (ifp->if_flags & IFF_BROADCAST) 426 rxcfg |= STE_RXMODE_BROADCAST; 427 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 428 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 429 rxcfg |= STE_RXMODE_ALLMULTI; 430 if ((ifp->if_flags & IFF_PROMISC) != 0) 431 rxcfg |= STE_RXMODE_PROMISC; 432 goto chipit; 433 } 434 435 rxcfg |= STE_RXMODE_MULTIHASH; 436 /* Now program new ones. */ 437 IF_ADDR_LOCK(ifp); 438 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 439 if (ifma->ifma_addr->sa_family != AF_LINK) 440 continue; 441 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 442 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 443 if (h < 32) 444 hashes[0] |= (1 << h); 445 else 446 hashes[1] |= (1 << (h - 32)); 447 } 448 IF_ADDR_UNLOCK(ifp); 449 450 chipit: 451 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 452 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 453 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 454 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 455 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 456 CSR_READ_1(sc, STE_RX_MODE); 457 } 458 459 #ifdef DEVICE_POLLING 460 static poll_handler_t ste_poll, ste_poll_locked; 461 462 static void 463 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 464 { 465 struct ste_softc *sc = ifp->if_softc; 466 467 STE_LOCK(sc); 468 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 469 ste_poll_locked(ifp, cmd, count); 470 STE_UNLOCK(sc); 471 } 472 473 static void 474 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 475 { 476 struct ste_softc *sc = ifp->if_softc; 477 478 STE_LOCK_ASSERT(sc); 479 480 ste_rxeof(sc, count); 481 ste_txeof(sc); 482 ste_txeoc(sc); 483 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 484 ste_start_locked(ifp); 485 486 if (cmd == POLL_AND_CHECK_STATUS) { 487 uint16_t status; 488 489 status = CSR_READ_2(sc, STE_ISR_ACK); 490 491 if (status & STE_ISR_STATS_OFLOW) 492 ste_stats_update(sc); 493 494 if (status & STE_ISR_HOSTERR) { 495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 496 ste_init_locked(sc); 497 } 498 } 499 } 500 #endif /* DEVICE_POLLING */ 501 502 static void 503 ste_intr(void *xsc) 504 { 505 struct ste_softc *sc; 506 struct ifnet *ifp; 507 uint16_t intrs, status; 508 509 sc = xsc; 510 STE_LOCK(sc); 511 ifp = sc->ste_ifp; 512 513 #ifdef DEVICE_POLLING 514 if (ifp->if_capenable & IFCAP_POLLING) { 515 STE_UNLOCK(sc); 516 return; 517 } 518 #endif 519 /* Reading STE_ISR_ACK clears STE_IMR register. */ 520 status = CSR_READ_2(sc, STE_ISR_ACK); 521 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 522 STE_UNLOCK(sc); 523 return; 524 } 525 526 intrs = STE_INTRS; 527 if (status == 0xFFFF || (status & intrs) == 0) 528 goto done; 529 530 if (sc->ste_int_rx_act > 0) { 531 status &= ~STE_ISR_RX_DMADONE; 532 intrs &= ~STE_IMR_RX_DMADONE; 533 } 534 535 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 536 ste_rxeof(sc, -1); 537 /* 538 * The controller has no ability to Rx interrupt 539 * moderation feature. Receiving 64 bytes frames 540 * from wire generates too many interrupts which in 541 * turn make system useless to process other useful 542 * things. Fortunately ST201 supports single shot 543 * timer so use the timer to implement Rx interrupt 544 * moderation in driver. This adds more register 545 * access but it greatly reduces number of Rx 546 * interrupts under high network load. 547 */ 548 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 549 (sc->ste_int_rx_mod != 0)) { 550 if ((status & STE_ISR_RX_DMADONE) != 0) { 551 CSR_WRITE_2(sc, STE_COUNTDOWN, 552 STE_TIMER_USECS(sc->ste_int_rx_mod)); 553 intrs &= ~STE_IMR_RX_DMADONE; 554 sc->ste_int_rx_act = 1; 555 } else { 556 intrs |= STE_IMR_RX_DMADONE; 557 sc->ste_int_rx_act = 0; 558 } 559 } 560 } 561 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 562 if ((status & STE_ISR_TX_DMADONE) != 0) 563 ste_txeof(sc); 564 if ((status & STE_ISR_TX_DONE) != 0) 565 ste_txeoc(sc); 566 if ((status & STE_ISR_STATS_OFLOW) != 0) 567 ste_stats_update(sc); 568 if ((status & STE_ISR_HOSTERR) != 0) { 569 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 570 ste_init_locked(sc); 571 STE_UNLOCK(sc); 572 return; 573 } 574 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 575 ste_start_locked(ifp); 576 done: 577 /* Re-enable interrupts */ 578 CSR_WRITE_2(sc, STE_IMR, intrs); 579 } 580 STE_UNLOCK(sc); 581 } 582 583 /* 584 * A frame has been uploaded: pass the resulting mbuf chain up to 585 * the higher level protocols. 586 */ 587 static void 588 ste_rxeof(struct ste_softc *sc, int count) 589 { 590 struct mbuf *m; 591 struct ifnet *ifp; 592 struct ste_chain_onefrag *cur_rx; 593 uint32_t rxstat; 594 int total_len, rx_npkts; 595 596 ifp = sc->ste_ifp; 597 598 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 599 sc->ste_cdata.ste_rx_list_map, 600 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 601 602 cur_rx = sc->ste_cdata.ste_rx_head; 603 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 604 cur_rx = cur_rx->ste_next) { 605 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 606 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 607 break; 608 #ifdef DEVICE_POLLING 609 if (ifp->if_capenable & IFCAP_POLLING) { 610 if (count == 0) 611 break; 612 count--; 613 } 614 #endif 615 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 616 break; 617 /* 618 * If an error occurs, update stats, clear the 619 * status word and leave the mbuf cluster in place: 620 * it should simply get re-used next time this descriptor 621 * comes up in the ring. 622 */ 623 if (rxstat & STE_RXSTAT_FRAME_ERR) { 624 ifp->if_ierrors++; 625 cur_rx->ste_ptr->ste_status = 0; 626 continue; 627 } 628 629 /* No errors; receive the packet. */ 630 m = cur_rx->ste_mbuf; 631 total_len = STE_RX_BYTES(rxstat); 632 633 /* 634 * Try to conjure up a new mbuf cluster. If that 635 * fails, it means we have an out of memory condition and 636 * should leave the buffer in place and continue. This will 637 * result in a lost packet, but there's little else we 638 * can do in this situation. 639 */ 640 if (ste_newbuf(sc, cur_rx) != 0) { 641 ifp->if_iqdrops++; 642 cur_rx->ste_ptr->ste_status = 0; 643 continue; 644 } 645 646 m->m_pkthdr.rcvif = ifp; 647 m->m_pkthdr.len = m->m_len = total_len; 648 649 ifp->if_ipackets++; 650 STE_UNLOCK(sc); 651 (*ifp->if_input)(ifp, m); 652 STE_LOCK(sc); 653 } 654 655 if (rx_npkts > 0) { 656 sc->ste_cdata.ste_rx_head = cur_rx; 657 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 658 sc->ste_cdata.ste_rx_list_map, 659 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 660 } 661 } 662 663 static void 664 ste_txeoc(struct ste_softc *sc) 665 { 666 uint16_t txstat; 667 struct ifnet *ifp; 668 669 STE_LOCK_ASSERT(sc); 670 671 ifp = sc->ste_ifp; 672 673 /* 674 * STE_TX_STATUS register implements a queue of up to 31 675 * transmit status byte. Writing an arbitrary value to the 676 * register will advance the queue to the next transmit 677 * status byte. This means if driver does not read 678 * STE_TX_STATUS register after completing sending more 679 * than 31 frames the controller would be stalled so driver 680 * should re-wake the Tx MAC. This is the most severe 681 * limitation of ST201 based controller. 682 */ 683 for (;;) { 684 txstat = CSR_READ_2(sc, STE_TX_STATUS); 685 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 686 break; 687 if ((txstat & (STE_TXSTATUS_UNDERRUN | 688 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 689 STE_TXSTATUS_STATSOFLOW)) != 0) { 690 ifp->if_oerrors++; 691 #ifdef STE_SHOW_TXERRORS 692 device_printf(sc->ste_dev, "TX error : 0x%b\n", 693 txstat & 0xFF, STE_ERR_BITS); 694 #endif 695 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 696 sc->ste_tx_thresh < STE_PACKET_SIZE) { 697 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 698 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 699 sc->ste_tx_thresh = STE_PACKET_SIZE; 700 device_printf(sc->ste_dev, 701 "TX underrun, increasing TX" 702 " start threshold to %d bytes\n", 703 sc->ste_tx_thresh); 704 /* Make sure to disable active DMA cycles. */ 705 STE_SETBIT4(sc, STE_DMACTL, 706 STE_DMACTL_TXDMA_STALL); 707 ste_wait(sc); 708 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 709 ste_init_locked(sc); 710 break; 711 } 712 /* Restart Tx. */ 713 ste_restart_tx(sc); 714 } 715 /* 716 * Advance to next status and ACK TxComplete 717 * interrupt. ST201 data sheet was wrong here, to 718 * get next Tx status, we have to write both 719 * STE_TX_STATUS and STE_TX_FRAMEID register. 720 * Otherwise controller returns the same status 721 * as well as not acknowledge Tx completion 722 * interrupt. 723 */ 724 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 725 } 726 } 727 728 static void 729 ste_tick(void *arg) 730 { 731 struct ste_softc *sc; 732 struct mii_data *mii; 733 734 sc = (struct ste_softc *)arg; 735 736 STE_LOCK_ASSERT(sc); 737 738 mii = device_get_softc(sc->ste_miibus); 739 mii_tick(mii); 740 /* 741 * ukphy(4) does not seem to generate CB that reports 742 * resolved link state so if we know we lost a link, 743 * explicitly check the link state. 744 */ 745 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 746 ste_miibus_statchg(sc->ste_dev); 747 /* 748 * Because we are not generating Tx completion 749 * interrupt for every frame, reclaim transmitted 750 * buffers here. 751 */ 752 ste_txeof(sc); 753 ste_txeoc(sc); 754 ste_stats_update(sc); 755 ste_watchdog(sc); 756 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 757 } 758 759 static void 760 ste_txeof(struct ste_softc *sc) 761 { 762 struct ifnet *ifp; 763 struct ste_chain *cur_tx; 764 uint32_t txstat; 765 int idx; 766 767 STE_LOCK_ASSERT(sc); 768 769 ifp = sc->ste_ifp; 770 idx = sc->ste_cdata.ste_tx_cons; 771 if (idx == sc->ste_cdata.ste_tx_prod) 772 return; 773 774 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 775 sc->ste_cdata.ste_tx_list_map, 776 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 777 778 while (idx != sc->ste_cdata.ste_tx_prod) { 779 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 780 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 781 if ((txstat & STE_TXCTL_DMADONE) == 0) 782 break; 783 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 784 BUS_DMASYNC_POSTWRITE); 785 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 786 KASSERT(cur_tx->ste_mbuf != NULL, 787 ("%s: freeing NULL mbuf!\n", __func__)); 788 m_freem(cur_tx->ste_mbuf); 789 cur_tx->ste_mbuf = NULL; 790 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 791 ifp->if_opackets++; 792 sc->ste_cdata.ste_tx_cnt--; 793 STE_INC(idx, STE_TX_LIST_CNT); 794 } 795 796 sc->ste_cdata.ste_tx_cons = idx; 797 if (sc->ste_cdata.ste_tx_cnt == 0) 798 sc->ste_timer = 0; 799 } 800 801 static void 802 ste_stats_clear(struct ste_softc *sc) 803 { 804 805 STE_LOCK_ASSERT(sc); 806 807 /* Rx stats. */ 808 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 809 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 810 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 811 CSR_READ_1(sc, STE_STAT_RX_BCAST); 812 CSR_READ_1(sc, STE_STAT_RX_MCAST); 813 CSR_READ_1(sc, STE_STAT_RX_LOST); 814 /* Tx stats. */ 815 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 816 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 817 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 818 CSR_READ_1(sc, STE_STAT_TX_BCAST); 819 CSR_READ_1(sc, STE_STAT_TX_MCAST); 820 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 821 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 822 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 823 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 824 CSR_READ_1(sc, STE_STAT_TX_DEFER); 825 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 826 CSR_READ_1(sc, STE_STAT_TX_ABORT); 827 } 828 829 static void 830 ste_stats_update(struct ste_softc *sc) 831 { 832 struct ifnet *ifp; 833 struct ste_hw_stats *stats; 834 uint32_t val; 835 836 STE_LOCK_ASSERT(sc); 837 838 ifp = sc->ste_ifp; 839 stats = &sc->ste_stats; 840 /* Rx stats. */ 841 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 842 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 843 val &= 0x000FFFFF; 844 stats->rx_bytes += val; 845 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 846 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 847 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 848 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 849 /* Tx stats. */ 850 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 851 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 852 val &= 0x000FFFFF; 853 stats->tx_bytes += val; 854 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 855 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 856 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 857 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 858 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 859 stats->tx_single_colls += val; 860 ifp->if_collisions += val; 861 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 862 stats->tx_multi_colls += val; 863 ifp->if_collisions += val; 864 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 865 stats->tx_late_colls += val; 866 ifp->if_collisions += val; 867 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 868 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 869 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 870 } 871 872 /* 873 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 874 * IDs against our list and return a device name if we find a match. 875 */ 876 static int 877 ste_probe(device_t dev) 878 { 879 const struct ste_type *t; 880 881 t = ste_devs; 882 883 while (t->ste_name != NULL) { 884 if ((pci_get_vendor(dev) == t->ste_vid) && 885 (pci_get_device(dev) == t->ste_did)) { 886 device_set_desc(dev, t->ste_name); 887 return (BUS_PROBE_DEFAULT); 888 } 889 t++; 890 } 891 892 return (ENXIO); 893 } 894 895 /* 896 * Attach the interface. Allocate softc structures, do ifmedia 897 * setup and ethernet/BPF attach. 898 */ 899 static int 900 ste_attach(device_t dev) 901 { 902 struct ste_softc *sc; 903 struct ifnet *ifp; 904 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 905 int error = 0, phy, pmc, prefer_iomap, rid; 906 907 sc = device_get_softc(dev); 908 sc->ste_dev = dev; 909 910 /* 911 * Only use one PHY since this chip reports multiple 912 * Note on the DFE-550 the PHY is at 1 on the DFE-580 913 * it is at 0 & 1. It is rev 0x12. 914 */ 915 if (pci_get_vendor(dev) == DL_VENDORID && 916 pci_get_device(dev) == DL_DEVICEID_DL10050 && 917 pci_get_revid(dev) == 0x12 ) 918 sc->ste_flags |= STE_FLAG_ONE_PHY; 919 920 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 921 MTX_DEF); 922 /* 923 * Map control/status registers. 924 */ 925 pci_enable_busmaster(dev); 926 927 /* 928 * Prefer memory space register mapping over IO space but use 929 * IO space for a device that is known to have issues on memory 930 * mapping. 931 */ 932 prefer_iomap = 0; 933 if (pci_get_device(dev) == ST_DEVICEID_ST201_1) 934 prefer_iomap = 1; 935 else 936 resource_int_value(device_get_name(sc->ste_dev), 937 device_get_unit(sc->ste_dev), "prefer_iomap", 938 &prefer_iomap); 939 if (prefer_iomap == 0) { 940 sc->ste_res_id = PCIR_BAR(1); 941 sc->ste_res_type = SYS_RES_MEMORY; 942 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 943 &sc->ste_res_id, RF_ACTIVE); 944 } 945 if (prefer_iomap || sc->ste_res == NULL) { 946 sc->ste_res_id = PCIR_BAR(0); 947 sc->ste_res_type = SYS_RES_IOPORT; 948 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 949 &sc->ste_res_id, RF_ACTIVE); 950 } 951 if (sc->ste_res == NULL) { 952 device_printf(dev, "couldn't map ports/memory\n"); 953 error = ENXIO; 954 goto fail; 955 } 956 957 /* Allocate interrupt */ 958 rid = 0; 959 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 960 RF_SHAREABLE | RF_ACTIVE); 961 962 if (sc->ste_irq == NULL) { 963 device_printf(dev, "couldn't map interrupt\n"); 964 error = ENXIO; 965 goto fail; 966 } 967 968 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 969 970 /* Reset the adapter. */ 971 ste_reset(sc); 972 973 /* 974 * Get station address from the EEPROM. 975 */ 976 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) { 977 device_printf(dev, "failed to read station address\n"); 978 error = ENXIO;; 979 goto fail; 980 } 981 ste_sysctl_node(sc); 982 983 if ((error = ste_dma_alloc(sc)) != 0) 984 goto fail; 985 986 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 987 if (ifp == NULL) { 988 device_printf(dev, "can not if_alloc()\n"); 989 error = ENOSPC; 990 goto fail; 991 } 992 993 /* Do MII setup. */ 994 phy = MII_PHY_ANY; 995 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0) 996 phy = 0; 997 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd, 998 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 999 if (error != 0) { 1000 device_printf(dev, "attaching PHYs failed\n"); 1001 goto fail; 1002 } 1003 1004 ifp->if_softc = sc; 1005 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1006 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1007 ifp->if_ioctl = ste_ioctl; 1008 ifp->if_start = ste_start; 1009 ifp->if_init = ste_init; 1010 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1011 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1012 IFQ_SET_READY(&ifp->if_snd); 1013 1014 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1015 1016 /* 1017 * Call MI attach routine. 1018 */ 1019 ether_ifattach(ifp, (uint8_t *)eaddr); 1020 1021 /* 1022 * Tell the upper layer(s) we support long frames. 1023 */ 1024 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1025 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1026 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 1027 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1028 ifp->if_capenable = ifp->if_capabilities; 1029 #ifdef DEVICE_POLLING 1030 ifp->if_capabilities |= IFCAP_POLLING; 1031 #endif 1032 1033 /* Hook interrupt last to avoid having to lock softc */ 1034 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1035 NULL, ste_intr, sc, &sc->ste_intrhand); 1036 1037 if (error) { 1038 device_printf(dev, "couldn't set up irq\n"); 1039 ether_ifdetach(ifp); 1040 goto fail; 1041 } 1042 1043 fail: 1044 if (error) 1045 ste_detach(dev); 1046 1047 return (error); 1048 } 1049 1050 /* 1051 * Shutdown hardware and free up resources. This can be called any 1052 * time after the mutex has been initialized. It is called in both 1053 * the error case in attach and the normal detach case so it needs 1054 * to be careful about only freeing resources that have actually been 1055 * allocated. 1056 */ 1057 static int 1058 ste_detach(device_t dev) 1059 { 1060 struct ste_softc *sc; 1061 struct ifnet *ifp; 1062 1063 sc = device_get_softc(dev); 1064 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1065 ifp = sc->ste_ifp; 1066 1067 #ifdef DEVICE_POLLING 1068 if (ifp->if_capenable & IFCAP_POLLING) 1069 ether_poll_deregister(ifp); 1070 #endif 1071 1072 /* These should only be active if attach succeeded */ 1073 if (device_is_attached(dev)) { 1074 ether_ifdetach(ifp); 1075 STE_LOCK(sc); 1076 ste_stop(sc); 1077 STE_UNLOCK(sc); 1078 callout_drain(&sc->ste_callout); 1079 } 1080 if (sc->ste_miibus) 1081 device_delete_child(dev, sc->ste_miibus); 1082 bus_generic_detach(dev); 1083 1084 if (sc->ste_intrhand) 1085 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1086 if (sc->ste_irq) 1087 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1088 if (sc->ste_res) 1089 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1090 sc->ste_res); 1091 1092 if (ifp) 1093 if_free(ifp); 1094 1095 ste_dma_free(sc); 1096 mtx_destroy(&sc->ste_mtx); 1097 1098 return (0); 1099 } 1100 1101 struct ste_dmamap_arg { 1102 bus_addr_t ste_busaddr; 1103 }; 1104 1105 static void 1106 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1107 { 1108 struct ste_dmamap_arg *ctx; 1109 1110 if (error != 0) 1111 return; 1112 1113 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1114 1115 ctx = (struct ste_dmamap_arg *)arg; 1116 ctx->ste_busaddr = segs[0].ds_addr; 1117 } 1118 1119 static int 1120 ste_dma_alloc(struct ste_softc *sc) 1121 { 1122 struct ste_chain *txc; 1123 struct ste_chain_onefrag *rxc; 1124 struct ste_dmamap_arg ctx; 1125 int error, i; 1126 1127 /* Create parent DMA tag. */ 1128 error = bus_dma_tag_create( 1129 bus_get_dma_tag(sc->ste_dev), /* parent */ 1130 1, 0, /* alignment, boundary */ 1131 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1132 BUS_SPACE_MAXADDR, /* highaddr */ 1133 NULL, NULL, /* filter, filterarg */ 1134 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1135 0, /* nsegments */ 1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1137 0, /* flags */ 1138 NULL, NULL, /* lockfunc, lockarg */ 1139 &sc->ste_cdata.ste_parent_tag); 1140 if (error != 0) { 1141 device_printf(sc->ste_dev, 1142 "could not create parent DMA tag.\n"); 1143 goto fail; 1144 } 1145 1146 /* Create DMA tag for Tx descriptor list. */ 1147 error = bus_dma_tag_create( 1148 sc->ste_cdata.ste_parent_tag, /* parent */ 1149 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1150 BUS_SPACE_MAXADDR, /* lowaddr */ 1151 BUS_SPACE_MAXADDR, /* highaddr */ 1152 NULL, NULL, /* filter, filterarg */ 1153 STE_TX_LIST_SZ, /* maxsize */ 1154 1, /* nsegments */ 1155 STE_TX_LIST_SZ, /* maxsegsize */ 1156 0, /* flags */ 1157 NULL, NULL, /* lockfunc, lockarg */ 1158 &sc->ste_cdata.ste_tx_list_tag); 1159 if (error != 0) { 1160 device_printf(sc->ste_dev, 1161 "could not create Tx list DMA tag.\n"); 1162 goto fail; 1163 } 1164 1165 /* Create DMA tag for Rx descriptor list. */ 1166 error = bus_dma_tag_create( 1167 sc->ste_cdata.ste_parent_tag, /* parent */ 1168 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1169 BUS_SPACE_MAXADDR, /* lowaddr */ 1170 BUS_SPACE_MAXADDR, /* highaddr */ 1171 NULL, NULL, /* filter, filterarg */ 1172 STE_RX_LIST_SZ, /* maxsize */ 1173 1, /* nsegments */ 1174 STE_RX_LIST_SZ, /* maxsegsize */ 1175 0, /* flags */ 1176 NULL, NULL, /* lockfunc, lockarg */ 1177 &sc->ste_cdata.ste_rx_list_tag); 1178 if (error != 0) { 1179 device_printf(sc->ste_dev, 1180 "could not create Rx list DMA tag.\n"); 1181 goto fail; 1182 } 1183 1184 /* Create DMA tag for Tx buffers. */ 1185 error = bus_dma_tag_create( 1186 sc->ste_cdata.ste_parent_tag, /* parent */ 1187 1, 0, /* alignment, boundary */ 1188 BUS_SPACE_MAXADDR, /* lowaddr */ 1189 BUS_SPACE_MAXADDR, /* highaddr */ 1190 NULL, NULL, /* filter, filterarg */ 1191 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1192 STE_MAXFRAGS, /* nsegments */ 1193 MCLBYTES, /* maxsegsize */ 1194 0, /* flags */ 1195 NULL, NULL, /* lockfunc, lockarg */ 1196 &sc->ste_cdata.ste_tx_tag); 1197 if (error != 0) { 1198 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1199 goto fail; 1200 } 1201 1202 /* Create DMA tag for Rx buffers. */ 1203 error = bus_dma_tag_create( 1204 sc->ste_cdata.ste_parent_tag, /* parent */ 1205 1, 0, /* alignment, boundary */ 1206 BUS_SPACE_MAXADDR, /* lowaddr */ 1207 BUS_SPACE_MAXADDR, /* highaddr */ 1208 NULL, NULL, /* filter, filterarg */ 1209 MCLBYTES, /* maxsize */ 1210 1, /* nsegments */ 1211 MCLBYTES, /* maxsegsize */ 1212 0, /* flags */ 1213 NULL, NULL, /* lockfunc, lockarg */ 1214 &sc->ste_cdata.ste_rx_tag); 1215 if (error != 0) { 1216 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1217 goto fail; 1218 } 1219 1220 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1221 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1222 (void **)&sc->ste_ldata.ste_tx_list, 1223 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1224 &sc->ste_cdata.ste_tx_list_map); 1225 if (error != 0) { 1226 device_printf(sc->ste_dev, 1227 "could not allocate DMA'able memory for Tx list.\n"); 1228 goto fail; 1229 } 1230 ctx.ste_busaddr = 0; 1231 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1232 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1233 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1234 if (error != 0 || ctx.ste_busaddr == 0) { 1235 device_printf(sc->ste_dev, 1236 "could not load DMA'able memory for Tx list.\n"); 1237 goto fail; 1238 } 1239 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1240 1241 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1242 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1243 (void **)&sc->ste_ldata.ste_rx_list, 1244 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1245 &sc->ste_cdata.ste_rx_list_map); 1246 if (error != 0) { 1247 device_printf(sc->ste_dev, 1248 "could not allocate DMA'able memory for Rx list.\n"); 1249 goto fail; 1250 } 1251 ctx.ste_busaddr = 0; 1252 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1253 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1254 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1255 if (error != 0 || ctx.ste_busaddr == 0) { 1256 device_printf(sc->ste_dev, 1257 "could not load DMA'able memory for Rx list.\n"); 1258 goto fail; 1259 } 1260 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1261 1262 /* Create DMA maps for Tx buffers. */ 1263 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1264 txc = &sc->ste_cdata.ste_tx_chain[i]; 1265 txc->ste_ptr = NULL; 1266 txc->ste_mbuf = NULL; 1267 txc->ste_next = NULL; 1268 txc->ste_phys = 0; 1269 txc->ste_map = NULL; 1270 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1271 &txc->ste_map); 1272 if (error != 0) { 1273 device_printf(sc->ste_dev, 1274 "could not create Tx dmamap.\n"); 1275 goto fail; 1276 } 1277 } 1278 /* Create DMA maps for Rx buffers. */ 1279 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1280 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1281 device_printf(sc->ste_dev, 1282 "could not create spare Rx dmamap.\n"); 1283 goto fail; 1284 } 1285 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1286 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1287 rxc->ste_ptr = NULL; 1288 rxc->ste_mbuf = NULL; 1289 rxc->ste_next = NULL; 1290 rxc->ste_map = NULL; 1291 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1292 &rxc->ste_map); 1293 if (error != 0) { 1294 device_printf(sc->ste_dev, 1295 "could not create Rx dmamap.\n"); 1296 goto fail; 1297 } 1298 } 1299 1300 fail: 1301 return (error); 1302 } 1303 1304 static void 1305 ste_dma_free(struct ste_softc *sc) 1306 { 1307 struct ste_chain *txc; 1308 struct ste_chain_onefrag *rxc; 1309 int i; 1310 1311 /* Tx buffers. */ 1312 if (sc->ste_cdata.ste_tx_tag != NULL) { 1313 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1314 txc = &sc->ste_cdata.ste_tx_chain[i]; 1315 if (txc->ste_map != NULL) { 1316 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1317 txc->ste_map); 1318 txc->ste_map = NULL; 1319 } 1320 } 1321 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1322 sc->ste_cdata.ste_tx_tag = NULL; 1323 } 1324 /* Rx buffers. */ 1325 if (sc->ste_cdata.ste_rx_tag != NULL) { 1326 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1327 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1328 if (rxc->ste_map != NULL) { 1329 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1330 rxc->ste_map); 1331 rxc->ste_map = NULL; 1332 } 1333 } 1334 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1335 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1336 sc->ste_cdata.ste_rx_sparemap); 1337 sc->ste_cdata.ste_rx_sparemap = NULL; 1338 } 1339 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1340 sc->ste_cdata.ste_rx_tag = NULL; 1341 } 1342 /* Tx descriptor list. */ 1343 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1344 if (sc->ste_cdata.ste_tx_list_map != NULL) 1345 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1346 sc->ste_cdata.ste_tx_list_map); 1347 if (sc->ste_cdata.ste_tx_list_map != NULL && 1348 sc->ste_ldata.ste_tx_list != NULL) 1349 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1350 sc->ste_ldata.ste_tx_list, 1351 sc->ste_cdata.ste_tx_list_map); 1352 sc->ste_ldata.ste_tx_list = NULL; 1353 sc->ste_cdata.ste_tx_list_map = NULL; 1354 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1355 sc->ste_cdata.ste_tx_list_tag = NULL; 1356 } 1357 /* Rx descriptor list. */ 1358 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1359 if (sc->ste_cdata.ste_rx_list_map != NULL) 1360 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1361 sc->ste_cdata.ste_rx_list_map); 1362 if (sc->ste_cdata.ste_rx_list_map != NULL && 1363 sc->ste_ldata.ste_rx_list != NULL) 1364 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1365 sc->ste_ldata.ste_rx_list, 1366 sc->ste_cdata.ste_rx_list_map); 1367 sc->ste_ldata.ste_rx_list = NULL; 1368 sc->ste_cdata.ste_rx_list_map = NULL; 1369 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1370 sc->ste_cdata.ste_rx_list_tag = NULL; 1371 } 1372 if (sc->ste_cdata.ste_parent_tag != NULL) { 1373 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1374 sc->ste_cdata.ste_parent_tag = NULL; 1375 } 1376 } 1377 1378 static int 1379 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1380 { 1381 struct mbuf *m; 1382 bus_dma_segment_t segs[1]; 1383 bus_dmamap_t map; 1384 int error, nsegs; 1385 1386 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1387 if (m == NULL) 1388 return (ENOBUFS); 1389 m->m_len = m->m_pkthdr.len = MCLBYTES; 1390 m_adj(m, ETHER_ALIGN); 1391 1392 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1393 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1394 m_freem(m); 1395 return (error); 1396 } 1397 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1398 1399 if (rxc->ste_mbuf != NULL) { 1400 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1401 BUS_DMASYNC_POSTREAD); 1402 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1403 } 1404 map = rxc->ste_map; 1405 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1406 sc->ste_cdata.ste_rx_sparemap = map; 1407 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1408 BUS_DMASYNC_PREREAD); 1409 rxc->ste_mbuf = m; 1410 rxc->ste_ptr->ste_status = 0; 1411 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1412 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1413 STE_FRAG_LAST); 1414 return (0); 1415 } 1416 1417 static int 1418 ste_init_rx_list(struct ste_softc *sc) 1419 { 1420 struct ste_chain_data *cd; 1421 struct ste_list_data *ld; 1422 int error, i; 1423 1424 sc->ste_int_rx_act = 0; 1425 cd = &sc->ste_cdata; 1426 ld = &sc->ste_ldata; 1427 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1428 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1429 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1430 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1431 if (error != 0) 1432 return (error); 1433 if (i == (STE_RX_LIST_CNT - 1)) { 1434 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1435 ld->ste_rx_list[i].ste_next = 1436 htole32(ld->ste_rx_list_paddr + 1437 (sizeof(struct ste_desc_onefrag) * 0)); 1438 } else { 1439 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1440 ld->ste_rx_list[i].ste_next = 1441 htole32(ld->ste_rx_list_paddr + 1442 (sizeof(struct ste_desc_onefrag) * (i + 1))); 1443 } 1444 } 1445 1446 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1447 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1448 sc->ste_cdata.ste_rx_list_map, 1449 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1450 1451 return (0); 1452 } 1453 1454 static void 1455 ste_init_tx_list(struct ste_softc *sc) 1456 { 1457 struct ste_chain_data *cd; 1458 struct ste_list_data *ld; 1459 int i; 1460 1461 cd = &sc->ste_cdata; 1462 ld = &sc->ste_ldata; 1463 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1464 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1465 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1466 cd->ste_tx_chain[i].ste_mbuf = NULL; 1467 if (i == (STE_TX_LIST_CNT - 1)) { 1468 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1469 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1470 ld->ste_tx_list_paddr + 1471 (sizeof(struct ste_desc) * 0))); 1472 } else { 1473 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1474 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1475 ld->ste_tx_list_paddr + 1476 (sizeof(struct ste_desc) * (i + 1)))); 1477 } 1478 } 1479 1480 cd->ste_last_tx = NULL; 1481 cd->ste_tx_prod = 0; 1482 cd->ste_tx_cons = 0; 1483 cd->ste_tx_cnt = 0; 1484 1485 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1486 sc->ste_cdata.ste_tx_list_map, 1487 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1488 } 1489 1490 static void 1491 ste_init(void *xsc) 1492 { 1493 struct ste_softc *sc; 1494 1495 sc = xsc; 1496 STE_LOCK(sc); 1497 ste_init_locked(sc); 1498 STE_UNLOCK(sc); 1499 } 1500 1501 static void 1502 ste_init_locked(struct ste_softc *sc) 1503 { 1504 struct ifnet *ifp; 1505 struct mii_data *mii; 1506 uint8_t val; 1507 int i; 1508 1509 STE_LOCK_ASSERT(sc); 1510 ifp = sc->ste_ifp; 1511 mii = device_get_softc(sc->ste_miibus); 1512 1513 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1514 return; 1515 1516 ste_stop(sc); 1517 /* Reset the chip to a known state. */ 1518 ste_reset(sc); 1519 1520 /* Init our MAC address */ 1521 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1522 CSR_WRITE_2(sc, STE_PAR0 + i, 1523 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1524 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1525 } 1526 1527 /* Init RX list */ 1528 if (ste_init_rx_list(sc) != 0) { 1529 device_printf(sc->ste_dev, 1530 "initialization failed: no memory for RX buffers\n"); 1531 ste_stop(sc); 1532 return; 1533 } 1534 1535 /* Set RX polling interval */ 1536 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1537 1538 /* Init TX descriptors */ 1539 ste_init_tx_list(sc); 1540 1541 /* Clear and disable WOL. */ 1542 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1543 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1544 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1545 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1546 1547 /* Set the TX freethresh value */ 1548 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1549 1550 /* Set the TX start threshold for best performance. */ 1551 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1552 1553 /* Set the TX reclaim threshold. */ 1554 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1555 1556 /* Accept VLAN length packets */ 1557 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1558 1559 /* Set up the RX filter. */ 1560 ste_rxfilter(sc); 1561 1562 /* Load the address of the RX list. */ 1563 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1564 ste_wait(sc); 1565 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1566 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1567 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1568 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1569 1570 /* Set TX polling interval(defer until we TX first packet). */ 1571 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1572 1573 /* Load address of the TX list */ 1574 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1575 ste_wait(sc); 1576 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1577 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1578 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1579 ste_wait(sc); 1580 /* Select 3.2us timer. */ 1581 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1582 STE_DMACTL_COUNTDOWN_MODE); 1583 1584 /* Enable receiver and transmitter */ 1585 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1586 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1587 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1588 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1589 1590 /* Enable stats counters. */ 1591 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1592 /* Clear stats counters. */ 1593 ste_stats_clear(sc); 1594 1595 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1596 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1597 #ifdef DEVICE_POLLING 1598 /* Disable interrupts if we are polling. */ 1599 if (ifp->if_capenable & IFCAP_POLLING) 1600 CSR_WRITE_2(sc, STE_IMR, 0); 1601 else 1602 #endif 1603 /* Enable interrupts. */ 1604 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1605 1606 sc->ste_flags &= ~STE_FLAG_LINK; 1607 /* Switch to the current media. */ 1608 mii_mediachg(mii); 1609 1610 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1611 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1612 1613 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1614 } 1615 1616 static void 1617 ste_stop(struct ste_softc *sc) 1618 { 1619 struct ifnet *ifp; 1620 struct ste_chain_onefrag *cur_rx; 1621 struct ste_chain *cur_tx; 1622 uint32_t val; 1623 int i; 1624 1625 STE_LOCK_ASSERT(sc); 1626 ifp = sc->ste_ifp; 1627 1628 callout_stop(&sc->ste_callout); 1629 sc->ste_timer = 0; 1630 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1631 1632 CSR_WRITE_2(sc, STE_IMR, 0); 1633 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1634 /* Stop pending DMA. */ 1635 val = CSR_READ_4(sc, STE_DMACTL); 1636 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1637 CSR_WRITE_4(sc, STE_DMACTL, val); 1638 ste_wait(sc); 1639 /* Disable auto-polling. */ 1640 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1641 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1642 /* Nullify DMA address to stop any further DMA. */ 1643 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1644 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1645 /* Stop TX/RX MAC. */ 1646 val = CSR_READ_2(sc, STE_MACCTL1); 1647 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1648 STE_MACCTL1_STATS_DISABLE; 1649 CSR_WRITE_2(sc, STE_MACCTL1, val); 1650 for (i = 0; i < STE_TIMEOUT; i++) { 1651 DELAY(10); 1652 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1653 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1654 break; 1655 } 1656 if (i == STE_TIMEOUT) 1657 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1658 /* Acknowledge any pending interrupts. */ 1659 CSR_READ_2(sc, STE_ISR_ACK); 1660 ste_stats_update(sc); 1661 1662 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1663 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1664 if (cur_rx->ste_mbuf != NULL) { 1665 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1666 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1667 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1668 cur_rx->ste_map); 1669 m_freem(cur_rx->ste_mbuf); 1670 cur_rx->ste_mbuf = NULL; 1671 } 1672 } 1673 1674 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1675 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1676 if (cur_tx->ste_mbuf != NULL) { 1677 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1678 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1679 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1680 cur_tx->ste_map); 1681 m_freem(cur_tx->ste_mbuf); 1682 cur_tx->ste_mbuf = NULL; 1683 } 1684 } 1685 } 1686 1687 static void 1688 ste_reset(struct ste_softc *sc) 1689 { 1690 uint32_t ctl; 1691 int i; 1692 1693 ctl = CSR_READ_4(sc, STE_ASICCTL); 1694 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1695 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1696 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1697 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1698 STE_ASICCTL_EXTRESET_RESET; 1699 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1700 CSR_READ_4(sc, STE_ASICCTL); 1701 /* 1702 * Due to the need of accessing EEPROM controller can take 1703 * up to 1ms to complete the global reset. 1704 */ 1705 DELAY(1000); 1706 1707 for (i = 0; i < STE_TIMEOUT; i++) { 1708 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1709 break; 1710 DELAY(10); 1711 } 1712 1713 if (i == STE_TIMEOUT) 1714 device_printf(sc->ste_dev, "global reset never completed\n"); 1715 } 1716 1717 static void 1718 ste_restart_tx(struct ste_softc *sc) 1719 { 1720 uint16_t mac; 1721 int i; 1722 1723 for (i = 0; i < STE_TIMEOUT; i++) { 1724 mac = CSR_READ_2(sc, STE_MACCTL1); 1725 mac |= STE_MACCTL1_TX_ENABLE; 1726 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1727 mac = CSR_READ_2(sc, STE_MACCTL1); 1728 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1729 break; 1730 DELAY(10); 1731 } 1732 1733 if (i == STE_TIMEOUT) 1734 device_printf(sc->ste_dev, "starting Tx failed"); 1735 } 1736 1737 static int 1738 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1739 { 1740 struct ste_softc *sc; 1741 struct ifreq *ifr; 1742 struct mii_data *mii; 1743 int error = 0, mask; 1744 1745 sc = ifp->if_softc; 1746 ifr = (struct ifreq *)data; 1747 1748 switch (command) { 1749 case SIOCSIFFLAGS: 1750 STE_LOCK(sc); 1751 if ((ifp->if_flags & IFF_UP) != 0) { 1752 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1753 ((ifp->if_flags ^ sc->ste_if_flags) & 1754 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1755 ste_rxfilter(sc); 1756 else 1757 ste_init_locked(sc); 1758 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1759 ste_stop(sc); 1760 sc->ste_if_flags = ifp->if_flags; 1761 STE_UNLOCK(sc); 1762 break; 1763 case SIOCADDMULTI: 1764 case SIOCDELMULTI: 1765 STE_LOCK(sc); 1766 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1767 ste_rxfilter(sc); 1768 STE_UNLOCK(sc); 1769 break; 1770 case SIOCGIFMEDIA: 1771 case SIOCSIFMEDIA: 1772 mii = device_get_softc(sc->ste_miibus); 1773 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1774 break; 1775 case SIOCSIFCAP: 1776 STE_LOCK(sc); 1777 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1778 #ifdef DEVICE_POLLING 1779 if ((mask & IFCAP_POLLING) != 0 && 1780 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 1781 ifp->if_capenable ^= IFCAP_POLLING; 1782 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 1783 error = ether_poll_register(ste_poll, ifp); 1784 if (error != 0) { 1785 STE_UNLOCK(sc); 1786 break; 1787 } 1788 /* Disable interrupts. */ 1789 CSR_WRITE_2(sc, STE_IMR, 0); 1790 } else { 1791 error = ether_poll_deregister(ifp); 1792 /* Enable interrupts. */ 1793 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1794 } 1795 } 1796 #endif /* DEVICE_POLLING */ 1797 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1798 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1799 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1800 STE_UNLOCK(sc); 1801 break; 1802 default: 1803 error = ether_ioctl(ifp, command, data); 1804 break; 1805 } 1806 1807 return (error); 1808 } 1809 1810 static int 1811 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1812 { 1813 struct ste_frag *frag; 1814 struct mbuf *m; 1815 struct ste_desc *desc; 1816 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1817 int error, i, nsegs; 1818 1819 STE_LOCK_ASSERT(sc); 1820 M_ASSERTPKTHDR((*m_head)); 1821 1822 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1823 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1824 if (error == EFBIG) { 1825 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1826 if (m == NULL) { 1827 m_freem(*m_head); 1828 *m_head = NULL; 1829 return (ENOMEM); 1830 } 1831 *m_head = m; 1832 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1833 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1834 if (error != 0) { 1835 m_freem(*m_head); 1836 *m_head = NULL; 1837 return (error); 1838 } 1839 } else if (error != 0) 1840 return (error); 1841 if (nsegs == 0) { 1842 m_freem(*m_head); 1843 *m_head = NULL; 1844 return (EIO); 1845 } 1846 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1847 BUS_DMASYNC_PREWRITE); 1848 1849 desc = txc->ste_ptr; 1850 for (i = 0; i < nsegs; i++) { 1851 frag = &desc->ste_frags[i]; 1852 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1853 frag->ste_len = htole32(txsegs[i].ds_len); 1854 } 1855 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1856 /* 1857 * Because we use Tx polling we can't chain multiple 1858 * Tx descriptors here. Otherwise we race with controller. 1859 */ 1860 desc->ste_next = 0; 1861 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1862 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1863 STE_TXCTL_DMAINTR); 1864 else 1865 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1866 txc->ste_mbuf = *m_head; 1867 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1868 sc->ste_cdata.ste_tx_cnt++; 1869 1870 return (0); 1871 } 1872 1873 static void 1874 ste_start(struct ifnet *ifp) 1875 { 1876 struct ste_softc *sc; 1877 1878 sc = ifp->if_softc; 1879 STE_LOCK(sc); 1880 ste_start_locked(ifp); 1881 STE_UNLOCK(sc); 1882 } 1883 1884 static void 1885 ste_start_locked(struct ifnet *ifp) 1886 { 1887 struct ste_softc *sc; 1888 struct ste_chain *cur_tx; 1889 struct mbuf *m_head = NULL; 1890 int enq; 1891 1892 sc = ifp->if_softc; 1893 STE_LOCK_ASSERT(sc); 1894 1895 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1896 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1897 return; 1898 1899 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1900 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1901 /* 1902 * Controller may have cached copy of the last used 1903 * next ptr so we have to reserve one TFD to avoid 1904 * TFD overruns. 1905 */ 1906 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1907 break; 1908 } 1909 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1910 if (m_head == NULL) 1911 break; 1912 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1913 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1914 if (m_head == NULL) 1915 break; 1916 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1917 break; 1918 } 1919 if (sc->ste_cdata.ste_last_tx == NULL) { 1920 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1921 sc->ste_cdata.ste_tx_list_map, 1922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1923 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1924 ste_wait(sc); 1925 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1926 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1927 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1928 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1929 ste_wait(sc); 1930 } else { 1931 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1932 sc->ste_cdata.ste_last_tx->ste_phys; 1933 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1934 sc->ste_cdata.ste_tx_list_map, 1935 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1936 } 1937 sc->ste_cdata.ste_last_tx = cur_tx; 1938 1939 enq++; 1940 /* 1941 * If there's a BPF listener, bounce a copy of this frame 1942 * to him. 1943 */ 1944 BPF_MTAP(ifp, m_head); 1945 } 1946 1947 if (enq > 0) 1948 sc->ste_timer = STE_TX_TIMEOUT; 1949 } 1950 1951 static void 1952 ste_watchdog(struct ste_softc *sc) 1953 { 1954 struct ifnet *ifp; 1955 1956 ifp = sc->ste_ifp; 1957 STE_LOCK_ASSERT(sc); 1958 1959 if (sc->ste_timer == 0 || --sc->ste_timer) 1960 return; 1961 1962 ifp->if_oerrors++; 1963 if_printf(ifp, "watchdog timeout\n"); 1964 1965 ste_txeof(sc); 1966 ste_txeoc(sc); 1967 ste_rxeof(sc, -1); 1968 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1969 ste_init_locked(sc); 1970 1971 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1972 ste_start_locked(ifp); 1973 } 1974 1975 static int 1976 ste_shutdown(device_t dev) 1977 { 1978 1979 return (ste_suspend(dev)); 1980 } 1981 1982 static int 1983 ste_suspend(device_t dev) 1984 { 1985 struct ste_softc *sc; 1986 1987 sc = device_get_softc(dev); 1988 1989 STE_LOCK(sc); 1990 ste_stop(sc); 1991 ste_setwol(sc); 1992 STE_UNLOCK(sc); 1993 1994 return (0); 1995 } 1996 1997 static int 1998 ste_resume(device_t dev) 1999 { 2000 struct ste_softc *sc; 2001 struct ifnet *ifp; 2002 int pmc; 2003 uint16_t pmstat; 2004 2005 sc = device_get_softc(dev); 2006 STE_LOCK(sc); 2007 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2008 /* Disable PME and clear PME status. */ 2009 pmstat = pci_read_config(sc->ste_dev, 2010 pmc + PCIR_POWER_STATUS, 2); 2011 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2012 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2013 pci_write_config(sc->ste_dev, 2014 pmc + PCIR_POWER_STATUS, pmstat, 2); 2015 } 2016 } 2017 ifp = sc->ste_ifp; 2018 if ((ifp->if_flags & IFF_UP) != 0) { 2019 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2020 ste_init_locked(sc); 2021 } 2022 STE_UNLOCK(sc); 2023 2024 return (0); 2025 } 2026 2027 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2028 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2029 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2030 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2031 2032 static void 2033 ste_sysctl_node(struct ste_softc *sc) 2034 { 2035 struct sysctl_ctx_list *ctx; 2036 struct sysctl_oid_list *child, *parent; 2037 struct sysctl_oid *tree; 2038 struct ste_hw_stats *stats; 2039 2040 stats = &sc->ste_stats; 2041 ctx = device_get_sysctl_ctx(sc->ste_dev); 2042 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2043 2044 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2045 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2046 /* Pull in device tunables. */ 2047 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2048 resource_int_value(device_get_name(sc->ste_dev), 2049 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2050 2051 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2052 NULL, "STE statistics"); 2053 parent = SYSCTL_CHILDREN(tree); 2054 2055 /* Rx statistics. */ 2056 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2057 NULL, "Rx MAC statistics"); 2058 child = SYSCTL_CHILDREN(tree); 2059 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2060 &stats->rx_bytes, "Good octets"); 2061 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2062 &stats->rx_frames, "Good frames"); 2063 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2064 &stats->rx_bcast_frames, "Good broadcast frames"); 2065 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2066 &stats->rx_mcast_frames, "Good multicast frames"); 2067 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2068 &stats->rx_lost_frames, "Lost frames"); 2069 2070 /* Tx statistics. */ 2071 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2072 NULL, "Tx MAC statistics"); 2073 child = SYSCTL_CHILDREN(tree); 2074 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2075 &stats->tx_bytes, "Good octets"); 2076 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2077 &stats->tx_frames, "Good frames"); 2078 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2079 &stats->tx_bcast_frames, "Good broadcast frames"); 2080 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2081 &stats->tx_mcast_frames, "Good multicast frames"); 2082 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2083 &stats->tx_carrsense_errs, "Carrier sense errors"); 2084 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2085 &stats->tx_single_colls, "Single collisions"); 2086 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2087 &stats->tx_multi_colls, "Multiple collisions"); 2088 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2089 &stats->tx_late_colls, "Late collisions"); 2090 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2091 &stats->tx_frames_defered, "Frames with deferrals"); 2092 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2093 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2094 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2095 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2096 } 2097 2098 #undef STE_SYSCTL_STAT_ADD32 2099 #undef STE_SYSCTL_STAT_ADD64 2100 2101 static void 2102 ste_setwol(struct ste_softc *sc) 2103 { 2104 struct ifnet *ifp; 2105 uint16_t pmstat; 2106 uint8_t val; 2107 int pmc; 2108 2109 STE_LOCK_ASSERT(sc); 2110 2111 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2112 /* Disable WOL. */ 2113 CSR_READ_1(sc, STE_WAKE_EVENT); 2114 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2115 return; 2116 } 2117 2118 ifp = sc->ste_ifp; 2119 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2120 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2121 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2122 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2123 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2124 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2125 /* Request PME. */ 2126 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2127 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2128 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2129 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2130 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2131 }
Cache object: e2b8e8fed62add882eb246b74a13dac7
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