The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ste/if_ste.c

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/8.1/sys/dev/ste/if_ste.c 203786 2010-02-11 18:34:06Z mjacob $");
   35 
   36 #ifdef HAVE_KERNEL_OPTION_HEADERS
   37 #include "opt_device_polling.h"
   38 #endif
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/bus.h>
   43 #include <sys/endian.h>
   44 #include <sys/kernel.h>
   45 #include <sys/lock.h>
   46 #include <sys/malloc.h>
   47 #include <sys/mbuf.h>
   48 #include <sys/module.h>
   49 #include <sys/rman.h>
   50 #include <sys/socket.h>
   51 #include <sys/sockio.h>
   52 #include <sys/sysctl.h>
   53 
   54 #include <net/bpf.h>
   55 #include <net/if.h>
   56 #include <net/if_arp.h>
   57 #include <net/ethernet.h>
   58 #include <net/if_dl.h>
   59 #include <net/if_media.h>
   60 #include <net/if_types.h>
   61 #include <net/if_vlan_var.h>
   62 
   63 #include <machine/bus.h>
   64 #include <machine/resource.h>
   65 
   66 #include <dev/mii/mii.h>
   67 #include <dev/mii/miivar.h>
   68 
   69 #include <dev/pci/pcireg.h>
   70 #include <dev/pci/pcivar.h>
   71 
   72 #include <dev/ste/if_stereg.h>
   73 
   74 /* "device miibus" required.  See GENERIC if you get errors here. */
   75 #include "miibus_if.h"
   76 
   77 MODULE_DEPEND(ste, pci, 1, 1, 1);
   78 MODULE_DEPEND(ste, ether, 1, 1, 1);
   79 MODULE_DEPEND(ste, miibus, 1, 1, 1);
   80 
   81 /* Define to show Tx error status. */
   82 #define STE_SHOW_TXERRORS
   83 
   84 /*
   85  * Various supported device vendors/types and their names.
   86  */
   87 static struct ste_type ste_devs[] = {
   88         { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
   89         { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
   90         { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
   91         { 0, 0, NULL }
   92 };
   93 
   94 static int      ste_attach(device_t);
   95 static int      ste_detach(device_t);
   96 static int      ste_probe(device_t);
   97 static int      ste_resume(device_t);
   98 static int      ste_shutdown(device_t);
   99 static int      ste_suspend(device_t);
  100 
  101 static int      ste_dma_alloc(struct ste_softc *);
  102 static void     ste_dma_free(struct ste_softc *);
  103 static void     ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
  104 static int      ste_eeprom_wait(struct ste_softc *);
  105 static int      ste_encap(struct ste_softc *, struct mbuf **,
  106                     struct ste_chain *);
  107 static int      ste_ifmedia_upd(struct ifnet *);
  108 static void     ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  109 static void     ste_init(void *);
  110 static void     ste_init_locked(struct ste_softc *);
  111 static int      ste_init_rx_list(struct ste_softc *);
  112 static void     ste_init_tx_list(struct ste_softc *);
  113 static void     ste_intr(void *);
  114 static int      ste_ioctl(struct ifnet *, u_long, caddr_t);
  115 static int      ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
  116 static void     ste_mii_send(struct ste_softc *, uint32_t, int);
  117 static void     ste_mii_sync(struct ste_softc *);
  118 static int      ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
  119 static int      ste_miibus_readreg(device_t, int, int);
  120 static void     ste_miibus_statchg(device_t);
  121 static int      ste_miibus_writereg(device_t, int, int, int);
  122 static int      ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
  123 static int      ste_read_eeprom(struct ste_softc *, uint16_t *, int, int);
  124 static void     ste_reset(struct ste_softc *);
  125 static void     ste_restart_tx(struct ste_softc *);
  126 static int      ste_rxeof(struct ste_softc *, int);
  127 static void     ste_rxfilter(struct ste_softc *);
  128 static void     ste_setwol(struct ste_softc *);
  129 static void     ste_start(struct ifnet *);
  130 static void     ste_start_locked(struct ifnet *);
  131 static void     ste_stats_clear(struct ste_softc *);
  132 static void     ste_stats_update(struct ste_softc *);
  133 static void     ste_stop(struct ste_softc *);
  134 static void     ste_sysctl_node(struct ste_softc *);
  135 static void     ste_tick(void *);
  136 static void     ste_txeoc(struct ste_softc *);
  137 static void     ste_txeof(struct ste_softc *);
  138 static void     ste_wait(struct ste_softc *);
  139 static void     ste_watchdog(struct ste_softc *);
  140 
  141 static device_method_t ste_methods[] = {
  142         /* Device interface */
  143         DEVMETHOD(device_probe,         ste_probe),
  144         DEVMETHOD(device_attach,        ste_attach),
  145         DEVMETHOD(device_detach,        ste_detach),
  146         DEVMETHOD(device_shutdown,      ste_shutdown),
  147         DEVMETHOD(device_suspend,       ste_suspend),
  148         DEVMETHOD(device_resume,        ste_resume),
  149 
  150         /* bus interface */
  151         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  152         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  153 
  154         /* MII interface */
  155         DEVMETHOD(miibus_readreg,       ste_miibus_readreg),
  156         DEVMETHOD(miibus_writereg,      ste_miibus_writereg),
  157         DEVMETHOD(miibus_statchg,       ste_miibus_statchg),
  158 
  159         { 0, 0 }
  160 };
  161 
  162 static driver_t ste_driver = {
  163         "ste",
  164         ste_methods,
  165         sizeof(struct ste_softc)
  166 };
  167 
  168 static devclass_t ste_devclass;
  169 
  170 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
  171 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
  172 
  173 #define STE_SETBIT4(sc, reg, x)                         \
  174         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
  175 
  176 #define STE_CLRBIT4(sc, reg, x)                         \
  177         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
  178 
  179 #define STE_SETBIT2(sc, reg, x)                         \
  180         CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
  181 
  182 #define STE_CLRBIT2(sc, reg, x)                         \
  183         CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
  184 
  185 #define STE_SETBIT1(sc, reg, x)                         \
  186         CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
  187 
  188 #define STE_CLRBIT1(sc, reg, x)                         \
  189         CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
  190 
  191 
  192 #define MII_SET(x)              STE_SETBIT1(sc, STE_PHYCTL, x)
  193 #define MII_CLR(x)              STE_CLRBIT1(sc, STE_PHYCTL, x)
  194 
  195 /*
  196  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  197  */
  198 static void
  199 ste_mii_sync(struct ste_softc *sc)
  200 {
  201         int i;
  202 
  203         MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
  204 
  205         for (i = 0; i < 32; i++) {
  206                 MII_SET(STE_PHYCTL_MCLK);
  207                 DELAY(1);
  208                 MII_CLR(STE_PHYCTL_MCLK);
  209                 DELAY(1);
  210         }
  211 }
  212 
  213 /*
  214  * Clock a series of bits through the MII.
  215  */
  216 static void
  217 ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt)
  218 {
  219         int i;
  220 
  221         MII_CLR(STE_PHYCTL_MCLK);
  222 
  223         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  224                 if (bits & i) {
  225                         MII_SET(STE_PHYCTL_MDATA);
  226                 } else {
  227                         MII_CLR(STE_PHYCTL_MDATA);
  228                 }
  229                 DELAY(1);
  230                 MII_CLR(STE_PHYCTL_MCLK);
  231                 DELAY(1);
  232                 MII_SET(STE_PHYCTL_MCLK);
  233         }
  234 }
  235 
  236 /*
  237  * Read an PHY register through the MII.
  238  */
  239 static int
  240 ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame)
  241 {
  242         int i, ack;
  243 
  244         /*
  245          * Set up frame for RX.
  246          */
  247         frame->mii_stdelim = STE_MII_STARTDELIM;
  248         frame->mii_opcode = STE_MII_READOP;
  249         frame->mii_turnaround = 0;
  250         frame->mii_data = 0;
  251 
  252         CSR_WRITE_2(sc, STE_PHYCTL, 0);
  253         /*
  254          * Turn on data xmit.
  255          */
  256         MII_SET(STE_PHYCTL_MDIR);
  257 
  258         ste_mii_sync(sc);
  259 
  260         /*
  261          * Send command/address info.
  262          */
  263         ste_mii_send(sc, frame->mii_stdelim, 2);
  264         ste_mii_send(sc, frame->mii_opcode, 2);
  265         ste_mii_send(sc, frame->mii_phyaddr, 5);
  266         ste_mii_send(sc, frame->mii_regaddr, 5);
  267 
  268         /* Turn off xmit. */
  269         MII_CLR(STE_PHYCTL_MDIR);
  270 
  271         /* Idle bit */
  272         MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
  273         DELAY(1);
  274         MII_SET(STE_PHYCTL_MCLK);
  275         DELAY(1);
  276 
  277         /* Check for ack */
  278         MII_CLR(STE_PHYCTL_MCLK);
  279         DELAY(1);
  280         ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
  281         MII_SET(STE_PHYCTL_MCLK);
  282         DELAY(1);
  283 
  284         /*
  285          * Now try reading data bits. If the ack failed, we still
  286          * need to clock through 16 cycles to keep the PHY(s) in sync.
  287          */
  288         if (ack) {
  289                 for (i = 0; i < 16; i++) {
  290                         MII_CLR(STE_PHYCTL_MCLK);
  291                         DELAY(1);
  292                         MII_SET(STE_PHYCTL_MCLK);
  293                         DELAY(1);
  294                 }
  295                 goto fail;
  296         }
  297 
  298         for (i = 0x8000; i; i >>= 1) {
  299                 MII_CLR(STE_PHYCTL_MCLK);
  300                 DELAY(1);
  301                 if (!ack) {
  302                         if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
  303                                 frame->mii_data |= i;
  304                         DELAY(1);
  305                 }
  306                 MII_SET(STE_PHYCTL_MCLK);
  307                 DELAY(1);
  308         }
  309 
  310 fail:
  311 
  312         MII_CLR(STE_PHYCTL_MCLK);
  313         DELAY(1);
  314         MII_SET(STE_PHYCTL_MCLK);
  315         DELAY(1);
  316 
  317         if (ack)
  318                 return (1);
  319         return (0);
  320 }
  321 
  322 /*
  323  * Write to a PHY register through the MII.
  324  */
  325 static int
  326 ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame)
  327 {
  328 
  329         /*
  330          * Set up frame for TX.
  331          */
  332 
  333         frame->mii_stdelim = STE_MII_STARTDELIM;
  334         frame->mii_opcode = STE_MII_WRITEOP;
  335         frame->mii_turnaround = STE_MII_TURNAROUND;
  336 
  337         /*
  338          * Turn on data output.
  339          */
  340         MII_SET(STE_PHYCTL_MDIR);
  341 
  342         ste_mii_sync(sc);
  343 
  344         ste_mii_send(sc, frame->mii_stdelim, 2);
  345         ste_mii_send(sc, frame->mii_opcode, 2);
  346         ste_mii_send(sc, frame->mii_phyaddr, 5);
  347         ste_mii_send(sc, frame->mii_regaddr, 5);
  348         ste_mii_send(sc, frame->mii_turnaround, 2);
  349         ste_mii_send(sc, frame->mii_data, 16);
  350 
  351         /* Idle bit. */
  352         MII_SET(STE_PHYCTL_MCLK);
  353         DELAY(1);
  354         MII_CLR(STE_PHYCTL_MCLK);
  355         DELAY(1);
  356 
  357         /*
  358          * Turn off xmit.
  359          */
  360         MII_CLR(STE_PHYCTL_MDIR);
  361 
  362         return (0);
  363 }
  364 
  365 static int
  366 ste_miibus_readreg(device_t dev, int phy, int reg)
  367 {
  368         struct ste_softc *sc;
  369         struct ste_mii_frame frame;
  370 
  371         sc = device_get_softc(dev);
  372 
  373         if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0)
  374                 return (0);
  375 
  376         bzero((char *)&frame, sizeof(frame));
  377 
  378         frame.mii_phyaddr = phy;
  379         frame.mii_regaddr = reg;
  380         ste_mii_readreg(sc, &frame);
  381 
  382         return (frame.mii_data);
  383 }
  384 
  385 static int
  386 ste_miibus_writereg(device_t dev, int phy, int reg, int data)
  387 {
  388         struct ste_softc *sc;
  389         struct ste_mii_frame frame;
  390 
  391         sc = device_get_softc(dev);
  392         bzero((char *)&frame, sizeof(frame));
  393 
  394         frame.mii_phyaddr = phy;
  395         frame.mii_regaddr = reg;
  396         frame.mii_data = data;
  397 
  398         ste_mii_writereg(sc, &frame);
  399 
  400         return (0);
  401 }
  402 
  403 static void
  404 ste_miibus_statchg(device_t dev)
  405 {
  406         struct ste_softc *sc;
  407         struct mii_data *mii;
  408         struct ifnet *ifp;
  409         uint16_t cfg;
  410 
  411         sc = device_get_softc(dev);
  412 
  413         mii = device_get_softc(sc->ste_miibus);
  414         ifp = sc->ste_ifp;
  415         if (mii == NULL || ifp == NULL ||
  416             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
  417                 return;
  418 
  419         sc->ste_flags &= ~STE_FLAG_LINK;
  420         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
  421             (IFM_ACTIVE | IFM_AVALID)) {
  422                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
  423                 case IFM_10_T:
  424                 case IFM_100_TX:
  425                 case IFM_100_FX:
  426                 case IFM_100_T4:
  427                         sc->ste_flags |= STE_FLAG_LINK;
  428                 default:
  429                         break;
  430                 }
  431         }
  432 
  433         /* Program MACs with resolved speed/duplex/flow-control. */
  434         if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
  435                 cfg = CSR_READ_2(sc, STE_MACCTL0);
  436                 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
  437                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
  438                         /*
  439                          * ST201 data sheet says driver should enable receiving
  440                          * MAC control frames bit of receive mode register to
  441                          * receive flow-control frames but the register has no
  442                          * such bits. In addition the controller has no ability
  443                          * to send pause frames so it should be handled in
  444                          * driver. Implementing pause timer handling in driver
  445                          * layer is not trivial, so don't enable flow-control
  446                          * here.
  447                          */
  448                         cfg |= STE_MACCTL0_FULLDUPLEX;
  449                 }
  450                 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
  451         }
  452 }
  453 
  454 static int
  455 ste_ifmedia_upd(struct ifnet *ifp)
  456 {
  457         struct ste_softc *sc;
  458         struct mii_data *mii;
  459         struct mii_softc *miisc;
  460         int error;
  461 
  462         sc = ifp->if_softc;
  463         STE_LOCK(sc);
  464         mii = device_get_softc(sc->ste_miibus);
  465         if (mii->mii_instance) {
  466                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
  467                         mii_phy_reset(miisc);
  468         }
  469         error = mii_mediachg(mii);
  470         STE_UNLOCK(sc);
  471 
  472         return (error);
  473 }
  474 
  475 static void
  476 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
  477 {
  478         struct ste_softc *sc;
  479         struct mii_data *mii;
  480 
  481         sc = ifp->if_softc;
  482         mii = device_get_softc(sc->ste_miibus);
  483 
  484         STE_LOCK(sc);
  485         if ((ifp->if_flags & IFF_UP) == 0) {
  486                 STE_UNLOCK(sc);
  487                 return;
  488         }
  489         mii_pollstat(mii);
  490         ifmr->ifm_active = mii->mii_media_active;
  491         ifmr->ifm_status = mii->mii_media_status;
  492         STE_UNLOCK(sc);
  493 }
  494 
  495 static void
  496 ste_wait(struct ste_softc *sc)
  497 {
  498         int i;
  499 
  500         for (i = 0; i < STE_TIMEOUT; i++) {
  501                 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
  502                         break;
  503                 DELAY(1);
  504         }
  505 
  506         if (i == STE_TIMEOUT)
  507                 device_printf(sc->ste_dev, "command never completed!\n");
  508 }
  509 
  510 /*
  511  * The EEPROM is slow: give it time to come ready after issuing
  512  * it a command.
  513  */
  514 static int
  515 ste_eeprom_wait(struct ste_softc *sc)
  516 {
  517         int i;
  518 
  519         DELAY(1000);
  520 
  521         for (i = 0; i < 100; i++) {
  522                 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
  523                         DELAY(1000);
  524                 else
  525                         break;
  526         }
  527 
  528         if (i == 100) {
  529                 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
  530                 return (1);
  531         }
  532 
  533         return (0);
  534 }
  535 
  536 /*
  537  * Read a sequence of words from the EEPROM. Note that ethernet address
  538  * data is stored in the EEPROM in network byte order.
  539  */
  540 static int
  541 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt)
  542 {
  543         int err = 0, i;
  544 
  545         if (ste_eeprom_wait(sc))
  546                 return (1);
  547 
  548         for (i = 0; i < cnt; i++) {
  549                 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
  550                 err = ste_eeprom_wait(sc);
  551                 if (err)
  552                         break;
  553                 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
  554                 dest++;
  555         }
  556 
  557         return (err ? 1 : 0);
  558 }
  559 
  560 static void
  561 ste_rxfilter(struct ste_softc *sc)
  562 {
  563         struct ifnet *ifp;
  564         struct ifmultiaddr *ifma;
  565         uint32_t hashes[2] = { 0, 0 };
  566         uint8_t rxcfg;
  567         int h;
  568 
  569         STE_LOCK_ASSERT(sc);
  570 
  571         ifp = sc->ste_ifp;
  572         rxcfg = CSR_READ_1(sc, STE_RX_MODE);
  573         rxcfg |= STE_RXMODE_UNICAST;
  574         rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
  575             STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
  576         if (ifp->if_flags & IFF_BROADCAST)
  577                 rxcfg |= STE_RXMODE_BROADCAST;
  578         if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
  579                 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
  580                         rxcfg |= STE_RXMODE_ALLMULTI;
  581                 if ((ifp->if_flags & IFF_PROMISC) != 0)
  582                         rxcfg |= STE_RXMODE_PROMISC;
  583                 goto chipit;
  584         }
  585 
  586         rxcfg |= STE_RXMODE_MULTIHASH;
  587         /* Now program new ones. */
  588         if_maddr_rlock(ifp);
  589         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  590                 if (ifma->ifma_addr->sa_family != AF_LINK)
  591                         continue;
  592                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
  593                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
  594                 if (h < 32)
  595                         hashes[0] |= (1 << h);
  596                 else
  597                         hashes[1] |= (1 << (h - 32));
  598         }
  599         if_maddr_runlock(ifp);
  600 
  601 chipit:
  602         CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
  603         CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
  604         CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
  605         CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
  606         CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
  607         CSR_READ_1(sc, STE_RX_MODE);
  608 }
  609 
  610 #ifdef DEVICE_POLLING
  611 static poll_handler_t ste_poll, ste_poll_locked;
  612 
  613 static int
  614 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
  615 {
  616         struct ste_softc *sc = ifp->if_softc;
  617         int rx_npkts = 0;
  618 
  619         STE_LOCK(sc);
  620         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
  621                 rx_npkts = ste_poll_locked(ifp, cmd, count);
  622         STE_UNLOCK(sc);
  623         return (rx_npkts);
  624 }
  625 
  626 static int
  627 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
  628 {
  629         struct ste_softc *sc = ifp->if_softc;
  630         int rx_npkts;
  631 
  632         STE_LOCK_ASSERT(sc);
  633 
  634         rx_npkts = ste_rxeof(sc, count);
  635         ste_txeof(sc);
  636         ste_txeoc(sc);
  637         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
  638                 ste_start_locked(ifp);
  639 
  640         if (cmd == POLL_AND_CHECK_STATUS) {
  641                 uint16_t status;
  642 
  643                 status = CSR_READ_2(sc, STE_ISR_ACK);
  644 
  645                 if (status & STE_ISR_STATS_OFLOW)
  646                         ste_stats_update(sc);
  647 
  648                 if (status & STE_ISR_HOSTERR) {
  649                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
  650                         ste_init_locked(sc);
  651                 }
  652         }
  653         return (rx_npkts);
  654 }
  655 #endif /* DEVICE_POLLING */
  656 
  657 static void
  658 ste_intr(void *xsc)
  659 {
  660         struct ste_softc *sc;
  661         struct ifnet *ifp;
  662         uint16_t intrs, status;
  663 
  664         sc = xsc;
  665         STE_LOCK(sc);
  666         ifp = sc->ste_ifp;
  667 
  668 #ifdef DEVICE_POLLING
  669         if (ifp->if_capenable & IFCAP_POLLING) {
  670                 STE_UNLOCK(sc);
  671                 return;
  672         }
  673 #endif
  674         /* Reading STE_ISR_ACK clears STE_IMR register. */
  675         status = CSR_READ_2(sc, STE_ISR_ACK);
  676         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
  677                 STE_UNLOCK(sc);
  678                 return;
  679         }
  680 
  681         intrs = STE_INTRS;
  682         if (status == 0xFFFF || (status & intrs) == 0)
  683                 goto done;
  684 
  685         if (sc->ste_int_rx_act > 0) {
  686                 status &= ~STE_ISR_RX_DMADONE;
  687                 intrs &= ~STE_IMR_RX_DMADONE;
  688         }
  689 
  690         if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) {
  691                 ste_rxeof(sc, -1);
  692                 /*
  693                  * The controller has no ability to Rx interrupt
  694                  * moderation feature. Receiving 64 bytes frames
  695                  * from wire generates too many interrupts which in
  696                  * turn make system useless to process other useful
  697                  * things. Fortunately ST201 supports single shot
  698                  * timer so use the timer to implement Rx interrupt
  699                  * moderation in driver. This adds more register
  700                  * access but it greatly reduces number of Rx
  701                  * interrupts under high network load.
  702                  */
  703                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
  704                     (sc->ste_int_rx_mod != 0)) {
  705                         if ((status & STE_ISR_RX_DMADONE) != 0) {
  706                                 CSR_WRITE_2(sc, STE_COUNTDOWN,
  707                                     STE_TIMER_USECS(sc->ste_int_rx_mod));
  708                                 intrs &= ~STE_IMR_RX_DMADONE;
  709                                 sc->ste_int_rx_act = 1;
  710                         } else {
  711                                 intrs |= STE_IMR_RX_DMADONE;
  712                                 sc->ste_int_rx_act = 0;
  713                         }
  714                 }
  715         }
  716         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
  717                 if ((status & STE_ISR_TX_DMADONE) != 0)
  718                         ste_txeof(sc);
  719                 if ((status & STE_ISR_TX_DONE) != 0)
  720                         ste_txeoc(sc);
  721                 if ((status & STE_ISR_STATS_OFLOW) != 0)
  722                         ste_stats_update(sc);
  723                 if ((status & STE_ISR_HOSTERR) != 0) {
  724                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
  725                         ste_init_locked(sc);
  726                         STE_UNLOCK(sc);
  727                         return;
  728                 }
  729                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
  730                         ste_start_locked(ifp);
  731 done:
  732                 /* Re-enable interrupts */
  733                 CSR_WRITE_2(sc, STE_IMR, intrs);
  734         }
  735         STE_UNLOCK(sc);
  736 }
  737 
  738 /*
  739  * A frame has been uploaded: pass the resulting mbuf chain up to
  740  * the higher level protocols.
  741  */
  742 static int
  743 ste_rxeof(struct ste_softc *sc, int count)
  744 {
  745         struct mbuf *m;
  746         struct ifnet *ifp;
  747         struct ste_chain_onefrag *cur_rx;
  748         uint32_t rxstat;
  749         int total_len, rx_npkts;
  750 
  751         ifp = sc->ste_ifp;
  752 
  753         bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
  754             sc->ste_cdata.ste_rx_list_map,
  755             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
  756 
  757         cur_rx = sc->ste_cdata.ste_rx_head;
  758         for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
  759             cur_rx = cur_rx->ste_next) {
  760                 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
  761                 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
  762                         break;
  763 #ifdef DEVICE_POLLING
  764                 if (ifp->if_capenable & IFCAP_POLLING) {
  765                         if (count == 0)
  766                                 break;
  767                         count--;
  768                 }
  769 #endif
  770                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
  771                         break;
  772                 /*
  773                  * If an error occurs, update stats, clear the
  774                  * status word and leave the mbuf cluster in place:
  775                  * it should simply get re-used next time this descriptor
  776                  * comes up in the ring.
  777                  */
  778                 if (rxstat & STE_RXSTAT_FRAME_ERR) {
  779                         ifp->if_ierrors++;
  780                         cur_rx->ste_ptr->ste_status = 0;
  781                         continue;
  782                 }
  783 
  784                 /* No errors; receive the packet. */
  785                 m = cur_rx->ste_mbuf;
  786                 total_len = STE_RX_BYTES(rxstat);
  787 
  788                 /*
  789                  * Try to conjure up a new mbuf cluster. If that
  790                  * fails, it means we have an out of memory condition and
  791                  * should leave the buffer in place and continue. This will
  792                  * result in a lost packet, but there's little else we
  793                  * can do in this situation.
  794                  */
  795                 if (ste_newbuf(sc, cur_rx) != 0) {
  796                         ifp->if_iqdrops++;
  797                         cur_rx->ste_ptr->ste_status = 0;
  798                         continue;
  799                 }
  800 
  801                 m->m_pkthdr.rcvif = ifp;
  802                 m->m_pkthdr.len = m->m_len = total_len;
  803 
  804                 ifp->if_ipackets++;
  805                 STE_UNLOCK(sc);
  806                 (*ifp->if_input)(ifp, m);
  807                 STE_LOCK(sc);
  808         }
  809 
  810         if (rx_npkts > 0) {
  811                 sc->ste_cdata.ste_rx_head = cur_rx;
  812                 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
  813                     sc->ste_cdata.ste_rx_list_map,
  814                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  815         }
  816 
  817         return (rx_npkts);
  818 }
  819 
  820 static void
  821 ste_txeoc(struct ste_softc *sc)
  822 {
  823         uint16_t txstat;
  824         struct ifnet *ifp;
  825 
  826         STE_LOCK_ASSERT(sc);
  827 
  828         ifp = sc->ste_ifp;
  829 
  830         /*
  831          * STE_TX_STATUS register implements a queue of up to 31
  832          * transmit status byte. Writing an arbitrary value to the
  833          * register will advance the queue to the next transmit
  834          * status byte. This means if driver does not read
  835          * STE_TX_STATUS register after completing sending more
  836          * than 31 frames the controller would be stalled so driver
  837          * should re-wake the Tx MAC. This is the most severe
  838          * limitation of ST201 based controller.
  839          */
  840         for (;;) {
  841                 txstat = CSR_READ_2(sc, STE_TX_STATUS);
  842                 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
  843                         break;
  844                 if ((txstat & (STE_TXSTATUS_UNDERRUN |
  845                     STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
  846                     STE_TXSTATUS_STATSOFLOW)) != 0) {
  847                         ifp->if_oerrors++;
  848 #ifdef  STE_SHOW_TXERRORS
  849                         device_printf(sc->ste_dev, "TX error : 0x%b\n",
  850                             txstat & 0xFF, STE_ERR_BITS);
  851 #endif
  852                         if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
  853                             sc->ste_tx_thresh < STE_PACKET_SIZE) {
  854                                 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
  855                                 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
  856                                         sc->ste_tx_thresh = STE_PACKET_SIZE;
  857                                 device_printf(sc->ste_dev,
  858                                     "TX underrun, increasing TX"
  859                                     " start threshold to %d bytes\n",
  860                                     sc->ste_tx_thresh);
  861                                 /* Make sure to disable active DMA cycles. */
  862                                 STE_SETBIT4(sc, STE_DMACTL,
  863                                     STE_DMACTL_TXDMA_STALL);
  864                                 ste_wait(sc);
  865                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
  866                                 ste_init_locked(sc);
  867                                 break;
  868                         }
  869                         /* Restart Tx. */
  870                         ste_restart_tx(sc);
  871                 }
  872                 /*
  873                  * Advance to next status and ACK TxComplete
  874                  * interrupt. ST201 data sheet was wrong here, to
  875                  * get next Tx status, we have to write both
  876                  * STE_TX_STATUS and STE_TX_FRAMEID register.
  877                  * Otherwise controller returns the same status
  878                  * as well as not acknowledge Tx completion
  879                  * interrupt.
  880                  */
  881                 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
  882         }
  883 }
  884 
  885 static void
  886 ste_tick(void *arg)
  887 {
  888         struct ste_softc *sc;
  889         struct mii_data *mii;
  890 
  891         sc = (struct ste_softc *)arg;
  892 
  893         STE_LOCK_ASSERT(sc);
  894 
  895         mii = device_get_softc(sc->ste_miibus);
  896         mii_tick(mii);
  897         /*
  898          * ukphy(4) does not seem to generate CB that reports
  899          * resolved link state so if we know we lost a link,
  900          * explicitly check the link state.
  901          */
  902         if ((sc->ste_flags & STE_FLAG_LINK) == 0)
  903                 ste_miibus_statchg(sc->ste_dev);
  904         /*
  905          * Because we are not generating Tx completion
  906          * interrupt for every frame, reclaim transmitted
  907          * buffers here.
  908          */
  909         ste_txeof(sc);
  910         ste_txeoc(sc);
  911         ste_stats_update(sc);
  912         ste_watchdog(sc);
  913         callout_reset(&sc->ste_callout, hz, ste_tick, sc);
  914 }
  915 
  916 static void
  917 ste_txeof(struct ste_softc *sc)
  918 {
  919         struct ifnet *ifp;
  920         struct ste_chain *cur_tx;
  921         uint32_t txstat;
  922         int idx;
  923 
  924         STE_LOCK_ASSERT(sc);
  925 
  926         ifp = sc->ste_ifp;
  927         idx = sc->ste_cdata.ste_tx_cons;
  928         if (idx == sc->ste_cdata.ste_tx_prod)
  929                 return;
  930 
  931         bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
  932             sc->ste_cdata.ste_tx_list_map,
  933             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
  934 
  935         while (idx != sc->ste_cdata.ste_tx_prod) {
  936                 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
  937                 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
  938                 if ((txstat & STE_TXCTL_DMADONE) == 0)
  939                         break;
  940                 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
  941                     BUS_DMASYNC_POSTWRITE);
  942                 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
  943                 KASSERT(cur_tx->ste_mbuf != NULL,
  944                     ("%s: freeing NULL mbuf!\n", __func__));
  945                 m_freem(cur_tx->ste_mbuf);
  946                 cur_tx->ste_mbuf = NULL;
  947                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
  948                 ifp->if_opackets++;
  949                 sc->ste_cdata.ste_tx_cnt--;
  950                 STE_INC(idx, STE_TX_LIST_CNT);
  951         }
  952 
  953         sc->ste_cdata.ste_tx_cons = idx;
  954         if (sc->ste_cdata.ste_tx_cnt == 0)
  955                 sc->ste_timer = 0;
  956 }
  957 
  958 static void
  959 ste_stats_clear(struct ste_softc *sc)
  960 {
  961 
  962         STE_LOCK_ASSERT(sc);
  963 
  964         /* Rx stats. */
  965         CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
  966         CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
  967         CSR_READ_2(sc, STE_STAT_RX_FRAMES);
  968         CSR_READ_1(sc, STE_STAT_RX_BCAST);
  969         CSR_READ_1(sc, STE_STAT_RX_MCAST);
  970         CSR_READ_1(sc, STE_STAT_RX_LOST);
  971         /* Tx stats. */
  972         CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
  973         CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
  974         CSR_READ_2(sc, STE_STAT_TX_FRAMES);
  975         CSR_READ_1(sc, STE_STAT_TX_BCAST);
  976         CSR_READ_1(sc, STE_STAT_TX_MCAST);
  977         CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
  978         CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
  979         CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
  980         CSR_READ_1(sc, STE_STAT_LATE_COLLS);
  981         CSR_READ_1(sc, STE_STAT_TX_DEFER);
  982         CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
  983         CSR_READ_1(sc, STE_STAT_TX_ABORT);
  984 }
  985 
  986 static void
  987 ste_stats_update(struct ste_softc *sc)
  988 {
  989         struct ifnet *ifp;
  990         struct ste_hw_stats *stats;
  991         uint32_t val;
  992 
  993         STE_LOCK_ASSERT(sc);
  994 
  995         ifp = sc->ste_ifp;
  996         stats = &sc->ste_stats;
  997         /* Rx stats. */
  998         val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
  999             ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
 1000         val &= 0x000FFFFF;
 1001         stats->rx_bytes += val;
 1002         stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
 1003         stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
 1004         stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
 1005         stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
 1006         /* Tx stats. */
 1007         val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
 1008             ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
 1009         val &= 0x000FFFFF;
 1010         stats->tx_bytes += val;
 1011         stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
 1012         stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
 1013         stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
 1014         stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
 1015         val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
 1016         stats->tx_single_colls += val;
 1017         ifp->if_collisions += val;
 1018         val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
 1019         stats->tx_multi_colls += val;
 1020         ifp->if_collisions += val;
 1021         val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
 1022         stats->tx_late_colls += val;
 1023         ifp->if_collisions += val;
 1024         stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
 1025         stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
 1026         stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
 1027 }
 1028 
 1029 /*
 1030  * Probe for a Sundance ST201 chip. Check the PCI vendor and device
 1031  * IDs against our list and return a device name if we find a match.
 1032  */
 1033 static int
 1034 ste_probe(device_t dev)
 1035 {
 1036         struct ste_type *t;
 1037 
 1038         t = ste_devs;
 1039 
 1040         while (t->ste_name != NULL) {
 1041                 if ((pci_get_vendor(dev) == t->ste_vid) &&
 1042                     (pci_get_device(dev) == t->ste_did)) {
 1043                         device_set_desc(dev, t->ste_name);
 1044                         return (BUS_PROBE_DEFAULT);
 1045                 }
 1046                 t++;
 1047         }
 1048 
 1049         return (ENXIO);
 1050 }
 1051 
 1052 /*
 1053  * Attach the interface. Allocate softc structures, do ifmedia
 1054  * setup and ethernet/BPF attach.
 1055  */
 1056 static int
 1057 ste_attach(device_t dev)
 1058 {
 1059         struct ste_softc *sc;
 1060         struct ifnet *ifp;
 1061         uint16_t eaddr[ETHER_ADDR_LEN / 2];
 1062         int error = 0, pmc, rid;
 1063 
 1064         sc = device_get_softc(dev);
 1065         sc->ste_dev = dev;
 1066 
 1067         /*
 1068          * Only use one PHY since this chip reports multiple
 1069          * Note on the DFE-550 the PHY is at 1 on the DFE-580
 1070          * it is at 0 & 1.  It is rev 0x12.
 1071          */
 1072         if (pci_get_vendor(dev) == DL_VENDORID &&
 1073             pci_get_device(dev) == DL_DEVICEID_DL10050 &&
 1074             pci_get_revid(dev) == 0x12 )
 1075                 sc->ste_flags |= STE_FLAG_ONE_PHY;
 1076 
 1077         mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 1078             MTX_DEF);
 1079         /*
 1080          * Map control/status registers.
 1081          */
 1082         pci_enable_busmaster(dev);
 1083 
 1084         /* Prefer memory space register mapping over IO space. */
 1085         sc->ste_res_id = PCIR_BAR(1);
 1086         sc->ste_res_type = SYS_RES_MEMORY;
 1087         sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
 1088             &sc->ste_res_id, RF_ACTIVE);
 1089         if (sc->ste_res == NULL) {
 1090                 sc->ste_res_id = PCIR_BAR(0);
 1091                 sc->ste_res_type = SYS_RES_IOPORT;
 1092                 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
 1093                     &sc->ste_res_id, RF_ACTIVE);
 1094         }
 1095         if (sc->ste_res == NULL) {
 1096                 device_printf(dev, "couldn't map ports/memory\n");
 1097                 error = ENXIO;
 1098                 goto fail;
 1099         }
 1100 
 1101         /* Allocate interrupt */
 1102         rid = 0;
 1103         sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 1104             RF_SHAREABLE | RF_ACTIVE);
 1105 
 1106         if (sc->ste_irq == NULL) {
 1107                 device_printf(dev, "couldn't map interrupt\n");
 1108                 error = ENXIO;
 1109                 goto fail;
 1110         }
 1111 
 1112         callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
 1113 
 1114         /* Reset the adapter. */
 1115         ste_reset(sc);
 1116 
 1117         /*
 1118          * Get station address from the EEPROM.
 1119          */
 1120         if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) {
 1121                 device_printf(dev, "failed to read station address\n");
 1122                 error = ENXIO;
 1123                 goto fail;
 1124         }
 1125         ste_sysctl_node(sc);
 1126 
 1127         if ((error = ste_dma_alloc(sc)) != 0)
 1128                 goto fail;
 1129 
 1130         ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
 1131         if (ifp == NULL) {
 1132                 device_printf(dev, "can not if_alloc()\n");
 1133                 error = ENOSPC;
 1134                 goto fail;
 1135         }
 1136 
 1137         /* Do MII setup. */
 1138         if (mii_phy_probe(dev, &sc->ste_miibus,
 1139             ste_ifmedia_upd, ste_ifmedia_sts)) {
 1140                 device_printf(dev, "MII without any phy!\n");
 1141                 error = ENXIO;
 1142                 goto fail;
 1143         }
 1144 
 1145         ifp->if_softc = sc;
 1146         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 1147         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1148         ifp->if_ioctl = ste_ioctl;
 1149         ifp->if_start = ste_start;
 1150         ifp->if_init = ste_init;
 1151         IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
 1152         ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
 1153         IFQ_SET_READY(&ifp->if_snd);
 1154 
 1155         sc->ste_tx_thresh = STE_TXSTART_THRESH;
 1156 
 1157         /*
 1158          * Call MI attach routine.
 1159          */
 1160         ether_ifattach(ifp, (uint8_t *)eaddr);
 1161 
 1162         /*
 1163          * Tell the upper layer(s) we support long frames.
 1164          */
 1165         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 1166         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 1167         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 1168                 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
 1169         ifp->if_capenable = ifp->if_capabilities;
 1170 #ifdef DEVICE_POLLING
 1171         ifp->if_capabilities |= IFCAP_POLLING;
 1172 #endif
 1173 
 1174         /* Hook interrupt last to avoid having to lock softc */
 1175         error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
 1176             NULL, ste_intr, sc, &sc->ste_intrhand);
 1177 
 1178         if (error) {
 1179                 device_printf(dev, "couldn't set up irq\n");
 1180                 ether_ifdetach(ifp);
 1181                 goto fail;
 1182         }
 1183 
 1184 fail:
 1185         if (error)
 1186                 ste_detach(dev);
 1187 
 1188         return (error);
 1189 }
 1190 
 1191 /*
 1192  * Shutdown hardware and free up resources. This can be called any
 1193  * time after the mutex has been initialized. It is called in both
 1194  * the error case in attach and the normal detach case so it needs
 1195  * to be careful about only freeing resources that have actually been
 1196  * allocated.
 1197  */
 1198 static int
 1199 ste_detach(device_t dev)
 1200 {
 1201         struct ste_softc *sc;
 1202         struct ifnet *ifp;
 1203 
 1204         sc = device_get_softc(dev);
 1205         KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
 1206         ifp = sc->ste_ifp;
 1207 
 1208 #ifdef DEVICE_POLLING
 1209         if (ifp->if_capenable & IFCAP_POLLING)
 1210                 ether_poll_deregister(ifp);
 1211 #endif
 1212 
 1213         /* These should only be active if attach succeeded */
 1214         if (device_is_attached(dev)) {
 1215                 ether_ifdetach(ifp);
 1216                 STE_LOCK(sc);
 1217                 ste_stop(sc);
 1218                 STE_UNLOCK(sc);
 1219                 callout_drain(&sc->ste_callout);
 1220         }
 1221         if (sc->ste_miibus)
 1222                 device_delete_child(dev, sc->ste_miibus);
 1223         bus_generic_detach(dev);
 1224 
 1225         if (sc->ste_intrhand)
 1226                 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
 1227         if (sc->ste_irq)
 1228                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
 1229         if (sc->ste_res)
 1230                 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
 1231                     sc->ste_res);
 1232 
 1233         if (ifp)
 1234                 if_free(ifp);
 1235 
 1236         ste_dma_free(sc);
 1237         mtx_destroy(&sc->ste_mtx);
 1238 
 1239         return (0);
 1240 }
 1241 
 1242 struct ste_dmamap_arg {
 1243         bus_addr_t      ste_busaddr;
 1244 };
 1245 
 1246 static void
 1247 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 1248 {
 1249         struct ste_dmamap_arg *ctx;
 1250 
 1251         if (error != 0)
 1252                 return;
 1253 
 1254         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 1255 
 1256         ctx = (struct ste_dmamap_arg *)arg;
 1257         ctx->ste_busaddr = segs[0].ds_addr;
 1258 }
 1259 
 1260 static int
 1261 ste_dma_alloc(struct ste_softc *sc)
 1262 {
 1263         struct ste_chain *txc;
 1264         struct ste_chain_onefrag *rxc;
 1265         struct ste_dmamap_arg ctx;
 1266         int error, i;
 1267 
 1268         /* Create parent DMA tag. */
 1269         error = bus_dma_tag_create(
 1270             bus_get_dma_tag(sc->ste_dev), /* parent */
 1271             1, 0,                       /* alignment, boundary */
 1272             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
 1273             BUS_SPACE_MAXADDR,          /* highaddr */
 1274             NULL, NULL,                 /* filter, filterarg */
 1275             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
 1276             0,                          /* nsegments */
 1277             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
 1278             0,                          /* flags */
 1279             NULL, NULL,                 /* lockfunc, lockarg */
 1280             &sc->ste_cdata.ste_parent_tag);
 1281         if (error != 0) {
 1282                 device_printf(sc->ste_dev,
 1283                     "could not create parent DMA tag.\n");
 1284                 goto fail;
 1285         }
 1286 
 1287         /* Create DMA tag for Tx descriptor list. */
 1288         error = bus_dma_tag_create(
 1289             sc->ste_cdata.ste_parent_tag, /* parent */
 1290             STE_DESC_ALIGN, 0,          /* alignment, boundary */
 1291             BUS_SPACE_MAXADDR,          /* lowaddr */
 1292             BUS_SPACE_MAXADDR,          /* highaddr */
 1293             NULL, NULL,                 /* filter, filterarg */
 1294             STE_TX_LIST_SZ,             /* maxsize */
 1295             1,                          /* nsegments */
 1296             STE_TX_LIST_SZ,             /* maxsegsize */
 1297             0,                          /* flags */
 1298             NULL, NULL,                 /* lockfunc, lockarg */
 1299             &sc->ste_cdata.ste_tx_list_tag);
 1300         if (error != 0) {
 1301                 device_printf(sc->ste_dev,
 1302                     "could not create Tx list DMA tag.\n");
 1303                 goto fail;
 1304         }
 1305 
 1306         /* Create DMA tag for Rx descriptor list. */
 1307         error = bus_dma_tag_create(
 1308             sc->ste_cdata.ste_parent_tag, /* parent */
 1309             STE_DESC_ALIGN, 0,          /* alignment, boundary */
 1310             BUS_SPACE_MAXADDR,          /* lowaddr */
 1311             BUS_SPACE_MAXADDR,          /* highaddr */
 1312             NULL, NULL,                 /* filter, filterarg */
 1313             STE_RX_LIST_SZ,             /* maxsize */
 1314             1,                          /* nsegments */
 1315             STE_RX_LIST_SZ,             /* maxsegsize */
 1316             0,                          /* flags */
 1317             NULL, NULL,                 /* lockfunc, lockarg */
 1318             &sc->ste_cdata.ste_rx_list_tag);
 1319         if (error != 0) {
 1320                 device_printf(sc->ste_dev,
 1321                     "could not create Rx list DMA tag.\n");
 1322                 goto fail;
 1323         }
 1324 
 1325         /* Create DMA tag for Tx buffers. */
 1326         error = bus_dma_tag_create(
 1327             sc->ste_cdata.ste_parent_tag, /* parent */
 1328             1, 0,                       /* alignment, boundary */
 1329             BUS_SPACE_MAXADDR,          /* lowaddr */
 1330             BUS_SPACE_MAXADDR,          /* highaddr */
 1331             NULL, NULL,                 /* filter, filterarg */
 1332             MCLBYTES * STE_MAXFRAGS,    /* maxsize */
 1333             STE_MAXFRAGS,               /* nsegments */
 1334             MCLBYTES,                   /* maxsegsize */
 1335             0,                          /* flags */
 1336             NULL, NULL,                 /* lockfunc, lockarg */
 1337             &sc->ste_cdata.ste_tx_tag);
 1338         if (error != 0) {
 1339                 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
 1340                 goto fail;
 1341         }
 1342 
 1343         /* Create DMA tag for Rx buffers. */
 1344         error = bus_dma_tag_create(
 1345             sc->ste_cdata.ste_parent_tag, /* parent */
 1346             1, 0,                       /* alignment, boundary */
 1347             BUS_SPACE_MAXADDR,          /* lowaddr */
 1348             BUS_SPACE_MAXADDR,          /* highaddr */
 1349             NULL, NULL,                 /* filter, filterarg */
 1350             MCLBYTES,                   /* maxsize */
 1351             1,                          /* nsegments */
 1352             MCLBYTES,                   /* maxsegsize */
 1353             0,                          /* flags */
 1354             NULL, NULL,                 /* lockfunc, lockarg */
 1355             &sc->ste_cdata.ste_rx_tag);
 1356         if (error != 0) {
 1357                 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
 1358                 goto fail;
 1359         }
 1360 
 1361         /* Allocate DMA'able memory and load the DMA map for Tx list. */
 1362         error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
 1363             (void **)&sc->ste_ldata.ste_tx_list,
 1364             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
 1365             &sc->ste_cdata.ste_tx_list_map);
 1366         if (error != 0) {
 1367                 device_printf(sc->ste_dev,
 1368                     "could not allocate DMA'able memory for Tx list.\n");
 1369                 goto fail;
 1370         }
 1371         ctx.ste_busaddr = 0;
 1372         error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
 1373             sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
 1374             STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
 1375         if (error != 0 || ctx.ste_busaddr == 0) {
 1376                 device_printf(sc->ste_dev,
 1377                     "could not load DMA'able memory for Tx list.\n");
 1378                 goto fail;
 1379         }
 1380         sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
 1381 
 1382         /* Allocate DMA'able memory and load the DMA map for Rx list. */
 1383         error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
 1384             (void **)&sc->ste_ldata.ste_rx_list,
 1385             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
 1386             &sc->ste_cdata.ste_rx_list_map);
 1387         if (error != 0) {
 1388                 device_printf(sc->ste_dev,
 1389                     "could not allocate DMA'able memory for Rx list.\n");
 1390                 goto fail;
 1391         }
 1392         ctx.ste_busaddr = 0;
 1393         error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
 1394             sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
 1395             STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
 1396         if (error != 0 || ctx.ste_busaddr == 0) {
 1397                 device_printf(sc->ste_dev,
 1398                     "could not load DMA'able memory for Rx list.\n");
 1399                 goto fail;
 1400         }
 1401         sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
 1402 
 1403         /* Create DMA maps for Tx buffers. */
 1404         for (i = 0; i < STE_TX_LIST_CNT; i++) {
 1405                 txc = &sc->ste_cdata.ste_tx_chain[i];
 1406                 txc->ste_ptr = NULL;
 1407                 txc->ste_mbuf = NULL;
 1408                 txc->ste_next = NULL;
 1409                 txc->ste_phys = 0;
 1410                 txc->ste_map = NULL;
 1411                 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
 1412                     &txc->ste_map);
 1413                 if (error != 0) {
 1414                         device_printf(sc->ste_dev,
 1415                             "could not create Tx dmamap.\n");
 1416                         goto fail;
 1417                 }
 1418         }
 1419         /* Create DMA maps for Rx buffers. */
 1420         if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
 1421             &sc->ste_cdata.ste_rx_sparemap)) != 0) {
 1422                 device_printf(sc->ste_dev,
 1423                     "could not create spare Rx dmamap.\n");
 1424                 goto fail;
 1425         }
 1426         for (i = 0; i < STE_RX_LIST_CNT; i++) {
 1427                 rxc = &sc->ste_cdata.ste_rx_chain[i];
 1428                 rxc->ste_ptr = NULL;
 1429                 rxc->ste_mbuf = NULL;
 1430                 rxc->ste_next = NULL;
 1431                 rxc->ste_map = NULL;
 1432                 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
 1433                     &rxc->ste_map);
 1434                 if (error != 0) {
 1435                         device_printf(sc->ste_dev,
 1436                             "could not create Rx dmamap.\n");
 1437                         goto fail;
 1438                 }
 1439         }
 1440 
 1441 fail:
 1442         return (error);
 1443 }
 1444 
 1445 static void
 1446 ste_dma_free(struct ste_softc *sc)
 1447 {
 1448         struct ste_chain *txc;
 1449         struct ste_chain_onefrag *rxc;
 1450         int i;
 1451 
 1452         /* Tx buffers. */
 1453         if (sc->ste_cdata.ste_tx_tag != NULL) {
 1454                 for (i = 0; i < STE_TX_LIST_CNT; i++) {
 1455                         txc = &sc->ste_cdata.ste_tx_chain[i];
 1456                         if (txc->ste_map != NULL) {
 1457                                 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
 1458                                     txc->ste_map);
 1459                                 txc->ste_map = NULL;
 1460                         }
 1461                 }
 1462                 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
 1463                 sc->ste_cdata.ste_tx_tag = NULL;
 1464         }
 1465         /* Rx buffers. */
 1466         if (sc->ste_cdata.ste_rx_tag != NULL) {
 1467                 for (i = 0; i < STE_RX_LIST_CNT; i++) {
 1468                         rxc = &sc->ste_cdata.ste_rx_chain[i];
 1469                         if (rxc->ste_map != NULL) {
 1470                                 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
 1471                                     rxc->ste_map);
 1472                                 rxc->ste_map = NULL;
 1473                         }
 1474                 }
 1475                 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
 1476                         bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
 1477                             sc->ste_cdata.ste_rx_sparemap);
 1478                         sc->ste_cdata.ste_rx_sparemap = NULL;
 1479                 }
 1480                 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
 1481                 sc->ste_cdata.ste_rx_tag = NULL;
 1482         }
 1483         /* Tx descriptor list. */
 1484         if (sc->ste_cdata.ste_tx_list_tag != NULL) {
 1485                 if (sc->ste_cdata.ste_tx_list_map != NULL)
 1486                         bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
 1487                             sc->ste_cdata.ste_tx_list_map);
 1488                 if (sc->ste_cdata.ste_tx_list_map != NULL &&
 1489                     sc->ste_ldata.ste_tx_list != NULL)
 1490                         bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
 1491                             sc->ste_ldata.ste_tx_list,
 1492                             sc->ste_cdata.ste_tx_list_map);
 1493                 sc->ste_ldata.ste_tx_list = NULL;
 1494                 sc->ste_cdata.ste_tx_list_map = NULL;
 1495                 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
 1496                 sc->ste_cdata.ste_tx_list_tag = NULL;
 1497         }
 1498         /* Rx descriptor list. */
 1499         if (sc->ste_cdata.ste_rx_list_tag != NULL) {
 1500                 if (sc->ste_cdata.ste_rx_list_map != NULL)
 1501                         bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
 1502                             sc->ste_cdata.ste_rx_list_map);
 1503                 if (sc->ste_cdata.ste_rx_list_map != NULL &&
 1504                     sc->ste_ldata.ste_rx_list != NULL)
 1505                         bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
 1506                             sc->ste_ldata.ste_rx_list,
 1507                             sc->ste_cdata.ste_rx_list_map);
 1508                 sc->ste_ldata.ste_rx_list = NULL;
 1509                 sc->ste_cdata.ste_rx_list_map = NULL;
 1510                 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
 1511                 sc->ste_cdata.ste_rx_list_tag = NULL;
 1512         }
 1513         if (sc->ste_cdata.ste_parent_tag != NULL) {
 1514                 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
 1515                 sc->ste_cdata.ste_parent_tag = NULL;
 1516         }
 1517 }
 1518 
 1519 static int
 1520 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
 1521 {
 1522         struct mbuf *m;
 1523         bus_dma_segment_t segs[1];
 1524         bus_dmamap_t map;
 1525         int error, nsegs;
 1526 
 1527         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 1528         if (m == NULL)
 1529                 return (ENOBUFS);
 1530         m->m_len = m->m_pkthdr.len = MCLBYTES;
 1531         m_adj(m, ETHER_ALIGN);
 1532 
 1533         if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
 1534             sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
 1535                 m_freem(m);
 1536                 return (error);
 1537         }
 1538         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 1539 
 1540         if (rxc->ste_mbuf != NULL) {
 1541                 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
 1542                     BUS_DMASYNC_POSTREAD);
 1543                 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
 1544         }
 1545         map = rxc->ste_map;
 1546         rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
 1547         sc->ste_cdata.ste_rx_sparemap = map;
 1548         bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
 1549             BUS_DMASYNC_PREREAD);
 1550         rxc->ste_mbuf = m;
 1551         rxc->ste_ptr->ste_status = 0;
 1552         rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
 1553         rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
 1554             STE_FRAG_LAST);
 1555         return (0);
 1556 }
 1557 
 1558 static int
 1559 ste_init_rx_list(struct ste_softc *sc)
 1560 {
 1561         struct ste_chain_data *cd;
 1562         struct ste_list_data *ld;
 1563         int error, i;
 1564 
 1565         sc->ste_int_rx_act = 0;
 1566         cd = &sc->ste_cdata;
 1567         ld = &sc->ste_ldata;
 1568         bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
 1569         for (i = 0; i < STE_RX_LIST_CNT; i++) {
 1570                 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
 1571                 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
 1572                 if (error != 0)
 1573                         return (error);
 1574                 if (i == (STE_RX_LIST_CNT - 1)) {
 1575                         cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
 1576                         ld->ste_rx_list[i].ste_next =
 1577                             htole32(ld->ste_rx_list_paddr +
 1578                             (sizeof(struct ste_desc_onefrag) * 0));
 1579                 } else {
 1580                         cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
 1581                         ld->ste_rx_list[i].ste_next =
 1582                             htole32(ld->ste_rx_list_paddr +
 1583                             (sizeof(struct ste_desc_onefrag) * (i + 1)));
 1584                 }
 1585         }
 1586 
 1587         cd->ste_rx_head = &cd->ste_rx_chain[0];
 1588         bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
 1589             sc->ste_cdata.ste_rx_list_map,
 1590             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1591 
 1592         return (0);
 1593 }
 1594 
 1595 static void
 1596 ste_init_tx_list(struct ste_softc *sc)
 1597 {
 1598         struct ste_chain_data *cd;
 1599         struct ste_list_data *ld;
 1600         int i;
 1601 
 1602         cd = &sc->ste_cdata;
 1603         ld = &sc->ste_ldata;
 1604         bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
 1605         for (i = 0; i < STE_TX_LIST_CNT; i++) {
 1606                 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
 1607                 cd->ste_tx_chain[i].ste_mbuf = NULL;
 1608                 if (i == (STE_TX_LIST_CNT - 1)) {
 1609                         cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
 1610                         cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
 1611                             ld->ste_tx_list_paddr +
 1612                             (sizeof(struct ste_desc) * 0)));
 1613                 } else {
 1614                         cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
 1615                         cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
 1616                             ld->ste_tx_list_paddr +
 1617                             (sizeof(struct ste_desc) * (i + 1))));
 1618                 }
 1619         }
 1620 
 1621         cd->ste_last_tx = NULL;
 1622         cd->ste_tx_prod = 0;
 1623         cd->ste_tx_cons = 0;
 1624         cd->ste_tx_cnt = 0;
 1625 
 1626         bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
 1627             sc->ste_cdata.ste_tx_list_map,
 1628             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1629 }
 1630 
 1631 static void
 1632 ste_init(void *xsc)
 1633 {
 1634         struct ste_softc *sc;
 1635 
 1636         sc = xsc;
 1637         STE_LOCK(sc);
 1638         ste_init_locked(sc);
 1639         STE_UNLOCK(sc);
 1640 }
 1641 
 1642 static void
 1643 ste_init_locked(struct ste_softc *sc)
 1644 {
 1645         struct ifnet *ifp;
 1646         struct mii_data *mii;
 1647         uint8_t val;
 1648         int i;
 1649 
 1650         STE_LOCK_ASSERT(sc);
 1651         ifp = sc->ste_ifp;
 1652         mii = device_get_softc(sc->ste_miibus);
 1653 
 1654         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 1655                 return;
 1656 
 1657         ste_stop(sc);
 1658         /* Reset the chip to a known state. */
 1659         ste_reset(sc);
 1660 
 1661         /* Init our MAC address */
 1662         for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
 1663                 CSR_WRITE_2(sc, STE_PAR0 + i,
 1664                     ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
 1665                      IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
 1666         }
 1667 
 1668         /* Init RX list */
 1669         if (ste_init_rx_list(sc) != 0) {
 1670                 device_printf(sc->ste_dev,
 1671                     "initialization failed: no memory for RX buffers\n");
 1672                 ste_stop(sc);
 1673                 return;
 1674         }
 1675 
 1676         /* Set RX polling interval */
 1677         CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
 1678 
 1679         /* Init TX descriptors */
 1680         ste_init_tx_list(sc);
 1681 
 1682         /* Clear and disable WOL. */
 1683         val = CSR_READ_1(sc, STE_WAKE_EVENT);
 1684         val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
 1685             STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
 1686         CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
 1687 
 1688         /* Set the TX freethresh value */
 1689         CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
 1690 
 1691         /* Set the TX start threshold for best performance. */
 1692         CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
 1693 
 1694         /* Set the TX reclaim threshold. */
 1695         CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
 1696 
 1697         /* Accept VLAN length packets */
 1698         CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
 1699 
 1700         /* Set up the RX filter. */
 1701         ste_rxfilter(sc);
 1702 
 1703         /* Load the address of the RX list. */
 1704         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
 1705         ste_wait(sc);
 1706         CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
 1707             STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
 1708         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
 1709         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
 1710 
 1711         /* Set TX polling interval(defer until we TX first packet). */
 1712         CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
 1713 
 1714         /* Load address of the TX list */
 1715         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
 1716         ste_wait(sc);
 1717         CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
 1718         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
 1719         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
 1720         ste_wait(sc);
 1721         /* Select 3.2us timer. */
 1722         STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED |
 1723             STE_DMACTL_COUNTDOWN_MODE);
 1724 
 1725         /* Enable receiver and transmitter */
 1726         CSR_WRITE_2(sc, STE_MACCTL0, 0);
 1727         CSR_WRITE_2(sc, STE_MACCTL1, 0);
 1728         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
 1729         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
 1730 
 1731         /* Enable stats counters. */
 1732         STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
 1733         /* Clear stats counters. */
 1734         ste_stats_clear(sc);
 1735 
 1736         CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
 1737         CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
 1738 #ifdef DEVICE_POLLING
 1739         /* Disable interrupts if we are polling. */
 1740         if (ifp->if_capenable & IFCAP_POLLING)
 1741                 CSR_WRITE_2(sc, STE_IMR, 0);
 1742         else
 1743 #endif
 1744         /* Enable interrupts. */
 1745         CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
 1746 
 1747         sc->ste_flags &= ~STE_FLAG_LINK;
 1748         /* Switch to the current media. */
 1749         mii_mediachg(mii);
 1750 
 1751         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 1752         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1753 
 1754         callout_reset(&sc->ste_callout, hz, ste_tick, sc);
 1755 }
 1756 
 1757 static void
 1758 ste_stop(struct ste_softc *sc)
 1759 {
 1760         struct ifnet *ifp;
 1761         struct ste_chain_onefrag *cur_rx;
 1762         struct ste_chain *cur_tx;
 1763         uint32_t val;
 1764         int i;
 1765 
 1766         STE_LOCK_ASSERT(sc);
 1767         ifp = sc->ste_ifp;
 1768 
 1769         callout_stop(&sc->ste_callout);
 1770         sc->ste_timer = 0;
 1771         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
 1772 
 1773         CSR_WRITE_2(sc, STE_IMR, 0);
 1774         CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
 1775         /* Stop pending DMA. */
 1776         val = CSR_READ_4(sc, STE_DMACTL);
 1777         val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
 1778         CSR_WRITE_4(sc, STE_DMACTL, val);
 1779         ste_wait(sc);
 1780         /* Disable auto-polling. */
 1781         CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
 1782         CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
 1783         /* Nullify DMA address to stop any further DMA. */
 1784         CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
 1785         CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
 1786         /* Stop TX/RX MAC. */
 1787         val = CSR_READ_2(sc, STE_MACCTL1);
 1788         val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
 1789             STE_MACCTL1_STATS_DISABLE;
 1790         CSR_WRITE_2(sc, STE_MACCTL1, val);
 1791         for (i = 0; i < STE_TIMEOUT; i++) {
 1792                 DELAY(10);
 1793                 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
 1794                     STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
 1795                         break;
 1796         }
 1797         if (i == STE_TIMEOUT)
 1798                 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
 1799         /* Acknowledge any pending interrupts. */
 1800         CSR_READ_2(sc, STE_ISR_ACK);
 1801         ste_stats_update(sc);
 1802 
 1803         for (i = 0; i < STE_RX_LIST_CNT; i++) {
 1804                 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
 1805                 if (cur_rx->ste_mbuf != NULL) {
 1806                         bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
 1807                             cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
 1808                         bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
 1809                             cur_rx->ste_map);
 1810                         m_freem(cur_rx->ste_mbuf);
 1811                         cur_rx->ste_mbuf = NULL;
 1812                 }
 1813         }
 1814 
 1815         for (i = 0; i < STE_TX_LIST_CNT; i++) {
 1816                 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
 1817                 if (cur_tx->ste_mbuf != NULL) {
 1818                         bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
 1819                             cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
 1820                         bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
 1821                             cur_tx->ste_map);
 1822                         m_freem(cur_tx->ste_mbuf);
 1823                         cur_tx->ste_mbuf = NULL;
 1824                 }
 1825         }
 1826 }
 1827 
 1828 static void
 1829 ste_reset(struct ste_softc *sc)
 1830 {
 1831         uint32_t ctl;
 1832         int i;
 1833 
 1834         ctl = CSR_READ_4(sc, STE_ASICCTL);
 1835         ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
 1836             STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
 1837             STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
 1838             STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
 1839             STE_ASICCTL_EXTRESET_RESET;
 1840         CSR_WRITE_4(sc, STE_ASICCTL, ctl);
 1841         CSR_READ_4(sc, STE_ASICCTL);
 1842         /*
 1843          * Due to the need of accessing EEPROM controller can take
 1844          * up to 1ms to complete the global reset.
 1845          */
 1846         DELAY(1000);
 1847 
 1848         for (i = 0; i < STE_TIMEOUT; i++) {
 1849                 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
 1850                         break;
 1851                 DELAY(10);
 1852         }
 1853 
 1854         if (i == STE_TIMEOUT)
 1855                 device_printf(sc->ste_dev, "global reset never completed\n");
 1856 }
 1857 
 1858 static void
 1859 ste_restart_tx(struct ste_softc *sc)
 1860 {
 1861         uint16_t mac;
 1862         int i;
 1863 
 1864         for (i = 0; i < STE_TIMEOUT; i++) {
 1865                 mac = CSR_READ_2(sc, STE_MACCTL1);
 1866                 mac |= STE_MACCTL1_TX_ENABLE;
 1867                 CSR_WRITE_2(sc, STE_MACCTL1, mac);
 1868                 mac = CSR_READ_2(sc, STE_MACCTL1);
 1869                 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
 1870                         break;
 1871                 DELAY(10);
 1872         }
 1873 
 1874         if (i == STE_TIMEOUT)
 1875                 device_printf(sc->ste_dev, "starting Tx failed");
 1876 }
 1877 
 1878 static int
 1879 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1880 {
 1881         struct ste_softc *sc;
 1882         struct ifreq *ifr;
 1883         struct mii_data *mii;
 1884         int error = 0, mask;
 1885 
 1886         sc = ifp->if_softc;
 1887         ifr = (struct ifreq *)data;
 1888 
 1889         switch (command) {
 1890         case SIOCSIFFLAGS:
 1891                 STE_LOCK(sc);
 1892                 if ((ifp->if_flags & IFF_UP) != 0) {
 1893                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
 1894                             ((ifp->if_flags ^ sc->ste_if_flags) &
 1895                              (IFF_PROMISC | IFF_ALLMULTI)) != 0)
 1896                                 ste_rxfilter(sc);
 1897                         else
 1898                                 ste_init_locked(sc);
 1899                 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 1900                         ste_stop(sc);
 1901                 sc->ste_if_flags = ifp->if_flags;
 1902                 STE_UNLOCK(sc);
 1903                 break;
 1904         case SIOCADDMULTI:
 1905         case SIOCDELMULTI:
 1906                 STE_LOCK(sc);
 1907                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 1908                         ste_rxfilter(sc);
 1909                 STE_UNLOCK(sc);
 1910                 break;
 1911         case SIOCGIFMEDIA:
 1912         case SIOCSIFMEDIA:
 1913                 mii = device_get_softc(sc->ste_miibus);
 1914                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1915                 break;
 1916         case SIOCSIFCAP:
 1917                 STE_LOCK(sc);
 1918                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 1919 #ifdef DEVICE_POLLING
 1920                 if ((mask & IFCAP_POLLING) != 0 &&
 1921                     (IFCAP_POLLING & ifp->if_capabilities) != 0) {
 1922                         ifp->if_capenable ^= IFCAP_POLLING;
 1923                         if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
 1924                                 error = ether_poll_register(ste_poll, ifp);
 1925                                 if (error != 0) {
 1926                                         STE_UNLOCK(sc);
 1927                                         break;
 1928                                 }
 1929                                 /* Disable interrupts. */
 1930                                 CSR_WRITE_2(sc, STE_IMR, 0);
 1931                         } else {
 1932                                 error = ether_poll_deregister(ifp);
 1933                                 /* Enable interrupts. */
 1934                                 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
 1935                         }
 1936                 }
 1937 #endif /* DEVICE_POLLING */
 1938                 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
 1939                     (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
 1940                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
 1941                 STE_UNLOCK(sc);
 1942                 break;
 1943         default:
 1944                 error = ether_ioctl(ifp, command, data);
 1945                 break;
 1946         }
 1947 
 1948         return (error);
 1949 }
 1950 
 1951 static int
 1952 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
 1953 {
 1954         struct ste_frag *frag;
 1955         struct mbuf *m;
 1956         struct ste_desc *desc;
 1957         bus_dma_segment_t txsegs[STE_MAXFRAGS];
 1958         int error, i, nsegs;
 1959 
 1960         STE_LOCK_ASSERT(sc);
 1961         M_ASSERTPKTHDR((*m_head));
 1962 
 1963         error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
 1964             txc->ste_map, *m_head, txsegs, &nsegs, 0);
 1965         if (error == EFBIG) {
 1966                 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS);
 1967                 if (m == NULL) {
 1968                         m_freem(*m_head);
 1969                         *m_head = NULL;
 1970                         return (ENOMEM);
 1971                 }
 1972                 *m_head = m;
 1973                 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
 1974                     txc->ste_map, *m_head, txsegs, &nsegs, 0);
 1975                 if (error != 0) {
 1976                         m_freem(*m_head);
 1977                         *m_head = NULL;
 1978                         return (error);
 1979                 }
 1980         } else if (error != 0)
 1981                 return (error);
 1982         if (nsegs == 0) {
 1983                 m_freem(*m_head);
 1984                 *m_head = NULL;
 1985                 return (EIO);
 1986         }
 1987         bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
 1988             BUS_DMASYNC_PREWRITE);
 1989 
 1990         desc = txc->ste_ptr;
 1991         for (i = 0; i < nsegs; i++) {
 1992                 frag = &desc->ste_frags[i];
 1993                 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
 1994                 frag->ste_len = htole32(txsegs[i].ds_len);
 1995         }
 1996         desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
 1997         /*
 1998          * Because we use Tx polling we can't chain multiple
 1999          * Tx descriptors here. Otherwise we race with controller.
 2000          */
 2001         desc->ste_next = 0;
 2002         if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
 2003                 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
 2004                     STE_TXCTL_DMAINTR);
 2005         else
 2006                 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
 2007         txc->ste_mbuf = *m_head;
 2008         STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
 2009         sc->ste_cdata.ste_tx_cnt++;
 2010 
 2011         return (0);
 2012 }
 2013 
 2014 static void
 2015 ste_start(struct ifnet *ifp)
 2016 {
 2017         struct ste_softc *sc;
 2018 
 2019         sc = ifp->if_softc;
 2020         STE_LOCK(sc);
 2021         ste_start_locked(ifp);
 2022         STE_UNLOCK(sc);
 2023 }
 2024 
 2025 static void
 2026 ste_start_locked(struct ifnet *ifp)
 2027 {
 2028         struct ste_softc *sc;
 2029         struct ste_chain *cur_tx;
 2030         struct mbuf *m_head = NULL;
 2031         int enq;
 2032 
 2033         sc = ifp->if_softc;
 2034         STE_LOCK_ASSERT(sc);
 2035 
 2036         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 2037             IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
 2038                 return;
 2039 
 2040         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
 2041                 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
 2042                         /*
 2043                          * Controller may have cached copy of the last used
 2044                          * next ptr so we have to reserve one TFD to avoid
 2045                          * TFD overruns.
 2046                          */
 2047                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 2048                         break;
 2049                 }
 2050                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 2051                 if (m_head == NULL)
 2052                         break;
 2053                 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
 2054                 if (ste_encap(sc, &m_head, cur_tx) != 0) {
 2055                         if (m_head == NULL)
 2056                                 break;
 2057                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 2058                         break;
 2059                 }
 2060                 if (sc->ste_cdata.ste_last_tx == NULL) {
 2061                         bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
 2062                             sc->ste_cdata.ste_tx_list_map,
 2063                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 2064                         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
 2065                         ste_wait(sc);
 2066                         CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
 2067                             STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
 2068                         CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
 2069                         STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
 2070                         ste_wait(sc);
 2071                 } else {
 2072                         sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
 2073                             sc->ste_cdata.ste_last_tx->ste_phys;
 2074                         bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
 2075                             sc->ste_cdata.ste_tx_list_map,
 2076                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 2077                 }
 2078                 sc->ste_cdata.ste_last_tx = cur_tx;
 2079 
 2080                 enq++;
 2081                 /*
 2082                  * If there's a BPF listener, bounce a copy of this frame
 2083                  * to him.
 2084                  */
 2085                 BPF_MTAP(ifp, m_head);
 2086         }
 2087 
 2088         if (enq > 0)
 2089                 sc->ste_timer = STE_TX_TIMEOUT;
 2090 }
 2091 
 2092 static void
 2093 ste_watchdog(struct ste_softc *sc)
 2094 {
 2095         struct ifnet *ifp;
 2096 
 2097         ifp = sc->ste_ifp;
 2098         STE_LOCK_ASSERT(sc);
 2099 
 2100         if (sc->ste_timer == 0 || --sc->ste_timer)
 2101                 return;
 2102 
 2103         ifp->if_oerrors++;
 2104         if_printf(ifp, "watchdog timeout\n");
 2105 
 2106         ste_txeof(sc);
 2107         ste_txeoc(sc);
 2108         ste_rxeof(sc, -1);
 2109         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 2110         ste_init_locked(sc);
 2111 
 2112         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 2113                 ste_start_locked(ifp);
 2114 }
 2115 
 2116 static int
 2117 ste_shutdown(device_t dev)
 2118 {
 2119 
 2120         return (ste_suspend(dev));
 2121 }
 2122 
 2123 static int
 2124 ste_suspend(device_t dev)
 2125 {
 2126         struct ste_softc *sc;
 2127 
 2128         sc = device_get_softc(dev);
 2129 
 2130         STE_LOCK(sc);
 2131         ste_stop(sc);
 2132         ste_setwol(sc);
 2133         STE_UNLOCK(sc);
 2134 
 2135         return (0);
 2136 }
 2137 
 2138 static int
 2139 ste_resume(device_t dev)
 2140 {
 2141         struct ste_softc *sc;
 2142         struct ifnet *ifp;
 2143         int pmc;
 2144         uint16_t pmstat;
 2145 
 2146         sc = device_get_softc(dev);
 2147         STE_LOCK(sc);
 2148         if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
 2149                 /* Disable PME and clear PME status. */
 2150                 pmstat = pci_read_config(sc->ste_dev,
 2151                     pmc + PCIR_POWER_STATUS, 2);
 2152                 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
 2153                         pmstat &= ~PCIM_PSTAT_PMEENABLE;
 2154                         pci_write_config(sc->ste_dev,
 2155                             pmc + PCIR_POWER_STATUS, pmstat, 2);
 2156                 }
 2157         }
 2158         ifp = sc->ste_ifp;
 2159         if ((ifp->if_flags & IFF_UP) != 0) {
 2160                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 2161                 ste_init_locked(sc);
 2162         }
 2163         STE_UNLOCK(sc);
 2164 
 2165         return (0);
 2166 }
 2167 
 2168 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d)    \
 2169             SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
 2170 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
 2171             SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
 2172 
 2173 static void
 2174 ste_sysctl_node(struct ste_softc *sc)
 2175 {
 2176         struct sysctl_ctx_list *ctx;
 2177         struct sysctl_oid_list *child, *parent;
 2178         struct sysctl_oid *tree;
 2179         struct ste_hw_stats *stats;
 2180 
 2181         stats = &sc->ste_stats;
 2182         ctx = device_get_sysctl_ctx(sc->ste_dev);
 2183         child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
 2184 
 2185         SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod",
 2186             CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation");
 2187         /* Pull in device tunables. */
 2188         sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT;
 2189         resource_int_value(device_get_name(sc->ste_dev),
 2190             device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod);
 2191 
 2192         tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
 2193             NULL, "STE statistics");
 2194         parent = SYSCTL_CHILDREN(tree);
 2195 
 2196         /* Rx statistics. */
 2197         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
 2198             NULL, "Rx MAC statistics");
 2199         child = SYSCTL_CHILDREN(tree);
 2200         STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
 2201             &stats->rx_bytes, "Good octets");
 2202         STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
 2203             &stats->rx_frames, "Good frames");
 2204         STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
 2205             &stats->rx_bcast_frames, "Good broadcast frames");
 2206         STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
 2207             &stats->rx_mcast_frames, "Good multicast frames");
 2208         STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
 2209             &stats->rx_lost_frames, "Lost frames");
 2210 
 2211         /* Tx statistics. */
 2212         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
 2213             NULL, "Tx MAC statistics");
 2214         child = SYSCTL_CHILDREN(tree);
 2215         STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
 2216             &stats->tx_bytes, "Good octets");
 2217         STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
 2218             &stats->tx_frames, "Good frames");
 2219         STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
 2220             &stats->tx_bcast_frames, "Good broadcast frames");
 2221         STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
 2222             &stats->tx_mcast_frames, "Good multicast frames");
 2223         STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
 2224             &stats->tx_carrsense_errs, "Carrier sense errors");
 2225         STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
 2226             &stats->tx_single_colls, "Single collisions");
 2227         STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
 2228             &stats->tx_multi_colls, "Multiple collisions");
 2229         STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
 2230             &stats->tx_late_colls, "Late collisions");
 2231         STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
 2232             &stats->tx_frames_defered, "Frames with deferrals");
 2233         STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
 2234             &stats->tx_excess_defers, "Frames with excessive derferrals");
 2235         STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
 2236             &stats->tx_abort, "Aborted frames due to Excessive collisions");
 2237 }
 2238 
 2239 #undef STE_SYSCTL_STAT_ADD32
 2240 #undef STE_SYSCTL_STAT_ADD64
 2241 
 2242 static void
 2243 ste_setwol(struct ste_softc *sc)
 2244 {
 2245         struct ifnet *ifp;
 2246         uint16_t pmstat;
 2247         uint8_t val;
 2248         int pmc;
 2249 
 2250         STE_LOCK_ASSERT(sc);
 2251 
 2252         if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
 2253                 /* Disable WOL. */
 2254                 CSR_READ_1(sc, STE_WAKE_EVENT);
 2255                 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
 2256                 return;
 2257         }
 2258 
 2259         ifp = sc->ste_ifp;
 2260         val = CSR_READ_1(sc, STE_WAKE_EVENT);
 2261         val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
 2262             STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
 2263         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 2264                 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB;
 2265         CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
 2266         /* Request PME. */
 2267         pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2);
 2268         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
 2269         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 2270                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
 2271         pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
 2272 }

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