1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD$
35 */
36
37 /*
38 * Sundance PCI device/vendor ID for the
39 * ST201 chip.
40 */
41 #define ST_VENDORID 0x13F0
42 #define ST_DEVICEID_ST201_1 0x0200
43 #define ST_DEVICEID_ST201_2 0x0201
44
45 /*
46 * D-Link PCI device/vendor ID for the DL10050[AB] chip
47 */
48 #define DL_VENDORID 0x1186
49 #define DL_DEVICEID_DL10050 0x1002
50
51 /*
52 * Register definitions for the Sundance Technologies ST201 PCI
53 * fast ethernet controller. The register space is 128 bytes long and
54 * can be accessed using either PCI I/O space or PCI memory mapping.
55 * There are 32-bit, 16-bit and 8-bit registers.
56 */
57
58 #define STE_DMACTL 0x00
59 #define STE_TX_DMALIST_PTR 0x04
60 #define STE_TX_DMABURST_THRESH 0x08
61 #define STE_TX_DMAURG_THRESH 0x09
62 #define STE_TX_DMAPOLL_PERIOD 0x0A
63 #define STE_RX_DMASTATUS 0x0C
64 #define STE_RX_DMALIST_PTR 0x10
65 #define STE_RX_DMABURST_THRESH 0x14
66 #define STE_RX_DMAURG_THRESH 0x15
67 #define STE_RX_DMAPOLL_PERIOD 0x16
68 #define STE_COUNTDOWN 0x18
69 #define STE_DEBUGCTL 0x1A
70 #define STE_ASICCTL 0x30
71 #define STE_EEPROM_DATA 0x34
72 #define STE_EEPROM_CTL 0x36
73 #define STE_FIFOCTL 0x3A
74 #define STE_TX_STARTTHRESH 0x3C
75 #define STE_RX_EARLYTHRESH 0x3E
76 #define STE_EXT_ROMADDR 0x40
77 #define STE_EXT_ROMDATA 0x44
78 #define STE_WAKE_EVENT 0x45
79 #define STE_TX_STATUS 0x46
80 #define STE_TX_FRAMEID 0x47
81 #define STE_ISR_ACK 0x4A
82 #define STE_IMR 0x4C
83 #define STE_ISR 0x4E
84 #define STE_MACCTL0 0x50
85 #define STE_MACCTL1 0x52
86 #define STE_PAR0 0x54
87 #define STE_PAR1 0x56
88 #define STE_PAR2 0x58
89 #define STE_MAX_FRAMELEN 0x5A
90 #define STE_RX_MODE 0x5C
91 #define STE_TX_RECLAIM_THRESH 0x5D
92 #define STE_PHYCTL 0x5E
93 #define STE_MAR0 0x60
94 #define STE_MAR1 0x62
95 #define STE_MAR2 0x64
96 #define STE_MAR3 0x66
97
98 #define STE_STAT_RX_OCTETS_LO 0x68
99 #define STE_STAT_RX_OCTETS_HI 0x6A
100 #define STE_STAT_TX_OCTETS_LO 0x6C
101 #define STE_STAT_TX_OCTETS_HI 0x6E
102 #define STE_STAT_TX_FRAMES 0x70
103 #define STE_STAT_RX_FRAMES 0x72
104 #define STE_STAT_CARRIER_ERR 0x74
105 #define STE_STAT_LATE_COLLS 0x75
106 #define STE_STAT_MULTI_COLLS 0x76
107 #define STE_STAT_SINGLE_COLLS 0x77
108 #define STE_STAT_TX_DEFER 0x78
109 #define STE_STAT_RX_LOST 0x79
110 #define STE_STAT_TX_EXDEFER 0x7A
111 #define STE_STAT_TX_ABORT 0x7B
112 #define STE_STAT_TX_BCAST 0x7C
113 #define STE_STAT_RX_BCAST 0x7D
114 #define STE_STAT_TX_MCAST 0x7E
115 #define STE_STAT_RX_MCAST 0x7F
116
117 #define STE_DMACTL_RXDMA_STOPPED 0x00000001
118 #define STE_DMACTL_TXDMA_CMPREQ 0x00000002
119 #define STE_DMACTL_TXDMA_STOPPED 0x00000004
120 #define STE_DMACTL_RXDMA_COMPLETE 0x00000008
121 #define STE_DMACTL_TXDMA_COMPLETE 0x00000010
122 #define STE_DMACTL_RXDMA_STALL 0x00000100
123 #define STE_DMACTL_RXDMA_UNSTALL 0x00000200
124 #define STE_DMACTL_TXDMA_STALL 0x00000400
125 #define STE_DMACTL_TXDMA_UNSTALL 0x00000800
126 #define STE_DMACTL_TXDMA_INPROG 0x00004000
127 #define STE_DMACTL_DMA_HALTINPROG 0x00008000
128 #define STE_DMACTL_RXEARLY_ENABLE 0x00020000
129 #define STE_DMACTL_COUNTDOWN_SPEED 0x00040000
130 #define STE_DMACTL_COUNTDOWN_MODE 0x00080000
131 #define STE_DMACTL_MWI_DISABLE 0x00100000
132 #define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000
133 #define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000
134 #define STE_DMACTL_TARGET_ABORT 0x40000000
135 #define STE_DMACTL_MASTER_ABORT 0x80000000
136
137 /*
138 * TX DMA burst thresh is the number of 32-byte blocks that
139 * must be loaded into the TX Fifo before a TXDMA burst request
140 * will be issued.
141 */
142 #define STE_TXDMABURST_THRESH 0x1F
143
144 /*
145 * The number of 32-byte blocks in the TX FIFO falls below the
146 * TX DMA urgent threshold, a TX DMA urgent request will be
147 * generated.
148 */
149 #define STE_TXDMAURG_THRESH 0x3F
150
151 /*
152 * Number of 320ns intervals between polls of the TXDMA next
153 * descriptor pointer (if we're using polling mode).
154 */
155 #define STE_TXDMA_POLL_PERIOD 0x7F
156
157 #define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF
158 #define STE_RX_DMASTATUS_RXERR 0x00004000
159 #define STE_RX_DMASTATUS_DMADONE 0x00008000
160 #define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000
161 #define STE_RX_DMASTATUS_RUNT 0x00020000
162 #define STE_RX_DMASTATUS_ALIGNERR 0x00040000
163 #define STE_RX_DMASTATUS_CRCERR 0x00080000
164 #define STE_RX_DMASTATUS_GIANT 0x00100000
165 #define STE_RX_DMASTATUS_DRIBBLE 0x00800000
166 #define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000
167
168 /*
169 * RX DMA burst thresh is the number of 32-byte blocks that
170 * must be present in the RX FIFO before a RXDMA bus master
171 * request will be issued.
172 */
173 #define STE_RXDMABURST_THRESH 0xFF
174
175 /*
176 * The number of 32-byte blocks in the RX FIFO falls below the
177 * RX DMA urgent threshold, a RX DMA urgent request will be
178 * generated.
179 */
180 #define STE_RXDMAURG_THRESH 0x1F
181
182 /*
183 * Number of 320ns intervals between polls of the RXDMA complete
184 * bit in the status field on the current RX descriptor (if we're
185 * using polling mode).
186 */
187 #define STE_RXDMA_POLL_PERIOD 0x7F
188
189 #define STE_DEBUGCTL_GPIO0_CTL 0x0001
190 #define STE_DEBUGCTL_GPIO1_CTL 0x0002
191 #define STE_DEBUGCTL_GPIO0_DATA 0x0004
192 #define STE_DEBUGCTL_GPIO1_DATA 0x0008
193
194 #define STE_ASICCTL_ROMSIZE 0x00000002
195 #define STE_ASICCTL_TX_LARGEPKTS 0x00000004
196 #define STE_ASICCTL_RX_LARGEPKTS 0x00000008
197 #define STE_ASICCTL_EXTROM_DISABLE 0x00000010
198 #define STE_ASICCTL_PHYSPEED_10 0x00000020
199 #define STE_ASICCTL_PHYSPEED_100 0x00000040
200 #define STE_ASICCTL_PHYMEDIA 0x00000080
201 #define STE_ASICCTL_FORCEDCONFIG 0x00000700
202 #define STE_ASICCTL_D3RESET_DISABLE 0x00000800
203 #define STE_ASICCTL_SPEEDUPMODE 0x00002000
204 #define STE_ASICCTL_LEDMODE 0x00004000
205 #define STE_ASICCTL_RSTOUT_POLARITY 0x00008000
206 #define STE_ASICCTL_GLOBAL_RESET 0x00010000
207 #define STE_ASICCTL_RX_RESET 0x00020000
208 #define STE_ASICCTL_TX_RESET 0x00040000
209 #define STE_ASICCTL_DMA_RESET 0x00080000
210 #define STE_ASICCTL_FIFO_RESET 0x00100000
211 #define STE_ASICCTL_NETWORK_RESET 0x00200000
212 #define STE_ASICCTL_HOST_RESET 0x00400000
213 #define STE_ASICCTL_AUTOINIT_RESET 0x00800000
214 #define STE_ASICCTL_EXTRESET_RESET 0x01000000
215 #define STE_ASICCTL_SOFTINTR 0x02000000
216 #define STE_ASICCTL_RESET_BUSY 0x04000000
217
218 #define STE_EECTL_ADDR 0x00FF
219 #define STE_EECTL_OPCODE 0x0300
220 #define STE_EECTL_BUSY 0x1000
221
222 #define STE_EEOPCODE_WRITE 0x0100
223 #define STE_EEOPCODE_READ 0x0200
224 #define STE_EEOPCODE_ERASE 0x0300
225
226 #define STE_FIFOCTL_RAMTESTMODE 0x0001
227 #define STE_FIFOCTL_OVERRUNMODE 0x0200
228 #define STE_FIFOCTL_RXFIFOFULL 0x0800
229 #define STE_FIFOCTL_TX_BUSY 0x4000
230 #define STE_FIFOCTL_RX_BUSY 0x8000
231
232 /*
233 * The number of bytes that must in present in the TX FIFO before
234 * transmission begins. Value should be in increments of 4 bytes.
235 */
236 #define STE_TXSTART_THRESH 0x1FFC
237
238 /*
239 * Number of bytes that must be present in the RX FIFO before
240 * an RX EARLY interrupt is generated.
241 */
242 #define STE_RXEARLY_THRESH 0x1FFC
243
244 #define STE_WAKEEVENT_WAKEPKT_ENB 0x01
245 #define STE_WAKEEVENT_MAGICPKT_ENB 0x02
246 #define STE_WAKEEVENT_LINKEVT_ENB 0x04
247 #define STE_WAKEEVENT_WAKEPOLARITY 0x08
248 #define STE_WAKEEVENT_WAKEPKTEVENT 0x10
249 #define STE_WAKEEVENT_MAGICPKTEVENT 0x20
250 #define STE_WAKEEVENT_LINKEVENT 0x40
251 #define STE_WAKEEVENT_WAKEONLAN_ENB 0x80
252
253 #define STE_TXSTATUS_RECLAIMERR 0x02
254 #define STE_TXSTATUS_STATSOFLOW 0x04
255 #define STE_TXSTATUS_EXCESSCOLLS 0x08
256 #define STE_TXSTATUS_UNDERRUN 0x10
257 #define STE_TXSTATUS_TXINTR_REQ 0x40
258 #define STE_TXSTATUS_TXDONE 0x80
259
260 #define STE_ERR_BITS "\2" \
261 "\2RECLAIM\3STSOFLOW" \
262 "\4EXCESSCOLLS\5UNDERRUN" \
263 "\6INTREQ\7DONE"
264
265 #define STE_ISRACK_INTLATCH 0x0001
266 #define STE_ISRACK_HOSTERR 0x0002
267 #define STE_ISRACK_TX_DONE 0x0004
268 #define STE_ISRACK_MACCTL_FRAME 0x0008
269 #define STE_ISRACK_RX_DONE 0x0010
270 #define STE_ISRACK_RX_EARLY 0x0020
271 #define STE_ISRACK_SOFTINTR 0x0040
272 #define STE_ISRACK_STATS_OFLOW 0x0080
273 #define STE_ISRACK_LINKEVENT 0x0100
274 #define STE_ISRACK_TX_DMADONE 0x0200
275 #define STE_ISRACK_RX_DMADONE 0x0400
276
277 #define STE_IMR_HOSTERR 0x0002
278 #define STE_IMR_TX_DONE 0x0004
279 #define STE_IMR_MACCTL_FRAME 0x0008
280 #define STE_IMR_RX_DONE 0x0010
281 #define STE_IMR_RX_EARLY 0x0020
282 #define STE_IMR_SOFTINTR 0x0040
283 #define STE_IMR_STATS_OFLOW 0x0080
284 #define STE_IMR_LINKEVENT 0x0100
285 #define STE_IMR_TX_DMADONE 0x0200
286 #define STE_IMR_RX_DMADONE 0x0400
287
288 #define STE_INTRS \
289 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \
290 STE_IMR_TX_DONE|STE_IMR_SOFTINTR| \
291 STE_IMR_HOSTERR)
292
293 #define STE_ISR_INTLATCH 0x0001
294 #define STE_ISR_HOSTERR 0x0002
295 #define STE_ISR_TX_DONE 0x0004
296 #define STE_ISR_MACCTL_FRAME 0x0008
297 #define STE_ISR_RX_DONE 0x0010
298 #define STE_ISR_RX_EARLY 0x0020
299 #define STE_ISR_SOFTINTR 0x0040
300 #define STE_ISR_STATS_OFLOW 0x0080
301 #define STE_ISR_LINKEVENT 0x0100
302 #define STE_ISR_TX_DMADONE 0x0200
303 #define STE_ISR_RX_DMADONE 0x0400
304
305 /*
306 * Note: the Sundance manual gives the impression that the's
307 * only one 32-bit MACCTL register. In fact, there are two
308 * 16-bit registers side by side, and you have to access them
309 * separately.
310 */
311 #define STE_MACCTL0_IPG 0x0003
312 #define STE_MACCTL0_FULLDUPLEX 0x0020
313 #define STE_MACCTL0_RX_GIANTS 0x0040
314 #define STE_MACCTL0_FLOWCTL_ENABLE 0x0100
315 #define STE_MACCTL0_RX_FCS 0x0200
316 #define STE_MACCTL0_FIFOLOOPBK 0x0400
317 #define STE_MACCTL0_MACLOOPBK 0x0800
318
319 #define STE_MACCTL1_COLLDETECT 0x0001
320 #define STE_MACCTL1_CARRSENSE 0x0002
321 #define STE_MACCTL1_TX_BUSY 0x0004
322 #define STE_MACCTL1_TX_ERROR 0x0008
323 #define STE_MACCTL1_STATS_ENABLE 0x0020
324 #define STE_MACCTL1_STATS_DISABLE 0x0040
325 #define STE_MACCTL1_STATS_ENABLED 0x0080
326 #define STE_MACCTL1_TX_ENABLE 0x0100
327 #define STE_MACCTL1_TX_DISABLE 0x0200
328 #define STE_MACCTL1_TX_ENABLED 0x0400
329 #define STE_MACCTL1_RX_ENABLE 0x0800
330 #define STE_MACCTL1_RX_DISABLE 0x1000
331 #define STE_MACCTL1_RX_ENABLED 0x2000
332 #define STE_MACCTL1_PAUSED 0x4000
333
334 #define STE_IPG_96BT 0x00000000
335 #define STE_IPG_128BT 0x00000001
336 #define STE_IPG_224BT 0x00000002
337 #define STE_IPG_544BT 0x00000003
338
339 #define STE_RXMODE_UNICAST 0x01
340 #define STE_RXMODE_ALLMULTI 0x02
341 #define STE_RXMODE_BROADCAST 0x04
342 #define STE_RXMODE_PROMISC 0x08
343 #define STE_RXMODE_MULTIHASH 0x10
344 #define STE_RXMODE_ALLIPMULTI 0x20
345
346 #define STE_PHYCTL_MCLK 0x01
347 #define STE_PHYCTL_MDATA 0x02
348 #define STE_PHYCTL_MDIR 0x04
349 #define STE_PHYCTL_CLK25_DISABLE 0x08
350 #define STE_PHYCTL_DUPLEXPOLARITY 0x10
351 #define STE_PHYCTL_DUPLEXSTAT 0x20
352 #define STE_PHYCTL_SPEEDSTAT 0x40
353 #define STE_PHYCTL_LINKSTAT 0x80
354
355 #define STE_TIMER_TICKS 32
356 #define STE_TIMER_USECS(x) ((x * 10) / STE_TIMER_TICKS)
357
358 #define STE_IM_RX_TIMER_MIN 0
359 #define STE_IM_RX_TIMER_MAX 209712
360 #define STE_IM_RX_TIMER_DEFAULT 150
361
362 /*
363 * EEPROM offsets.
364 */
365 #define STE_EEADDR_CONFIGPARM 0x00
366 #define STE_EEADDR_ASICCTL 0x02
367 #define STE_EEADDR_SUBSYS_ID 0x04
368 #define STE_EEADDR_SUBVEN_ID 0x08
369
370 #define STE_EEADDR_NODE0 0x10
371 #define STE_EEADDR_NODE1 0x12
372 #define STE_EEADDR_NODE2 0x14
373
374 /* PCI registers */
375 #define STE_PCI_VENDOR_ID 0x00
376 #define STE_PCI_DEVICE_ID 0x02
377 #define STE_PCI_COMMAND 0x04
378 #define STE_PCI_STATUS 0x06
379 #define STE_PCI_CLASSCODE 0x09
380 #define STE_PCI_LATENCY_TIMER 0x0D
381 #define STE_PCI_HEADER_TYPE 0x0E
382 #define STE_PCI_LOIO 0x10
383 #define STE_PCI_LOMEM 0x14
384 #define STE_PCI_BIOSROM 0x30
385 #define STE_PCI_INTLINE 0x3C
386 #define STE_PCI_INTPIN 0x3D
387 #define STE_PCI_MINGNT 0x3E
388 #define STE_PCI_MINLAT 0x0F
389
390 #define STE_PCI_CAPID 0x50 /* 8 bits */
391 #define STE_PCI_NEXTPTR 0x51 /* 8 bits */
392 #define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
393 #define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
394
395 #define STE_PSTATE_MASK 0x0003
396 #define STE_PSTATE_D0 0x0000
397 #define STE_PSTATE_D1 0x0002
398 #define STE_PSTATE_D2 0x0002
399 #define STE_PSTATE_D3 0x0003
400 #define STE_PME_EN 0x0010
401 #define STE_PME_STATUS 0x8000
402
403 struct ste_hw_stats {
404 uint64_t rx_bytes;
405 uint32_t rx_frames;
406 uint32_t rx_bcast_frames;
407 uint32_t rx_mcast_frames;
408 uint32_t rx_lost_frames;
409 uint64_t tx_bytes;
410 uint32_t tx_frames;
411 uint32_t tx_bcast_frames;
412 uint32_t tx_mcast_frames;
413 uint32_t tx_carrsense_errs;
414 uint32_t tx_single_colls;
415 uint32_t tx_multi_colls;
416 uint32_t tx_late_colls;
417 uint32_t tx_frames_defered;
418 uint32_t tx_excess_defers;
419 uint32_t tx_abort;
420 };
421
422 struct ste_frag {
423 uint32_t ste_addr;
424 uint32_t ste_len;
425 };
426
427 #define STE_FRAG_LAST 0x80000000
428 #define STE_FRAG_LEN 0x00001FFF
429
430 /*
431 * A TFD is 16 to 512 bytes in length which means it can have up to 126
432 * fragments for a single Tx frame. Since most frames used in stack have
433 * 3-4 fragments supporting 8 fragments would be enough for normal
434 * operation. If we encounter more than 8 fragments we'll collapse them
435 * into a frame that has less than or equal to 8 fragments. Each buffer
436 * address of a fragment has no alignment limitation.
437 */
438 #define STE_MAXFRAGS 8
439
440 struct ste_desc {
441 uint32_t ste_next;
442 uint32_t ste_ctl;
443 struct ste_frag ste_frags[STE_MAXFRAGS];
444 };
445
446 /*
447 * A RFD has the same structure of TFD which in turn means hardware
448 * supports scatter operation in Rx buffer. Since we just allocate Rx
449 * buffer with m_getcl(9) there is no fragmentation at all so use
450 * single fragment for RFD.
451 */
452 struct ste_desc_onefrag {
453 uint32_t ste_next;
454 uint32_t ste_status;
455 struct ste_frag ste_frag;
456 };
457
458 #define STE_TXCTL_WORDALIGN 0x00000003
459 #define STE_TXCTL_ALIGN_DIS 0x00000001
460 #define STE_TXCTL_FRAMEID 0x000003FC
461 #define STE_TXCTL_NOCRC 0x00002000
462 #define STE_TXCTL_TXINTR 0x00008000
463 #define STE_TXCTL_DMADONE 0x00010000
464 #define STE_TXCTL_DMAINTR 0x80000000
465
466 #define STE_RXSTAT_FRAMELEN 0x00001FFF
467 #define STE_RXSTAT_FRAME_ERR 0x00004000
468 #define STE_RXSTAT_DMADONE 0x00008000
469 #define STE_RXSTAT_FIFO_OFLOW 0x00010000
470 #define STE_RXSTAT_RUNT 0x00020000
471 #define STE_RXSTAT_ALIGNERR 0x00040000
472 #define STE_RXSTAT_CRCERR 0x00080000
473 #define STE_RXSTAT_GIANT 0x00100000
474 #define STE_RXSTAT_DRIBBLEBITS 0x00800000
475 #define STE_RXSTAT_DMA_OFLOW 0x01000000
476 #define STE_RXATAT_ONEBUF 0x10000000
477
478 #define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN)
479
480 /*
481 * register space access macros
482 */
483 #define CSR_WRITE_4(sc, reg, val) \
484 bus_write_4((sc)->ste_res, reg, val)
485 #define CSR_WRITE_2(sc, reg, val) \
486 bus_write_2((sc)->ste_res, reg, val)
487 #define CSR_WRITE_1(sc, reg, val) \
488 bus_write_1((sc)->ste_res, reg, val)
489
490 #define CSR_READ_4(sc, reg) \
491 bus_read_4((sc)->ste_res, reg)
492 #define CSR_READ_2(sc, reg) \
493 bus_read_2((sc)->ste_res, reg)
494 #define CSR_READ_1(sc, reg) \
495 bus_read_1((sc)->ste_res, reg)
496
497 #define CSR_BARRIER(sc, reg, length, flags) \
498 bus_barrier((sc)->ste_res, reg, length, flags)
499
500 #define STE_DESC_ALIGN 8
501 #define STE_RX_LIST_CNT 128
502 #define STE_TX_LIST_CNT 128
503 #define STE_RX_LIST_SZ \
504 (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT)
505 #define STE_TX_LIST_SZ \
506 (sizeof(struct ste_desc) * STE_TX_LIST_CNT)
507 #define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
508 #define STE_ADDR_HI(x) ((uint64_t)(x) >> 32)
509
510 /*
511 * Since Tx status can hold up to 31 status bytes we should
512 * check Tx status before controller fills it up. Otherwise
513 * Tx MAC stalls.
514 */
515 #define STE_TX_INTR_FRAMES 16
516 #define STE_TX_TIMEOUT 5
517 #define STE_TIMEOUT 1000
518 #define STE_MIN_FRAMELEN 60
519 #define STE_PACKET_SIZE 1536
520 #define STE_INC(x, y) (x) = (x + 1) % y
521 #define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y)
522 #define STE_NEXT(x, y) (x + 1) % y
523
524 struct ste_type {
525 uint16_t ste_vid;
526 uint16_t ste_did;
527 const char *ste_name;
528 };
529
530 struct ste_list_data {
531 struct ste_desc_onefrag *ste_rx_list;
532 bus_addr_t ste_rx_list_paddr;
533 struct ste_desc *ste_tx_list;
534 bus_addr_t ste_tx_list_paddr;
535 };
536
537 struct ste_chain {
538 struct ste_desc *ste_ptr;
539 struct mbuf *ste_mbuf;
540 struct ste_chain *ste_next;
541 uint32_t ste_phys;
542 bus_dmamap_t ste_map;
543 };
544
545 struct ste_chain_onefrag {
546 struct ste_desc_onefrag *ste_ptr;
547 struct mbuf *ste_mbuf;
548 struct ste_chain_onefrag *ste_next;
549 bus_dmamap_t ste_map;
550 };
551
552 struct ste_chain_data {
553 bus_dma_tag_t ste_parent_tag;
554 bus_dma_tag_t ste_rx_tag;
555 bus_dma_tag_t ste_tx_tag;
556 bus_dma_tag_t ste_rx_list_tag;
557 bus_dmamap_t ste_rx_list_map;
558 bus_dma_tag_t ste_tx_list_tag;
559 bus_dmamap_t ste_tx_list_map;
560 bus_dmamap_t ste_rx_sparemap;
561 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT];
562 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT];
563 struct ste_chain_onefrag *ste_rx_head;
564 struct ste_chain *ste_last_tx;
565 int ste_tx_prod;
566 int ste_tx_cons;
567 int ste_tx_cnt;
568 };
569
570 struct ste_softc {
571 struct ifnet *ste_ifp;
572 struct resource *ste_res;
573 int ste_res_id;
574 int ste_res_type;
575 struct resource *ste_irq;
576 void *ste_intrhand;
577 struct ste_type *ste_info;
578 device_t ste_miibus;
579 device_t ste_dev;
580 int ste_tx_thresh;
581 int ste_flags;
582 #define STE_FLAG_ONE_PHY 0x0001
583 #define STE_FLAG_LINK 0x8000
584 int ste_if_flags;
585 int ste_timer;
586 int ste_int_rx_act;
587 int ste_int_rx_mod;
588 struct ste_list_data ste_ldata;
589 struct ste_chain_data ste_cdata;
590 struct callout ste_callout;
591 struct ste_hw_stats ste_stats;
592 struct mtx ste_mtx;
593 };
594
595 #define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx)
596 #define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx)
597 #define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED)
Cache object: ed5ef6ac26f5be379c09a9779f35ae4c
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