1 /* $FreeBSD: releng/11.2/sys/dev/stg/tmc18c30reg.h 331722 2018-03-29 02:50:57Z eadler $ */
2 /* $NecBSD: tmc18c30reg.h,v 1.4.24.1 2001/06/08 06:27:50 honda Exp $ */
3 /* $NetBSD$ */
4
5 /*-
6 * [NetBSD for NEC PC-98 series]
7 * Copyright (c) 1996, 1997, 1998
8 * NetBSD/pc98 porting staff. All rights reserved.
9 * Copyright (c) 1996, 1997, 1998
10 * Kouichi Matsuda. All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
32 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #ifndef _TMC18C30REG_H_
37 #define _TMC18C30REG_H_
38
39 #define tmc_wdata 0x00
40 #define tmc_rdata 0x00
41
42 #define tmc_bctl 0x01
43 #define BCTL_BUSFREE 0x00
44 #define BCTL_RST 0x01
45 #define BCTL_SEL 0x02
46 #define BCTL_BSY 0x04
47 #define BCTL_ATN 0x08
48 #define BCTL_IO 0x10
49 #define BCTL_CD 0x20
50 #define BCTL_MSG 0x40
51 #define BCTL_BUSEN 0x80
52 #define tmc_bstat 0x01
53 #define BSTAT_BSY 0x01
54 #define BSTAT_MSG 0x02
55 #define BSTAT_IO 0x04
56 #define BSTAT_CMD 0x08
57 #define BSTAT_REQ 0x10
58 #define BSTAT_SEL 0x20
59 #define BSTAT_ACK 0x40
60
61 #define tmc_ictl 0x02
62 #define ICTL_FIFO 0x10
63 #define ICTL_ARBIT 0x20
64 #define ICTL_SEL 0x40
65 #define ICTL_CD 0x80
66 #define ICTL_ALLINT (ICTL_ARBIT | ICTL_CD | ICTL_SEL | ICTL_FIFO)
67 #define tmc_astat 0x02
68 #define ASTAT_INT 0x01
69 #define ASTAT_ARBIT 0x02
70 #define ASTAT_PARERR 0x04
71 #define ASTAT_SCSIRST 0x08
72 #define ASTAT_STATMASK 0x0f
73 #define ASTAT_FIFODIR 0x10
74 #define ASTAT_FIFOEN 0x20
75 #define ASTAT_PARENB 0x40
76 #define ASTAT_BUSEN 0x80
77
78 #define tmc_ssctl 0x03
79 #define SSCTL_FSYNCHEN 0x40
80 #define SSCTL_SYNCHEN 0x80
81 #define tmc_fstat 0x03
82
83 #define tmc_fctl 0x04
84 #define FCTL_CLRFIFO 0x01
85 #define FCTL_ARBIT 0x04
86 #define FCTL_PARENB 0x08
87 #define FCTL_INTEN 0x10
88 #define FCTL_CLRINT 0x20
89 #define FCTL_FIFOW 0x40
90 #define FCTL_FIFOEN 0x80
91 #define tmc_icnd 0x04
92
93 #define tmc_mctl 0x05
94 #define tmc_idlsb 0x05
95
96 #define tmc_idmsb 0x06
97
98 #define tmc_wlb 0x07
99 #define tmc_rlb 0x07
100
101 #define tmc_scsiid 0x08
102 #define tmc_sdna 0x08
103
104 #define tmc_istat 0x09
105 #define ISTAT_INTEN 0x08
106 #define ISTAT_FIFO 0x10
107 #define ISTAT_ARBIT 0x20
108 #define ISTAT_SEL 0x40
109 #define ISTAT_CD 0x80
110
111 #define tmc_cfg1 0x0a
112
113 #define tmc_ioctl 0x0b
114 #define IOCTL_IO32 0x80
115 #define tmc_cfg2 0x0b
116
117 #define tmc_wfifo 0x0c
118 #define tmc_rfifo 0x0c
119
120 #define tmc_fdcnt 0x0e
121
122 /* Information transfer phases */
123 #define BUSFREE_PHASE 0x00
124 #define DATA_OUT_PHASE (BSTAT_BSY)
125 #define DATA_IN_PHASE (BSTAT_BSY|BSTAT_IO)
126 #define COMMAND_PHASE (BSTAT_CMD|BSTAT_BSY)
127 #define STATUS_PHASE (BSTAT_CMD|BSTAT_BSY|BSTAT_IO)
128 #define MESSAGE_OUT_PHASE (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY)
129 #define MESSAGE_IN_PHASE (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY|BSTAT_IO)
130 #define PHASE_RESELECTED (BSTAT_SEL|BSTAT_IO)
131
132 #define BSTAT_PHMASK (BSTAT_MSG | BSTAT_IO | BSTAT_CMD)
133 #define PHASE_MASK (BSTAT_SEL | BSTAT_BSY | BSTAT_PHMASK)
134 #define RESEL_PHASE_MASK (BSTAT_SEL | BSTAT_PHMASK)
135
136 #define STG_IS_PHASE_DATA(st) \
137 ((((st) & PHASE_MASK) & ~BSTAT_IO) == BSTAT_BSY)
138
139 /* chip type */
140 #define TMCCHIP_UNK 0x00
141 #define TMCCHIP_1800 0x01
142 #define TMCCHIP_18C50 0x02
143 #define TMCCHIP_18C30 0x03
144
145 #define STGIOSZ 0x10
146
147 #endif /* !_TMC18C30REG_H_ */
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