Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/stg/tmc18c30reg.h
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1 /* $FreeBSD: releng/12.0/sys/dev/stg/tmc18c30reg.h 326255 2017-11-27 14:52:40Z pfg $ */ 2 /* $NecBSD: tmc18c30reg.h,v 1.4.24.1 2001/06/08 06:27:50 honda Exp $ */ 3 /* $NetBSD$ */ 4 5 /*- 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * [NetBSD for NEC PC-98 series] 9 * Copyright (c) 1996, 1997, 1998 10 * NetBSD/pc98 porting staff. All rights reserved. 11 * Copyright (c) 1996, 1997, 1998 12 * Kouichi Matsuda. All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _TMC18C30REG_H_ 39 #define _TMC18C30REG_H_ 40 41 #define tmc_wdata 0x00 42 #define tmc_rdata 0x00 43 44 #define tmc_bctl 0x01 45 #define BCTL_BUSFREE 0x00 46 #define BCTL_RST 0x01 47 #define BCTL_SEL 0x02 48 #define BCTL_BSY 0x04 49 #define BCTL_ATN 0x08 50 #define BCTL_IO 0x10 51 #define BCTL_CD 0x20 52 #define BCTL_MSG 0x40 53 #define BCTL_BUSEN 0x80 54 #define tmc_bstat 0x01 55 #define BSTAT_BSY 0x01 56 #define BSTAT_MSG 0x02 57 #define BSTAT_IO 0x04 58 #define BSTAT_CMD 0x08 59 #define BSTAT_REQ 0x10 60 #define BSTAT_SEL 0x20 61 #define BSTAT_ACK 0x40 62 63 #define tmc_ictl 0x02 64 #define ICTL_FIFO 0x10 65 #define ICTL_ARBIT 0x20 66 #define ICTL_SEL 0x40 67 #define ICTL_CD 0x80 68 #define ICTL_ALLINT (ICTL_ARBIT | ICTL_CD | ICTL_SEL | ICTL_FIFO) 69 #define tmc_astat 0x02 70 #define ASTAT_INT 0x01 71 #define ASTAT_ARBIT 0x02 72 #define ASTAT_PARERR 0x04 73 #define ASTAT_SCSIRST 0x08 74 #define ASTAT_STATMASK 0x0f 75 #define ASTAT_FIFODIR 0x10 76 #define ASTAT_FIFOEN 0x20 77 #define ASTAT_PARENB 0x40 78 #define ASTAT_BUSEN 0x80 79 80 #define tmc_ssctl 0x03 81 #define SSCTL_FSYNCHEN 0x40 82 #define SSCTL_SYNCHEN 0x80 83 #define tmc_fstat 0x03 84 85 #define tmc_fctl 0x04 86 #define FCTL_CLRFIFO 0x01 87 #define FCTL_ARBIT 0x04 88 #define FCTL_PARENB 0x08 89 #define FCTL_INTEN 0x10 90 #define FCTL_CLRINT 0x20 91 #define FCTL_FIFOW 0x40 92 #define FCTL_FIFOEN 0x80 93 #define tmc_icnd 0x04 94 95 #define tmc_mctl 0x05 96 #define tmc_idlsb 0x05 97 98 #define tmc_idmsb 0x06 99 100 #define tmc_wlb 0x07 101 #define tmc_rlb 0x07 102 103 #define tmc_scsiid 0x08 104 #define tmc_sdna 0x08 105 106 #define tmc_istat 0x09 107 #define ISTAT_INTEN 0x08 108 #define ISTAT_FIFO 0x10 109 #define ISTAT_ARBIT 0x20 110 #define ISTAT_SEL 0x40 111 #define ISTAT_CD 0x80 112 113 #define tmc_cfg1 0x0a 114 115 #define tmc_ioctl 0x0b 116 #define IOCTL_IO32 0x80 117 #define tmc_cfg2 0x0b 118 119 #define tmc_wfifo 0x0c 120 #define tmc_rfifo 0x0c 121 122 #define tmc_fdcnt 0x0e 123 124 /* Information transfer phases */ 125 #define BUSFREE_PHASE 0x00 126 #define DATA_OUT_PHASE (BSTAT_BSY) 127 #define DATA_IN_PHASE (BSTAT_BSY|BSTAT_IO) 128 #define COMMAND_PHASE (BSTAT_CMD|BSTAT_BSY) 129 #define STATUS_PHASE (BSTAT_CMD|BSTAT_BSY|BSTAT_IO) 130 #define MESSAGE_OUT_PHASE (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY) 131 #define MESSAGE_IN_PHASE (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY|BSTAT_IO) 132 #define PHASE_RESELECTED (BSTAT_SEL|BSTAT_IO) 133 134 #define BSTAT_PHMASK (BSTAT_MSG | BSTAT_IO | BSTAT_CMD) 135 #define PHASE_MASK (BSTAT_SEL | BSTAT_BSY | BSTAT_PHMASK) 136 #define RESEL_PHASE_MASK (BSTAT_SEL | BSTAT_PHMASK) 137 138 #define STG_IS_PHASE_DATA(st) \ 139 ((((st) & PHASE_MASK) & ~BSTAT_IO) == BSTAT_BSY) 140 141 /* chip type */ 142 #define TMCCHIP_UNK 0x00 143 #define TMCCHIP_1800 0x01 144 #define TMCCHIP_18C50 0x02 145 #define TMCCHIP_18C30 0x03 146 147 #define STGIOSZ 0x10 148 149 #endif /* !_TMC18C30REG_H_ */
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