The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/sun/cgsixreg.h

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    1 /*      $NetBSD: cgsixreg.h,v 1.5 2003/08/07 16:31:23 agc Exp $ */
    2 
    3 /*
    4  * Copyright (c) 1993
    5  *      The Regents of the University of California.  All rights reserved.
    6  *
    7  * This software was developed by the Computer Systems Engineering group
    8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
    9  * contributed to Berkeley.
   10  *
   11  * All advertising materials mentioning features or use of this software
   12  * must display the following acknowledgement:
   13  *      This product includes software developed by the University of
   14  *      California, Lawrence Berkeley Laboratory.
   15  *
   16  * Redistribution and use in source and binary forms, with or without
   17  * modification, are permitted provided that the following conditions
   18  * are met:
   19  * 1. Redistributions of source code must retain the above copyright
   20  *    notice, this list of conditions and the following disclaimer.
   21  * 2. Redistributions in binary form must reproduce the above copyright
   22  *    notice, this list of conditions and the following disclaimer in the
   23  *    documentation and/or other materials provided with the distribution.
   24  * 3. Neither the name of the University nor the names of its contributors
   25  *    may be used to endorse or promote products derived from this software
   26  *    without specific prior written permission.
   27  *
   28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   38  * SUCH DAMAGE.
   39  *
   40  *      @(#)cgsixreg.h  8.4 (Berkeley) 1/21/94
   41  */
   42 
   43 /*
   44  * CG6 display registers.  (Note, I got tired of writing `cgsix' about
   45  * halfway through and changed everything to cg6, but I probably missed
   46  * some.  Unfortunately, the way config works, we need to spell out `six'
   47  * in some places anyway.)
   48  *
   49  * The cg6 is a complicated beastie.  We have been unable to extract any
   50  * documentation and most of the following are guesses based on a limited
   51  * amount of reverse engineering.
   52  *
   53  * A cg6 is composed of numerous groups of control registers, all with TLAs:
   54  *      FBC - frame buffer control?
   55  *      FHC - fbc hardware configuration / control? register (32 bits)
   56  *      DHC - ???
   57  *      TEC - transform engine control?
   58  *      THC - TEC Hardware Configuration
   59  *      ROM - a 64Kbyte ROM with who knows what in it.
   60  *      colormap - see below
   61  *      frame buffer memory (video RAM)
   62  *      possible other stuff
   63  *
   64  * Like the cg3, the cg6 uses a Brooktree Video DAC (see btreg.h).
   65  *
   66  * Various revisions of the cgsix have various hardware bugs.  So far,
   67  * we have only seen rev 1 & 2.
   68  */
   69 
   70 /* Control register banks offsets */
   71 #define CGSIX_ROM_OFFSET        0x000000
   72 #define CGSIX_BT_OFFSET         0x200000
   73 #define CGSIX_DHC_OFFSET        0x240000
   74 #define CGSIX_ALT_OFFSET        0x280000
   75 #define CGSIX_FHC_OFFSET        0x300000
   76 #define CGSIX_THC_OFFSET        0x301000
   77 #define CGSIX_FBC_OFFSET        0x700000
   78 #define CGSIX_TEC_OFFSET        0x701000
   79 #define CGSIX_RAM_OFFSET        0x800000
   80 
   81 /* bits in FHC register */
   82 #define FHC_FBID_MASK   0xff000000      /* bits 24..31 are frame buffer ID */
   83 #define FHC_FBID_SHIFT  24
   84 #define FHC_REV_MASK    0x00f00000      /* bits 20..23 are revision */
   85 #define FHC_REV_SHIFT   20
   86 #define FHC_FROP_DISABLE 0x00080000     /* disable fast/font? rasterops */
   87 #define FHC_ROW_DISABLE 0x00040000      /* ??? */
   88 #define FHC_SRC_DISABLE 0x00020000      /* ??? */
   89 #define FHC_DST_DISABLE 0x00010000      /* disable destination cache */
   90 #define FHC_RESET       0x00008000      /* ??? */
   91 #define FHC_XXX0        0x00004000      /* ??? */
   92 #define FHC_LEBO        0x00002000      /* set little endian byte order? */
   93 #define FHC_RES_MASK    0x00001800      /* bits 11&12 are resolution */
   94 #define FHC_RES_1024     0x00000000             /* res = 1024x768 */
   95 #define FHC_RES_1152     0x00000800             /* res = 1152x900 */
   96 #define FHC_RES_1280     0x00001000             /* res = 1280x1024 */
   97 #define FHC_RES_1600     0x00001800             /* res = 1600x1200 */
   98 #define FHC_CPU_MASK    0x00000600      /* bits 9&10 are cpu type */
   99 #define FHC_CPU_SPARC    0x00000000             /* cpu = sparc */
  100 #define FHC_CPU_68020    0x00000200             /* cpu = 68020 */
  101 #define FHC_CPU_386      0x00000400             /* cpu = 80386 */
  102 #define FHC_CPU_XXX      0x00000600             /* ??? */
  103 #define FHC_TEST        0x00000100      /* ??? test window ??? */
  104 #define FHC_TESTX_MASK  0x000000f0      /* bits 4..7 are test window X */
  105 #define FHC_TESTX_SHIFT 4
  106 #define FHC_TESTY_MASK  0x0000000f      /* bits 0..3 are test window Y */
  107 #define FHC_TESTY_SHIFT 0
  108 
  109 /*
  110  * The layout of the THC.
  111  */
  112 struct cg6_thc {
  113         u_int32_t       thc_xxx0[512];  /* ??? */
  114         u_int32_t       thc_hsync1;     /* horizontal sync timing */
  115         u_int32_t       thc_hsync2;     /* more hsync timing */
  116         u_int32_t       thc_hsync3;     /* yet more hsync timing */
  117         u_int32_t       thc_vsync1;     /* vertical sync timing */
  118         u_int32_t       thc_vsync2;     /* only two of these */
  119         u_int32_t       thc_refresh;    /* refresh counter */
  120         u_int32_t       thc_misc;       /* miscellaneous control & status */
  121         u_int32_t       thc_xxx1[56];   /* ??? */
  122         u_int32_t       thc_cursxy;     /* cursor x,y position (16 bits each) */
  123         u_int32_t       thc_cursmask[32];/* cursor mask bits */
  124         u_int32_t       thc_cursbits[32];/* what to show where mask enabled */
  125 };
  126 
  127 /* bits in thc_misc */
  128 #define THC_MISC_XXX0           0xfff00000      /* unused */
  129 #define THC_MISC_REVMASK        0x000f0000      /* cg6 revision? */
  130 #define THC_MISC_REVSHIFT       16
  131 #define THC_MISC_XXX1           0x0000e000      /* unused */
  132 #define THC_MISC_RESET          0x00001000      /* ??? */
  133 #define THC_MISC_XXX2           0x00000800      /* unused */
  134 #define THC_MISC_VIDEN          0x00000400      /* video enable */
  135 #define THC_MISC_SYNC           0x00000200      /* not sure what ... */
  136 #define THC_MISC_VSYNC          0x00000100      /* ... these really are */
  137 #define THC_MISC_SYNCEN         0x00000080      /* sync enable */
  138 #define THC_MISC_CURSRES        0x00000040      /* cursor resolution */
  139 #define THC_MISC_INTEN          0x00000020      /* v.retrace intr enable */
  140 #define THC_MISC_INTR           0x00000010      /* intr pending / ack bit */
  141 #define THC_MISC_XXX            0x0000000f      /* ??? */
  142 
  143 /* cursor x / y position value for `off' */
  144 #define THC_CURSOFF     (65536-32)      /* i.e., USHRT_MAX+1-32 */
  145 
  146 /*
  147  * Partial description of TEC (needed to get around FHC rev 1 bugs).
  148  */
  149 struct cg6_tec_xxx {
  150         u_int32_t       tec_mv;         /* matrix stuff */
  151         u_int32_t       tec_clip;       /* clipping stuff */
  152         u_int32_t       tec_vdc;        /* ??? */
  153 };
  154 
  155 /*
  156  * Partial description of FBC
  157  *
  158  * Most of this we don't care about; here are only the portions
  159  * we need, most notably the blitter.  Comments are merely my
  160  * best guesses as to register functions, based largely on the
  161  * X11R6.4 sunGX code.  Some of these are here only so we can
  162  * stuff canned values in them (eg, offx).
  163  */
  164 struct cg6_fbc {
  165         u_int32_t fbc_pad1[1];
  166         u_int32_t fbc_mode;             /* mode setting */
  167         u_int32_t fbc_clip;             /* function unknown */
  168         u_int32_t fbc_pad2[1];
  169         u_int32_t fbc_s;                /* global status */
  170         u_int32_t fbc_draw;             /* drawing pipeline status */
  171         u_int32_t fbc_blit;             /* blitter status */
  172         u_int32_t fbc_pad3[25];
  173         u_int32_t fbc_x0;               /* blitter, src llx */
  174         u_int32_t fbc_y0;               /* blitter, src lly */
  175         u_int32_t fbc_pad4[2];
  176         u_int32_t fbc_x1;               /* blitter, src urx */
  177         u_int32_t fbc_y1;               /* blitter, src ury */
  178         u_int32_t fbc_pad5[2];
  179         u_int32_t fbc_x2;               /* blitter, dst llx */
  180         u_int32_t fbc_y2;               /* blitter, dst lly */
  181         u_int32_t fbc_pad6[2];
  182         u_int32_t fbc_x3;               /* blitter, dst urx */
  183         u_int32_t fbc_y3;               /* blitter, dst ury */
  184         u_int32_t fbc_pad7[2];
  185         u_int32_t fbc_offx;             /* x offset for drawing */
  186         u_int32_t fbc_offy;             /* y offset for drawing */
  187         u_int32_t fbc_pad8[6];
  188         u_int32_t fbc_clipminx;         /* clip rectangle llx */
  189         u_int32_t fbc_clipminy;         /* clip rectangle lly */
  190         u_int32_t fbc_pad9[2];
  191         u_int32_t fbc_clipmaxx;         /* clip rectangle urx */
  192         u_int32_t fbc_clipmaxy;         /* clip rectangle ury */
  193         u_int32_t fbc_pad10[2];
  194         u_int32_t fbc_fg;               /* fg value for rop */
  195         u_int32_t fbc_pad11[1];
  196         u_int32_t fbc_alu;              /* operation to be performed */
  197         u_int32_t fbc_pad12[509];
  198         u_int32_t fbc_arectx;           /* rectangle drawing, x coord */
  199         u_int32_t fbc_arecty;           /* rectangle drawing, y coord */
  200         /* actually much more, but nothing more we need */
  201 };
  202 
  203 #if _CG6_LAYOUT_NOT_USED_ANYMORE
  204 /*
  205  * This structure exists only to compute the layout of the CG6
  206  * hardware.  Each of the individual substructures lives on a
  207  * separate `page' (where a `page' is at least 4K), and many are
  208  * very far apart.  We avoid large offsets (which make for lousy
  209  * code) by using pointers to the individual interesting pieces,
  210  * and map them in independently (to avoid using up PTEs unnecessarily).
  211  */
  212 struct cg6_layout {
  213         /* ROM at 0 */
  214         union {
  215                 int un_id;              /* ID = ?? */
  216                 char un_rom[65536];     /* 64K rom */
  217                 char un_pad[0x200000];
  218         } cg6_rom_un;
  219 
  220         /* Brooktree DAC at 0x200000 */
  221         union {
  222                 struct bt_regs un_btregs;
  223                 char un_pad[0x040000];
  224         } cg6_bt_un;
  225 
  226         /* DHC, whatever that is, at 0x240000 */
  227         union {
  228                 char un_pad[0x40000];
  229         } cg6_dhc_un;
  230 
  231         /* ALT, whatever that is, at 0x280000 */
  232         union {
  233                 char un_pad[0x80000];
  234         } cg6_alt_un;
  235 
  236         /* FHC register at 0x300000 */
  237         union {
  238                 int un_fhc;
  239                 char un_pad[0x1000];
  240         } cg6_fhc_un;
  241 
  242         /* THC at 0x301000 */
  243         union {
  244                 struct cg6_thc un_thc;
  245                 char un_pad[0x400000 - 0x1000];
  246         } cg6_thc_un;
  247 
  248         /* FBC at 0x700000 */
  249         union {
  250                 char un_pad[0x1000];
  251         } cg6_fbc_un;
  252 
  253         /* TEC at 0x701000 */
  254         union {
  255                 char un_pad[0x100000 - 0x1000];
  256                 struct cg6_tec_xxx un_tec;
  257         } cg6_tec_un;
  258 
  259         /* Video RAM at 0x800000 */
  260         char    cg6_ram[1024 * 1024];   /* approx.? */
  261 };
  262 #endif

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