FreeBSD/Linux Kernel Cross Reference
sys/dev/sx/cd1865.h
1 /*-
2 * Device driver for Specialix I/O8+ multiport serial card.
3 *
4 * Copyright 2003 Frank Mayhar <frank@exit.com>
5 *
6 * Derived from the "si" driver by Peter Wemm <peter@netplex.com.au>, using
7 * lots of information from the Linux "specialix" driver by Roger Wolff
8 * <R.E.Wolff@BitWizard.nl> and from the Intel CD1865 "Intelligent Eight-
9 * Channel Communications Controller" datasheet. Roger was also nice
10 * enough to answer numerous questions about stuff specific to the I/O8+
11 * not covered by the CD1865 datasheet.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notices, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notices, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE.
26 *
27 * $FreeBSD$
28 */
29
30
31 /* CD1865 chip register definitions. */
32
33 /*
34 * Service Match Register interrupt acknowledgement values.
35 *
36 * These values are "obligatory" if you use the register based
37 * interrupt acknowledgements; the wrong values can cause a lockup.
38 * See section 8.11.1 of the Intel CD1865 "Intelligent Eight-Channel
39 * Communications Controller" datasheet.
40 */
41 #define CD1865_ACK_MINT 0x75 /* goes to MSMR */
42 #define CD1865_ACK_TINT 0x76 /* goes to TSMR */
43 #define CD1865_ACK_RINT 0x77 /* goes to RSMR */
44
45
46 #define CD1865_NUMCHAN 8 /* Total number of channels. */
47 #define CD1865_CHARTICK 16 /* Ticks per character. */
48 #define CD1865_TFIFOSZ 8 /* TX FIFO size. */
49 #define CD1865_RFIFOSZ 8 /* RX FIFO size. */
50
51 /*
52 * Global registers.
53 * These registers are not associated with any particular channel;
54 * some define the general behavior of the card and others are only
55 * active during service requests.
56 */
57 #define CD1865_GIVR 0x40 /* Global Interrupt Vector Register. */
58 /* The CD1865 datasheet calls this the */
59 /* "Global Vector Register" _and_ the */
60 /* "Global Service Vector Register," GSVR. */
61 #define CD1865_GSVR CD1865_GIVR
62 #define CD1865_GICR 0x41 /* Global Interrupting Channel Register. */
63 /* The CD1865 datasheet calls this the */
64 /* "Global Channel Register 1," GSCR1. */
65 #define CD1865_GSCR1 CD1865_GICR
66 #define CD1865_GSCR2 0x42 /* Global Channel Register 2. */
67 #define CD1865_GSCR3 0x43 /* Global Channel Register 3. */
68 #define CD1865_MSMR 0x61 /* Priority Interrupt Level Register 1. */
69 #define CD1865_TSMR 0x62 /* Priority Interrupt Level Register 2. */
70 #define CD1865_RSMR 0x63 /* Priority Interrupt Level Register 3. */
71 #define CD1865_CAR 0x64 /* Channel Access Register. */
72 #define CD1865_SRSR 0x65 /* Service Request Status Register. */
73 #define CD1865_SRCR 0x66 /* Service Request Configuration Register. */
74 #define CD1865_GFRCR 0x6b /* Global Firmware Revision Code Register. */
75 #define CD1865_PPRH 0x70 /* Prescaler Period Register High. */
76 #define CD1865_PPRL 0x71 /* Prescaler Period Register Low. */
77 #define CD1865_RDR 0x78 /* Receiver Data Register. */
78 #define CD1865_RCSR 0x7a /* Receiver Character Status Register. */
79 #define CD1865_TDR 0x7b /* Transmit Data Register. */
80 #define CD1865_EOIR 0x7f /* End of Interrupt Register. */
81 #define CD1865_MRAR 0x75 /* Modem Request Acknowlege Register. */
82 #define CD1865_TRAR 0x76 /* Transmit Request Acknowlege Register. */
83 #define CD1865_RRAR 0x77 /* Receive Request Acknowlege Register. */
84
85 /*
86 * Channel Registers
87 * These registers control or provide status for individual channels.
88 * Use the CD1865_CAR register to set up access to the channel before
89 * using these registers.
90 */
91 #define CD1865_CCR 0x01 /* Channel Command Register. */
92 #define CD1865_IER 0x02 /* Interrupt Enable Register. */
93 /* The CD1865 datasheet calls this the */
94 /* "Service Request Enable Register," SRER. */
95 #define CD1865_SRER CD1865_IER
96 #define CD1865_COR1 0x03 /* Channel Option Register 1. */
97 #define CD1865_COR2 0x04 /* Channel Option Register 2. */
98 #define CD1865_COR3 0x05 /* Channel Option Register 3. */
99 #define CD1865_CCSR 0x06 /* Channel Control Status Register. */
100 #define CD1865_RDCR 0x07 /* Receive Data Count Register. */
101 #define CD1865_SCHR1 0x09 /* Special Character Register 1. */
102 #define CD1865_SCHR2 0x0a /* Special Character Register 2. */
103 #define CD1865_SCHR3 0x0b /* Special Character Register 3. */
104 #define CD1865_SCHR4 0x0c /* Special Character Register 4. */
105 #define CD1865_MCOR1 0x10 /* Modem Change Option 1 Register. */
106 #define CD1865_MCOR2 0x11 /* Modem Change Option 2 Register. */
107 #define CD1865_MCR 0x12 /* Modem Change Register. */
108 #define CD1865_RTPR 0x18 /* Receive Timeout Period Register. */
109 #define CD1865_MSVR 0x28 /* Modem Signal Value Register. */
110 #define CD1865_MSVRTS 0x29 /* Modem Signal Value Register. */
111 #define CD1865_MSVDTR 0x2a /* Modem Signal Value Register. */
112 #define CD1865_RBPRH 0x31 /* Receive Baud Rate Period Register High. */
113 #define CD1865_RBPRL 0x32 /* Receive Baud Rate Period Register Low. */
114 #define CD1865_TBPRH 0x39 /* Transmit Baud Rate Period Register High. */
115 #define CD1865_TBPRL 0x3a /* Transmit Baud Rate Period Register Low. */
116
117
118 /*
119 * Global Interrupt Vector Register, read/write (0x40).
120 */
121 #define CD1865_GIVR_ITMASK 0x07 /* Interrupt type mask. */
122 #define CD1865_GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt. */
123 #define CD1865_GIVR_IT_TX 0x02 /* Transmit Data Interrupt. */
124 #define CD1865_GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt. */
125 #define CD1865_GIVR_IT_REXC 0x07 /* Receive Exception Interrupt. */
126
127
128 /*
129 * Global Interrupt Channel Register read/write (0x41)
130 */
131 #define CD1865_GICR_CHAN_MASK 0x1c /* Channel Number Mask. */
132 #define CD1865_GICR_CHAN_SHIFT 2 /* Channel Number shift. */
133
134
135 /*
136 * Channel Access Register, read/write (0x64).
137 */
138 #define CD1865_CAR_CHAN_MASK 0x07 /* Channel Number Mask. */
139 #define CD1865_CAR_A7 0x08 /* A7 Address Extension (unused). */
140
141
142 /*
143 * Receive Character Status Register, readonly (0x7a).
144 */
145 #define CD1865_RCSR_TOUT 0x80 /* Rx Timeout. */
146 #define CD1865_RCSR_SCDET 0x70 /* Special Character Detected Mask. */
147 #define CD1865_RCSR_NO_SC 0x00 /* No Special Characters Detected. */
148 #define CD1865_RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected. */
149 #define CD1865_RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected. */
150 #define CD1865_RCSR_SC_3 0x30 /* Special Char 3 Detected. */
151 #define CD1865_RCSR_SC_4 0x40 /* Special Char 4 Detected. */
152 #define CD1865_RCSR_BREAK 0x08 /* Break detected. */
153 #define CD1865_RCSR_PE 0x04 /* Parity Error. */
154 #define CD1865_RCSR_FE 0x02 /* Frame Error. */
155 #define CD1865_RCSR_OE 0x01 /* Overrun Error. */
156
157
158 /*
159 * Channel Command Register, read/write (0x01)
160 * Commands in groups can be OR-ed together.
161 */
162 #define CD1865_CCR_HARDRESET 0x81 /* Reset the CD1865 (like a powercycle). */
163
164 #define CD1865_CCR_SOFTRESET 0x80 /* Soft Channel Reset (one channel). */
165
166 #define CD1865_CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed. */
167 #define CD1865_CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed. */
168 #define CD1865_CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed. */
169
170 #define CD1865_CCR_SSCH1 0x21 /* Send Special Character 1. */
171
172 #define CD1865_CCR_SSCH2 0x22 /* Send Special Character 2. */
173
174 #define CD1865_CCR_SSCH3 0x23 /* Send Special Character 3. */
175
176 #define CD1865_CCR_SSCH4 0x24 /* Send Special Character 4. */
177
178 #define CD1865_CCR_TXEN 0x18 /* Enable Transmitter. */
179 #define CD1865_CCR_RXEN 0x12 /* Enable Receiver. */
180
181 #define CD1865_CCR_TXDIS 0x14 /* Disable Transmitter. */
182 #define CD1865_CCR_RXDIS 0x11 /* Disable Receiver. */
183
184
185 /*
186 * Interrupt Enable Register, read/write (0x02).
187 * (aka Service Request Enable Register)
188 */
189 #define CD1865_IER_DSR 0x80 /* Enable DSR change interrupt. */
190 #define CD1865_IER_CD 0x40 /* Enable CD change interrupt. */
191 #define CD1865_IER_CTS 0x20 /* Enable CTS change interrupt. */
192 #define CD1865_IER_RXD 0x10 /* Enable Receive Data interrupt. */
193 #define CD1865_IER_RXSC 0x08 /* Enable Receive Special Character int. */
194 #define CD1865_IER_TXRDY 0x04 /* Enable Transmit ready interrupt. */
195 #define CD1865_IER_TXEMPTY 0x02 /* Enable Transmit empty interrupt. */
196 #define CD1865_IER_NNDT 0x01 /* Enable "No New Data Timeout" int. */
197
198
199 /*
200 * Channel Option Register 1, read/write (0x03).
201 */
202 #define CD1865_COR1_ODDP 0x80 /* Odd Parity. */
203 #define CD1865_COR1_PARMODE 0x60 /* Parity enable mask. */
204 #define CD1865_COR1_NOPAR 0x00 /* No Parity. */
205 #define CD1865_COR1_FORCEPAR 0x20 /* Force Parity. */
206 #define CD1865_COR1_NORMPAR 0x40 /* Normal Parity. */
207 #define CD1865_COR1_IGNORE 0x10 /* Ignore Parity on RX. */
208 #define CD1865_COR1_STOPBITS 0x0c /* Number of Stop Bits. */
209 #define CD1865_COR1_1SB 0x00 /* 1 Stop Bit. */
210 #define CD1865_COR1_15SB 0x04 /* 1.5 Stop Bits. */
211 #define CD1865_COR1_2SB 0x08 /* 2 Stop Bits. */
212 #define CD1865_COR1_CHARLEN 0x03 /* Character Length. */
213 #define CD1865_COR1_5BITS 0x00 /* 5 bits. */
214 #define CD1865_COR1_6BITS 0x01 /* 6 bits. */
215 #define CD1865_COR1_7BITS 0x02 /* 7 bits. */
216 #define CD1865_COR1_8BITS 0x03 /* 8 bits. */
217
218
219 /*
220 * Channel Option Register 2, read/write (0x04).
221 */
222 #define CD1865_COR2_IXM 0x80 /* Implied XON mode. */
223 #define CD1865_COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control*/
224 #define CD1865_COR2_ETC 0x20 /* Embedded Tx Commands Enable. */
225 #define CD1865_COR2_LLM 0x10 /* Local Loopback Mode. */
226 #define CD1865_COR2_RLM 0x08 /* Remote Loopback Mode. */
227 #define CD1865_COR2_RTSAO 0x04 /* RTS Automatic Output Enable. */
228 #define CD1865_COR2_CTSAE 0x02 /* CTS Automatic Enable. */
229 #define CD1865_COR2_DSRAE 0x01 /* DSR Automatic Enable. */
230
231
232 /*
233 * Channel Option Register 3, read/write (0x05).
234 */
235 #define CD1865_COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3). */
236 #define CD1865_COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4). */
237 #define CD1865_COR3_FCT 0x20 /* Flow-Control Transparency Mode. */
238 #define CD1865_COR3_SCDE 0x10 /* Special Character Detection Enable. */
239 #define CD1865_COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8). */
240
241
242 /*
243 * Channel Control Status Register, readonly (0x06)
244 */
245 #define CD1865_CCSR_RXEN 0x80 /* Receiver Enabled. */
246 #define CD1865_CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent). */
247 #define CD1865_CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent). */
248 #define CD1865_CCSR_TXEN 0x08 /* Transmitter Enabled. */
249 #define CD1865_CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF). */
250 #define CD1865_CCSR_TXFLON 0x02 /* Transmit Flow On (got XON). */
251
252
253 /*
254 * Modem Change Option Register 1, read/write (0x10).
255 */
256 #define CD1865_MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR. */
257 #define CD1865_MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD. */
258 #define CD1865_MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS. */
259 #define CD1865_MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8).*/
260 #define CD1865_MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled. */
261
262
263 /*
264 * Modem Change Option Register 2, read/write (0x11).
265 */
266 #define CD1865_MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR. */
267 #define CD1865_MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD. */
268 #define CD1865_MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS. */
269
270 /*
271 * Modem Change Register, read/write (0x12).
272 */
273 #define CD1865_MCR_DSRCHG 0x80 /* DSR Changed. */
274 #define CD1865_MCR_CDCHG 0x40 /* CD Changed. */
275 #define CD1865_MCR_CTSCHG 0x20 /* CTS Changed. */
276
277
278 /*
279 * Modem Signal Value Register, read/write (0x28)
280 *
281 * Note:
282 * These are inverted with respect to the actual signals! If the
283 * signal is present, the bit is zero, else the bit is one.
284 */
285 #define CD1865_MSVR_DSR 0x80 /* Current state of DSR input. */
286 #define CD1865_MSVR_CD 0x40 /* Current state of CD input. */
287 #define CD1865_MSVR_CTS 0x20 /* Current state of CTS input. */
288 #define CD1865_MSVR_DTR 0x02 /* Current state of DTR output. */
289 #define CD1865_MSVR_RTS 0x01 /* Current state of RTS output. */
290 #define CD1865_MSVR_OFF 0xe3 /* All signals off. */
291 #define CD1865_MSVR_ON 0x00 /* All signals on. */
292
293 /*
294 * Escape characters. These are sent in-band when embedded commands are
295 * enabled with CD1865_COR2_ETC.
296 */
297 #define CD1865_C_ESC 0x00 /* Escape character. */
298 #define CD1865_C_SBRK 0x81 /* Start sending BREAK. */
299 #define CD1865_C_DELAY 0x82 /* Delay output. */
300 #define CD1865_C_EBRK 0x83 /* Stop sending BREAK. */
301
302 #define CD1865_SRSR_RREQint 0x10 /* Receive request interrupt. */
303 #define CD1865_SRSR_TREQint 0x04 /* Transmit request interrupt. */
304 #define CD1865_SRSR_MREQint 0x01 /* Modem signal change request interrupt.*/
305 #define CD1865_SRSR_REQint 0x15 /* All of the above. */
306
307 #define CD1865_SRCR_PKGTYPE 0x80
308 #define CD1865_SRCR_REGACKEN 0x40
309 #define CD1865_SRCR_DAISYEN 0x20
310 #define CD1865_SRCR_GLOBPRI 0x10
311 #define CD1865_SRCR_UNFAIR 0x08
312 #define CD1865_SRCR_AUTOPRI 0x02
313 #define CD1865_SRCR_PRISEL 0x01
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