FreeBSD/Linux Kernel Cross Reference
sys/dev/sx/sx.h
1 /*
2 * Device driver for Specialix I/O8+ multiport serial card.
3 *
4 * Copyright 2003 Frank Mayhar <frank@exit.com>
5 *
6 * Derived from the "si" driver by Peter Wemm <peter@netplex.com.au>, using
7 * lots of information from the Linux "specialix" driver by Roger Wolff
8 * <R.E.Wolff@BitWizard.nl> and from the Intel CD1865 "Intelligent Eight-
9 * Channel Communications Controller" datasheet. Roger was also nice
10 * enough to answer numerous questions about stuff specific to the I/O8+
11 * not covered by the CD1865 datasheet.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notices, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notices, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE.
26 *
27 * $FreeBSD: releng/5.3/sys/dev/sx/sx.h 131981 2004-07-11 15:18:39Z phk $
28 */
29
30
31 /*
32 * Per-channel soft information structure, stored in the driver. It's called
33 * "sx_port" just because the si driver calls it "si_port."
34 *
35 * This information is mostly visible via ioctl().
36 */
37 struct sx_port {
38 int sp_chan; /* Channel number, for convenience. */
39 struct tty *sp_tty;
40 int sp_state;
41 int sp_active_out; /* callout is open */
42 int sp_delta_overflows;
43 u_int sp_wopeners; /* Processes waiting for DCD. */
44 struct termios sp_iin; /* Initial state. */
45 struct termios sp_iout;
46 struct termios sp_lin; /* Lock state. */
47 struct termios sp_lout;
48 #ifdef SX_DEBUG
49 int sp_debug; /* debug mask */
50 #endif
51 };
52
53 /*
54 * Various important values.
55 */
56 #define SX_NUMCHANS 8 /* Eight channels on an I/O8+. */
57 #define SX_PCI_IO_SPACE 8 /* How much address space to use. */
58 #define SX_CCR_TIMEOUT 10000 /* Channel Command Register timeout, 10ms. */
59 #define SX_GSVR_TIMEOUT 1000 /* GSVR reset timeout, 1ms. */
60 #define SX_CD1865_ID 0x10 /* ID of the I/O8+ CD1865 chip. */
61 #define SX_EI 0x80 /* "Enable interrupt" flag for I/O8+ commands.*/
62
63 #define SX_DATA_REG 0 /* Data register. */
64 #define SX_ADDR_REG 1 /* Address register. */
65
66 /*
67 * The I/O8+ has a 25MHz oscillator on board, but the CD1865 runs at half
68 * that.
69 */
70 #define SX_CD1865_CLOCK 12500000 /* CD1865 clock on I/O8+. */
71 #define SX_CD1865_TICK 4000 /* Timer tick rate, via prescaler. */
72 #define SX_CD1865_PRESCALE (SX_CD1865_CLOCK/SX_CD1865_TICK) /* Prescale value.*/
73
74 #include <sys/callout.h>
75
76 /*
77 * Device numbering for the sx device.
78 *
79 * The minor number is broken up into four fields as follows:
80 * Field Bits Mask
81 * --------------------- ---- ----
82 * Channel (port) number 0-2 0x07
83 * "DTR pin is DTR" flag 3 0x08
84 * Unused (zero) 4 0x10
85 * Card number 5-6 0x60
86 * Callout device flag 7 0x80
87 *
88 * The next 8 bits in the word is the major number, followed by the
89 * "initial state device" flag and then the "lock state device" flag.
90 */
91 #define SX_CHAN_MASK 0x07
92 #define SX_DTRPIN_MASK 0x08
93 #define SX_CARD_MASK 0x60
94 #define SX_TTY_MASK 0x7f
95 #define SX_CALLOUT_MASK 0x80
96 #define SX_INIT_STATE_MASK 0x10000
97 #define SX_LOCK_STATE_MASK 0x20000
98 #define SX_STATE_MASK 0x30000
99 #define SX_SPECIAL_MASK 0x30000
100
101 #define SX_CARDSHIFT 5
102 #define SX_MINOR2CHAN(m) (m & SX_CHAN_MASK)
103 #define SX_MINOR2CARD(m) ((m & SX_CARD_MASK) >> SX_CARDSHIFT)
104 #define SX_MINOR2TTY(m) (m & SX_TTY_MASK)
105
106 #define DEV_IS_CALLOUT(m) (m & SX_CALLOUT_MASK)
107 #define DEV_IS_STATE(m) (m & SX_STATE_MASK)
108 #define DEV_IS_SPECIAL(m) (m & SX_SPECIAL_MASK)
109 #define DEV_DTRPIN(m) (m & SX_DTRPIN_MASK)
110
111 #define MINOR2SC(m) ((struct sx_softc *)devclass_get_softc(sx_devclass,\
112 SX_MINOR2CARD(m)))
113 #define MINOR2PP(m) (MINOR2SC((m))->sc_ports + SX_MINOR2CHAN((m)))
114 #define MINOR2TP(m) (MINOR2PP((m))->sp_tty)
115 #define TP2PP(tp) (MINOR2PP(SX_MINOR2TTY(minor((tp)->t_dev))))
116 #define TP2SC(tp) (MINOR2SC(minor((tp)->t_dev)))
117 #define PP2SC(pp) (MINOR2SC(minor((pp)->sp_tty->t_dev)))
118
119 /* Buffer parameters */
120 #define SX_BUFFERSIZE CD1865_RFIFOSZ /* Just the size of the receive FIFO. */
121 #define SX_I_HIGH_WATER (TTYHOG - 2 * SX_BUFFERSIZE)
122
123 /*
124 * Precomputed bitrate clock divisors. Formula is
125 *
126 * Clock rate (Hz) 12500000
127 * divisor = --------------- or ------------
128 * 16 * bit rate 16 * bitrate
129 *
130 * All values are rounded to the nearest integer.
131 */
132 #define CLK75 0x28b1 /* 10416.666667 */
133 #define CLK110 0x1bbe /* 7102.272727 */
134 #define CLK150 0x1458 /* 5208.333333 */
135 #define CLK300 0x0a2c /* 2604.166667 */
136 #define CLK600 0x0516 /* 1302.083333 */
137 #define CLK1200 0x028b /* 651.0416667 */
138 #define CLK2000 0x0187 /* 390.625 */
139 #define CLK2400 0x0146 /* 325.5208333 */
140 #define CLK4800 0x00a3 /* 162.7604167 */
141 #define CLK7200 0x006d /* 108.5069444 */
142 #define CLK9600 0x0051 /* 81.38020833 */
143 #define CLK19200 0x0029 /* 40.69010417 */
144 #define CLK38400 0x0014 /* 20.34505208 */
145 #define CLK57600 0x000e /* 13.56336806 */
146 #define CLK115200 0x0007 /* 6.781684028 */
147
148
149 /* sp_state */
150 #define SX_SS_CLOSED 0x00000 /* Port is closed. */
151 #define SX_SS_OPEN 0x00001 /* Port is open and active. */
152 #define SX_SS_XMIT 0x00002 /* We're transmitting data. */
153 #define SX_SS_INTR 0x00004 /* We're processing an interrupt. */
154 #define SX_SS_CLOSING 0x00008 /* in the middle of an sxclose() */
155 #define SX_SS_WAITWRITE 0x00010
156 #define SX_SS_BLOCKWRITE 0x00020
157 #define SX_SS_DTR_OFF 0x00040 /* DTR held off */
158 #define SX_SS_IFLOW 0x00080 /* Input (RTS) flow control on. */
159 #define SX_SS_OFLOW 0x00100 /* Output (CTS) flow control on. */
160 #define SX_SS_IRCV 0x00200 /* In a receive interrupt. */
161 #define SX_SS_IMODEM 0x00400 /* In a modem-signal interrupt. */
162 #define SX_SS_IRCVEXC 0x00800 /* In a receive-exception interrupt. */
163 #define SX_SS_IXMIT 0x01000 /* In a transmit interrupt. */
164 #define SX_SS_OSTOP 0x02000 /* Stopped by output flow control. */
165 #define SX_SS_ISTOP 0x04000 /* Stopped by input flow control. */
166 #define SX_SS_DTRPIN 0x08000 /* DTR/RTS pin is DTR. */
167 #define SX_SS_DOBRK 0x10000 /* Change break status. */
168 #define SX_SS_BREAK 0x20000 /* Doing break. */
169
170 #define SX_DTRPIN(pp) ((pp)->sp_state & SX_SS_DTRPIN) /* DTR/RTS pin is DTR.*/
171 #define SX_XMITTING(pp) ((pp)->sp_state & SX_SS_XMIT) /* We're transmitting. */
172 #define SX_INTR(pp) ((pp)->sp_state & SX_SS_INTR) /* In an interrupt. */
173 #define SX_IXMIT(pp) ((pp)->sp_state & SX_SS_IXMIT) /* Transmit interrupt. */
174 #define SX_IFLOW(pp) ((pp)->sp_state & SX_SS_IFLOW) /* Input flow control. */
175 #define SX_OFLOW(pp) ((pp)->sp_state & SX_SS_OFLOW) /* Output flow control.*/
176 #define SX_IRCV(pp) ((pp)->sp_state & SX_SS_IRCV) /* Receive interrupt. */
177 #define SX_IMODEM(pp) ((pp)->sp_state & SX_SS_IMODEM) /* Modem state change.*/
178 #define SX_IRCVEXC(pp) ((pp)->sp_state & SX_SS_IRCVEXC) /* Rcv exception. */
179 #define SX_OSTOP(pp) ((pp)->sp_state & SX_SS_OSTOP) /* Output stopped. */
180 #define SX_ISTOP(pp) ((pp)->sp_state & SX_SS_ISTOP) /* Input stopped. */
181 #define SX_DOBRK(pp) ((pp)->sp_state & SX_SS_DOBRK) /* Change break status.*/
182 #define SX_BREAK(pp) ((pp)->sp_state & SX_SS_BREAK) /* Doing break. */
183
184 #define DBG_ENTRY 0x00000001
185 #define DBG_DRAIN 0x00000002
186 #define DBG_OPEN 0x00000004
187 #define DBG_CLOSE 0x00000008
188 /* 0x00000010*/
189 #define DBG_WRITE 0x00000020
190 #define DBG_PARAM 0x00000040
191 #define DBG_INTR 0x00000080
192 #define DBG_IOCTL 0x00000100
193 /* 0x00000200 */
194 /* 0x00000400*/
195 #define DBG_OPTIM 0x00000800
196 #define DBG_START 0x00001000
197 #define DBG_EXIT 0x00002000
198 #define DBG_FAIL 0x00004000
199 #define DBG_STOP 0x00008000
200 #define DBG_AUTOBOOT 0x00010000
201 #define DBG_MODEM 0x00020000
202 #define DBG_MODEM_STATE 0x00040000
203 #define DBG_RECEIVE 0x00080000
204 #define DBG_POLL 0x00100000
205 #define DBG_TRANSMIT 0x00200000
206 #define DBG_RECEIVE_EXC 0x00400000
207 #define DBG_PRINTF 0x80000000
208 #define DBG_ALL 0xffffffff
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