Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/sym/sym_fw1.h
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 5 * PCI-SCSI controllers. 6 * 7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 8 * 9 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 10 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 11 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 12 * 13 * 14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 15 * Copyright (C) 1998-1999 Gerard Roudier 16 * 17 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 18 * a port of the FreeBSD ncr driver to Linux-1.2.13. 19 * 20 * The original ncr driver has been written for 386bsd and FreeBSD by 21 * Wolfgang Stanglmeier <wolf@cologne.de> 22 * Stefan Esser <se@mi.Uni-Koeln.de> 23 * Copyright (C) 1994 Wolfgang Stanglmeier 24 * 25 * The initialisation code, and part of the code that addresses 26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 27 * written by Justin T. Gibbs. 28 * 29 * Other major contributions: 30 * 31 * NVRAM detection and reading. 32 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 33 * 34 *----------------------------------------------------------------------------- 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 51 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 */ 59 60 /* $FreeBSD$ */ 61 62 /* 63 * Scripts for SYMBIOS-Processor 64 * 65 * We have to know the offsets of all labels before we reach 66 * them (for forward jumps). Therefore we declare a struct 67 * here. If you make changes inside the script, 68 * 69 * DONT FORGET TO CHANGE THE LENGTHS HERE! 70 */ 71 72 /* 73 * Script fragments which are loaded into the on-chip RAM 74 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 75 * Must not exceed 4K bytes. 76 */ 77 struct SYM_FWA_SCR { 78 u32 start [ 11]; 79 u32 getjob_begin [ 4]; 80 u32 _sms_a10 [ 5]; 81 u32 getjob_end [ 4]; 82 u32 _sms_a20 [ 4]; 83 u32 select [ 8]; 84 u32 _sms_a30 [ 8]; 85 u32 wf_sel_done [ 2]; 86 u32 send_ident [ 2]; 87 #ifdef SYM_CONF_IARB_SUPPORT 88 u32 select2 [ 8]; 89 #else 90 u32 select2 [ 2]; 91 #endif 92 u32 command [ 2]; 93 u32 dispatch [ 28]; 94 u32 sel_no_cmd [ 10]; 95 u32 init [ 6]; 96 u32 clrack [ 4]; 97 u32 disp_status [ 4]; 98 u32 datai_done [ 26]; 99 u32 datao_done [ 12]; 100 u32 datai_phase [ 2]; 101 u32 datao_phase [ 2]; 102 u32 msg_in [ 2]; 103 u32 msg_in2 [ 10]; 104 #ifdef SYM_CONF_IARB_SUPPORT 105 u32 status [ 14]; 106 #else 107 u32 status [ 10]; 108 #endif 109 u32 complete [ 9]; 110 u32 complete2 [ 8]; 111 u32 _sms_a40 [ 12]; 112 u32 complete_error [ 5]; 113 u32 done [ 5]; 114 u32 _sms_a50 [ 5]; 115 u32 _sms_a60 [ 2]; 116 u32 done_end [ 4]; 117 u32 save_dp [ 9]; 118 u32 restore_dp [ 5]; 119 u32 disconnect [ 20]; 120 u32 disconnect2 [ 5]; 121 u32 _sms_a65 [ 3]; 122 #ifdef SYM_CONF_IARB_SUPPORT 123 u32 idle [ 4]; 124 #else 125 u32 idle [ 2]; 126 #endif 127 #ifdef SYM_CONF_IARB_SUPPORT 128 u32 ungetjob [ 7]; 129 #else 130 u32 ungetjob [ 5]; 131 #endif 132 u32 reselect [ 4]; 133 u32 reselected [ 19]; 134 u32 _sms_a70 [ 6]; 135 u32 _sms_a80 [ 4]; 136 u32 reselected1 [ 25]; 137 u32 _sms_a90 [ 4]; 138 u32 resel_lun0 [ 7]; 139 u32 _sms_a100 [ 4]; 140 u32 resel_tag [ 8]; 141 #if SYM_CONF_MAX_TASK*4 > 512 142 u32 _sms_a110 [ 23]; 143 #elif SYM_CONF_MAX_TASK*4 > 256 144 u32 _sms_a110 [ 17]; 145 #else 146 u32 _sms_a110 [ 13]; 147 #endif 148 u32 _sms_a120 [ 2]; 149 u32 resel_go [ 4]; 150 u32 _sms_a130 [ 7]; 151 u32 resel_dsa [ 2]; 152 u32 resel_dsa1 [ 4]; 153 u32 _sms_a140 [ 10]; 154 u32 resel_no_tag [ 4]; 155 u32 _sms_a145 [ 7]; 156 u32 data_in [SYM_CONF_MAX_SG * 2]; 157 u32 data_in2 [ 4]; 158 u32 data_out [SYM_CONF_MAX_SG * 2]; 159 u32 data_out2 [ 4]; 160 u32 pm0_data [ 12]; 161 u32 pm0_data_out [ 6]; 162 u32 pm0_data_end [ 7]; 163 u32 pm_data_end [ 4]; 164 u32 _sms_a150 [ 4]; 165 u32 pm1_data [ 12]; 166 u32 pm1_data_out [ 6]; 167 u32 pm1_data_end [ 9]; 168 }; 169 170 /* 171 * Script fragments which stay in main memory for all chips 172 * except for chips that support 8K on-chip RAM. 173 */ 174 struct SYM_FWB_SCR { 175 u32 no_data [ 2]; 176 u32 sel_for_abort [ 18]; 177 u32 sel_for_abort_1 [ 2]; 178 u32 msg_in_etc [ 12]; 179 u32 msg_received [ 5]; 180 u32 msg_weird_seen [ 5]; 181 u32 msg_extended [ 17]; 182 u32 _sms_b10 [ 4]; 183 u32 msg_bad [ 6]; 184 u32 msg_weird [ 4]; 185 u32 msg_weird1 [ 8]; 186 u32 wdtr_resp [ 6]; 187 u32 send_wdtr [ 4]; 188 u32 sdtr_resp [ 6]; 189 u32 send_sdtr [ 4]; 190 u32 ppr_resp [ 6]; 191 u32 send_ppr [ 4]; 192 u32 nego_bad_phase [ 4]; 193 u32 msg_out [ 4]; 194 u32 msg_out_done [ 4]; 195 u32 data_ovrun [ 3]; 196 u32 data_ovrun1 [ 22]; 197 u32 data_ovrun2 [ 8]; 198 u32 abort_resel [ 16]; 199 u32 resend_ident [ 4]; 200 u32 ident_break [ 4]; 201 u32 ident_break_atn [ 4]; 202 u32 sdata_in [ 6]; 203 u32 resel_bad_lun [ 4]; 204 u32 bad_i_t_l [ 4]; 205 u32 bad_i_t_l_q [ 4]; 206 u32 bad_status [ 7]; 207 u32 wsr_ma_helper [ 4]; 208 209 /* Data area */ 210 u32 zero [ 1]; 211 u32 scratch [ 1]; 212 u32 scratch1 [ 1]; 213 u32 prev_done [ 1]; 214 u32 done_pos [ 1]; 215 u32 nextjob [ 1]; 216 u32 startpos [ 1]; 217 u32 targtbl [ 1]; 218 /* End of data area */ 219 220 u32 snooptest [ 9]; 221 u32 snoopend [ 2]; 222 }; 223 224 static const struct SYM_FWA_SCR SYM_FWA_SCR = { 225 /*--------------------------< START >----------------------------*/ { 226 /* 227 * Switch the LED on. 228 * Will be patched with a NO_OP if LED 229 * not needed or not desired. 230 */ 231 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 232 0, 233 /* 234 * Clear SIGP. 235 */ 236 SCR_FROM_REG (ctest2), 237 0, 238 /* 239 * Stop here if the C code wants to perform 240 * some error recovery procedure manually. 241 * (Indicate this by setting SEM in ISTAT) 242 */ 243 SCR_FROM_REG (istat), 244 0, 245 /* 246 * Report to the C code the next position in 247 * the start queue the SCRIPTS will schedule. 248 * The C code must not change SCRATCHA. 249 */ 250 SCR_COPY (4), 251 PADDR_B (startpos), 252 RADDR_1 (scratcha), 253 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 254 SIR_SCRIPT_STOPPED, 255 /* 256 * Start the next job. 257 * 258 * @DSA = start point for this job. 259 * SCRATCHA = address of this job in the start queue. 260 * 261 * We will restore startpos with SCRATCHA if we fails the 262 * arbitration or if it is the idle job. 263 * 264 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 265 * is a critical path. If it is partially executed, it then 266 * may happen that the job address is not yet in the DSA 267 * and the next queue position points to the next JOB. 268 */ 269 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 270 /* 271 * Copy to a fixed location both the next STARTPOS 272 * and the current JOB address, using self modifying 273 * SCRIPTS. 274 */ 275 SCR_COPY (4), 276 RADDR_1 (scratcha), 277 PADDR_A (_sms_a10), 278 SCR_COPY (8), 279 }/*-------------------------< _SMS_A10 >-------------------------*/,{ 280 0, 281 PADDR_B (nextjob), 282 /* 283 * Move the start address to TEMP using self- 284 * modifying SCRIPTS and jump indirectly to 285 * that address. 286 */ 287 SCR_COPY (4), 288 PADDR_B (nextjob), 289 RADDR_1 (dsa), 290 }/*-------------------------< GETJOB_END >-----------------------*/,{ 291 SCR_COPY (4), 292 RADDR_1 (dsa), 293 PADDR_A (_sms_a20), 294 SCR_COPY (4), 295 }/*-------------------------< _SMS_A20 >-------------------------*/,{ 296 0, 297 RADDR_1 (temp), 298 SCR_RETURN, 299 0, 300 }/*-------------------------< SELECT >---------------------------*/,{ 301 /* 302 * DSA contains the address of a scheduled 303 * data structure. 304 * 305 * SCRATCHA contains the address of the start queue 306 * entry which points to the next job. 307 * 308 * Set Initiator mode. 309 * 310 * (Target mode is left as an exercise for the reader) 311 */ 312 SCR_CLR (SCR_TRG), 313 0, 314 /* 315 * And try to select this target. 316 */ 317 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 318 PADDR_A (ungetjob), 319 /* 320 * Now there are 4 possibilities: 321 * 322 * (1) The chip loses arbitration. 323 * This is ok, because it will try again, 324 * when the bus becomes idle. 325 * (But beware of the timeout function!) 326 * 327 * (2) The chip is reselected. 328 * Then the script processor takes the jump 329 * to the RESELECT label. 330 * 331 * (3) The chip wins arbitration. 332 * Then it will execute SCRIPTS instruction until 333 * the next instruction that checks SCSI phase. 334 * Then will stop and wait for selection to be 335 * complete or selection time-out to occur. 336 * 337 * After having won arbitration, the SCRIPTS 338 * processor is able to execute instructions while 339 * the SCSI core is performing SCSI selection. 340 */ 341 342 /* 343 * Copy the CCB header to a fixed location 344 * in the HCB using self-modifying SCRIPTS. 345 */ 346 SCR_COPY (4), 347 RADDR_1 (dsa), 348 PADDR_A (_sms_a30), 349 SCR_COPY (sizeof(struct sym_ccbh)), 350 }/*-------------------------< _SMS_A30 >-------------------------*/,{ 351 0, 352 HADDR_1 (ccb_head), 353 /* 354 * Load the savep (saved data pointer) into 355 * the actual data pointer. 356 */ 357 SCR_COPY (4), 358 HADDR_1 (ccb_head.savep), 359 RADDR_1 (temp), 360 /* 361 * Initialize the status register 362 */ 363 SCR_COPY (4), 364 HADDR_1 (ccb_head.status), 365 RADDR_1 (scr0), 366 }/*-------------------------< WF_SEL_DONE >----------------------*/,{ 367 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 368 SIR_SEL_ATN_NO_MSG_OUT, 369 }/*-------------------------< SEND_IDENT >-----------------------*/,{ 370 /* 371 * Selection complete. 372 * Send the IDENTIFY and possibly the TAG message 373 * and negotiation message if present. 374 */ 375 SCR_MOVE_TBL ^ SCR_MSG_OUT, 376 offsetof (struct sym_dsb, smsg), 377 }/*-------------------------< SELECT2 >--------------------------*/,{ 378 #ifdef SYM_CONF_IARB_SUPPORT 379 /* 380 * Set IMMEDIATE ARBITRATION if we have been given 381 * a hint to do so. (Some job to do after this one). 382 */ 383 SCR_FROM_REG (HF_REG), 384 0, 385 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 386 8, 387 SCR_REG_REG (scntl1, SCR_OR, IARB), 388 0, 389 #endif 390 /* 391 * Anticipate the COMMAND phase. 392 * This is the PHASE we expect at this point. 393 */ 394 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 395 PADDR_A (sel_no_cmd), 396 }/*-------------------------< COMMAND >--------------------------*/,{ 397 /* 398 * ... and send the command 399 */ 400 SCR_MOVE_TBL ^ SCR_COMMAND, 401 offsetof (struct sym_dsb, cmd), 402 }/*-------------------------< DISPATCH >-------------------------*/,{ 403 /* 404 * MSG_IN is the only phase that shall be 405 * entered at least once for each (re)selection. 406 * So we test it first. 407 */ 408 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 409 PADDR_A (msg_in), 410 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 411 PADDR_A (datao_phase), 412 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 413 PADDR_A (datai_phase), 414 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 415 PADDR_A (status), 416 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 417 PADDR_A (command), 418 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 419 PADDR_B (msg_out), 420 /* 421 * Discard as many illegal phases as 422 * required and tell the C code about. 423 */ 424 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 425 16, 426 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 427 HADDR_1 (scratch), 428 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 429 -16, 430 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 431 16, 432 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 433 HADDR_1 (scratch), 434 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 435 -16, 436 SCR_INT, 437 SIR_BAD_PHASE, 438 SCR_JUMP, 439 PADDR_A (dispatch), 440 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 441 /* 442 * The target does not switch to command 443 * phase after IDENTIFY has been sent. 444 * 445 * If it stays in MSG OUT phase send it 446 * the IDENTIFY again. 447 */ 448 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 449 PADDR_B (resend_ident), 450 /* 451 * If target does not switch to MSG IN phase 452 * and we sent a negotiation, assert the 453 * failure immediately. 454 */ 455 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 456 PADDR_A (dispatch), 457 SCR_FROM_REG (HS_REG), 458 0, 459 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 460 SIR_NEGO_FAILED, 461 /* 462 * Jump to dispatcher. 463 */ 464 SCR_JUMP, 465 PADDR_A (dispatch), 466 }/*-------------------------< INIT >-----------------------------*/,{ 467 /* 468 * Wait for the SCSI RESET signal to be 469 * inactive before restarting operations, 470 * since the chip may hang on SEL_ATN 471 * if SCSI RESET is active. 472 */ 473 SCR_FROM_REG (sstat0), 474 0, 475 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 476 -16, 477 SCR_JUMP, 478 PADDR_A (start), 479 }/*-------------------------< CLRACK >---------------------------*/,{ 480 /* 481 * Terminate possible pending message phase. 482 */ 483 SCR_CLR (SCR_ACK), 484 0, 485 SCR_JUMP, 486 PADDR_A (dispatch), 487 }/*-------------------------< DISP_STATUS >----------------------*/,{ 488 /* 489 * Anticipate STATUS phase. 490 * 491 * Does spare 3 SCRIPTS instructions when we have 492 * completed the INPUT of the data. 493 */ 494 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 495 PADDR_A (status), 496 SCR_JUMP, 497 PADDR_A (dispatch), 498 }/*-------------------------< DATAI_DONE >-----------------------*/,{ 499 /* 500 * If the device still wants to send us data, 501 * we must count the extra bytes. 502 */ 503 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)), 504 PADDR_B (data_ovrun), 505 /* 506 * If the SWIDE is not full, jump to dispatcher. 507 * We anticipate a STATUS phase. 508 */ 509 SCR_FROM_REG (scntl2), 510 0, 511 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)), 512 PADDR_A (disp_status), 513 /* 514 * The SWIDE is full. 515 * Clear this condition. 516 */ 517 SCR_REG_REG (scntl2, SCR_OR, WSR), 518 0, 519 /* 520 * We are expecting an IGNORE RESIDUE message 521 * from the device, otherwise we are in data 522 * overrun condition. Check against MSG_IN phase. 523 */ 524 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 525 SIR_SWIDE_OVERRUN, 526 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 527 PADDR_A (disp_status), 528 /* 529 * We are in MSG_IN phase, 530 * Read the first byte of the message. 531 * If it is not an IGNORE RESIDUE message, 532 * signal overrun and jump to message 533 * processing. 534 */ 535 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 536 HADDR_1 (msgin[0]), 537 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 538 SIR_SWIDE_OVERRUN, 539 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 540 PADDR_A (msg_in2), 541 /* 542 * We got the message we expected. 543 * Read the 2nd byte, and jump to dispatcher. 544 */ 545 SCR_CLR (SCR_ACK), 546 0, 547 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 548 HADDR_1 (msgin[1]), 549 SCR_CLR (SCR_ACK), 550 0, 551 SCR_JUMP, 552 PADDR_A (disp_status), 553 }/*-------------------------< DATAO_DONE >-----------------------*/,{ 554 /* 555 * If the device wants us to send more data, 556 * we must count the extra bytes. 557 */ 558 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 559 PADDR_B (data_ovrun), 560 /* 561 * If the SODL is not full jump to dispatcher. 562 * We anticipate a STATUS phase. 563 */ 564 SCR_FROM_REG (scntl2), 565 0, 566 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)), 567 PADDR_A (disp_status), 568 /* 569 * The SODL is full, clear this condition. 570 */ 571 SCR_REG_REG (scntl2, SCR_OR, WSS), 572 0, 573 /* 574 * And signal a DATA UNDERRUN condition 575 * to the C code. 576 */ 577 SCR_INT, 578 SIR_SODL_UNDERRUN, 579 SCR_JUMP, 580 PADDR_A (dispatch), 581 }/*-------------------------< DATAI_PHASE >----------------------*/,{ 582 SCR_RETURN, 583 0, 584 }/*-------------------------< DATAO_PHASE >----------------------*/,{ 585 SCR_RETURN, 586 0, 587 }/*-------------------------< MSG_IN >---------------------------*/,{ 588 /* 589 * Get the first byte of the message. 590 * 591 * The script processor doesn't negate the 592 * ACK signal after this transfer. 593 */ 594 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 595 HADDR_1 (msgin[0]), 596 }/*-------------------------< MSG_IN2 >--------------------------*/,{ 597 /* 598 * Check first against 1 byte messages 599 * that we handle from SCRIPTS. 600 */ 601 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 602 PADDR_A (complete), 603 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 604 PADDR_A (disconnect), 605 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 606 PADDR_A (save_dp), 607 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 608 PADDR_A (restore_dp), 609 /* 610 * We handle all other messages from the 611 * C code, so no need to waste on-chip RAM 612 * for those ones. 613 */ 614 SCR_JUMP, 615 PADDR_B (msg_in_etc), 616 }/*-------------------------< STATUS >---------------------------*/,{ 617 /* 618 * get the status 619 */ 620 SCR_MOVE_ABS (1) ^ SCR_STATUS, 621 HADDR_1 (scratch), 622 #ifdef SYM_CONF_IARB_SUPPORT 623 /* 624 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 625 * since we may have to tamper the start queue from 626 * the C code. 627 */ 628 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 629 8, 630 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 631 0, 632 #endif 633 /* 634 * save status to scsi_status. 635 * mark as complete. 636 */ 637 SCR_TO_REG (SS_REG), 638 0, 639 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 640 0, 641 /* 642 * Anticipate the MESSAGE PHASE for 643 * the TASK COMPLETE message. 644 */ 645 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 646 PADDR_A (msg_in), 647 SCR_JUMP, 648 PADDR_A (dispatch), 649 }/*-------------------------< COMPLETE >-------------------------*/,{ 650 /* 651 * Complete message. 652 * 653 * Copy the data pointer to LASTP. 654 */ 655 SCR_COPY (4), 656 RADDR_1 (temp), 657 HADDR_1 (ccb_head.lastp), 658 /* 659 * When we terminate the cycle by clearing ACK, 660 * the target may disconnect immediately. 661 * 662 * We don't want to be told of an "unexpected disconnect", 663 * so we disable this feature. 664 */ 665 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 666 0, 667 /* 668 * Terminate cycle ... 669 */ 670 SCR_CLR (SCR_ACK|SCR_ATN), 671 0, 672 /* 673 * ... and wait for the disconnect. 674 */ 675 SCR_WAIT_DISC, 676 0, 677 }/*-------------------------< COMPLETE2 >------------------------*/,{ 678 /* 679 * Save host status. 680 */ 681 SCR_COPY (4), 682 RADDR_1 (scr0), 683 HADDR_1 (ccb_head.status), 684 /* 685 * Move back the CCB header using self-modifying 686 * SCRIPTS. 687 */ 688 SCR_COPY (4), 689 RADDR_1 (dsa), 690 PADDR_A (_sms_a40), 691 SCR_COPY (sizeof(struct sym_ccbh)), 692 HADDR_1 (ccb_head), 693 }/*-------------------------< _SMS_A40 >-------------------------*/,{ 694 0, 695 /* 696 * Some bridges may reorder DMA writes to memory. 697 * We donnot want the CPU to deal with completions 698 * without all the posted write having been flushed 699 * to memory. This DUMMY READ should flush posted 700 * buffers prior to the CPU having to deal with 701 * completions. 702 */ 703 SCR_COPY (4), /* DUMMY READ */ 704 HADDR_1 (ccb_head.status), 705 RADDR_1 (scr0), 706 /* 707 * If command resulted in not GOOD status, 708 * call the C code if needed. 709 */ 710 SCR_FROM_REG (SS_REG), 711 0, 712 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 713 PADDR_B (bad_status), 714 /* 715 * If we performed an auto-sense, call 716 * the C code to synchronyze task aborts 717 * with UNIT ATTENTION conditions. 718 */ 719 SCR_FROM_REG (HF_REG), 720 0, 721 SCR_JUMP ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 722 PADDR_A (done), 723 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 724 SCR_COPY (4), 725 PADDR_B (startpos), 726 RADDR_1 (scratcha), 727 SCR_INT, 728 SIR_COMPLETE_ERROR, 729 }/*-------------------------< DONE >-----------------------------*/,{ 730 /* 731 * Copy the DSA to the DONE QUEUE and 732 * signal completion to the host. 733 * If we are interrupted between DONE 734 * and DONE_END, we must reset, otherwise 735 * the completed CCB may be lost. 736 */ 737 SCR_COPY (4), 738 PADDR_B (done_pos), 739 PADDR_A (_sms_a50), 740 SCR_COPY (4), 741 RADDR_1 (dsa), 742 }/*-------------------------< _SMS_A50 >-------------------------*/,{ 743 0, 744 SCR_COPY (4), 745 PADDR_B (done_pos), 746 PADDR_A (_sms_a60), 747 /* 748 * The instruction below reads the DONE QUEUE next 749 * free position from memory. 750 * In addition it ensures that all PCI posted writes 751 * are flushed and so the DSA value of the done 752 * CCB is visible by the CPU before INTFLY is raised. 753 */ 754 SCR_COPY (8), 755 }/*-------------------------< _SMS_A60 >-------------------------*/,{ 756 0, 757 PADDR_B (prev_done), 758 }/*-------------------------< DONE_END >-------------------------*/,{ 759 SCR_INT_FLY, 760 0, 761 SCR_JUMP, 762 PADDR_A (start), 763 }/*-------------------------< SAVE_DP >--------------------------*/,{ 764 /* 765 * Clear ACK immediately. 766 * No need to delay it. 767 */ 768 SCR_CLR (SCR_ACK), 769 0, 770 /* 771 * Keep track we received a SAVE DP, so 772 * we will switch to the other PM context 773 * on the next PM since the DP may point 774 * to the current PM context. 775 */ 776 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 777 0, 778 /* 779 * SAVE_DP message: 780 * Copy the data pointer to SAVEP. 781 */ 782 SCR_COPY (4), 783 RADDR_1 (temp), 784 HADDR_1 (ccb_head.savep), 785 SCR_JUMP, 786 PADDR_A (dispatch), 787 }/*-------------------------< RESTORE_DP >-----------------------*/,{ 788 /* 789 * RESTORE_DP message: 790 * Copy SAVEP to actual data pointer. 791 */ 792 SCR_COPY (4), 793 HADDR_1 (ccb_head.savep), 794 RADDR_1 (temp), 795 SCR_JUMP, 796 PADDR_A (clrack), 797 }/*-------------------------< DISCONNECT >-----------------------*/,{ 798 /* 799 * DISCONNECTing ... 800 * 801 * disable the "unexpected disconnect" feature, 802 * and remove the ACK signal. 803 */ 804 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 805 0, 806 SCR_CLR (SCR_ACK|SCR_ATN), 807 0, 808 /* 809 * Wait for the disconnect. 810 */ 811 SCR_WAIT_DISC, 812 0, 813 /* 814 * Status is: DISCONNECTED. 815 */ 816 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 817 0, 818 /* 819 * Save host status. 820 */ 821 SCR_COPY (4), 822 RADDR_1 (scr0), 823 HADDR_1 (ccb_head.status), 824 /* 825 * If QUIRK_AUTOSAVE is set, 826 * do a "save pointer" operation. 827 */ 828 SCR_FROM_REG (QU_REG), 829 0, 830 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)), 831 PADDR_A (disconnect2), 832 /* 833 * like SAVE_DP message: 834 * Remember we saved the data pointer. 835 * Copy data pointer to SAVEP. 836 */ 837 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 838 0, 839 SCR_COPY (4), 840 RADDR_1 (temp), 841 HADDR_1 (ccb_head.savep), 842 }/*-------------------------< DISCONNECT2 >----------------------*/,{ 843 /* 844 * Move back the CCB header using self-modifying 845 * SCRIPTS. 846 */ 847 SCR_COPY (4), 848 RADDR_1 (dsa), 849 PADDR_A (_sms_a65), 850 SCR_COPY (sizeof(struct sym_ccbh)), 851 HADDR_1 (ccb_head), 852 }/*-------------------------< _SMS_A65 >-------------------------*/,{ 853 0, 854 SCR_JUMP, 855 PADDR_A (start), 856 }/*-------------------------< IDLE >-----------------------------*/,{ 857 /* 858 * Nothing to do? 859 * Switch the LED off and wait for reselect. 860 * Will be patched with a NO_OP if LED 861 * not needed or not desired. 862 */ 863 SCR_REG_REG (gpreg, SCR_OR, 0x01), 864 0, 865 #ifdef SYM_CONF_IARB_SUPPORT 866 SCR_JUMPR, 867 8, 868 #endif 869 }/*-------------------------< UNGETJOB >-------------------------*/,{ 870 #ifdef SYM_CONF_IARB_SUPPORT 871 /* 872 * Set IMMEDIATE ARBITRATION, for the next time. 873 * This will give us better chance to win arbitration 874 * for the job we just wanted to do. 875 */ 876 SCR_REG_REG (scntl1, SCR_OR, IARB), 877 0, 878 #endif 879 /* 880 * We are not able to restart the SCRIPTS if we are 881 * interrupted and these instruction haven't been 882 * all executed. BTW, this is very unlikely to 883 * happen, but we check that from the C code. 884 */ 885 SCR_LOAD_REG (dsa, 0xff), 886 0, 887 SCR_COPY (4), 888 RADDR_1 (scratcha), 889 PADDR_B (startpos), 890 }/*-------------------------< RESELECT >-------------------------*/,{ 891 /* 892 * Make sure we are in initiator mode. 893 */ 894 SCR_CLR (SCR_TRG), 895 0, 896 /* 897 * Sleep waiting for a reselection. 898 */ 899 SCR_WAIT_RESEL, 900 PADDR_A(start), 901 }/*-------------------------< RESELECTED >-----------------------*/,{ 902 /* 903 * Switch the LED on. 904 * Will be patched with a NO_OP if LED 905 * not needed or not desired. 906 */ 907 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 908 0, 909 /* 910 * load the target id into the sdid 911 */ 912 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 913 0, 914 SCR_TO_REG (sdid), 915 0, 916 /* 917 * Load the target control block address 918 */ 919 SCR_COPY (4), 920 PADDR_B (targtbl), 921 RADDR_1 (dsa), 922 SCR_SFBR_REG (dsa, SCR_SHL, 0), 923 0, 924 SCR_REG_REG (dsa, SCR_SHL, 0), 925 0, 926 SCR_REG_REG (dsa, SCR_AND, 0x3c), 927 0, 928 SCR_COPY (4), 929 RADDR_1 (dsa), 930 PADDR_A (_sms_a70), 931 SCR_COPY (4), 932 }/*-------------------------< _SMS_A70 >-------------------------*/,{ 933 0, 934 RADDR_1 (dsa), 935 /* 936 * Copy the TCB header to a fixed place in 937 * the HCB. 938 */ 939 SCR_COPY (4), 940 RADDR_1 (dsa), 941 PADDR_A (_sms_a80), 942 SCR_COPY (sizeof(struct sym_tcbh)), 943 }/*-------------------------< _SMS_A80 >-------------------------*/,{ 944 0, 945 HADDR_1 (tcb_head), 946 /* 947 * We expect MESSAGE IN phase. 948 * If not, get help from the C code. 949 */ 950 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 951 SIR_RESEL_NO_MSG_IN, 952 }/*-------------------------< RESELECTED1 >----------------------*/,{ 953 /* 954 * Load the synchronous transfer registers. 955 */ 956 SCR_COPY (1), 957 HADDR_1 (tcb_head.wval), 958 RADDR_1 (scntl3), 959 SCR_COPY (1), 960 HADDR_1 (tcb_head.sval), 961 RADDR_1 (sxfer), 962 /* 963 * Get the IDENTIFY message. 964 */ 965 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 966 HADDR_1 (msgin), 967 /* 968 * If IDENTIFY LUN #0, use a faster path 969 * to find the LCB structure. 970 */ 971 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 972 PADDR_A (resel_lun0), 973 /* 974 * If message isn't an IDENTIFY, 975 * tell the C code about. 976 */ 977 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 978 SIR_RESEL_NO_IDENTIFY, 979 /* 980 * It is an IDENTIFY message, 981 * Load the LUN control block address. 982 */ 983 SCR_COPY (4), 984 HADDR_1 (tcb_head.luntbl_sa), 985 RADDR_1 (dsa), 986 SCR_SFBR_REG (dsa, SCR_SHL, 0), 987 0, 988 SCR_REG_REG (dsa, SCR_SHL, 0), 989 0, 990 SCR_REG_REG (dsa, SCR_AND, 0xfc), 991 0, 992 SCR_COPY (4), 993 RADDR_1 (dsa), 994 PADDR_A (_sms_a90), 995 SCR_COPY (4), 996 }/*-------------------------< _SMS_A90 >-------------------------*/,{ 997 0, 998 RADDR_1 (dsa), 999 SCR_JUMPR, 1000 12, 1001 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 1002 /* 1003 * LUN 0 special case (but usual one :)) 1004 */ 1005 SCR_COPY (4), 1006 HADDR_1 (tcb_head.lun0_sa), 1007 RADDR_1 (dsa), 1008 /* 1009 * Jump indirectly to the reselect action for this LUN. 1010 * (lcb.head.resel_sa assumed at offset zero of lcb). 1011 */ 1012 SCR_COPY (4), 1013 RADDR_1 (dsa), 1014 PADDR_A (_sms_a100), 1015 SCR_COPY (4), 1016 }/*-------------------------< _SMS_A100 >------------------------*/,{ 1017 0, 1018 RADDR_1 (temp), 1019 SCR_RETURN, 1020 0, 1021 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 1022 }/*-------------------------< RESEL_TAG >------------------------*/,{ 1023 /* 1024 * ACK the IDENTIFY previously received. 1025 */ 1026 SCR_CLR (SCR_ACK), 1027 0, 1028 /* 1029 * It shall be a tagged command. 1030 * Read SIMPLE+TAG. 1031 * The C code will deal with errors. 1032 * Aggressive optimization, isn't it? :) 1033 */ 1034 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 1035 HADDR_1 (msgin), 1036 /* 1037 * Copy the LCB header to a fixed place in 1038 * the HCB using self-modifying SCRIPTS. 1039 */ 1040 SCR_COPY (4), 1041 RADDR_1 (dsa), 1042 PADDR_A (_sms_a110), 1043 SCR_COPY (sizeof(struct sym_lcbh)), 1044 }/*-------------------------< _SMS_A110 >------------------------*/,{ 1045 0, 1046 HADDR_1 (lcb_head), 1047 /* 1048 * Load the pointer to the tagged task 1049 * table for this LUN. 1050 */ 1051 SCR_COPY (4), 1052 HADDR_1 (lcb_head.itlq_tbl_sa), 1053 RADDR_1 (dsa), 1054 /* 1055 * The SIDL still contains the TAG value. 1056 * Aggressive optimization, isn't it? :):) 1057 */ 1058 SCR_REG_SFBR (sidl, SCR_SHL, 0), 1059 0, 1060 #if SYM_CONF_MAX_TASK*4 > 512 1061 SCR_JUMPR ^ IFFALSE (CARRYSET), 1062 8, 1063 SCR_REG_REG (dsa1, SCR_OR, 2), 1064 0, 1065 SCR_REG_REG (sfbr, SCR_SHL, 0), 1066 0, 1067 SCR_JUMPR ^ IFFALSE (CARRYSET), 1068 8, 1069 SCR_REG_REG (dsa1, SCR_OR, 1), 1070 0, 1071 #elif SYM_CONF_MAX_TASK*4 > 256 1072 SCR_JUMPR ^ IFFALSE (CARRYSET), 1073 8, 1074 SCR_REG_REG (dsa1, SCR_OR, 1), 1075 0, 1076 #endif 1077 /* 1078 * Retrieve the DSA of this task. 1079 * JUMP indirectly to the restart point of the CCB. 1080 */ 1081 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 1082 0, 1083 SCR_COPY (4), 1084 RADDR_1 (dsa), 1085 PADDR_A (_sms_a120), 1086 SCR_COPY (4), 1087 }/*-------------------------< _SMS_A120 >------------------------*/,{ 1088 0, 1089 RADDR_1 (dsa), 1090 }/*-------------------------< RESEL_GO >-------------------------*/,{ 1091 SCR_COPY (4), 1092 RADDR_1 (dsa), 1093 PADDR_A (_sms_a130), 1094 /* 1095 * Move 'ccb.phys.head.go' action to 1096 * scratch/scratch1. So scratch1 will 1097 * contain the 'restart' field of the 1098 * 'go' structure. 1099 */ 1100 SCR_COPY (8), 1101 }/*-------------------------< _SMS_A130 >------------------------*/,{ 1102 0, 1103 PADDR_B (scratch), 1104 SCR_COPY (4), 1105 PADDR_B (scratch1), /* phys.head.go.restart */ 1106 RADDR_1 (temp), 1107 SCR_RETURN, 1108 0, 1109 /* In normal situations we branch to RESEL_DSA */ 1110 }/*-------------------------< RESEL_DSA >------------------------*/,{ 1111 /* 1112 * ACK the IDENTIFY or TAG previously received. 1113 */ 1114 SCR_CLR (SCR_ACK), 1115 0, 1116 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1117 /* 1118 * Copy the CCB header to a fixed location 1119 * in the HCB using self-modifying SCRIPTS. 1120 */ 1121 SCR_COPY (4), 1122 RADDR_1 (dsa), 1123 PADDR_A (_sms_a140), 1124 SCR_COPY (sizeof(struct sym_ccbh)), 1125 }/*-------------------------< _SMS_A140 >------------------------*/,{ 1126 0, 1127 HADDR_1 (ccb_head), 1128 /* 1129 * Load the savep (saved data pointer) into 1130 * the actual data pointer. 1131 */ 1132 SCR_COPY (4), 1133 HADDR_1 (ccb_head.savep), 1134 RADDR_1 (temp), 1135 /* 1136 * Initialize the status register 1137 */ 1138 SCR_COPY (4), 1139 HADDR_1 (ccb_head.status), 1140 RADDR_1 (scr0), 1141 /* 1142 * Jump to dispatcher. 1143 */ 1144 SCR_JUMP, 1145 PADDR_A (dispatch), 1146 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1147 /* 1148 * Copy the LCB header to a fixed place in 1149 * the HCB using self-modifying SCRIPTS. 1150 */ 1151 SCR_COPY (4), 1152 RADDR_1 (dsa), 1153 PADDR_A (_sms_a145), 1154 SCR_COPY (sizeof(struct sym_lcbh)), 1155 }/*-------------------------< _SMS_A145 >------------------------*/,{ 1156 0, 1157 HADDR_1 (lcb_head), 1158 /* 1159 * Load the DSA with the unique ITL task. 1160 */ 1161 SCR_COPY (4), 1162 HADDR_1 (lcb_head.itl_task_sa), 1163 RADDR_1 (dsa), 1164 SCR_JUMP, 1165 PADDR_A (resel_go), 1166 }/*-------------------------< DATA_IN >--------------------------*/,{ 1167 /* 1168 * Because the size depends on the 1169 * #define SYM_CONF_MAX_SG parameter, 1170 * it is filled in at runtime. 1171 * 1172 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1173 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1174 * || offsetof (struct sym_dsb, data[ i]), 1175 * ##========================================== 1176 */ 1177 1178 }/*-------------------------< DATA_IN2 >-------------------------*/,{ 1179 SCR_CALL, 1180 PADDR_A (datai_done), 1181 SCR_JUMP, 1182 PADDR_B (data_ovrun), 1183 }/*-------------------------< DATA_OUT >-------------------------*/,{ 1184 /* 1185 * Because the size depends on the 1186 * #define SYM_CONF_MAX_SG parameter, 1187 * it is filled in at runtime. 1188 * 1189 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1190 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1191 * || offsetof (struct sym_dsb, data[ i]), 1192 * ##========================================== 1193 */ 1194 1195 }/*-------------------------< DATA_OUT2 >------------------------*/,{ 1196 SCR_CALL, 1197 PADDR_A (datao_done), 1198 SCR_JUMP, 1199 PADDR_B (data_ovrun), 1200 }/*-------------------------< PM0_DATA >-------------------------*/,{ 1201 /* 1202 * Read our host flags to SFBR, so we will be able 1203 * to check against the data direction we expect. 1204 */ 1205 SCR_FROM_REG (HF_REG), 1206 0, 1207 /* 1208 * Check against actual DATA PHASE. 1209 */ 1210 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1211 PADDR_A (pm0_data_out), 1212 /* 1213 * Actual phase is DATA IN. 1214 * Check against expected direction. 1215 */ 1216 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1217 PADDR_B (data_ovrun), 1218 /* 1219 * Keep track we are moving data from the 1220 * PM0 DATA mini-script. 1221 */ 1222 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1223 0, 1224 /* 1225 * Move the data to memory. 1226 */ 1227 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1228 offsetof (struct sym_ccb, phys.pm0.sg), 1229 SCR_JUMP, 1230 PADDR_A (pm0_data_end), 1231 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1232 /* 1233 * Actual phase is DATA OUT. 1234 * Check against expected direction. 1235 */ 1236 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1237 PADDR_B (data_ovrun), 1238 /* 1239 * Keep track we are moving data from the 1240 * PM0 DATA mini-script. 1241 */ 1242 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1243 0, 1244 /* 1245 * Move the data from memory. 1246 */ 1247 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1248 offsetof (struct sym_ccb, phys.pm0.sg), 1249 }/*-------------------------< PM0_DATA_END >---------------------*/,{ 1250 /* 1251 * Clear the flag that told we were moving 1252 * data from the PM0 DATA mini-script. 1253 */ 1254 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1255 0, 1256 /* 1257 * Return to the previous DATA script which 1258 * is guaranteed by design (if no bug) to be 1259 * the main DATA script for this transfer. 1260 */ 1261 SCR_COPY (4), 1262 RADDR_1 (dsa), 1263 RADDR_1 (scratcha), 1264 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)), 1265 0, 1266 }/*-------------------------< PM_DATA_END >----------------------*/,{ 1267 SCR_COPY (4), 1268 RADDR_1 (scratcha), 1269 PADDR_A (_sms_a150), 1270 SCR_COPY (4), 1271 }/*-------------------------< _SMS_A150 >------------------------*/,{ 1272 0, 1273 RADDR_1 (temp), 1274 SCR_RETURN, 1275 0, 1276 }/*-------------------------< PM1_DATA >-------------------------*/,{ 1277 /* 1278 * Read our host flags to SFBR, so we will be able 1279 * to check against the data direction we expect. 1280 */ 1281 SCR_FROM_REG (HF_REG), 1282 0, 1283 /* 1284 * Check against actual DATA PHASE. 1285 */ 1286 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1287 PADDR_A (pm1_data_out), 1288 /* 1289 * Actual phase is DATA IN. 1290 * Check against expected direction. 1291 */ 1292 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1293 PADDR_B (data_ovrun), 1294 /* 1295 * Keep track we are moving data from the 1296 * PM1 DATA mini-script. 1297 */ 1298 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1299 0, 1300 /* 1301 * Move the data to memory. 1302 */ 1303 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1304 offsetof (struct sym_ccb, phys.pm1.sg), 1305 SCR_JUMP, 1306 PADDR_A (pm1_data_end), 1307 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1308 /* 1309 * Actual phase is DATA OUT. 1310 * Check against expected direction. 1311 */ 1312 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1313 PADDR_B (data_ovrun), 1314 /* 1315 * Keep track we are moving data from the 1316 * PM1 DATA mini-script. 1317 */ 1318 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1319 0, 1320 /* 1321 * Move the data from memory. 1322 */ 1323 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1324 offsetof (struct sym_ccb, phys.pm1.sg), 1325 }/*-------------------------< PM1_DATA_END >---------------------*/,{ 1326 /* 1327 * Clear the flag that told we were moving 1328 * data from the PM1 DATA mini-script. 1329 */ 1330 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1331 0, 1332 /* 1333 * Return to the previous DATA script which 1334 * is guaranteed by design (if no bug) to be 1335 * the main DATA script for this transfer. 1336 */ 1337 SCR_COPY (4), 1338 RADDR_1 (dsa), 1339 RADDR_1 (scratcha), 1340 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)), 1341 0, 1342 SCR_JUMP, 1343 PADDR_A (pm_data_end), 1344 }/*--------------------------<>----------------------------------*/ 1345 }; 1346 1347 static const struct SYM_FWB_SCR SYM_FWB_SCR = { 1348 /*-------------------------< NO_DATA >--------------------------*/ { 1349 SCR_JUMP, 1350 PADDR_B (data_ovrun), 1351 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1352 /* 1353 * We are jumped here by the C code, if we have 1354 * some target to reset or some disconnected 1355 * job to abort. Since error recovery is a serious 1356 * busyness, we will really reset the SCSI BUS, if 1357 * case of a SCSI interrupt occurring in this path. 1358 */ 1359 1360 /* 1361 * Set initiator mode. 1362 */ 1363 SCR_CLR (SCR_TRG), 1364 0, 1365 /* 1366 * And try to select this target. 1367 */ 1368 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1369 PADDR_A (reselect), 1370 /* 1371 * Wait for the selection to complete or 1372 * the selection to time out. 1373 */ 1374 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1375 -8, 1376 /* 1377 * Call the C code. 1378 */ 1379 SCR_INT, 1380 SIR_TARGET_SELECTED, 1381 /* 1382 * The C code should let us continue here. 1383 * Send the 'kiss of death' message. 1384 * We expect an immediate disconnect once 1385 * the target has eaten the message. 1386 */ 1387 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1388 0, 1389 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1390 offsetof (struct sym_hcb, abrt_tbl), 1391 SCR_CLR (SCR_ACK|SCR_ATN), 1392 0, 1393 SCR_WAIT_DISC, 1394 0, 1395 /* 1396 * Tell the C code that we are done. 1397 */ 1398 SCR_INT, 1399 SIR_ABORT_SENT, 1400 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1401 /* 1402 * Jump at scheduler. 1403 */ 1404 SCR_JUMP, 1405 PADDR_A (start), 1406 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1407 /* 1408 * If it is an EXTENDED (variable size message) 1409 * Handle it. 1410 */ 1411 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1412 PADDR_B (msg_extended), 1413 /* 1414 * Let the C code handle any other 1415 * 1 byte message. 1416 */ 1417 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1418 PADDR_B (msg_received), 1419 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1420 PADDR_B (msg_received), 1421 /* 1422 * We donnot handle 2 bytes messages from SCRIPTS. 1423 * So, let the C code deal with these ones too. 1424 */ 1425 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1426 PADDR_B (msg_weird_seen), 1427 SCR_CLR (SCR_ACK), 1428 0, 1429 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1430 HADDR_1 (msgin[1]), 1431 }/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1432 SCR_COPY (4), /* DUMMY READ */ 1433 HADDR_1 (cache), 1434 RADDR_1 (scratcha), 1435 SCR_INT, 1436 SIR_MSG_RECEIVED, 1437 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1438 SCR_COPY (4), /* DUMMY READ */ 1439 HADDR_1 (cache), 1440 RADDR_1 (scratcha), 1441 SCR_INT, 1442 SIR_MSG_WEIRD, 1443 }/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1444 /* 1445 * Clear ACK and get the next byte 1446 * assumed to be the message length. 1447 */ 1448 SCR_CLR (SCR_ACK), 1449 0, 1450 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1451 HADDR_1 (msgin[1]), 1452 /* 1453 * Try to catch some unlikely situations as 0 length 1454 * or too large the length. 1455 */ 1456 SCR_JUMP ^ IFTRUE (DATA (0)), 1457 PADDR_B (msg_weird_seen), 1458 SCR_TO_REG (scratcha), 1459 0, 1460 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1461 0, 1462 SCR_JUMP ^ IFTRUE (CARRYSET), 1463 PADDR_B (msg_weird_seen), 1464 /* 1465 * We donnot handle extended messages from SCRIPTS. 1466 * Read the amount of data corresponding to the 1467 * message length and call the C code. 1468 */ 1469 SCR_COPY (1), 1470 RADDR_1 (scratcha), 1471 PADDR_B (_sms_b10), 1472 SCR_CLR (SCR_ACK), 1473 0, 1474 }/*-------------------------< _SMS_B10 >-------------------------*/,{ 1475 SCR_MOVE_ABS (0) ^ SCR_MSG_IN, 1476 HADDR_1 (msgin[2]), 1477 SCR_JUMP, 1478 PADDR_B (msg_received), 1479 }/*-------------------------< MSG_BAD >--------------------------*/,{ 1480 /* 1481 * unimplemented message - reject it. 1482 */ 1483 SCR_INT, 1484 SIR_REJECT_TO_SEND, 1485 SCR_SET (SCR_ATN), 1486 0, 1487 SCR_JUMP, 1488 PADDR_A (clrack), 1489 }/*-------------------------< MSG_WEIRD >------------------------*/,{ 1490 /* 1491 * weird message received 1492 * ignore all MSG IN phases and reject it. 1493 */ 1494 SCR_INT, 1495 SIR_REJECT_TO_SEND, 1496 SCR_SET (SCR_ATN), 1497 0, 1498 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1499 SCR_CLR (SCR_ACK), 1500 0, 1501 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1502 PADDR_A (dispatch), 1503 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1504 HADDR_1 (scratch), 1505 SCR_JUMP, 1506 PADDR_B (msg_weird1), 1507 }/*-------------------------< WDTR_RESP >------------------------*/,{ 1508 /* 1509 * let the target fetch our answer. 1510 */ 1511 SCR_SET (SCR_ATN), 1512 0, 1513 SCR_CLR (SCR_ACK), 1514 0, 1515 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1516 PADDR_B (nego_bad_phase), 1517 }/*-------------------------< SEND_WDTR >------------------------*/,{ 1518 /* 1519 * Send the M_X_WIDE_REQ 1520 */ 1521 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1522 HADDR_1 (msgout), 1523 SCR_JUMP, 1524 PADDR_B (msg_out_done), 1525 }/*-------------------------< SDTR_RESP >------------------------*/,{ 1526 /* 1527 * let the target fetch our answer. 1528 */ 1529 SCR_SET (SCR_ATN), 1530 0, 1531 SCR_CLR (SCR_ACK), 1532 0, 1533 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1534 PADDR_B (nego_bad_phase), 1535 }/*-------------------------< SEND_SDTR >------------------------*/,{ 1536 /* 1537 * Send the M_X_SYNC_REQ 1538 */ 1539 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1540 HADDR_1 (msgout), 1541 SCR_JUMP, 1542 PADDR_B (msg_out_done), 1543 }/*-------------------------< PPR_RESP >-------------------------*/,{ 1544 /* 1545 * let the target fetch our answer. 1546 */ 1547 SCR_SET (SCR_ATN), 1548 0, 1549 SCR_CLR (SCR_ACK), 1550 0, 1551 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1552 PADDR_B (nego_bad_phase), 1553 }/*-------------------------< SEND_PPR >-------------------------*/,{ 1554 /* 1555 * Send the M_X_PPR_REQ 1556 */ 1557 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1558 HADDR_1 (msgout), 1559 SCR_JUMP, 1560 PADDR_B (msg_out_done), 1561 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1562 SCR_INT, 1563 SIR_NEGO_PROTO, 1564 SCR_JUMP, 1565 PADDR_A (dispatch), 1566 }/*-------------------------< MSG_OUT >--------------------------*/,{ 1567 /* 1568 * The target requests a message. 1569 * We donnot send messages that may 1570 * require the device to go to bus free. 1571 */ 1572 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1573 HADDR_1 (msgout), 1574 /* 1575 * ... wait for the next phase 1576 * if it's a message out, send it again, ... 1577 */ 1578 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1579 PADDR_B (msg_out), 1580 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1581 /* 1582 * Let the C code be aware of the 1583 * sent message and clear the message. 1584 */ 1585 SCR_INT, 1586 SIR_MSG_OUT_DONE, 1587 /* 1588 * ... and process the next phase 1589 */ 1590 SCR_JUMP, 1591 PADDR_A (dispatch), 1592 }/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1593 /* 1594 * Zero scratcha that will count the 1595 * extras bytes. 1596 */ 1597 SCR_COPY (4), 1598 PADDR_B (zero), 1599 RADDR_1 (scratcha), 1600 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1601 /* 1602 * The target may want to transfer too much data. 1603 * 1604 * If phase is DATA OUT write 1 byte and count it. 1605 */ 1606 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1607 16, 1608 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1609 HADDR_1 (scratch), 1610 SCR_JUMP, 1611 PADDR_B (data_ovrun2), 1612 /* 1613 * If WSR is set, clear this condition, and 1614 * count this byte. 1615 */ 1616 SCR_FROM_REG (scntl2), 1617 0, 1618 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1619 16, 1620 SCR_REG_REG (scntl2, SCR_OR, WSR), 1621 0, 1622 SCR_JUMP, 1623 PADDR_B (data_ovrun2), 1624 /* 1625 * Finally check against DATA IN phase. 1626 * Signal data overrun to the C code 1627 * and jump to dispatcher if not so. 1628 * Read 1 byte otherwise and count it. 1629 */ 1630 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1631 16, 1632 SCR_INT, 1633 SIR_DATA_OVERRUN, 1634 SCR_JUMP, 1635 PADDR_A (dispatch), 1636 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1637 HADDR_1 (scratch), 1638 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1639 /* 1640 * Count this byte. 1641 * This will allow to return a negative 1642 * residual to user. 1643 */ 1644 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1645 0, 1646 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1647 0, 1648 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1649 0, 1650 /* 1651 * .. and repeat as required. 1652 */ 1653 SCR_JUMP, 1654 PADDR_B (data_ovrun1), 1655 }/*-------------------------< ABORT_RESEL >----------------------*/,{ 1656 SCR_SET (SCR_ATN), 1657 0, 1658 SCR_CLR (SCR_ACK), 1659 0, 1660 /* 1661 * send the abort/abortag/reset message 1662 * we expect an immediate disconnect 1663 */ 1664 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1665 0, 1666 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1667 HADDR_1 (msgout), 1668 SCR_CLR (SCR_ACK|SCR_ATN), 1669 0, 1670 SCR_WAIT_DISC, 1671 0, 1672 SCR_INT, 1673 SIR_RESEL_ABORTED, 1674 SCR_JUMP, 1675 PADDR_A (start), 1676 }/*-------------------------< RESEND_IDENT >---------------------*/,{ 1677 /* 1678 * The target stays in MSG OUT phase after having acked 1679 * Identify [+ Tag [+ Extended message ]]. Targets shall 1680 * behave this way on parity error. 1681 * We must send it again all the messages. 1682 */ 1683 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1684 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1685 SCR_JUMP, 1686 PADDR_A (send_ident), 1687 }/*-------------------------< IDENT_BREAK >----------------------*/,{ 1688 SCR_CLR (SCR_ATN), 1689 0, 1690 SCR_JUMP, 1691 PADDR_A (select2), 1692 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1693 SCR_SET (SCR_ATN), 1694 0, 1695 SCR_JUMP, 1696 PADDR_A (select2), 1697 }/*-------------------------< SDATA_IN >-------------------------*/,{ 1698 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1699 offsetof (struct sym_dsb, sense), 1700 SCR_CALL, 1701 PADDR_A (datai_done), 1702 SCR_JUMP, 1703 PADDR_B (data_ovrun), 1704 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1705 /* 1706 * Message is an IDENTIFY, but lun is unknown. 1707 * Signal problem to C code for logging the event. 1708 * Send a M_ABORT to clear all pending tasks. 1709 */ 1710 SCR_INT, 1711 SIR_RESEL_BAD_LUN, 1712 SCR_JUMP, 1713 PADDR_B (abort_resel), 1714 }/*-------------------------< BAD_I_T_L >------------------------*/,{ 1715 /* 1716 * We donnot have a task for that I_T_L. 1717 * Signal problem to C code for logging the event. 1718 * Send a M_ABORT message. 1719 */ 1720 SCR_INT, 1721 SIR_RESEL_BAD_I_T_L, 1722 SCR_JUMP, 1723 PADDR_B (abort_resel), 1724 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1725 /* 1726 * We donnot have a task that matches the tag. 1727 * Signal problem to C code for logging the event. 1728 * Send a M_ABORTTAG message. 1729 */ 1730 SCR_INT, 1731 SIR_RESEL_BAD_I_T_L_Q, 1732 SCR_JUMP, 1733 PADDR_B (abort_resel), 1734 }/*-------------------------< BAD_STATUS >-----------------------*/,{ 1735 /* 1736 * Anything different from INTERMEDIATE 1737 * CONDITION MET should be a bad SCSI status, 1738 * given that GOOD status has already been tested. 1739 * Call the C code. 1740 */ 1741 SCR_COPY (4), 1742 PADDR_B (startpos), 1743 RADDR_1 (scratcha), 1744 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1745 SIR_BAD_SCSI_STATUS, 1746 SCR_RETURN, 1747 0, 1748 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1749 /* 1750 * Helper for the C code when WSR bit is set. 1751 * Perform the move of the residual byte. 1752 */ 1753 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1754 offsetof (struct sym_ccb, phys.wresid), 1755 SCR_JUMP, 1756 PADDR_A (dispatch), 1757 }/*-------------------------< ZERO >-----------------------------*/,{ 1758 SCR_DATA_ZERO, 1759 }/*-------------------------< SCRATCH >--------------------------*/,{ 1760 SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */ 1761 }/*-------------------------< SCRATCH1 >-------------------------*/,{ 1762 SCR_DATA_ZERO, 1763 }/*-------------------------< PREV_DONE >------------------------*/,{ 1764 SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */ 1765 }/*-------------------------< DONE_POS >-------------------------*/,{ 1766 SCR_DATA_ZERO, 1767 }/*-------------------------< NEXTJOB >--------------------------*/,{ 1768 SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */ 1769 }/*-------------------------< STARTPOS >-------------------------*/,{ 1770 SCR_DATA_ZERO, 1771 }/*-------------------------< TARGTBL >--------------------------*/,{ 1772 SCR_DATA_ZERO, 1773 1774 }/*-------------------------< SNOOPTEST >------------------------*/,{ 1775 /* 1776 * Read the variable. 1777 */ 1778 SCR_COPY (4), 1779 HADDR_1 (cache), 1780 RADDR_1 (scratcha), 1781 /* 1782 * Write the variable. 1783 */ 1784 SCR_COPY (4), 1785 RADDR_1 (temp), 1786 HADDR_1 (cache), 1787 /* 1788 * Read back the variable. 1789 */ 1790 SCR_COPY (4), 1791 HADDR_1 (cache), 1792 RADDR_1 (temp), 1793 }/*-------------------------< SNOOPEND >-------------------------*/,{ 1794 /* 1795 * And stop. 1796 */ 1797 SCR_INT, 1798 99, 1799 }/*--------------------------<>----------------------------------*/ 1800 };
Cache object: fc69a3a784540c53b6677b16e56b21f8
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