Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/sym/sym_fw2.h
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 5 * PCI-SCSI controllers. 6 * 7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 8 * 9 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 10 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 11 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 12 * 13 * 14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 15 * Copyright (C) 1998-1999 Gerard Roudier 16 * 17 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 18 * a port of the FreeBSD ncr driver to Linux-1.2.13. 19 * 20 * The original ncr driver has been written for 386bsd and FreeBSD by 21 * Wolfgang Stanglmeier <wolf@cologne.de> 22 * Stefan Esser <se@mi.Uni-Koeln.de> 23 * Copyright (C) 1994 Wolfgang Stanglmeier 24 * 25 * The initialisation code, and part of the code that addresses 26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 27 * written by Justin T. Gibbs. 28 * 29 * Other major contributions: 30 * 31 * NVRAM detection and reading. 32 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 33 * 34 *----------------------------------------------------------------------------- 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 51 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 */ 59 60 /* $FreeBSD$ */ 61 62 /* 63 * Scripts for SYMBIOS-Processor 64 * 65 * We have to know the offsets of all labels before we reach 66 * them (for forward jumps). Therefore we declare a struct 67 * here. If you make changes inside the script, 68 * 69 * DONT FORGET TO CHANGE THE LENGTHS HERE! 70 */ 71 72 /* 73 * Script fragments which are loaded into the on-chip RAM 74 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 75 * Must not exceed 4K bytes. 76 */ 77 struct SYM_FWA_SCR { 78 u32 start [ 14]; 79 u32 getjob_begin [ 4]; 80 u32 getjob_end [ 4]; 81 u32 select [ 8]; 82 u32 wf_sel_done [ 2]; 83 u32 sel_done [ 2]; 84 u32 send_ident [ 2]; 85 #ifdef SYM_CONF_IARB_SUPPORT 86 u32 select2 [ 8]; 87 #else 88 u32 select2 [ 2]; 89 #endif 90 u32 command [ 2]; 91 u32 dispatch [ 28]; 92 u32 sel_no_cmd [ 10]; 93 u32 init [ 6]; 94 u32 clrack [ 4]; 95 u32 disp_status [ 4]; 96 u32 datai_done [ 26]; 97 u32 datao_done [ 12]; 98 u32 datai_phase [ 2]; 99 u32 datao_phase [ 4]; 100 u32 msg_in [ 2]; 101 u32 msg_in2 [ 10]; 102 #ifdef SYM_CONF_IARB_SUPPORT 103 u32 status [ 14]; 104 #else 105 u32 status [ 10]; 106 #endif 107 u32 complete [ 8]; 108 u32 complete2 [ 12]; 109 u32 complete_error [ 4]; 110 u32 done [ 14]; 111 u32 done_end [ 2]; 112 u32 save_dp [ 8]; 113 u32 restore_dp [ 4]; 114 u32 disconnect [ 20]; 115 #ifdef SYM_CONF_IARB_SUPPORT 116 u32 idle [ 4]; 117 #else 118 u32 idle [ 2]; 119 #endif 120 #ifdef SYM_CONF_IARB_SUPPORT 121 u32 ungetjob [ 6]; 122 #else 123 u32 ungetjob [ 4]; 124 #endif 125 u32 reselect [ 4]; 126 u32 reselected [ 22]; 127 u32 resel_scntl4 [ 20]; 128 u32 resel_lun0 [ 6]; 129 #if SYM_CONF_MAX_TASK*4 > 512 130 u32 resel_tag [ 26]; 131 #elif SYM_CONF_MAX_TASK*4 > 256 132 u32 resel_tag [ 20]; 133 #else 134 u32 resel_tag [ 16]; 135 #endif 136 u32 resel_dsa [ 2]; 137 u32 resel_dsa1 [ 6]; 138 u32 resel_no_tag [ 6]; 139 u32 data_in [SYM_CONF_MAX_SG * 2]; 140 u32 data_in2 [ 4]; 141 u32 data_out [SYM_CONF_MAX_SG * 2]; 142 u32 data_out2 [ 4]; 143 u32 pm0_data [ 12]; 144 u32 pm0_data_out [ 6]; 145 u32 pm0_data_end [ 6]; 146 u32 pm1_data [ 12]; 147 u32 pm1_data_out [ 6]; 148 u32 pm1_data_end [ 6]; 149 }; 150 151 /* 152 * Script fragments which stay in main memory for all chips 153 * except for chips that support 8K on-chip RAM. 154 */ 155 struct SYM_FWB_SCR { 156 u32 start64 [ 2]; 157 u32 no_data [ 2]; 158 u32 sel_for_abort [ 18]; 159 u32 sel_for_abort_1 [ 2]; 160 u32 msg_in_etc [ 12]; 161 u32 msg_received [ 4]; 162 u32 msg_weird_seen [ 4]; 163 u32 msg_extended [ 20]; 164 u32 msg_bad [ 6]; 165 u32 msg_weird [ 4]; 166 u32 msg_weird1 [ 8]; 167 168 u32 wdtr_resp [ 6]; 169 u32 send_wdtr [ 4]; 170 u32 sdtr_resp [ 6]; 171 u32 send_sdtr [ 4]; 172 u32 ppr_resp [ 6]; 173 u32 send_ppr [ 4]; 174 u32 nego_bad_phase [ 4]; 175 u32 msg_out [ 4]; 176 u32 msg_out_done [ 4]; 177 u32 data_ovrun [ 2]; 178 u32 data_ovrun1 [ 22]; 179 u32 data_ovrun2 [ 8]; 180 u32 abort_resel [ 16]; 181 u32 resend_ident [ 4]; 182 u32 ident_break [ 4]; 183 u32 ident_break_atn [ 4]; 184 u32 sdata_in [ 6]; 185 u32 resel_bad_lun [ 4]; 186 u32 bad_i_t_l [ 4]; 187 u32 bad_i_t_l_q [ 4]; 188 u32 bad_status [ 6]; 189 u32 pm_handle [ 20]; 190 u32 pm_handle1 [ 4]; 191 u32 pm_save [ 4]; 192 u32 pm0_save [ 14]; 193 u32 pm1_save [ 14]; 194 195 /* WSR handling */ 196 u32 pm_wsr_handle [ 42]; 197 u32 wsr_ma_helper [ 4]; 198 199 /* Data area */ 200 u32 zero [ 1]; 201 u32 scratch [ 1]; 202 u32 pm0_data_addr [ 1]; 203 u32 pm1_data_addr [ 1]; 204 u32 saved_dsa [ 1]; 205 u32 saved_drs [ 1]; 206 u32 done_pos [ 1]; 207 u32 startpos [ 1]; 208 u32 targtbl [ 1]; 209 /* End of data area */ 210 211 u32 snooptest [ 6]; 212 u32 snoopend [ 2]; 213 }; 214 215 static const struct SYM_FWA_SCR SYM_FWA_SCR = { 216 /*--------------------------< START >----------------------------*/ { 217 /* 218 * Switch the LED on. 219 * Will be patched with a NO_OP if LED 220 * not needed or not desired. 221 */ 222 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 223 0, 224 /* 225 * Clear SIGP. 226 */ 227 SCR_FROM_REG (ctest2), 228 0, 229 /* 230 * Stop here if the C code wants to perform 231 * some error recovery procedure manually. 232 * (Indicate this by setting SEM in ISTAT) 233 */ 234 SCR_FROM_REG (istat), 235 0, 236 /* 237 * Report to the C code the next position in 238 * the start queue the SCRIPTS will schedule. 239 * The C code must not change SCRATCHA. 240 */ 241 SCR_LOAD_ABS (scratcha, 4), 242 PADDR_B (startpos), 243 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 244 SIR_SCRIPT_STOPPED, 245 /* 246 * Start the next job. 247 * 248 * @DSA = start point for this job. 249 * SCRATCHA = address of this job in the start queue. 250 * 251 * We will restore startpos with SCRATCHA if we fails the 252 * arbitration or if it is the idle job. 253 * 254 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 255 * is a critical path. If it is partially executed, it then 256 * may happen that the job address is not yet in the DSA 257 * and the next queue position points to the next JOB. 258 */ 259 SCR_LOAD_ABS (dsa, 4), 260 PADDR_B (startpos), 261 SCR_LOAD_REL (temp, 4), 262 4, 263 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 264 SCR_STORE_ABS (temp, 4), 265 PADDR_B (startpos), 266 SCR_LOAD_REL (dsa, 4), 267 0, 268 }/*-------------------------< GETJOB_END >-----------------------*/,{ 269 SCR_LOAD_REL (temp, 4), 270 0, 271 SCR_RETURN, 272 0, 273 }/*-------------------------< SELECT >---------------------------*/,{ 274 /* 275 * DSA contains the address of a scheduled 276 * data structure. 277 * 278 * SCRATCHA contains the address of the start queue 279 * entry which points to the next job. 280 * 281 * Set Initiator mode. 282 * 283 * (Target mode is left as an exercise for the reader) 284 */ 285 SCR_CLR (SCR_TRG), 286 0, 287 /* 288 * And try to select this target. 289 */ 290 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 291 PADDR_A (ungetjob), 292 /* 293 * Now there are 4 possibilities: 294 * 295 * (1) The chip loses arbitration. 296 * This is ok, because it will try again, 297 * when the bus becomes idle. 298 * (But beware of the timeout function!) 299 * 300 * (2) The chip is reselected. 301 * Then the script processor takes the jump 302 * to the RESELECT label. 303 * 304 * (3) The chip wins arbitration. 305 * Then it will execute SCRIPTS instruction until 306 * the next instruction that checks SCSI phase. 307 * Then will stop and wait for selection to be 308 * complete or selection time-out to occur. 309 * 310 * After having won arbitration, the SCRIPTS 311 * processor is able to execute instructions while 312 * the SCSI core is performing SCSI selection. 313 */ 314 /* 315 * load the savep (saved data pointer) into 316 * the actual data pointer. 317 */ 318 SCR_LOAD_REL (temp, 4), 319 offsetof (struct sym_ccb, phys.head.savep), 320 /* 321 * Initialize the status registers 322 */ 323 SCR_LOAD_REL (scr0, 4), 324 offsetof (struct sym_ccb, phys.head.status), 325 }/*-------------------------< WF_SEL_DONE >----------------------*/,{ 326 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 327 SIR_SEL_ATN_NO_MSG_OUT, 328 }/*-------------------------< SEL_DONE >-------------------------*/,{ 329 /* 330 * C1010-33 errata work-around. 331 * Due to a race, the SCSI core may not have 332 * loaded SCNTL3 on SEL_TBL instruction. 333 * We reload it once phase is stable. 334 * Patched with a NOOP for other chips. 335 */ 336 SCR_LOAD_REL (scntl3, 1), 337 offsetof(struct sym_dsb, select.sel_scntl3), 338 }/*-------------------------< SEND_IDENT >-----------------------*/,{ 339 /* 340 * Selection complete. 341 * Send the IDENTIFY and possibly the TAG message 342 * and negotiation message if present. 343 */ 344 SCR_MOVE_TBL ^ SCR_MSG_OUT, 345 offsetof (struct sym_dsb, smsg), 346 }/*-------------------------< SELECT2 >--------------------------*/,{ 347 #ifdef SYM_CONF_IARB_SUPPORT 348 /* 349 * Set IMMEDIATE ARBITRATION if we have been given 350 * a hint to do so. (Some job to do after this one). 351 */ 352 SCR_FROM_REG (HF_REG), 353 0, 354 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 355 8, 356 SCR_REG_REG (scntl1, SCR_OR, IARB), 357 0, 358 #endif 359 /* 360 * Anticipate the COMMAND phase. 361 * This is the PHASE we expect at this point. 362 */ 363 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 364 PADDR_A (sel_no_cmd), 365 }/*-------------------------< COMMAND >--------------------------*/,{ 366 /* 367 * ... and send the command 368 */ 369 SCR_MOVE_TBL ^ SCR_COMMAND, 370 offsetof (struct sym_dsb, cmd), 371 }/*-------------------------< DISPATCH >-------------------------*/,{ 372 /* 373 * MSG_IN is the only phase that shall be 374 * entered at least once for each (re)selection. 375 * So we test it first. 376 */ 377 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 378 PADDR_A (msg_in), 379 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 380 PADDR_A (datao_phase), 381 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 382 PADDR_A (datai_phase), 383 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 384 PADDR_A (status), 385 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 386 PADDR_A (command), 387 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 388 PADDR_B (msg_out), 389 /* 390 * Discard as many illegal phases as 391 * required and tell the C code about. 392 */ 393 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 394 16, 395 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 396 HADDR_1 (scratch), 397 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 398 -16, 399 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 400 16, 401 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 402 HADDR_1 (scratch), 403 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 404 -16, 405 SCR_INT, 406 SIR_BAD_PHASE, 407 SCR_JUMP, 408 PADDR_A (dispatch), 409 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 410 /* 411 * The target does not switch to command 412 * phase after IDENTIFY has been sent. 413 * 414 * If it stays in MSG OUT phase send it 415 * the IDENTIFY again. 416 */ 417 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 418 PADDR_B (resend_ident), 419 /* 420 * If target does not switch to MSG IN phase 421 * and we sent a negotiation, assert the 422 * failure immediately. 423 */ 424 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 425 PADDR_A (dispatch), 426 SCR_FROM_REG (HS_REG), 427 0, 428 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 429 SIR_NEGO_FAILED, 430 /* 431 * Jump to dispatcher. 432 */ 433 SCR_JUMP, 434 PADDR_A (dispatch), 435 }/*-------------------------< INIT >-----------------------------*/,{ 436 /* 437 * Wait for the SCSI RESET signal to be 438 * inactive before restarting operations, 439 * since the chip may hang on SEL_ATN 440 * if SCSI RESET is active. 441 */ 442 SCR_FROM_REG (sstat0), 443 0, 444 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 445 -16, 446 SCR_JUMP, 447 PADDR_A (start), 448 }/*-------------------------< CLRACK >---------------------------*/,{ 449 /* 450 * Terminate possible pending message phase. 451 */ 452 SCR_CLR (SCR_ACK), 453 0, 454 SCR_JUMP, 455 PADDR_A (dispatch), 456 }/*-------------------------< DISP_STATUS >----------------------*/,{ 457 /* 458 * Anticipate STATUS phase. 459 * 460 * Does spare 3 SCRIPTS instructions when we have 461 * completed the INPUT of the data. 462 */ 463 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 464 PADDR_A (status), 465 SCR_JUMP, 466 PADDR_A (dispatch), 467 }/*-------------------------< DATAI_DONE >-----------------------*/,{ 468 /* 469 * If the device still wants to send us data, 470 * we must count the extra bytes. 471 */ 472 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)), 473 PADDR_B (data_ovrun), 474 /* 475 * If the SWIDE is not full, jump to dispatcher. 476 * We anticipate a STATUS phase. 477 */ 478 SCR_FROM_REG (scntl2), 479 0, 480 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)), 481 PADDR_A (disp_status), 482 /* 483 * The SWIDE is full. 484 * Clear this condition. 485 */ 486 SCR_REG_REG (scntl2, SCR_OR, WSR), 487 0, 488 /* 489 * We are expecting an IGNORE RESIDUE message 490 * from the device, otherwise we are in data 491 * overrun condition. Check against MSG_IN phase. 492 */ 493 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 494 SIR_SWIDE_OVERRUN, 495 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 496 PADDR_A (disp_status), 497 /* 498 * We are in MSG_IN phase, 499 * Read the first byte of the message. 500 * If it is not an IGNORE RESIDUE message, 501 * signal overrun and jump to message 502 * processing. 503 */ 504 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 505 HADDR_1 (msgin[0]), 506 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 507 SIR_SWIDE_OVERRUN, 508 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 509 PADDR_A (msg_in2), 510 /* 511 * We got the message we expected. 512 * Read the 2nd byte, and jump to dispatcher. 513 */ 514 SCR_CLR (SCR_ACK), 515 0, 516 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 517 HADDR_1 (msgin[1]), 518 SCR_CLR (SCR_ACK), 519 0, 520 SCR_JUMP, 521 PADDR_A (disp_status), 522 }/*-------------------------< DATAO_DONE >-----------------------*/,{ 523 /* 524 * If the device wants us to send more data, 525 * we must count the extra bytes. 526 */ 527 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 528 PADDR_B (data_ovrun), 529 /* 530 * If the SODL is not full jump to dispatcher. 531 * We anticipate a STATUS phase. 532 */ 533 SCR_FROM_REG (scntl2), 534 0, 535 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)), 536 PADDR_A (disp_status), 537 /* 538 * The SODL is full, clear this condition. 539 */ 540 SCR_REG_REG (scntl2, SCR_OR, WSS), 541 0, 542 /* 543 * And signal a DATA UNDERRUN condition 544 * to the C code. 545 */ 546 SCR_INT, 547 SIR_SODL_UNDERRUN, 548 SCR_JUMP, 549 PADDR_A (dispatch), 550 }/*-------------------------< DATAI_PHASE >----------------------*/,{ 551 SCR_RETURN, 552 0, 553 }/*-------------------------< DATAO_PHASE >----------------------*/,{ 554 /* 555 * C1010-66 errata work-around. 556 * Extra clocks of data hold must be inserted 557 * in DATA OUT phase on 33 MHz PCI BUS. 558 * Patched with a NOOP for other chips. 559 */ 560 SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)), 561 0, 562 SCR_RETURN, 563 0, 564 }/*-------------------------< MSG_IN >---------------------------*/,{ 565 /* 566 * Get the first byte of the message. 567 * 568 * The script processor doesn't negate the 569 * ACK signal after this transfer. 570 */ 571 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 572 HADDR_1 (msgin[0]), 573 }/*-------------------------< MSG_IN2 >--------------------------*/,{ 574 /* 575 * Check first against 1 byte messages 576 * that we handle from SCRIPTS. 577 */ 578 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 579 PADDR_A (complete), 580 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 581 PADDR_A (disconnect), 582 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 583 PADDR_A (save_dp), 584 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 585 PADDR_A (restore_dp), 586 /* 587 * We handle all other messages from the 588 * C code, so no need to waste on-chip RAM 589 * for those ones. 590 */ 591 SCR_JUMP, 592 PADDR_B (msg_in_etc), 593 }/*-------------------------< STATUS >---------------------------*/,{ 594 /* 595 * get the status 596 */ 597 SCR_MOVE_ABS (1) ^ SCR_STATUS, 598 HADDR_1 (scratch), 599 #ifdef SYM_CONF_IARB_SUPPORT 600 /* 601 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 602 * since we may have to tamper the start queue from 603 * the C code. 604 */ 605 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 606 8, 607 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 608 0, 609 #endif 610 /* 611 * save status to scsi_status. 612 * mark as complete. 613 */ 614 SCR_TO_REG (SS_REG), 615 0, 616 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 617 0, 618 /* 619 * Anticipate the MESSAGE PHASE for 620 * the TASK COMPLETE message. 621 */ 622 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 623 PADDR_A (msg_in), 624 SCR_JUMP, 625 PADDR_A (dispatch), 626 }/*-------------------------< COMPLETE >-------------------------*/,{ 627 /* 628 * Complete message. 629 * 630 * Copy the data pointer to LASTP. 631 */ 632 SCR_STORE_REL (temp, 4), 633 offsetof (struct sym_ccb, phys.head.lastp), 634 /* 635 * When we terminate the cycle by clearing ACK, 636 * the target may disconnect immediately. 637 * 638 * We don't want to be told of an "unexpected disconnect", 639 * so we disable this feature. 640 */ 641 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 642 0, 643 /* 644 * Terminate cycle ... 645 */ 646 SCR_CLR (SCR_ACK|SCR_ATN), 647 0, 648 /* 649 * ... and wait for the disconnect. 650 */ 651 SCR_WAIT_DISC, 652 0, 653 }/*-------------------------< COMPLETE2 >------------------------*/,{ 654 /* 655 * Save host status. 656 */ 657 SCR_STORE_REL (scr0, 4), 658 offsetof (struct sym_ccb, phys.head.status), 659 /* 660 * Some bridges may reorder DMA writes to memory. 661 * We donnot want the CPU to deal with completions 662 * without all the posted write having been flushed 663 * to memory. This DUMMY READ should flush posted 664 * buffers prior to the CPU having to deal with 665 * completions. 666 */ 667 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */ 668 offsetof (struct sym_ccb, phys.head.status), 669 670 /* 671 * If command resulted in not GOOD status, 672 * call the C code if needed. 673 */ 674 SCR_FROM_REG (SS_REG), 675 0, 676 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 677 PADDR_B (bad_status), 678 /* 679 * If we performed an auto-sense, call 680 * the C code to synchronyze task aborts 681 * with UNIT ATTENTION conditions. 682 */ 683 SCR_FROM_REG (HF_REG), 684 0, 685 SCR_JUMPR ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 686 16, 687 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 688 SCR_LOAD_ABS (scratcha, 4), 689 PADDR_B (startpos), 690 SCR_INT, 691 SIR_COMPLETE_ERROR, 692 }/*-------------------------< DONE >-----------------------------*/,{ 693 /* 694 * Copy the DSA to the DONE QUEUE and 695 * signal completion to the host. 696 * If we are interrupted between DONE 697 * and DONE_END, we must reset, otherwise 698 * the completed CCB may be lost. 699 */ 700 SCR_STORE_ABS (dsa, 4), 701 PADDR_B (saved_dsa), 702 SCR_LOAD_ABS (dsa, 4), 703 PADDR_B (done_pos), 704 SCR_LOAD_ABS (scratcha, 4), 705 PADDR_B (saved_dsa), 706 SCR_STORE_REL (scratcha, 4), 707 0, 708 /* 709 * The instruction below reads the DONE QUEUE next 710 * free position from memory. 711 * In addition it ensures that all PCI posted writes 712 * are flushed and so the DSA value of the done 713 * CCB is visible by the CPU before INTFLY is raised. 714 */ 715 SCR_LOAD_REL (temp, 4), 716 4, 717 SCR_INT_FLY, 718 0, 719 SCR_STORE_ABS (temp, 4), 720 PADDR_B (done_pos), 721 }/*-------------------------< DONE_END >-------------------------*/,{ 722 SCR_JUMP, 723 PADDR_A (start), 724 }/*-------------------------< SAVE_DP >--------------------------*/,{ 725 /* 726 * Clear ACK immediately. 727 * No need to delay it. 728 */ 729 SCR_CLR (SCR_ACK), 730 0, 731 /* 732 * Keep track we received a SAVE DP, so 733 * we will switch to the other PM context 734 * on the next PM since the DP may point 735 * to the current PM context. 736 */ 737 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 738 0, 739 /* 740 * SAVE_DP message: 741 * Copy the data pointer to SAVEP. 742 */ 743 SCR_STORE_REL (temp, 4), 744 offsetof (struct sym_ccb, phys.head.savep), 745 SCR_JUMP, 746 PADDR_A (dispatch), 747 }/*-------------------------< RESTORE_DP >-----------------------*/,{ 748 /* 749 * RESTORE_DP message: 750 * Copy SAVEP to actual data pointer. 751 */ 752 SCR_LOAD_REL (temp, 4), 753 offsetof (struct sym_ccb, phys.head.savep), 754 SCR_JUMP, 755 PADDR_A (clrack), 756 }/*-------------------------< DISCONNECT >-----------------------*/,{ 757 /* 758 * DISCONNECTing ... 759 * 760 * disable the "unexpected disconnect" feature, 761 * and remove the ACK signal. 762 */ 763 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 764 0, 765 SCR_CLR (SCR_ACK|SCR_ATN), 766 0, 767 /* 768 * Wait for the disconnect. 769 */ 770 SCR_WAIT_DISC, 771 0, 772 /* 773 * Status is: DISCONNECTED. 774 */ 775 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 776 0, 777 /* 778 * Save host status. 779 */ 780 SCR_STORE_REL (scr0, 4), 781 offsetof (struct sym_ccb, phys.head.status), 782 /* 783 * If QUIRK_AUTOSAVE is set, 784 * do a "save pointer" operation. 785 */ 786 SCR_FROM_REG (QU_REG), 787 0, 788 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)), 789 PADDR_A (start), 790 /* 791 * like SAVE_DP message: 792 * Remember we saved the data pointer. 793 * Copy data pointer to SAVEP. 794 */ 795 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 796 0, 797 SCR_STORE_REL (temp, 4), 798 offsetof (struct sym_ccb, phys.head.savep), 799 SCR_JUMP, 800 PADDR_A (start), 801 }/*-------------------------< IDLE >-----------------------------*/,{ 802 /* 803 * Nothing to do? 804 * Switch the LED off and wait for reselect. 805 * Will be patched with a NO_OP if LED 806 * not needed or not desired. 807 */ 808 SCR_REG_REG (gpreg, SCR_OR, 0x01), 809 0, 810 #ifdef SYM_CONF_IARB_SUPPORT 811 SCR_JUMPR, 812 8, 813 #endif 814 }/*-------------------------< UNGETJOB >-------------------------*/,{ 815 #ifdef SYM_CONF_IARB_SUPPORT 816 /* 817 * Set IMMEDIATE ARBITRATION, for the next time. 818 * This will give us better chance to win arbitration 819 * for the job we just wanted to do. 820 */ 821 SCR_REG_REG (scntl1, SCR_OR, IARB), 822 0, 823 #endif 824 /* 825 * We are not able to restart the SCRIPTS if we are 826 * interrupted and these instruction haven't been 827 * all executed. BTW, this is very unlikely to 828 * happen, but we check that from the C code. 829 */ 830 SCR_LOAD_REG (dsa, 0xff), 831 0, 832 SCR_STORE_ABS (scratcha, 4), 833 PADDR_B (startpos), 834 }/*-------------------------< RESELECT >-------------------------*/,{ 835 /* 836 * Make sure we are in initiator mode. 837 */ 838 SCR_CLR (SCR_TRG), 839 0, 840 /* 841 * Sleep waiting for a reselection. 842 */ 843 SCR_WAIT_RESEL, 844 PADDR_A(start), 845 }/*-------------------------< RESELECTED >-----------------------*/,{ 846 /* 847 * Switch the LED on. 848 * Will be patched with a NO_OP if LED 849 * not needed or not desired. 850 */ 851 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 852 0, 853 /* 854 * load the target id into the sdid 855 */ 856 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 857 0, 858 SCR_TO_REG (sdid), 859 0, 860 /* 861 * Load the target control block address 862 */ 863 SCR_LOAD_ABS (dsa, 4), 864 PADDR_B (targtbl), 865 SCR_SFBR_REG (dsa, SCR_SHL, 0), 866 0, 867 SCR_REG_REG (dsa, SCR_SHL, 0), 868 0, 869 SCR_REG_REG (dsa, SCR_AND, 0x3c), 870 0, 871 SCR_LOAD_REL (dsa, 4), 872 0, 873 /* 874 * We expect MESSAGE IN phase. 875 * If not, get help from the C code. 876 */ 877 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 878 SIR_RESEL_NO_MSG_IN, 879 /* 880 * Load the legacy synchronous transfer registers. 881 */ 882 SCR_LOAD_REL (scntl3, 1), 883 offsetof(struct sym_tcb, head.wval), 884 SCR_LOAD_REL (sxfer, 1), 885 offsetof(struct sym_tcb, head.sval), 886 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{ 887 /* 888 * The C1010 uses a new synchronous timing scheme. 889 * Will be patched with a NO_OP if not a C1010. 890 */ 891 SCR_LOAD_REL (scntl4, 1), 892 offsetof(struct sym_tcb, head.uval), 893 /* 894 * Get the IDENTIFY message. 895 */ 896 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 897 HADDR_1 (msgin), 898 /* 899 * If IDENTIFY LUN #0, use a faster path 900 * to find the LCB structure. 901 */ 902 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 903 PADDR_A (resel_lun0), 904 /* 905 * If message isn't an IDENTIFY, 906 * tell the C code about. 907 */ 908 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 909 SIR_RESEL_NO_IDENTIFY, 910 /* 911 * It is an IDENTIFY message, 912 * Load the LUN control block address. 913 */ 914 SCR_LOAD_REL (dsa, 4), 915 offsetof(struct sym_tcb, head.luntbl_sa), 916 SCR_SFBR_REG (dsa, SCR_SHL, 0), 917 0, 918 SCR_REG_REG (dsa, SCR_SHL, 0), 919 0, 920 SCR_REG_REG (dsa, SCR_AND, 0xfc), 921 0, 922 SCR_LOAD_REL (dsa, 4), 923 0, 924 SCR_JUMPR, 925 8, 926 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 927 /* 928 * LUN 0 special case (but usual one :)) 929 */ 930 SCR_LOAD_REL (dsa, 4), 931 offsetof(struct sym_tcb, head.lun0_sa), 932 /* 933 * Jump indirectly to the reselect action for this LUN. 934 */ 935 SCR_LOAD_REL (temp, 4), 936 offsetof(struct sym_lcb, head.resel_sa), 937 SCR_RETURN, 938 0, 939 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 940 }/*-------------------------< RESEL_TAG >------------------------*/,{ 941 /* 942 * ACK the IDENTIFY previously received. 943 */ 944 SCR_CLR (SCR_ACK), 945 0, 946 /* 947 * It shall be a tagged command. 948 * Read SIMPLE+TAG. 949 * The C code will deal with errors. 950 * Aggressive optimization, isn't it? :) 951 */ 952 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 953 HADDR_1 (msgin), 954 /* 955 * Load the pointer to the tagged task 956 * table for this LUN. 957 */ 958 SCR_LOAD_REL (dsa, 4), 959 offsetof(struct sym_lcb, head.itlq_tbl_sa), 960 /* 961 * The SIDL still contains the TAG value. 962 * Aggressive optimization, isn't it? :):) 963 */ 964 SCR_REG_SFBR (sidl, SCR_SHL, 0), 965 0, 966 #if SYM_CONF_MAX_TASK*4 > 512 967 SCR_JUMPR ^ IFFALSE (CARRYSET), 968 8, 969 SCR_REG_REG (dsa1, SCR_OR, 2), 970 0, 971 SCR_REG_REG (sfbr, SCR_SHL, 0), 972 0, 973 SCR_JUMPR ^ IFFALSE (CARRYSET), 974 8, 975 SCR_REG_REG (dsa1, SCR_OR, 1), 976 0, 977 #elif SYM_CONF_MAX_TASK*4 > 256 978 SCR_JUMPR ^ IFFALSE (CARRYSET), 979 8, 980 SCR_REG_REG (dsa1, SCR_OR, 1), 981 0, 982 #endif 983 /* 984 * Retrieve the DSA of this task. 985 * JUMP indirectly to the restart point of the CCB. 986 */ 987 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 988 0, 989 SCR_LOAD_REL (dsa, 4), 990 0, 991 SCR_LOAD_REL (temp, 4), 992 offsetof(struct sym_ccb, phys.head.go.restart), 993 SCR_RETURN, 994 0, 995 /* In normal situations we branch to RESEL_DSA */ 996 }/*-------------------------< RESEL_DSA >------------------------*/,{ 997 /* 998 * ACK the IDENTIFY or TAG previously received. 999 */ 1000 SCR_CLR (SCR_ACK), 1001 0, 1002 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1003 /* 1004 * load the savep (saved pointer) into 1005 * the actual data pointer. 1006 */ 1007 SCR_LOAD_REL (temp, 4), 1008 offsetof (struct sym_ccb, phys.head.savep), 1009 /* 1010 * Initialize the status registers 1011 */ 1012 SCR_LOAD_REL (scr0, 4), 1013 offsetof (struct sym_ccb, phys.head.status), 1014 /* 1015 * Jump to dispatcher. 1016 */ 1017 SCR_JUMP, 1018 PADDR_A (dispatch), 1019 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1020 /* 1021 * Load the DSA with the unique ITL task. 1022 */ 1023 SCR_LOAD_REL (dsa, 4), 1024 offsetof(struct sym_lcb, head.itl_task_sa), 1025 /* 1026 * JUMP indirectly to the restart point of the CCB. 1027 */ 1028 SCR_LOAD_REL (temp, 4), 1029 offsetof(struct sym_ccb, phys.head.go.restart), 1030 SCR_RETURN, 1031 0, 1032 /* In normal situations we branch to RESEL_DSA */ 1033 }/*-------------------------< DATA_IN >--------------------------*/,{ 1034 /* 1035 * Because the size depends on the 1036 * #define SYM_CONF_MAX_SG parameter, 1037 * it is filled in at runtime. 1038 * 1039 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1040 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1041 * || offsetof (struct sym_dsb, data[ i]), 1042 * ##========================================== 1043 */ 1044 1045 }/*-------------------------< DATA_IN2 >-------------------------*/,{ 1046 SCR_CALL, 1047 PADDR_A (datai_done), 1048 SCR_JUMP, 1049 PADDR_B (data_ovrun), 1050 }/*-------------------------< DATA_OUT >-------------------------*/,{ 1051 /* 1052 * Because the size depends on the 1053 * #define SYM_CONF_MAX_SG parameter, 1054 * it is filled in at runtime. 1055 * 1056 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1057 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1058 * || offsetof (struct sym_dsb, data[ i]), 1059 * ##========================================== 1060 */ 1061 1062 }/*-------------------------< DATA_OUT2 >------------------------*/,{ 1063 SCR_CALL, 1064 PADDR_A (datao_done), 1065 SCR_JUMP, 1066 PADDR_B (data_ovrun), 1067 }/*-------------------------< PM0_DATA >-------------------------*/,{ 1068 /* 1069 * Read our host flags to SFBR, so we will be able 1070 * to check against the data direction we expect. 1071 */ 1072 SCR_FROM_REG (HF_REG), 1073 0, 1074 /* 1075 * Check against actual DATA PHASE. 1076 */ 1077 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1078 PADDR_A (pm0_data_out), 1079 /* 1080 * Actual phase is DATA IN. 1081 * Check against expected direction. 1082 */ 1083 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1084 PADDR_B (data_ovrun), 1085 /* 1086 * Keep track we are moving data from the 1087 * PM0 DATA mini-script. 1088 */ 1089 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1090 0, 1091 /* 1092 * Move the data to memory. 1093 */ 1094 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1095 offsetof (struct sym_ccb, phys.pm0.sg), 1096 SCR_JUMP, 1097 PADDR_A (pm0_data_end), 1098 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1099 /* 1100 * Actual phase is DATA OUT. 1101 * Check against expected direction. 1102 */ 1103 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1104 PADDR_B (data_ovrun), 1105 /* 1106 * Keep track we are moving data from the 1107 * PM0 DATA mini-script. 1108 */ 1109 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1110 0, 1111 /* 1112 * Move the data from memory. 1113 */ 1114 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1115 offsetof (struct sym_ccb, phys.pm0.sg), 1116 }/*-------------------------< PM0_DATA_END >---------------------*/,{ 1117 /* 1118 * Clear the flag that told we were moving 1119 * data from the PM0 DATA mini-script. 1120 */ 1121 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1122 0, 1123 /* 1124 * Return to the previous DATA script which 1125 * is guaranteed by design (if no bug) to be 1126 * the main DATA script for this transfer. 1127 */ 1128 SCR_LOAD_REL (temp, 4), 1129 offsetof (struct sym_ccb, phys.pm0.ret), 1130 SCR_RETURN, 1131 0, 1132 }/*-------------------------< PM1_DATA >-------------------------*/,{ 1133 /* 1134 * Read our host flags to SFBR, so we will be able 1135 * to check against the data direction we expect. 1136 */ 1137 SCR_FROM_REG (HF_REG), 1138 0, 1139 /* 1140 * Check against actual DATA PHASE. 1141 */ 1142 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1143 PADDR_A (pm1_data_out), 1144 /* 1145 * Actual phase is DATA IN. 1146 * Check against expected direction. 1147 */ 1148 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1149 PADDR_B (data_ovrun), 1150 /* 1151 * Keep track we are moving data from the 1152 * PM1 DATA mini-script. 1153 */ 1154 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1155 0, 1156 /* 1157 * Move the data to memory. 1158 */ 1159 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1160 offsetof (struct sym_ccb, phys.pm1.sg), 1161 SCR_JUMP, 1162 PADDR_A (pm1_data_end), 1163 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1164 /* 1165 * Actual phase is DATA OUT. 1166 * Check against expected direction. 1167 */ 1168 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1169 PADDR_B (data_ovrun), 1170 /* 1171 * Keep track we are moving data from the 1172 * PM1 DATA mini-script. 1173 */ 1174 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1175 0, 1176 /* 1177 * Move the data from memory. 1178 */ 1179 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1180 offsetof (struct sym_ccb, phys.pm1.sg), 1181 }/*-------------------------< PM1_DATA_END >---------------------*/,{ 1182 /* 1183 * Clear the flag that told we were moving 1184 * data from the PM1 DATA mini-script. 1185 */ 1186 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1187 0, 1188 /* 1189 * Return to the previous DATA script which 1190 * is guaranteed by design (if no bug) to be 1191 * the main DATA script for this transfer. 1192 */ 1193 SCR_LOAD_REL (temp, 4), 1194 offsetof (struct sym_ccb, phys.pm1.ret), 1195 SCR_RETURN, 1196 0, 1197 }/*-------------------------<>-----------------------------------*/ 1198 }; 1199 1200 static const struct SYM_FWB_SCR SYM_FWB_SCR = { 1201 /*--------------------------< START64 >--------------------------*/ { 1202 /* 1203 * SCRIPT entry point for the 895A, 896 and 1010. 1204 * For now, there is no specific stuff for those 1205 * chips at this point, but this may come. 1206 */ 1207 SCR_JUMP, 1208 PADDR_A (init), 1209 }/*-------------------------< NO_DATA >--------------------------*/,{ 1210 SCR_JUMP, 1211 PADDR_B (data_ovrun), 1212 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1213 /* 1214 * We are jumped here by the C code, if we have 1215 * some target to reset or some disconnected 1216 * job to abort. Since error recovery is a serious 1217 * busyness, we will really reset the SCSI BUS, if 1218 * case of a SCSI interrupt occurring in this path. 1219 */ 1220 1221 /* 1222 * Set initiator mode. 1223 */ 1224 SCR_CLR (SCR_TRG), 1225 0, 1226 /* 1227 * And try to select this target. 1228 */ 1229 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1230 PADDR_A (reselect), 1231 /* 1232 * Wait for the selection to complete or 1233 * the selection to time out. 1234 */ 1235 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1236 -8, 1237 /* 1238 * Call the C code. 1239 */ 1240 SCR_INT, 1241 SIR_TARGET_SELECTED, 1242 /* 1243 * The C code should let us continue here. 1244 * Send the 'kiss of death' message. 1245 * We expect an immediate disconnect once 1246 * the target has eaten the message. 1247 */ 1248 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1249 0, 1250 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1251 offsetof (struct sym_hcb, abrt_tbl), 1252 SCR_CLR (SCR_ACK|SCR_ATN), 1253 0, 1254 SCR_WAIT_DISC, 1255 0, 1256 /* 1257 * Tell the C code that we are done. 1258 */ 1259 SCR_INT, 1260 SIR_ABORT_SENT, 1261 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1262 /* 1263 * Jump at scheduler. 1264 */ 1265 SCR_JUMP, 1266 PADDR_A (start), 1267 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1268 /* 1269 * If it is an EXTENDED (variable size message) 1270 * Handle it. 1271 */ 1272 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1273 PADDR_B (msg_extended), 1274 /* 1275 * Let the C code handle any other 1276 * 1 byte message. 1277 */ 1278 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1279 PADDR_B (msg_received), 1280 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1281 PADDR_B (msg_received), 1282 /* 1283 * We donnot handle 2 bytes messages from SCRIPTS. 1284 * So, let the C code deal with these ones too. 1285 */ 1286 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1287 PADDR_B (msg_weird_seen), 1288 SCR_CLR (SCR_ACK), 1289 0, 1290 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1291 HADDR_1 (msgin[1]), 1292 }/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1293 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1294 0, 1295 SCR_INT, 1296 SIR_MSG_RECEIVED, 1297 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1298 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1299 0, 1300 SCR_INT, 1301 SIR_MSG_WEIRD, 1302 }/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1303 /* 1304 * Clear ACK and get the next byte 1305 * assumed to be the message length. 1306 */ 1307 SCR_CLR (SCR_ACK), 1308 0, 1309 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1310 HADDR_1 (msgin[1]), 1311 /* 1312 * Try to catch some unlikely situations as 0 length 1313 * or too large the length. 1314 */ 1315 SCR_JUMP ^ IFTRUE (DATA (0)), 1316 PADDR_B (msg_weird_seen), 1317 SCR_TO_REG (scratcha), 1318 0, 1319 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1320 0, 1321 SCR_JUMP ^ IFTRUE (CARRYSET), 1322 PADDR_B (msg_weird_seen), 1323 /* 1324 * We donnot handle extended messages from SCRIPTS. 1325 * Read the amount of data corresponding to the 1326 * message length and call the C code. 1327 */ 1328 SCR_STORE_REL (scratcha, 1), 1329 offsetof (struct sym_dsb, smsg_ext.size), 1330 SCR_CLR (SCR_ACK), 1331 0, 1332 SCR_MOVE_TBL ^ SCR_MSG_IN, 1333 offsetof (struct sym_dsb, smsg_ext), 1334 SCR_JUMP, 1335 PADDR_B (msg_received), 1336 }/*-------------------------< MSG_BAD >--------------------------*/,{ 1337 /* 1338 * unimplemented message - reject it. 1339 */ 1340 SCR_INT, 1341 SIR_REJECT_TO_SEND, 1342 SCR_SET (SCR_ATN), 1343 0, 1344 SCR_JUMP, 1345 PADDR_A (clrack), 1346 }/*-------------------------< MSG_WEIRD >------------------------*/,{ 1347 /* 1348 * weird message received 1349 * ignore all MSG IN phases and reject it. 1350 */ 1351 SCR_INT, 1352 SIR_REJECT_TO_SEND, 1353 SCR_SET (SCR_ATN), 1354 0, 1355 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1356 SCR_CLR (SCR_ACK), 1357 0, 1358 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1359 PADDR_A (dispatch), 1360 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1361 HADDR_1 (scratch), 1362 SCR_JUMP, 1363 PADDR_B (msg_weird1), 1364 }/*-------------------------< WDTR_RESP >------------------------*/,{ 1365 /* 1366 * let the target fetch our answer. 1367 */ 1368 SCR_SET (SCR_ATN), 1369 0, 1370 SCR_CLR (SCR_ACK), 1371 0, 1372 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1373 PADDR_B (nego_bad_phase), 1374 }/*-------------------------< SEND_WDTR >------------------------*/,{ 1375 /* 1376 * Send the M_X_WIDE_REQ 1377 */ 1378 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1379 HADDR_1 (msgout), 1380 SCR_JUMP, 1381 PADDR_B (msg_out_done), 1382 }/*-------------------------< SDTR_RESP >------------------------*/,{ 1383 /* 1384 * let the target fetch our answer. 1385 */ 1386 SCR_SET (SCR_ATN), 1387 0, 1388 SCR_CLR (SCR_ACK), 1389 0, 1390 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1391 PADDR_B (nego_bad_phase), 1392 }/*-------------------------< SEND_SDTR >------------------------*/,{ 1393 /* 1394 * Send the M_X_SYNC_REQ 1395 */ 1396 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1397 HADDR_1 (msgout), 1398 SCR_JUMP, 1399 PADDR_B (msg_out_done), 1400 }/*-------------------------< PPR_RESP >-------------------------*/,{ 1401 /* 1402 * let the target fetch our answer. 1403 */ 1404 SCR_SET (SCR_ATN), 1405 0, 1406 SCR_CLR (SCR_ACK), 1407 0, 1408 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1409 PADDR_B (nego_bad_phase), 1410 }/*-------------------------< SEND_PPR >-------------------------*/,{ 1411 /* 1412 * Send the M_X_PPR_REQ 1413 */ 1414 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1415 HADDR_1 (msgout), 1416 SCR_JUMP, 1417 PADDR_B (msg_out_done), 1418 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1419 SCR_INT, 1420 SIR_NEGO_PROTO, 1421 SCR_JUMP, 1422 PADDR_A (dispatch), 1423 }/*-------------------------< MSG_OUT >--------------------------*/,{ 1424 /* 1425 * The target requests a message. 1426 * We donnot send messages that may 1427 * require the device to go to bus free. 1428 */ 1429 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1430 HADDR_1 (msgout), 1431 /* 1432 * ... wait for the next phase 1433 * if it's a message out, send it again, ... 1434 */ 1435 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1436 PADDR_B (msg_out), 1437 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1438 /* 1439 * Let the C code be aware of the 1440 * sent message and clear the message. 1441 */ 1442 SCR_INT, 1443 SIR_MSG_OUT_DONE, 1444 /* 1445 * ... and process the next phase 1446 */ 1447 SCR_JUMP, 1448 PADDR_A (dispatch), 1449 }/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1450 /* 1451 * Use scratcha to count the extra bytes. 1452 */ 1453 SCR_LOAD_ABS (scratcha, 4), 1454 PADDR_B (zero), 1455 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1456 /* 1457 * The target may want to transfer too much data. 1458 * 1459 * If phase is DATA OUT write 1 byte and count it. 1460 */ 1461 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1462 16, 1463 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1464 HADDR_1 (scratch), 1465 SCR_JUMP, 1466 PADDR_B (data_ovrun2), 1467 /* 1468 * If WSR is set, clear this condition, and 1469 * count this byte. 1470 */ 1471 SCR_FROM_REG (scntl2), 1472 0, 1473 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1474 16, 1475 SCR_REG_REG (scntl2, SCR_OR, WSR), 1476 0, 1477 SCR_JUMP, 1478 PADDR_B (data_ovrun2), 1479 /* 1480 * Finally check against DATA IN phase. 1481 * Signal data overrun to the C code 1482 * and jump to dispatcher if not so. 1483 * Read 1 byte otherwise and count it. 1484 */ 1485 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1486 16, 1487 SCR_INT, 1488 SIR_DATA_OVERRUN, 1489 SCR_JUMP, 1490 PADDR_A (dispatch), 1491 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1492 HADDR_1 (scratch), 1493 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1494 /* 1495 * Count this byte. 1496 * This will allow to return a negative 1497 * residual to user. 1498 */ 1499 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1500 0, 1501 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1502 0, 1503 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1504 0, 1505 /* 1506 * .. and repeat as required. 1507 */ 1508 SCR_JUMP, 1509 PADDR_B (data_ovrun1), 1510 }/*-------------------------< ABORT_RESEL >----------------------*/,{ 1511 SCR_SET (SCR_ATN), 1512 0, 1513 SCR_CLR (SCR_ACK), 1514 0, 1515 /* 1516 * send the abort/abortag/reset message 1517 * we expect an immediate disconnect 1518 */ 1519 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1520 0, 1521 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1522 HADDR_1 (msgout), 1523 SCR_CLR (SCR_ACK|SCR_ATN), 1524 0, 1525 SCR_WAIT_DISC, 1526 0, 1527 SCR_INT, 1528 SIR_RESEL_ABORTED, 1529 SCR_JUMP, 1530 PADDR_A (start), 1531 }/*-------------------------< RESEND_IDENT >---------------------*/,{ 1532 /* 1533 * The target stays in MSG OUT phase after having acked 1534 * Identify [+ Tag [+ Extended message ]]. Targets shall 1535 * behave this way on parity error. 1536 * We must send it again all the messages. 1537 */ 1538 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1539 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1540 SCR_JUMP, 1541 PADDR_A (send_ident), 1542 }/*-------------------------< IDENT_BREAK >----------------------*/,{ 1543 SCR_CLR (SCR_ATN), 1544 0, 1545 SCR_JUMP, 1546 PADDR_A (select2), 1547 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1548 SCR_SET (SCR_ATN), 1549 0, 1550 SCR_JUMP, 1551 PADDR_A (select2), 1552 }/*-------------------------< SDATA_IN >-------------------------*/,{ 1553 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1554 offsetof (struct sym_dsb, sense), 1555 SCR_CALL, 1556 PADDR_A (datai_done), 1557 SCR_JUMP, 1558 PADDR_B (data_ovrun), 1559 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1560 /* 1561 * Message is an IDENTIFY, but lun is unknown. 1562 * Signal problem to C code for logging the event. 1563 * Send a M_ABORT to clear all pending tasks. 1564 */ 1565 SCR_INT, 1566 SIR_RESEL_BAD_LUN, 1567 SCR_JUMP, 1568 PADDR_B (abort_resel), 1569 }/*-------------------------< BAD_I_T_L >------------------------*/,{ 1570 /* 1571 * We donnot have a task for that I_T_L. 1572 * Signal problem to C code for logging the event. 1573 * Send a M_ABORT message. 1574 */ 1575 SCR_INT, 1576 SIR_RESEL_BAD_I_T_L, 1577 SCR_JUMP, 1578 PADDR_B (abort_resel), 1579 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1580 /* 1581 * We donnot have a task that matches the tag. 1582 * Signal problem to C code for logging the event. 1583 * Send a M_ABORTTAG message. 1584 */ 1585 SCR_INT, 1586 SIR_RESEL_BAD_I_T_L_Q, 1587 SCR_JUMP, 1588 PADDR_B (abort_resel), 1589 }/*-------------------------< BAD_STATUS >-----------------------*/,{ 1590 /* 1591 * Anything different from INTERMEDIATE 1592 * CONDITION MET should be a bad SCSI status, 1593 * given that GOOD status has already been tested. 1594 * Call the C code. 1595 */ 1596 SCR_LOAD_ABS (scratcha, 4), 1597 PADDR_B (startpos), 1598 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1599 SIR_BAD_SCSI_STATUS, 1600 SCR_RETURN, 1601 0, 1602 }/*-------------------------< PM_HANDLE >------------------------*/,{ 1603 /* 1604 * Phase mismatch handling. 1605 * 1606 * Since we have to deal with 2 SCSI data pointers 1607 * (current and saved), we need at least 2 contexts. 1608 * Each context (pm0 and pm1) has a saved area, a 1609 * SAVE mini-script and a DATA phase mini-script. 1610 */ 1611 /* 1612 * Get the PM handling flags. 1613 */ 1614 SCR_FROM_REG (HF_REG), 1615 0, 1616 /* 1617 * If no flags (1rst PM for example), avoid 1618 * all the below heavy flags testing. 1619 * This makes the normal case a bit faster. 1620 */ 1621 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))), 1622 PADDR_B (pm_handle1), 1623 /* 1624 * If we received a SAVE DP, switch to the 1625 * other PM context since the savep may point 1626 * to the current PM context. 1627 */ 1628 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)), 1629 8, 1630 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM), 1631 0, 1632 /* 1633 * If we have been interrupt in a PM DATA mini-script, 1634 * we take the return address from the corresponding 1635 * saved area. 1636 * This ensure the return address always points to the 1637 * main DATA script for this transfer. 1638 */ 1639 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))), 1640 PADDR_B (pm_handle1), 1641 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)), 1642 16, 1643 SCR_LOAD_REL (ia, 4), 1644 offsetof(struct sym_ccb, phys.pm0.ret), 1645 SCR_JUMP, 1646 PADDR_B (pm_save), 1647 SCR_LOAD_REL (ia, 4), 1648 offsetof(struct sym_ccb, phys.pm1.ret), 1649 SCR_JUMP, 1650 PADDR_B (pm_save), 1651 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{ 1652 /* 1653 * Normal case. 1654 * Update the return address so that it 1655 * will point after the interrupted MOVE. 1656 */ 1657 SCR_REG_REG (ia, SCR_ADD, 8), 1658 0, 1659 SCR_REG_REG (ia1, SCR_ADDC, 0), 1660 0, 1661 }/*-------------------------< PM_SAVE >--------------------------*/,{ 1662 /* 1663 * Clear all the flags that told us if we were 1664 * interrupted in a PM DATA mini-script and/or 1665 * we received a SAVE DP. 1666 */ 1667 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))), 1668 0, 1669 /* 1670 * Choose the current PM context. 1671 */ 1672 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)), 1673 PADDR_B (pm1_save), 1674 }/*-------------------------< PM0_SAVE >-------------------------*/,{ 1675 SCR_STORE_REL (ia, 4), 1676 offsetof(struct sym_ccb, phys.pm0.ret), 1677 /* 1678 * If WSR bit is set, either UA and RBC may 1679 * have to be changed whether the device wants 1680 * to ignore this residue or not. 1681 */ 1682 SCR_FROM_REG (scntl2), 1683 0, 1684 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1685 PADDR_B (pm_wsr_handle), 1686 /* 1687 * Save the remaining byte count, the updated 1688 * address and the return address. 1689 */ 1690 SCR_STORE_REL (rbc, 4), 1691 offsetof(struct sym_ccb, phys.pm0.sg.size), 1692 SCR_STORE_REL (ua, 4), 1693 offsetof(struct sym_ccb, phys.pm0.sg.addr), 1694 /* 1695 * Set the current pointer at the PM0 DATA mini-script. 1696 */ 1697 SCR_LOAD_ABS (temp, 4), 1698 PADDR_B (pm0_data_addr), 1699 SCR_JUMP, 1700 PADDR_A (dispatch), 1701 }/*-------------------------< PM1_SAVE >-------------------------*/,{ 1702 SCR_STORE_REL (ia, 4), 1703 offsetof(struct sym_ccb, phys.pm1.ret), 1704 /* 1705 * If WSR bit is set, either UA and RBC may 1706 * have to be changed whether the device wants 1707 * to ignore this residue or not. 1708 */ 1709 SCR_FROM_REG (scntl2), 1710 0, 1711 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1712 PADDR_B (pm_wsr_handle), 1713 /* 1714 * Save the remaining byte count, the updated 1715 * address and the return address. 1716 */ 1717 SCR_STORE_REL (rbc, 4), 1718 offsetof(struct sym_ccb, phys.pm1.sg.size), 1719 SCR_STORE_REL (ua, 4), 1720 offsetof(struct sym_ccb, phys.pm1.sg.addr), 1721 /* 1722 * Set the current pointer at the PM1 DATA mini-script. 1723 */ 1724 SCR_LOAD_ABS (temp, 4), 1725 PADDR_B (pm1_data_addr), 1726 SCR_JUMP, 1727 PADDR_A (dispatch), 1728 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{ 1729 /* 1730 * Phase mismatch handling from SCRIPT with WSR set. 1731 * Such a condition can occur if the chip wants to 1732 * execute a CHMOV(size > 1) when the WSR bit is 1733 * set and the target changes PHASE. 1734 * 1735 * We must move the residual byte to memory. 1736 * 1737 * UA contains bit 0..31 of the address to 1738 * move the residual byte. 1739 * Move it to the table indirect. 1740 */ 1741 SCR_STORE_REL (ua, 4), 1742 offsetof (struct sym_ccb, phys.wresid.addr), 1743 /* 1744 * Increment UA (move address to next position). 1745 */ 1746 SCR_REG_REG (ua, SCR_ADD, 1), 1747 0, 1748 SCR_REG_REG (ua1, SCR_ADDC, 0), 1749 0, 1750 SCR_REG_REG (ua2, SCR_ADDC, 0), 1751 0, 1752 SCR_REG_REG (ua3, SCR_ADDC, 0), 1753 0, 1754 /* 1755 * Compute SCRATCHA as: 1756 * - size to transfer = 1 byte. 1757 * - bit 24..31 = high address bit [32...39]. 1758 */ 1759 SCR_LOAD_ABS (scratcha, 4), 1760 PADDR_B (zero), 1761 SCR_REG_REG (scratcha, SCR_OR, 1), 1762 0, 1763 SCR_FROM_REG (rbc3), 1764 0, 1765 SCR_TO_REG (scratcha3), 1766 0, 1767 /* 1768 * Move this value to the table indirect. 1769 */ 1770 SCR_STORE_REL (scratcha, 4), 1771 offsetof (struct sym_ccb, phys.wresid.size), 1772 /* 1773 * Wait for a valid phase. 1774 * While testing with bogus QUANTUM drives, the C1010 1775 * sometimes raised a spurious phase mismatch with 1776 * WSR and the CHMOV(1) triggered another PM. 1777 * Waiting explicitly for the PHASE seemed to avoid 1778 * the nested phase mismatch. Btw, this didn't happen 1779 * using my IBM drives. 1780 */ 1781 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)), 1782 0, 1783 /* 1784 * Perform the move of the residual byte. 1785 */ 1786 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1787 offsetof (struct sym_ccb, phys.wresid), 1788 /* 1789 * We can now handle the phase mismatch with UA fixed. 1790 * RBC[0..23]=0 is a special case that does not require 1791 * a PM context. The C code also checks against this. 1792 */ 1793 SCR_FROM_REG (rbc), 1794 0, 1795 SCR_RETURN ^ IFFALSE (DATA (0)), 1796 0, 1797 SCR_FROM_REG (rbc1), 1798 0, 1799 SCR_RETURN ^ IFFALSE (DATA (0)), 1800 0, 1801 SCR_FROM_REG (rbc2), 1802 0, 1803 SCR_RETURN ^ IFFALSE (DATA (0)), 1804 0, 1805 /* 1806 * RBC[0..23]=0. 1807 * Not only we donnot need a PM context, but this would 1808 * lead to a bogus CHMOV(0). This condition means that 1809 * the residual was the last byte to move from this CHMOV. 1810 * So, we just have to move the current data script pointer 1811 * (i.e. TEMP) to the SCRIPTS address following the 1812 * interrupted CHMOV and jump to dispatcher. 1813 */ 1814 SCR_STORE_ABS (ia, 4), 1815 PADDR_B (scratch), 1816 SCR_LOAD_ABS (temp, 4), 1817 PADDR_B (scratch), 1818 SCR_JUMP, 1819 PADDR_A (dispatch), 1820 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1821 /* 1822 * Helper for the C code when WSR bit is set. 1823 * Perform the move of the residual byte. 1824 */ 1825 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1826 offsetof (struct sym_ccb, phys.wresid), 1827 SCR_JUMP, 1828 PADDR_A (dispatch), 1829 }/*-------------------------< ZERO >-----------------------------*/,{ 1830 SCR_DATA_ZERO, 1831 }/*-------------------------< SCRATCH >--------------------------*/,{ 1832 SCR_DATA_ZERO, 1833 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{ 1834 SCR_DATA_ZERO, 1835 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{ 1836 SCR_DATA_ZERO, 1837 }/*-------------------------< SAVED_DSA >------------------------*/,{ 1838 SCR_DATA_ZERO, 1839 }/*-------------------------< SAVED_DRS >------------------------*/,{ 1840 SCR_DATA_ZERO, 1841 }/*-------------------------< DONE_POS >-------------------------*/,{ 1842 SCR_DATA_ZERO, 1843 }/*-------------------------< STARTPOS >-------------------------*/,{ 1844 SCR_DATA_ZERO, 1845 }/*-------------------------< TARGTBL >--------------------------*/,{ 1846 SCR_DATA_ZERO, 1847 1848 }/*-------------------------< SNOOPTEST >------------------------*/,{ 1849 /* 1850 * Read the variable from memory. 1851 */ 1852 SCR_LOAD_REL (scratcha, 4), 1853 offsetof(struct sym_hcb, cache), 1854 /* 1855 * Write the variable to memory. 1856 */ 1857 SCR_STORE_REL (temp, 4), 1858 offsetof(struct sym_hcb, cache), 1859 /* 1860 * Read back the variable from memory. 1861 */ 1862 SCR_LOAD_REL (temp, 4), 1863 offsetof(struct sym_hcb, cache), 1864 }/*-------------------------< SNOOPEND >-------------------------*/,{ 1865 /* 1866 * And stop. 1867 */ 1868 SCR_INT, 1869 99, 1870 }/*-------------------------<>-----------------------------------*/ 1871 };
Cache object: 9c76ad7b58e05e23ce66048fddd4f630
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