FreeBSD/Linux Kernel Cross Reference
sys/dev/sym/sym_hipd.c
1 /*-
2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
10 *
11 *
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
14 *
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 *
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
22 *
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
26 *
27 * Other major contributions:
28 *
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31 *
32 *-----------------------------------------------------------------------------
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
60
61 #define SYM_DRIVER_NAME "sym-1.6.5-20000902"
62
63 /* #define SYM_DEBUG_GENERIC_SUPPORT */
64 /* #define CAM_NEW_TRAN_CODE */
65
66 #include <sys/param.h>
67
68 /*
69 * Driver configuration options.
70 */
71 #include "opt_sym.h"
72 #include <dev/sym/sym_conf.h>
73
74
75 #include <sys/systm.h>
76 #include <sys/malloc.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/lock.h>
80 #include <sys/mutex.h>
81 #include <sys/module.h>
82 #include <sys/bus.h>
83
84 #include <sys/proc.h>
85
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88
89 #include <machine/bus.h>
90 #include <machine/resource.h>
91 #include <sys/rman.h>
92
93 #include <cam/cam.h>
94 #include <cam/cam_ccb.h>
95 #include <cam/cam_sim.h>
96 #include <cam/cam_xpt_sim.h>
97 #include <cam/cam_debug.h>
98
99 #include <cam/scsi/scsi_all.h>
100 #include <cam/scsi/scsi_message.h>
101
102 #include <vm/vm.h>
103 #include <vm/vm_param.h>
104 #include <vm/pmap.h>
105
106 /* Short and quite clear integer types */
107 typedef int8_t s8;
108 typedef int16_t s16;
109 typedef int32_t s32;
110 typedef u_int8_t u8;
111 typedef u_int16_t u16;
112 typedef u_int32_t u32;
113
114 /*
115 * From 'cam.error_recovery_diffs.20010313.context' patch.
116 */
117 #ifdef CAM_NEW_TRAN_CODE
118 #define FreeBSD_New_Tran_Settings
119 #endif /* CAM_NEW_TRAN_CODE */
120
121 /*
122 * Driver definitions.
123 */
124 #include <dev/sym/sym_defs.h>
125 #include <dev/sym/sym_fw.h>
126
127 /*
128 * IA32 architecture does not reorder STORES and prevents
129 * LOADS from passing STORES. It is called `program order'
130 * by Intel and allows device drivers to deal with memory
131 * ordering by only ensuring that the code is not reordered
132 * by the compiler when ordering is required.
133 * Other architectures implement a weaker ordering that
134 * requires memory barriers (and also IO barriers when they
135 * make sense) to be used.
136 */
137
138 #if defined __i386__ || defined __amd64__
139 #define MEMORY_BARRIER() do { ; } while(0)
140 #elif defined __alpha__
141 #define MEMORY_BARRIER() alpha_mb()
142 #elif defined __powerpc__
143 #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory")
144 #elif defined __ia64__
145 #define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory")
146 #elif defined __sparc64__
147 #define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory")
148 #else
149 #error "Not supported platform"
150 #endif
151
152 /*
153 * A la VMS/CAM-3 queue management.
154 */
155
156 typedef struct sym_quehead {
157 struct sym_quehead *flink; /* Forward pointer */
158 struct sym_quehead *blink; /* Backward pointer */
159 } SYM_QUEHEAD;
160
161 #define sym_que_init(ptr) do { \
162 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \
163 } while (0)
164
165 static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head)
166 {
167 return (head->flink == head) ? NULL : head->flink;
168 }
169
170 static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head)
171 {
172 return (head->blink == head) ? NULL : head->blink;
173 }
174
175 static __inline void __sym_que_add(struct sym_quehead * new,
176 struct sym_quehead * blink,
177 struct sym_quehead * flink)
178 {
179 flink->blink = new;
180 new->flink = flink;
181 new->blink = blink;
182 blink->flink = new;
183 }
184
185 static __inline void __sym_que_del(struct sym_quehead * blink,
186 struct sym_quehead * flink)
187 {
188 flink->blink = blink;
189 blink->flink = flink;
190 }
191
192 static __inline int sym_que_empty(struct sym_quehead *head)
193 {
194 return head->flink == head;
195 }
196
197 static __inline void sym_que_splice(struct sym_quehead *list,
198 struct sym_quehead *head)
199 {
200 struct sym_quehead *first = list->flink;
201
202 if (first != list) {
203 struct sym_quehead *last = list->blink;
204 struct sym_quehead *at = head->flink;
205
206 first->blink = head;
207 head->flink = first;
208
209 last->flink = at;
210 at->blink = last;
211 }
212 }
213
214 #define sym_que_entry(ptr, type, member) \
215 ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member)))
216
217
218 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink)
219
220 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink)
221
222 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink)
223
224 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head)
225 {
226 struct sym_quehead *elem = head->flink;
227
228 if (elem != head)
229 __sym_que_del(head, elem->flink);
230 else
231 elem = NULL;
232 return elem;
233 }
234
235 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head)
236
237 static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head)
238 {
239 struct sym_quehead *elem = head->blink;
240
241 if (elem != head)
242 __sym_que_del(elem->blink, head);
243 else
244 elem = NULL;
245 return elem;
246 }
247
248 /*
249 * This one may be useful.
250 */
251 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \
252 for (qp = (head)->flink; qp != (head); qp = qp->flink)
253 /*
254 * FreeBSD does not offer our kind of queue in the CAM CCB.
255 * So, we have to cast.
256 */
257 #define sym_qptr(p) ((struct sym_quehead *) (p))
258
259 /*
260 * Simple bitmap operations.
261 */
262 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f)))
263 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f)))
264 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f)))
265
266 /*
267 * Number of tasks per device we want to handle.
268 */
269 #if SYM_CONF_MAX_TAG_ORDER > 8
270 #error "more than 256 tags per logical unit not allowed."
271 #endif
272 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER)
273
274 /*
275 * Donnot use more tasks that we can handle.
276 */
277 #ifndef SYM_CONF_MAX_TAG
278 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
279 #endif
280 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK
281 #undef SYM_CONF_MAX_TAG
282 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
283 #endif
284
285 /*
286 * This one means 'NO TAG for this job'
287 */
288 #define NO_TAG (256)
289
290 /*
291 * Number of SCSI targets.
292 */
293 #if SYM_CONF_MAX_TARGET > 16
294 #error "more than 16 targets not allowed."
295 #endif
296
297 /*
298 * Number of logical units per target.
299 */
300 #if SYM_CONF_MAX_LUN > 64
301 #error "more than 64 logical units per target not allowed."
302 #endif
303
304 /*
305 * Asynchronous pre-scaler (ns). Shall be 40 for
306 * the SCSI timings to be compliant.
307 */
308 #define SYM_CONF_MIN_ASYNC (40)
309
310 /*
311 * Number of entries in the START and DONE queues.
312 *
313 * We limit to 1 PAGE in order to succeed allocation of
314 * these queues. Each entry is 8 bytes long (2 DWORDS).
315 */
316 #ifdef SYM_CONF_MAX_START
317 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2)
318 #else
319 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2)
320 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
321 #endif
322
323 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8
324 #undef SYM_CONF_MAX_QUEUE
325 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8
326 #undef SYM_CONF_MAX_START
327 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
328 #endif
329
330 /*
331 * For this one, we want a short name :-)
332 */
333 #define MAX_QUEUE SYM_CONF_MAX_QUEUE
334
335 /*
336 * Active debugging tags and verbosity.
337 */
338 #define DEBUG_ALLOC (0x0001)
339 #define DEBUG_PHASE (0x0002)
340 #define DEBUG_POLL (0x0004)
341 #define DEBUG_QUEUE (0x0008)
342 #define DEBUG_RESULT (0x0010)
343 #define DEBUG_SCATTER (0x0020)
344 #define DEBUG_SCRIPT (0x0040)
345 #define DEBUG_TINY (0x0080)
346 #define DEBUG_TIMING (0x0100)
347 #define DEBUG_NEGO (0x0200)
348 #define DEBUG_TAGS (0x0400)
349 #define DEBUG_POINTER (0x0800)
350
351 #if 0
352 static int sym_debug = 0;
353 #define DEBUG_FLAGS sym_debug
354 #else
355 /* #define DEBUG_FLAGS (0x0631) */
356 #define DEBUG_FLAGS (0x0000)
357
358 #endif
359 #define sym_verbose (np->verbose)
360
361 /*
362 * Insert a delay in micro-seconds and milli-seconds.
363 */
364 static void UDELAY(int us) { DELAY(us); }
365 static void MDELAY(int ms) { while (ms--) UDELAY(1000); }
366
367 /*
368 * Simple power of two buddy-like allocator.
369 *
370 * This simple code is not intended to be fast, but to
371 * provide power of 2 aligned memory allocations.
372 * Since the SCRIPTS processor only supplies 8 bit arithmetic,
373 * this allocator allows simple and fast address calculations
374 * from the SCRIPTS code. In addition, cache line alignment
375 * is guaranteed for power of 2 cache line size.
376 *
377 * This allocator has been developped for the Linux sym53c8xx
378 * driver, since this O/S does not provide naturally aligned
379 * allocations.
380 * It has the advantage of allowing the driver to use private
381 * pages of memory that will be useful if we ever need to deal
382 * with IO MMUs for PCI.
383 */
384
385 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
386 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
387 #if 0
388 #define MEMO_FREE_UNUSED /* Free unused pages immediately */
389 #endif
390 #define MEMO_WARN 1
391 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
392 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
393 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
394
395 #define get_pages() malloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_NOWAIT)
396 #define free_pages(p) free((p), M_DEVBUF)
397
398 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
399
400 typedef struct m_link { /* Link between free memory chunks */
401 struct m_link *next;
402 } m_link_s;
403
404 typedef struct m_vtob { /* Virtual to Bus address translation */
405 struct m_vtob *next;
406 bus_dmamap_t dmamap; /* Map for this chunk */
407 m_addr_t vaddr; /* Virtual address */
408 m_addr_t baddr; /* Bus physical address */
409 } m_vtob_s;
410 /* Hash this stuff a bit to speed up translations */
411 #define VTOB_HASH_SHIFT 5
412 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
413 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
414 #define VTOB_HASH_CODE(m) \
415 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
416
417 typedef struct m_pool { /* Memory pool of a given kind */
418 bus_dma_tag_t dev_dmat; /* Identifies the pool */
419 bus_dma_tag_t dmat; /* Tag for our fixed allocations */
420 m_addr_t (*getp)(struct m_pool *);
421 #ifdef MEMO_FREE_UNUSED
422 void (*freep)(struct m_pool *, m_addr_t);
423 #endif
424 #define M_GETP() mp->getp(mp)
425 #define M_FREEP(p) mp->freep(mp, p)
426 int nump;
427 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
428 struct m_pool *next;
429 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1];
430 } m_pool_s;
431
432 static void *___sym_malloc(m_pool_s *mp, int size)
433 {
434 int i = 0;
435 int s = (1 << MEMO_SHIFT);
436 int j;
437 m_addr_t a;
438 m_link_s *h = mp->h;
439
440 if (size > MEMO_CLUSTER_SIZE)
441 return NULL;
442
443 while (size > s) {
444 s <<= 1;
445 ++i;
446 }
447
448 j = i;
449 while (!h[j].next) {
450 if (s == MEMO_CLUSTER_SIZE) {
451 h[j].next = (m_link_s *) M_GETP();
452 if (h[j].next)
453 h[j].next->next = NULL;
454 break;
455 }
456 ++j;
457 s <<= 1;
458 }
459 a = (m_addr_t) h[j].next;
460 if (a) {
461 h[j].next = h[j].next->next;
462 while (j > i) {
463 j -= 1;
464 s >>= 1;
465 h[j].next = (m_link_s *) (a+s);
466 h[j].next->next = NULL;
467 }
468 }
469 #ifdef DEBUG
470 printf("___sym_malloc(%d) = %p\n", size, (void *) a);
471 #endif
472 return (void *) a;
473 }
474
475 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size)
476 {
477 int i = 0;
478 int s = (1 << MEMO_SHIFT);
479 m_link_s *q;
480 m_addr_t a, b;
481 m_link_s *h = mp->h;
482
483 #ifdef DEBUG
484 printf("___sym_mfree(%p, %d)\n", ptr, size);
485 #endif
486
487 if (size > MEMO_CLUSTER_SIZE)
488 return;
489
490 while (size > s) {
491 s <<= 1;
492 ++i;
493 }
494
495 a = (m_addr_t) ptr;
496
497 while (1) {
498 #ifdef MEMO_FREE_UNUSED
499 if (s == MEMO_CLUSTER_SIZE) {
500 M_FREEP(a);
501 break;
502 }
503 #endif
504 b = a ^ s;
505 q = &h[i];
506 while (q->next && q->next != (m_link_s *) b) {
507 q = q->next;
508 }
509 if (!q->next) {
510 ((m_link_s *) a)->next = h[i].next;
511 h[i].next = (m_link_s *) a;
512 break;
513 }
514 q->next = q->next->next;
515 a = a & b;
516 s <<= 1;
517 ++i;
518 }
519 }
520
521 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags)
522 {
523 void *p;
524
525 p = ___sym_malloc(mp, size);
526
527 if (DEBUG_FLAGS & DEBUG_ALLOC)
528 printf ("new %-10s[%4d] @%p.\n", name, size, p);
529
530 if (p)
531 bzero(p, size);
532 else if (uflags & MEMO_WARN)
533 printf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size);
534
535 return p;
536 }
537
538 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN)
539
540 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name)
541 {
542 if (DEBUG_FLAGS & DEBUG_ALLOC)
543 printf ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
544
545 ___sym_mfree(mp, ptr, size);
546
547 }
548
549 /*
550 * Default memory pool we donnot need to involve in DMA.
551 */
552 /*
553 * With the `bus dma abstraction', we use a separate pool for
554 * memory we donnot need to involve in DMA.
555 */
556 static m_addr_t ___mp0_getp(m_pool_s *mp)
557 {
558 m_addr_t m = (m_addr_t) get_pages();
559 if (m)
560 ++mp->nump;
561 return m;
562 }
563
564 #ifdef MEMO_FREE_UNUSED
565 static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
566 {
567 free_pages(m);
568 --mp->nump;
569 }
570 #endif
571
572 #ifdef MEMO_FREE_UNUSED
573 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep};
574 #else
575 static m_pool_s mp0 = {0, 0, ___mp0_getp};
576 #endif
577
578
579 /*
580 * Actual memory allocation routine for non-DMAed memory.
581 */
582 static void *sym_calloc(int size, char *name)
583 {
584 void *m;
585 /* Lock */
586 m = __sym_calloc(&mp0, size, name);
587 /* Unlock */
588 return m;
589 }
590
591 /*
592 * Actual memory allocation routine for non-DMAed memory.
593 */
594 static void sym_mfree(void *ptr, int size, char *name)
595 {
596 /* Lock */
597 __sym_mfree(&mp0, ptr, size, name);
598 /* Unlock */
599 }
600
601 /*
602 * DMAable pools.
603 */
604 /*
605 * With `bus dma abstraction', we use a separate pool per parent
606 * BUS handle. A reverse table (hashed) is maintained for virtual
607 * to BUS address translation.
608 */
609 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
610 {
611 bus_addr_t *baddr;
612 baddr = (bus_addr_t *)arg;
613 *baddr = segs->ds_addr;
614 }
615
616 static m_addr_t ___dma_getp(m_pool_s *mp)
617 {
618 m_vtob_s *vbp;
619 void *vaddr = NULL;
620 bus_addr_t baddr = 0;
621
622 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB");
623 if (!vbp)
624 goto out_err;
625
626 if (bus_dmamem_alloc(mp->dmat, &vaddr,
627 BUS_DMA_NOWAIT, &vbp->dmamap))
628 goto out_err;
629 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr,
630 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, BUS_DMA_NOWAIT);
631 if (baddr) {
632 int hc = VTOB_HASH_CODE(vaddr);
633 vbp->vaddr = (m_addr_t) vaddr;
634 vbp->baddr = (m_addr_t) baddr;
635 vbp->next = mp->vtob[hc];
636 mp->vtob[hc] = vbp;
637 ++mp->nump;
638 return (m_addr_t) vaddr;
639 }
640 out_err:
641 if (baddr)
642 bus_dmamap_unload(mp->dmat, vbp->dmamap);
643 if (vaddr)
644 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap);
645 if (vbp) {
646 if (vbp->dmamap)
647 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
648 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
649 }
650 return 0;
651 }
652
653 #ifdef MEMO_FREE_UNUSED
654 static void ___dma_freep(m_pool_s *mp, m_addr_t m)
655 {
656 m_vtob_s **vbpp, *vbp;
657 int hc = VTOB_HASH_CODE(m);
658
659 vbpp = &mp->vtob[hc];
660 while (*vbpp && (*vbpp)->vaddr != m)
661 vbpp = &(*vbpp)->next;
662 if (*vbpp) {
663 vbp = *vbpp;
664 *vbpp = (*vbpp)->next;
665 bus_dmamap_unload(mp->dmat, vbp->dmamap);
666 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap);
667 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
668 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
669 --mp->nump;
670 }
671 }
672 #endif
673
674 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat)
675 {
676 m_pool_s *mp;
677 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next);
678 return mp;
679 }
680
681 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat)
682 {
683 m_pool_s *mp = NULL;
684
685 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL");
686 if (mp) {
687 mp->dev_dmat = dev_dmat;
688 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE,
689 BUS_SPACE_MAXADDR_32BIT,
690 BUS_SPACE_MAXADDR,
691 NULL, NULL, MEMO_CLUSTER_SIZE, 1,
692 MEMO_CLUSTER_SIZE, 0,
693 busdma_lock_mutex, &Giant, &mp->dmat)) {
694 mp->getp = ___dma_getp;
695 #ifdef MEMO_FREE_UNUSED
696 mp->freep = ___dma_freep;
697 #endif
698 mp->next = mp0.next;
699 mp0.next = mp;
700 return mp;
701 }
702 }
703 if (mp)
704 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL");
705 return NULL;
706 }
707
708 #ifdef MEMO_FREE_UNUSED
709 static void ___del_dma_pool(m_pool_s *p)
710 {
711 struct m_pool **pp = &mp0.next;
712
713 while (*pp && *pp != p)
714 pp = &(*pp)->next;
715 if (*pp) {
716 *pp = (*pp)->next;
717 bus_dma_tag_destroy(p->dmat);
718 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL");
719 }
720 }
721 #endif
722
723 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name)
724 {
725 struct m_pool *mp;
726 void *m = NULL;
727
728 /* Lock */
729 mp = ___get_dma_pool(dev_dmat);
730 if (!mp)
731 mp = ___cre_dma_pool(dev_dmat);
732 if (mp)
733 m = __sym_calloc(mp, size, name);
734 #ifdef MEMO_FREE_UNUSED
735 if (mp && !mp->nump)
736 ___del_dma_pool(mp);
737 #endif
738 /* Unlock */
739
740 return m;
741 }
742
743 static void
744 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name)
745 {
746 struct m_pool *mp;
747
748 /* Lock */
749 mp = ___get_dma_pool(dev_dmat);
750 if (mp)
751 __sym_mfree(mp, m, size, name);
752 #ifdef MEMO_FREE_UNUSED
753 if (mp && !mp->nump)
754 ___del_dma_pool(mp);
755 #endif
756 /* Unlock */
757 }
758
759 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m)
760 {
761 m_pool_s *mp;
762 int hc = VTOB_HASH_CODE(m);
763 m_vtob_s *vp = NULL;
764 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
765
766 /* Lock */
767 mp = ___get_dma_pool(dev_dmat);
768 if (mp) {
769 vp = mp->vtob[hc];
770 while (vp && (m_addr_t) vp->vaddr != a)
771 vp = vp->next;
772 }
773 /* Unlock */
774 if (!vp)
775 panic("sym: VTOBUS FAILED!\n");
776 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
777 }
778
779
780 /*
781 * Verbs for DMAable memory handling.
782 * The _uvptv_ macro avoids a nasty warning about pointer to volatile
783 * being discarded.
784 */
785 #define _uvptv_(p) ((void *)((vm_offset_t)(p)))
786 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n)
787 #define _sym_mfree_dma(np, p, s, n) \
788 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n)
789 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n)
790 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n)
791 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p))
792 #define vtobus(p) _vtobus(np, p)
793
794
795 /*
796 * Print a buffer in hexadecimal format.
797 */
798 static void sym_printb_hex (u_char *p, int n)
799 {
800 while (n-- > 0)
801 printf (" %x", *p++);
802 }
803
804 /*
805 * Same with a label at beginning and .\n at end.
806 */
807 static void sym_printl_hex (char *label, u_char *p, int n)
808 {
809 printf ("%s", label);
810 sym_printb_hex (p, n);
811 printf (".\n");
812 }
813
814 /*
815 * Return a string for SCSI BUS mode.
816 */
817 static const char *sym_scsi_bus_mode(int mode)
818 {
819 switch(mode) {
820 case SMODE_HVD: return "HVD";
821 case SMODE_SE: return "SE";
822 case SMODE_LVD: return "LVD";
823 }
824 return "??";
825 }
826
827 /*
828 * Some poor and bogus sync table that refers to Tekram NVRAM layout.
829 */
830 #ifdef SYM_CONF_NVRAM_SUPPORT
831 static const u_char Tekram_sync[16] =
832 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10};
833 #endif
834
835 /*
836 * Union of supported NVRAM formats.
837 */
838 struct sym_nvram {
839 int type;
840 #define SYM_SYMBIOS_NVRAM (1)
841 #define SYM_TEKRAM_NVRAM (2)
842 #ifdef SYM_CONF_NVRAM_SUPPORT
843 union {
844 Symbios_nvram Symbios;
845 Tekram_nvram Tekram;
846 } data;
847 #endif
848 };
849
850 /*
851 * This one is hopefully useless, but actually useful. :-)
852 */
853 #ifndef assert
854 #define assert(expression) { \
855 if (!(expression)) { \
856 (void)panic( \
857 "assertion \"%s\" failed: file \"%s\", line %d\n", \
858 #expression, \
859 __FILE__, __LINE__); \
860 } \
861 }
862 #endif
863
864 /*
865 * Some provision for a possible big endian mode supported by
866 * Symbios chips (never seen, by the way).
867 * For now, this stuff does not deserve any comments. :)
868 */
869
870 #define sym_offb(o) (o)
871 #define sym_offw(o) (o)
872
873 /*
874 * Some provision for support for BIG ENDIAN CPU.
875 */
876
877 #define cpu_to_scr(dw) htole32(dw)
878 #define scr_to_cpu(dw) le32toh(dw)
879
880 /*
881 * Access to the chip IO registers and on-chip RAM.
882 * We use the `bus space' interface under FreeBSD-4 and
883 * later kernel versions.
884 */
885
886
887 #if defined(SYM_CONF_IOMAPPED)
888
889 #define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o)
890 #define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o)
891 #define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o)
892
893 #define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v))
894 #define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v))
895 #define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v))
896
897 #else /* Memory mapped IO */
898
899 #define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o)
900 #define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o)
901 #define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o)
902
903 #define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v))
904 #define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v))
905 #define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v))
906
907 #endif /* SYM_CONF_IOMAPPED */
908
909 #define OUTRAM_OFF(o, a, l) \
910 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l))
911
912
913 /*
914 * Common definitions for both bus space and legacy IO methods.
915 */
916 #define INB(r) INB_OFF(offsetof(struct sym_reg,r))
917 #define INW(r) INW_OFF(offsetof(struct sym_reg,r))
918 #define INL(r) INL_OFF(offsetof(struct sym_reg,r))
919
920 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v))
921 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v))
922 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v))
923
924 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
925 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
926 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
927 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
928 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
929 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
930
931 /*
932 * We normally want the chip to have a consistent view
933 * of driver internal data structures when we restart it.
934 * Thus these macros.
935 */
936 #define OUTL_DSP(v) \
937 do { \
938 MEMORY_BARRIER(); \
939 OUTL (nc_dsp, (v)); \
940 } while (0)
941
942 #define OUTONB_STD() \
943 do { \
944 MEMORY_BARRIER(); \
945 OUTONB (nc_dcntl, (STD|NOCOM)); \
946 } while (0)
947
948 /*
949 * Command control block states.
950 */
951 #define HS_IDLE (0)
952 #define HS_BUSY (1)
953 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/
954 #define HS_DISCONNECT (3) /* Disconnected by target */
955 #define HS_WAIT (4) /* waiting for resource */
956
957 #define HS_DONEMASK (0x80)
958 #define HS_COMPLETE (4|HS_DONEMASK)
959 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
960 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */
961 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */
962
963 /*
964 * Software Interrupt Codes
965 */
966 #define SIR_BAD_SCSI_STATUS (1)
967 #define SIR_SEL_ATN_NO_MSG_OUT (2)
968 #define SIR_MSG_RECEIVED (3)
969 #define SIR_MSG_WEIRD (4)
970 #define SIR_NEGO_FAILED (5)
971 #define SIR_NEGO_PROTO (6)
972 #define SIR_SCRIPT_STOPPED (7)
973 #define SIR_REJECT_TO_SEND (8)
974 #define SIR_SWIDE_OVERRUN (9)
975 #define SIR_SODL_UNDERRUN (10)
976 #define SIR_RESEL_NO_MSG_IN (11)
977 #define SIR_RESEL_NO_IDENTIFY (12)
978 #define SIR_RESEL_BAD_LUN (13)
979 #define SIR_TARGET_SELECTED (14)
980 #define SIR_RESEL_BAD_I_T_L (15)
981 #define SIR_RESEL_BAD_I_T_L_Q (16)
982 #define SIR_ABORT_SENT (17)
983 #define SIR_RESEL_ABORTED (18)
984 #define SIR_MSG_OUT_DONE (19)
985 #define SIR_COMPLETE_ERROR (20)
986 #define SIR_DATA_OVERRUN (21)
987 #define SIR_BAD_PHASE (22)
988 #define SIR_MAX (22)
989
990 /*
991 * Extended error bit codes.
992 * xerr_status field of struct sym_ccb.
993 */
994 #define XE_EXTRA_DATA (1) /* unexpected data phase */
995 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */
996 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */
997 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */
998 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */
999
1000 /*
1001 * Negotiation status.
1002 * nego_status field of struct sym_ccb.
1003 */
1004 #define NS_SYNC (1)
1005 #define NS_WIDE (2)
1006 #define NS_PPR (3)
1007
1008 /*
1009 * A CCB hashed table is used to retrieve CCB address
1010 * from DSA value.
1011 */
1012 #define CCB_HASH_SHIFT 8
1013 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT)
1014 #define CCB_HASH_MASK (CCB_HASH_SIZE-1)
1015 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK)
1016
1017 /*
1018 * Device flags.
1019 */
1020 #define SYM_DISC_ENABLED (1)
1021 #define SYM_TAGS_ENABLED (1<<1)
1022 #define SYM_SCAN_BOOT_DISABLED (1<<2)
1023 #define SYM_SCAN_LUNS_DISABLED (1<<3)
1024
1025 /*
1026 * Host adapter miscellaneous flags.
1027 */
1028 #define SYM_AVOID_BUS_RESET (1)
1029 #define SYM_SCAN_TARGETS_HILO (1<<1)
1030
1031 /*
1032 * Device quirks.
1033 * Some devices, for example the CHEETAH 2 LVD, disconnects without
1034 * saving the DATA POINTER then reselects and terminates the IO.
1035 * On reselection, the automatic RESTORE DATA POINTER makes the
1036 * CURRENT DATA POINTER not point at the end of the IO.
1037 * This behaviour just breaks our calculation of the residual.
1038 * For now, we just force an AUTO SAVE on disconnection and will
1039 * fix that in a further driver version.
1040 */
1041 #define SYM_QUIRK_AUTOSAVE 1
1042
1043 /*
1044 * Misc.
1045 */
1046 #define SYM_SNOOP_TIMEOUT (10000000)
1047 #define SYM_PCI_IO PCIR_BAR(0)
1048 #define SYM_PCI_MMIO PCIR_BAR(1)
1049 #define SYM_PCI_RAM PCIR_BAR(2)
1050 #define SYM_PCI_RAM64 PCIR_BAR(3)
1051
1052 /*
1053 * Back-pointer from the CAM CCB to our data structures.
1054 */
1055 #define sym_hcb_ptr spriv_ptr0
1056 /* #define sym_ccb_ptr spriv_ptr1 */
1057
1058 /*
1059 * We mostly have to deal with pointers.
1060 * Thus these typedef's.
1061 */
1062 typedef struct sym_tcb *tcb_p;
1063 typedef struct sym_lcb *lcb_p;
1064 typedef struct sym_ccb *ccb_p;
1065 typedef struct sym_hcb *hcb_p;
1066
1067 /*
1068 * Gather negotiable parameters value
1069 */
1070 struct sym_trans {
1071 #ifdef FreeBSD_New_Tran_Settings
1072 u8 scsi_version;
1073 u8 spi_version;
1074 #endif
1075 u8 period;
1076 u8 offset;
1077 u8 width;
1078 u8 options; /* PPR options */
1079 };
1080
1081 struct sym_tinfo {
1082 struct sym_trans current;
1083 struct sym_trans goal;
1084 struct sym_trans user;
1085 };
1086
1087 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT
1088 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT
1089
1090 /*
1091 * Global TCB HEADER.
1092 *
1093 * Due to lack of indirect addressing on earlier NCR chips,
1094 * this substructure is copied from the TCB to a global
1095 * address after selection.
1096 * For SYMBIOS chips that support LOAD/STORE this copy is
1097 * not needed and thus not performed.
1098 */
1099 struct sym_tcbh {
1100 /*
1101 * Scripts bus addresses of LUN table accessed from scripts.
1102 * LUN #0 is a special case, since multi-lun devices are rare,
1103 * and we we want to speed-up the general case and not waste
1104 * resources.
1105 */
1106 u32 luntbl_sa; /* bus address of this table */
1107 u32 lun0_sa; /* bus address of LCB #0 */
1108 /*
1109 * Actual SYNC/WIDE IO registers value for this target.
1110 * 'sval', 'wval' and 'uval' are read from SCRIPTS and
1111 * so have alignment constraints.
1112 */
1113 /**/ u_char uval; /* -> SCNTL4 register */
1114 /*1*/ u_char sval; /* -> SXFER io register */
1115 /*2*/ u_char filler1;
1116 /*3*/ u_char wval; /* -> SCNTL3 io register */
1117 };
1118
1119 /*
1120 * Target Control Block
1121 */
1122 struct sym_tcb {
1123 /*
1124 * TCB header.
1125 * Assumed at offset 0.
1126 */
1127 /**/ struct sym_tcbh head;
1128
1129 /*
1130 * LUN table used by the SCRIPTS processor.
1131 * An array of bus addresses is used on reselection.
1132 */
1133 u32 *luntbl; /* LCBs bus address table */
1134
1135 /*
1136 * LUN table used by the C code.
1137 */
1138 lcb_p lun0p; /* LCB of LUN #0 (usual case) */
1139 #if SYM_CONF_MAX_LUN > 1
1140 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */
1141 #endif
1142
1143 /*
1144 * Bitmap that tells about LUNs that succeeded at least
1145 * 1 IO and therefore assumed to be a real device.
1146 * Avoid useless allocation of the LCB structure.
1147 */
1148 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32];
1149
1150 /*
1151 * Bitmap that tells about LUNs that haven't yet an LCB
1152 * allocated (not discovered or LCB allocation failed).
1153 */
1154 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32];
1155
1156 /*
1157 * Transfer capabilities (SIP)
1158 */
1159 struct sym_tinfo tinfo;
1160
1161 /*
1162 * Keep track of the CCB used for the negotiation in order
1163 * to ensure that only 1 negotiation is queued at a time.
1164 */
1165 ccb_p nego_cp; /* CCB used for the nego */
1166
1167 /*
1168 * Set when we want to reset the device.
1169 */
1170 u_char to_reset;
1171
1172 /*
1173 * Other user settable limits and options.
1174 * These limits are read from the NVRAM if present.
1175 */
1176 u_char usrflags;
1177 u_short usrtags;
1178 };
1179
1180 /*
1181 * Global LCB HEADER.
1182 *
1183 * Due to lack of indirect addressing on earlier NCR chips,
1184 * this substructure is copied from the LCB to a global
1185 * address after selection.
1186 * For SYMBIOS chips that support LOAD/STORE this copy is
1187 * not needed and thus not performed.
1188 */
1189 struct sym_lcbh {
1190 /*
1191 * SCRIPTS address jumped by SCRIPTS on reselection.
1192 * For not probed logical units, this address points to
1193 * SCRIPTS that deal with bad LU handling (must be at
1194 * offset zero of the LCB for that reason).
1195 */
1196 /**/ u32 resel_sa;
1197
1198 /*
1199 * Task (bus address of a CCB) read from SCRIPTS that points
1200 * to the unique ITL nexus allowed to be disconnected.
1201 */
1202 u32 itl_task_sa;
1203
1204 /*
1205 * Task table bus address (read from SCRIPTS).
1206 */
1207 u32 itlq_tbl_sa;
1208 };
1209
1210 /*
1211 * Logical Unit Control Block
1212 */
1213 struct sym_lcb {
1214 /*
1215 * TCB header.
1216 * Assumed at offset 0.
1217 */
1218 /**/ struct sym_lcbh head;
1219
1220 /*
1221 * Task table read from SCRIPTS that contains pointers to
1222 * ITLQ nexuses. The bus address read from SCRIPTS is
1223 * inside the header.
1224 */
1225 u32 *itlq_tbl; /* Kernel virtual address */
1226
1227 /*
1228 * Busy CCBs management.
1229 */
1230 u_short busy_itlq; /* Number of busy tagged CCBs */
1231 u_short busy_itl; /* Number of busy untagged CCBs */
1232
1233 /*
1234 * Circular tag allocation buffer.
1235 */
1236 u_short ia_tag; /* Tag allocation index */
1237 u_short if_tag; /* Tag release index */
1238 u_char *cb_tags; /* Circular tags buffer */
1239
1240 /*
1241 * Set when we want to clear all tasks.
1242 */
1243 u_char to_clear;
1244
1245 /*
1246 * Capabilities.
1247 */
1248 u_char user_flags;
1249 u_char current_flags;
1250 };
1251
1252 /*
1253 * Action from SCRIPTS on a task.
1254 * Is part of the CCB, but is also used separately to plug
1255 * error handling action to perform from SCRIPTS.
1256 */
1257 struct sym_actscr {
1258 u32 start; /* Jumped by SCRIPTS after selection */
1259 u32 restart; /* Jumped by SCRIPTS on relection */
1260 };
1261
1262 /*
1263 * Phase mismatch context.
1264 *
1265 * It is part of the CCB and is used as parameters for the
1266 * DATA pointer. We need two contexts to handle correctly the
1267 * SAVED DATA POINTER.
1268 */
1269 struct sym_pmc {
1270 struct sym_tblmove sg; /* Updated interrupted SG block */
1271 u32 ret; /* SCRIPT return address */
1272 };
1273
1274 /*
1275 * LUN control block lookup.
1276 * We use a direct pointer for LUN #0, and a table of
1277 * pointers which is only allocated for devices that support
1278 * LUN(s) > 0.
1279 */
1280 #if SYM_CONF_MAX_LUN <= 1
1281 #define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0
1282 #else
1283 #define sym_lp(np, tp, lun) \
1284 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0
1285 #endif
1286
1287 /*
1288 * Status are used by the host and the script processor.
1289 *
1290 * The last four bytes (status[4]) are copied to the
1291 * scratchb register (declared as scr0..scr3) just after the
1292 * select/reselect, and copied back just after disconnecting.
1293 * Inside the script the XX_REG are used.
1294 */
1295
1296 /*
1297 * Last four bytes (script)
1298 */
1299 #define QU_REG scr0
1300 #define HS_REG scr1
1301 #define HS_PRT nc_scr1
1302 #define SS_REG scr2
1303 #define SS_PRT nc_scr2
1304 #define HF_REG scr3
1305 #define HF_PRT nc_scr3
1306
1307 /*
1308 * Last four bytes (host)
1309 */
1310 #define actualquirks phys.head.status[0]
1311 #define host_status phys.head.status[1]
1312 #define ssss_status phys.head.status[2]
1313 #define host_flags phys.head.status[3]
1314
1315 /*
1316 * Host flags
1317 */
1318 #define HF_IN_PM0 1u
1319 #define HF_IN_PM1 (1u<<1)
1320 #define HF_ACT_PM (1u<<2)
1321 #define HF_DP_SAVED (1u<<3)
1322 #define HF_SENSE (1u<<4)
1323 #define HF_EXT_ERR (1u<<5)
1324 #define HF_DATA_IN (1u<<6)
1325 #ifdef SYM_CONF_IARB_SUPPORT
1326 #define HF_HINT_IARB (1u<<7)
1327 #endif
1328
1329 /*
1330 * Global CCB HEADER.
1331 *
1332 * Due to lack of indirect addressing on earlier NCR chips,
1333 * this substructure is copied from the ccb to a global
1334 * address after selection (or reselection) and copied back
1335 * before disconnect.
1336 * For SYMBIOS chips that support LOAD/STORE this copy is
1337 * not needed and thus not performed.
1338 */
1339
1340 struct sym_ccbh {
1341 /*
1342 * Start and restart SCRIPTS addresses (must be at 0).
1343 */
1344 /**/ struct sym_actscr go;
1345
1346 /*
1347 * SCRIPTS jump address that deal with data pointers.
1348 * 'savep' points to the position in the script responsible
1349 * for the actual transfer of data.
1350 * It's written on reception of a SAVE_DATA_POINTER message.
1351 */
1352 u32 savep; /* Jump address to saved data pointer */
1353 u32 lastp; /* SCRIPTS address at end of data */
1354 u32 goalp; /* Not accessed for now from SCRIPTS */
1355
1356 /*
1357 * Status fields.
1358 */
1359 u8 status[4];
1360 };
1361
1362 /*
1363 * Data Structure Block
1364 *
1365 * During execution of a ccb by the script processor, the
1366 * DSA (data structure address) register points to this
1367 * substructure of the ccb.
1368 */
1369 struct sym_dsb {
1370 /*
1371 * CCB header.
1372 * Also assumed at offset 0 of the sym_ccb structure.
1373 */
1374 /**/ struct sym_ccbh head;
1375
1376 /*
1377 * Phase mismatch contexts.
1378 * We need two to handle correctly the SAVED DATA POINTER.
1379 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic
1380 * for address calculation from SCRIPTS.
1381 */
1382 struct sym_pmc pm0;
1383 struct sym_pmc pm1;
1384
1385 /*
1386 * Table data for Script
1387 */
1388 struct sym_tblsel select;
1389 struct sym_tblmove smsg;
1390 struct sym_tblmove smsg_ext;
1391 struct sym_tblmove cmd;
1392 struct sym_tblmove sense;
1393 struct sym_tblmove wresid;
1394 struct sym_tblmove data [SYM_CONF_MAX_SG];
1395 };
1396
1397 /*
1398 * Our Command Control Block
1399 */
1400 struct sym_ccb {
1401 /*
1402 * This is the data structure which is pointed by the DSA
1403 * register when it is executed by the script processor.
1404 * It must be the first entry.
1405 */
1406 struct sym_dsb phys;
1407
1408 /*
1409 * Pointer to CAM ccb and related stuff.
1410 */
1411 union ccb *cam_ccb; /* CAM scsiio ccb */
1412 u8 cdb_buf[16]; /* Copy of CDB */
1413 u8 *sns_bbuf; /* Bounce buffer for sense data */
1414 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data)
1415 int data_len; /* Total data length */
1416 int segments; /* Number of SG segments */
1417
1418 /*
1419 * Miscellaneous status'.
1420 */
1421 u_char nego_status; /* Negotiation status */
1422 u_char xerr_status; /* Extended error flags */
1423 u32 extra_bytes; /* Extraneous bytes transferred */
1424
1425 /*
1426 * Message areas.
1427 * We prepare a message to be sent after selection.
1428 * We may use a second one if the command is rescheduled
1429 * due to CHECK_CONDITION or COMMAND TERMINATED.
1430 * Contents are IDENTIFY and SIMPLE_TAG.
1431 * While negotiating sync or wide transfer,
1432 * a SDTR or WDTR message is appended.
1433 */
1434 u_char scsi_smsg [12];
1435 u_char scsi_smsg2[12];
1436
1437 /*
1438 * Auto request sense related fields.
1439 */
1440 u_char sensecmd[6]; /* Request Sense command */
1441 u_char sv_scsi_status; /* Saved SCSI status */
1442 u_char sv_xerr_status; /* Saved extended status */
1443 int sv_resid; /* Saved residual */
1444
1445 /*
1446 * Map for the DMA of user data.
1447 */
1448 void *arg; /* Argument for some callback */
1449 bus_dmamap_t dmamap; /* DMA map for user data */
1450 u_char dmamapped;
1451 #define SYM_DMA_NONE 0
1452 #define SYM_DMA_READ 1
1453 #define SYM_DMA_WRITE 2
1454 /*
1455 * Other fields.
1456 */
1457 u32 ccb_ba; /* BUS address of this CCB */
1458 u_short tag; /* Tag for this transfer */
1459 /* NO_TAG means no tag */
1460 u_char target;
1461 u_char lun;
1462 ccb_p link_ccbh; /* Host adapter CCB hash chain */
1463 SYM_QUEHEAD
1464 link_ccbq; /* Link to free/busy CCB queue */
1465 u32 startp; /* Initial data pointer */
1466 int ext_sg; /* Extreme data pointer, used */
1467 int ext_ofs; /* to calculate the residual. */
1468 u_char to_abort; /* Want this IO to be aborted */
1469 };
1470
1471 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl))
1472
1473 /*
1474 * Host Control Block
1475 */
1476 struct sym_hcb {
1477 /*
1478 * Global headers.
1479 * Due to poorness of addressing capabilities, earlier
1480 * chips (810, 815, 825) copy part of the data structures
1481 * (CCB, TCB and LCB) in fixed areas.
1482 */
1483 #ifdef SYM_CONF_GENERIC_SUPPORT
1484 struct sym_ccbh ccb_head;
1485 struct sym_tcbh tcb_head;
1486 struct sym_lcbh lcb_head;
1487 #endif
1488 /*
1489 * Idle task and invalid task actions and
1490 * their bus addresses.
1491 */
1492 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1493 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1494
1495 /*
1496 * Dummy lun table to protect us against target
1497 * returning bad lun number on reselection.
1498 */
1499 u32 *badluntbl; /* Table physical address */
1500 u32 badlun_sa; /* SCRIPT handler BUS address */
1501
1502 /*
1503 * Bus address of this host control block.
1504 */
1505 u32 hcb_ba;
1506
1507 /*
1508 * Bit 32-63 of the on-chip RAM bus address in LE format.
1509 * The START_RAM64 script loads the MMRS and MMWS from this
1510 * field.
1511 */
1512 u32 scr_ram_seg;
1513
1514 /*
1515 * Chip and controller indentification.
1516 */
1517 device_t device;
1518
1519 /*
1520 * Initial value of some IO register bits.
1521 * These values are assumed to have been set by BIOS, and may
1522 * be used to probe adapter implementation differences.
1523 */
1524 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1525 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1526 sv_stest1;
1527
1528 /*
1529 * Actual initial value of IO register bits used by the
1530 * driver. They are loaded at initialisation according to
1531 * features that are to be enabled/disabled.
1532 */
1533 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1534 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1535
1536 /*
1537 * Target data.
1538 */
1539 #ifdef __amd64__
1540 struct sym_tcb *target;
1541 #else
1542 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1543 #endif
1544
1545 /*
1546 * Target control block bus address array used by the SCRIPT
1547 * on reselection.
1548 */
1549 u32 *targtbl;
1550 u32 targtbl_ba;
1551
1552 /*
1553 * CAM SIM information for this instance.
1554 */
1555 struct cam_sim *sim;
1556 struct cam_path *path;
1557
1558 /*
1559 * Allocated hardware resources.
1560 */
1561 struct resource *irq_res;
1562 struct resource *io_res;
1563 struct resource *mmio_res;
1564 struct resource *ram_res;
1565 int ram_id;
1566 void *intr;
1567
1568 /*
1569 * Bus stuff.
1570 *
1571 * My understanding of PCI is that all agents must share the
1572 * same addressing range and model.
1573 * But some hardware architecture guys provide complex and
1574 * brain-deaded stuff that makes shit.
1575 * This driver only support PCI compliant implementations and
1576 * deals with part of the BUS stuff complexity only to fit O/S
1577 * requirements.
1578 */
1579 bus_space_handle_t io_bsh;
1580 bus_space_tag_t io_tag;
1581 bus_space_handle_t mmio_bsh;
1582 bus_space_tag_t mmio_tag;
1583 bus_space_handle_t ram_bsh;
1584 bus_space_tag_t ram_tag;
1585
1586 /*
1587 * DMA stuff.
1588 */
1589 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1590 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1591 /*
1592 * BUS addresses of the chip
1593 */
1594 vm_offset_t mmio_ba; /* MMIO BUS address */
1595 int mmio_ws; /* MMIO Window size */
1596
1597 vm_offset_t ram_ba; /* RAM BUS address */
1598 int ram_ws; /* RAM window size */
1599
1600 /*
1601 * SCRIPTS virtual and physical bus addresses.
1602 * 'script' is loaded in the on-chip RAM if present.
1603 * 'scripth' stays in main memory for all chips except the
1604 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM.
1605 */
1606 u_char *scripta0; /* Copies of script and scripth */
1607 u_char *scriptb0; /* Copies of script and scripth */
1608 vm_offset_t scripta_ba; /* Actual script and scripth */
1609 vm_offset_t scriptb_ba; /* bus addresses. */
1610 vm_offset_t scriptb0_ba;
1611 u_short scripta_sz; /* Actual size of script A */
1612 u_short scriptb_sz; /* Actual size of script B */
1613
1614 /*
1615 * Bus addresses, setup and patch methods for
1616 * the selected firmware.
1617 */
1618 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1619 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1620 void (*fw_setup)(hcb_p np, const struct sym_fw *fw);
1621 void (*fw_patch)(hcb_p np);
1622 const char *fw_name;
1623
1624 /*
1625 * General controller parameters and configuration.
1626 */
1627 u_short device_id; /* PCI device id */
1628 u_char revision_id; /* PCI device revision id */
1629 u_int features; /* Chip features map */
1630 u_char myaddr; /* SCSI id of the adapter */
1631 u_char maxburst; /* log base 2 of dwords burst */
1632 u_char maxwide; /* Maximum transfer width */
1633 u_char minsync; /* Min sync period factor (ST) */
1634 u_char maxsync; /* Max sync period factor (ST) */
1635 u_char maxoffs; /* Max scsi offset (ST) */
1636 u_char minsync_dt; /* Min sync period factor (DT) */
1637 u_char maxsync_dt; /* Max sync period factor (DT) */
1638 u_char maxoffs_dt; /* Max scsi offset (DT) */
1639 u_char multiplier; /* Clock multiplier (1,2,4) */
1640 u_char clock_divn; /* Number of clock divisors */
1641 u32 clock_khz; /* SCSI clock frequency in KHz */
1642 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1643 /*
1644 * Start queue management.
1645 * It is filled up by the host processor and accessed by the
1646 * SCRIPTS processor in order to start SCSI commands.
1647 */
1648 volatile /* Prevent code optimizations */
1649 u32 *squeue; /* Start queue virtual address */
1650 u32 squeue_ba; /* Start queue BUS address */
1651 u_short squeueput; /* Next free slot of the queue */
1652 u_short actccbs; /* Number of allocated CCBs */
1653
1654 /*
1655 * Command completion queue.
1656 * It is the same size as the start queue to avoid overflow.
1657 */
1658 u_short dqueueget; /* Next position to scan */
1659 volatile /* Prevent code optimizations */
1660 u32 *dqueue; /* Completion (done) queue */
1661 u32 dqueue_ba; /* Done queue BUS address */
1662
1663 /*
1664 * Miscellaneous buffers accessed by the scripts-processor.
1665 * They shall be DWORD aligned, because they may be read or
1666 * written with a script command.
1667 */
1668 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1669 u_char msgin [8]; /* Buffer for MESSAGE IN */
1670 u32 lastmsg; /* Last SCSI message sent */
1671 u_char scratch; /* Scratch for SCSI receive */
1672
1673 /*
1674 * Miscellaneous configuration and status parameters.
1675 */
1676 u_char usrflags; /* Miscellaneous user flags */
1677 u_char scsi_mode; /* Current SCSI BUS mode */
1678 u_char verbose; /* Verbosity for this controller*/
1679 u32 cache; /* Used for cache test at init. */
1680
1681 /*
1682 * CCB lists and queue.
1683 */
1684 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1685 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1686 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1687
1688 /*
1689 * During error handling and/or recovery,
1690 * active CCBs that are to be completed with
1691 * error or requeued are moved from the busy_ccbq
1692 * to the comp_ccbq prior to completion.
1693 */
1694 SYM_QUEHEAD comp_ccbq;
1695
1696 /*
1697 * CAM CCB pending queue.
1698 */
1699 SYM_QUEHEAD cam_ccbq;
1700
1701 /*
1702 * IMMEDIATE ARBITRATION (IARB) control.
1703 *
1704 * We keep track in 'last_cp' of the last CCB that has been
1705 * queued to the SCRIPTS processor and clear 'last_cp' when
1706 * this CCB completes. If last_cp is not zero at the moment
1707 * we queue a new CCB, we set a flag in 'last_cp' that is
1708 * used by the SCRIPTS as a hint for setting IARB.
1709 * We donnot set more than 'iarb_max' consecutive hints for
1710 * IARB in order to leave devices a chance to reselect.
1711 * By the way, any non zero value of 'iarb_max' is unfair. :)
1712 */
1713 #ifdef SYM_CONF_IARB_SUPPORT
1714 u_short iarb_max; /* Max. # consecutive IARB hints*/
1715 u_short iarb_count; /* Actual # of these hints */
1716 ccb_p last_cp;
1717 #endif
1718
1719 /*
1720 * Command abort handling.
1721 * We need to synchronize tightly with the SCRIPTS
1722 * processor in order to handle things correctly.
1723 */
1724 u_char abrt_msg[4]; /* Message to send buffer */
1725 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */
1726 struct sym_tblsel abrt_sel; /* Sync params for selection */
1727 u_char istat_sem; /* Tells the chip to stop (SEM) */
1728 };
1729
1730 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl))
1731
1732 /*
1733 * Return the name of the controller.
1734 */
1735 static __inline const char *sym_name(hcb_p np)
1736 {
1737 return device_get_nameunit(np->device);
1738 }
1739
1740 /*--------------------------------------------------------------------------*/
1741 /*------------------------------ FIRMWARES ---------------------------------*/
1742 /*--------------------------------------------------------------------------*/
1743
1744 /*
1745 * This stuff will be moved to a separate source file when
1746 * the driver will be broken into several source modules.
1747 */
1748
1749 /*
1750 * Macros used for all firmwares.
1751 */
1752 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)),
1753 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)),
1754 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label)
1755 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label)
1756
1757
1758 #ifdef SYM_CONF_GENERIC_SUPPORT
1759 /*
1760 * Allocate firmware #1 script area.
1761 */
1762 #define SYM_FWA_SCR sym_fw1a_scr
1763 #define SYM_FWB_SCR sym_fw1b_scr
1764 #include <dev/sym/sym_fw1.h>
1765 static const struct sym_fwa_ofs sym_fw1a_ofs = {
1766 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1767 };
1768 static const struct sym_fwb_ofs sym_fw1b_ofs = {
1769 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1770 };
1771 #undef SYM_FWA_SCR
1772 #undef SYM_FWB_SCR
1773 #endif /* SYM_CONF_GENERIC_SUPPORT */
1774
1775 /*
1776 * Allocate firmware #2 script area.
1777 */
1778 #define SYM_FWA_SCR sym_fw2a_scr
1779 #define SYM_FWB_SCR sym_fw2b_scr
1780 #include <dev/sym/sym_fw2.h>
1781 static const struct sym_fwa_ofs sym_fw2a_ofs = {
1782 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1783 };
1784 static const struct sym_fwb_ofs sym_fw2b_ofs = {
1785 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1786 SYM_GEN_B(struct SYM_FWB_SCR, start64)
1787 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle)
1788 };
1789 #undef SYM_FWA_SCR
1790 #undef SYM_FWB_SCR
1791
1792 #undef SYM_GEN_A
1793 #undef SYM_GEN_B
1794 #undef PADDR_A
1795 #undef PADDR_B
1796
1797 #ifdef SYM_CONF_GENERIC_SUPPORT
1798 /*
1799 * Patch routine for firmware #1.
1800 */
1801 static void
1802 sym_fw1_patch(hcb_p np)
1803 {
1804 struct sym_fw1a_scr *scripta0;
1805 struct sym_fw1b_scr *scriptb0;
1806
1807 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1808 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
1809
1810 /*
1811 * Remove LED support if not needed.
1812 */
1813 if (!(np->features & FE_LED0)) {
1814 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1815 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1816 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1817 }
1818
1819 #ifdef SYM_CONF_IARB_SUPPORT
1820 /*
1821 * If user does not want to use IMMEDIATE ARBITRATION
1822 * when we are reselected while attempting to arbitrate,
1823 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1824 */
1825 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1826 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1827 #endif
1828 /*
1829 * Patch some data in SCRIPTS.
1830 * - start and done queue initial bus address.
1831 * - target bus address table bus address.
1832 */
1833 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
1834 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
1835 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
1836 }
1837 #endif /* SYM_CONF_GENERIC_SUPPORT */
1838
1839 /*
1840 * Patch routine for firmware #2.
1841 */
1842 static void
1843 sym_fw2_patch(hcb_p np)
1844 {
1845 struct sym_fw2a_scr *scripta0;
1846 struct sym_fw2b_scr *scriptb0;
1847
1848 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
1849 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
1850
1851 /*
1852 * Remove LED support if not needed.
1853 */
1854 if (!(np->features & FE_LED0)) {
1855 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1856 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1857 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1858 }
1859
1860 #ifdef SYM_CONF_IARB_SUPPORT
1861 /*
1862 * If user does not want to use IMMEDIATE ARBITRATION
1863 * when we are reselected while attempting to arbitrate,
1864 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1865 */
1866 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1867 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1868 #endif
1869 /*
1870 * Patch some variable in SCRIPTS.
1871 * - start and done queue initial bus address.
1872 * - target bus address table bus address.
1873 */
1874 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
1875 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
1876 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
1877
1878 /*
1879 * Remove the load of SCNTL4 on reselection if not a C10.
1880 */
1881 if (!(np->features & FE_C10)) {
1882 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP);
1883 scripta0->resel_scntl4[1] = cpu_to_scr(0);
1884 }
1885
1886 /*
1887 * Remove a couple of work-arounds specific to C1010 if
1888 * they are not desirable. See `sym_fw2.h' for more details.
1889 */
1890 if (!(np->device_id == PCI_ID_LSI53C1010_2 &&
1891 np->revision_id < 0x1 &&
1892 np->pciclk_khz < 60000)) {
1893 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP);
1894 scripta0->datao_phase[1] = cpu_to_scr(0);
1895 }
1896 if (!(np->device_id == PCI_ID_LSI53C1010 &&
1897 /* np->revision_id < 0xff */ 1)) {
1898 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP);
1899 scripta0->sel_done[1] = cpu_to_scr(0);
1900 }
1901
1902 /*
1903 * Patch some other variables in SCRIPTS.
1904 * These ones are loaded by the SCRIPTS processor.
1905 */
1906 scriptb0->pm0_data_addr[0] =
1907 cpu_to_scr(np->scripta_ba +
1908 offsetof(struct sym_fw2a_scr, pm0_data));
1909 scriptb0->pm1_data_addr[0] =
1910 cpu_to_scr(np->scripta_ba +
1911 offsetof(struct sym_fw2a_scr, pm1_data));
1912 }
1913
1914 /*
1915 * Fill the data area in scripts.
1916 * To be done for all firmwares.
1917 */
1918 static void
1919 sym_fw_fill_data (u32 *in, u32 *out)
1920 {
1921 int i;
1922
1923 for (i = 0; i < SYM_CONF_MAX_SG; i++) {
1924 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN;
1925 *in++ = offsetof (struct sym_dsb, data[i]);
1926 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT;
1927 *out++ = offsetof (struct sym_dsb, data[i]);
1928 }
1929 }
1930
1931 /*
1932 * Setup useful script bus addresses.
1933 * To be done for all firmwares.
1934 */
1935 static void
1936 sym_fw_setup_bus_addresses(hcb_p np, const struct sym_fw *fw)
1937 {
1938 u32 *pa;
1939 const u_short *po;
1940 int i;
1941
1942 /*
1943 * Build the bus address table for script A
1944 * from the script A offset table.
1945 */
1946 po = (const u_short *) fw->a_ofs;
1947 pa = (u32 *) &np->fwa_bas;
1948 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++)
1949 pa[i] = np->scripta_ba + po[i];
1950
1951 /*
1952 * Same for script B.
1953 */
1954 po = (const u_short *) fw->b_ofs;
1955 pa = (u32 *) &np->fwb_bas;
1956 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++)
1957 pa[i] = np->scriptb_ba + po[i];
1958 }
1959
1960 #ifdef SYM_CONF_GENERIC_SUPPORT
1961 /*
1962 * Setup routine for firmware #1.
1963 */
1964 static void
1965 sym_fw1_setup(hcb_p np, const struct sym_fw *fw)
1966 {
1967 struct sym_fw1a_scr *scripta0;
1968 struct sym_fw1b_scr *scriptb0;
1969
1970 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1971 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
1972
1973 /*
1974 * Fill variable parts in scripts.
1975 */
1976 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
1977
1978 /*
1979 * Setup bus addresses used from the C code..
1980 */
1981 sym_fw_setup_bus_addresses(np, fw);
1982 }
1983 #endif /* SYM_CONF_GENERIC_SUPPORT */
1984
1985 /*
1986 * Setup routine for firmware #2.
1987 */
1988 static void
1989 sym_fw2_setup(hcb_p np, const struct sym_fw *fw)
1990 {
1991 struct sym_fw2a_scr *scripta0;
1992 struct sym_fw2b_scr *scriptb0;
1993
1994 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
1995 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
1996
1997 /*
1998 * Fill variable parts in scripts.
1999 */
2000 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2001
2002 /*
2003 * Setup bus addresses used from the C code..
2004 */
2005 sym_fw_setup_bus_addresses(np, fw);
2006 }
2007
2008 /*
2009 * Allocate firmware descriptors.
2010 */
2011 #ifdef SYM_CONF_GENERIC_SUPPORT
2012 static const struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic");
2013 #endif /* SYM_CONF_GENERIC_SUPPORT */
2014 static const struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based");
2015
2016 /*
2017 * Find the most appropriate firmware for a chip.
2018 */
2019 static const struct sym_fw *
2020 sym_find_firmware(const struct sym_pci_chip *chip)
2021 {
2022 if (chip->features & FE_LDSTR)
2023 return &sym_fw2;
2024 #ifdef SYM_CONF_GENERIC_SUPPORT
2025 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC)))
2026 return &sym_fw1;
2027 #endif
2028 else
2029 return NULL;
2030 }
2031
2032 /*
2033 * Bind a script to physical addresses.
2034 */
2035 static void sym_fw_bind_script (hcb_p np, u32 *start, int len)
2036 {
2037 u32 opcode, new, old, tmp1, tmp2;
2038 u32 *end, *cur;
2039 int relocs;
2040
2041 cur = start;
2042 end = start + len/4;
2043
2044 while (cur < end) {
2045
2046 opcode = *cur;
2047
2048 /*
2049 * If we forget to change the length
2050 * in scripts, a field will be
2051 * padded with 0. This is an illegal
2052 * command.
2053 */
2054 if (opcode == 0) {
2055 printf ("%s: ERROR0 IN SCRIPT at %d.\n",
2056 sym_name(np), (int) (cur-start));
2057 MDELAY (10000);
2058 ++cur;
2059 continue;
2060 };
2061
2062 /*
2063 * We use the bogus value 0xf00ff00f ;-)
2064 * to reserve data area in SCRIPTS.
2065 */
2066 if (opcode == SCR_DATA_ZERO) {
2067 *cur++ = 0;
2068 continue;
2069 }
2070
2071 if (DEBUG_FLAGS & DEBUG_SCRIPT)
2072 printf ("%d: <%x>\n", (int) (cur-start),
2073 (unsigned)opcode);
2074
2075 /*
2076 * We don't have to decode ALL commands
2077 */
2078 switch (opcode >> 28) {
2079 case 0xf:
2080 /*
2081 * LOAD / STORE DSA relative, don't relocate.
2082 */
2083 relocs = 0;
2084 break;
2085 case 0xe:
2086 /*
2087 * LOAD / STORE absolute.
2088 */
2089 relocs = 1;
2090 break;
2091 case 0xc:
2092 /*
2093 * COPY has TWO arguments.
2094 */
2095 relocs = 2;
2096 tmp1 = cur[1];
2097 tmp2 = cur[2];
2098 if ((tmp1 ^ tmp2) & 3) {
2099 printf ("%s: ERROR1 IN SCRIPT at %d.\n",
2100 sym_name(np), (int) (cur-start));
2101 MDELAY (10000);
2102 }
2103 /*
2104 * If PREFETCH feature not enabled, remove
2105 * the NO FLUSH bit if present.
2106 */
2107 if ((opcode & SCR_NO_FLUSH) &&
2108 !(np->features & FE_PFEN)) {
2109 opcode = (opcode & ~SCR_NO_FLUSH);
2110 }
2111 break;
2112 case 0x0:
2113 /*
2114 * MOVE/CHMOV (absolute address)
2115 */
2116 if (!(np->features & FE_WIDE))
2117 opcode = (opcode | OPC_MOVE);
2118 relocs = 1;
2119 break;
2120 case 0x1:
2121 /*
2122 * MOVE/CHMOV (table indirect)
2123 */
2124 if (!(np->features & FE_WIDE))
2125 opcode = (opcode | OPC_MOVE);
2126 relocs = 0;
2127 break;
2128 case 0x8:
2129 /*
2130 * JUMP / CALL
2131 * dont't relocate if relative :-)
2132 */
2133 if (opcode & 0x00800000)
2134 relocs = 0;
2135 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/
2136 relocs = 2;
2137 else
2138 relocs = 1;
2139 break;
2140 case 0x4:
2141 case 0x5:
2142 case 0x6:
2143 case 0x7:
2144 relocs = 1;
2145 break;
2146 default:
2147 relocs = 0;
2148 break;
2149 };
2150
2151 /*
2152 * Scriptify:) the opcode.
2153 */
2154 *cur++ = cpu_to_scr(opcode);
2155
2156 /*
2157 * If no relocation, assume 1 argument
2158 * and just scriptize:) it.
2159 */
2160 if (!relocs) {
2161 *cur = cpu_to_scr(*cur);
2162 ++cur;
2163 continue;
2164 }
2165
2166 /*
2167 * Otherwise performs all needed relocations.
2168 */
2169 while (relocs--) {
2170 old = *cur;
2171
2172 switch (old & RELOC_MASK) {
2173 case RELOC_REGISTER:
2174 new = (old & ~RELOC_MASK) + np->mmio_ba;
2175 break;
2176 case RELOC_LABEL_A:
2177 new = (old & ~RELOC_MASK) + np->scripta_ba;
2178 break;
2179 case RELOC_LABEL_B:
2180 new = (old & ~RELOC_MASK) + np->scriptb_ba;
2181 break;
2182 case RELOC_SOFTC:
2183 new = (old & ~RELOC_MASK) + np->hcb_ba;
2184 break;
2185 case 0:
2186 /*
2187 * Don't relocate a 0 address.
2188 * They are mostly used for patched or
2189 * script self-modified areas.
2190 */
2191 if (old == 0) {
2192 new = old;
2193 break;
2194 }
2195 /* fall through */
2196 default:
2197 new = 0;
2198 panic("sym_fw_bind_script: "
2199 "weird relocation %x\n", old);
2200 break;
2201 }
2202
2203 *cur++ = cpu_to_scr(new);
2204 }
2205 };
2206 }
2207
2208 /*---------------------------------------------------------------------------*/
2209 /*--------------------------- END OF FIRMWARES -----------------------------*/
2210 /*---------------------------------------------------------------------------*/
2211
2212 /*
2213 * Function prototypes.
2214 */
2215 static void sym_save_initial_setting (hcb_p np);
2216 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram);
2217 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr);
2218 static void sym_put_start_queue (hcb_p np, ccb_p cp);
2219 static void sym_chip_reset (hcb_p np);
2220 static void sym_soft_reset (hcb_p np);
2221 static void sym_start_reset (hcb_p np);
2222 static int sym_reset_scsi_bus (hcb_p np, int enab_int);
2223 static int sym_wakeup_done (hcb_p np);
2224 static void sym_flush_busy_queue (hcb_p np, int cam_status);
2225 static void sym_flush_comp_queue (hcb_p np, int cam_status);
2226 static void sym_init (hcb_p np, int reason);
2227 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp,
2228 u_char *fakp);
2229 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per,
2230 u_char div, u_char fak);
2231 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide);
2232 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2233 u_char per, u_char wide, u_char div, u_char fak);
2234 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2235 u_char per, u_char wide, u_char div, u_char fak);
2236 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat);
2237 static void sym_intr (void *arg);
2238 static void sym_poll (struct cam_sim *sim);
2239 static void sym_recover_scsi_int (hcb_p np, u_char hsts);
2240 static void sym_int_sto (hcb_p np);
2241 static void sym_int_udc (hcb_p np);
2242 static void sym_int_sbmc (hcb_p np);
2243 static void sym_int_par (hcb_p np, u_short sist);
2244 static void sym_int_ma (hcb_p np);
2245 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun,
2246 int task);
2247 static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp);
2248 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task);
2249 static void sym_sir_task_recovery (hcb_p np, int num);
2250 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs);
2251 static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs);
2252 static int sym_compute_residual (hcb_p np, ccb_p cp);
2253 static int sym_show_msg (u_char * msg);
2254 static void sym_print_msg (ccb_p cp, char *label, u_char *msg);
2255 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp);
2256 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp);
2257 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp);
2258 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp);
2259 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp);
2260 static void sym_int_sir (hcb_p np);
2261 static void sym_free_ccb (hcb_p np, ccb_p cp);
2262 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order);
2263 static ccb_p sym_alloc_ccb (hcb_p np);
2264 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);
2265 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln);
2266 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln);
2267 static int sym_snooptest (hcb_p np);
2268 static void sym_selectclock(hcb_p np, u_char scntl3);
2269 static void sym_getclock (hcb_p np, int mult);
2270 static int sym_getpciclock (hcb_p np);
2271 static void sym_complete_ok (hcb_p np, ccb_p cp);
2272 static void sym_complete_error (hcb_p np, ccb_p cp);
2273 static void sym_timeout (void *arg);
2274 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out);
2275 static void sym_reset_dev (hcb_p np, union ccb *ccb);
2276 static void sym_action (struct cam_sim *sim, union ccb *ccb);
2277 static void sym_action1 (struct cam_sim *sim, union ccb *ccb);
2278 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp);
2279 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio,
2280 ccb_p cp);
2281 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
2282 bus_dma_segment_t *psegs, int nsegs);
2283 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp,
2284 bus_dma_segment_t *psegs, int nsegs);
2285 static void sym_action2 (struct cam_sim *sim, union ccb *ccb);
2286 static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip,
2287 struct ccb_trans_settings *cts);
2288 static void sym_update_dflags(hcb_p np, u_char *flags,
2289 struct ccb_trans_settings *cts);
2290
2291 static const struct sym_pci_chip *sym_find_pci_chip (device_t dev);
2292 static int sym_pci_probe (device_t dev);
2293 static int sym_pci_attach (device_t dev);
2294
2295 static void sym_pci_free (hcb_p np);
2296 static int sym_cam_attach (hcb_p np);
2297 static void sym_cam_free (hcb_p np);
2298
2299 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram);
2300 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp);
2301 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp);
2302
2303 /*
2304 * Print something which allows to retrieve the controler type,
2305 * unit, target, lun concerned by a kernel message.
2306 */
2307 static void PRINT_TARGET (hcb_p np, int target)
2308 {
2309 printf ("%s:%d:", sym_name(np), target);
2310 }
2311
2312 static void PRINT_LUN(hcb_p np, int target, int lun)
2313 {
2314 printf ("%s:%d:%d:", sym_name(np), target, lun);
2315 }
2316
2317 static void PRINT_ADDR (ccb_p cp)
2318 {
2319 if (cp && cp->cam_ccb)
2320 xpt_print_path(cp->cam_ccb->ccb_h.path);
2321 }
2322
2323 /*
2324 * Take into account this ccb in the freeze count.
2325 */
2326 static void sym_freeze_cam_ccb(union ccb *ccb)
2327 {
2328 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) {
2329 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2330 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2331 xpt_freeze_devq(ccb->ccb_h.path, 1);
2332 }
2333 }
2334 }
2335
2336 /*
2337 * Set the status field of a CAM CCB.
2338 */
2339 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status)
2340 {
2341 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2342 ccb->ccb_h.status |= status;
2343 }
2344
2345 /*
2346 * Get the status field of a CAM CCB.
2347 */
2348 static __inline int sym_get_cam_status(union ccb *ccb)
2349 {
2350 return ccb->ccb_h.status & CAM_STATUS_MASK;
2351 }
2352
2353 /*
2354 * Enqueue a CAM CCB.
2355 */
2356 static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb)
2357 {
2358 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED));
2359 ccb->ccb_h.status = CAM_REQ_INPROG;
2360
2361 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb,
2362 ccb->ccb_h.timeout*hz/1000);
2363 ccb->ccb_h.status |= CAM_SIM_QUEUED;
2364 ccb->ccb_h.sym_hcb_ptr = np;
2365
2366 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq);
2367 }
2368
2369 /*
2370 * Complete a pending CAM CCB.
2371 */
2372 static void sym_xpt_done(hcb_p np, union ccb *ccb)
2373 {
2374 if (ccb->ccb_h.status & CAM_SIM_QUEUED) {
2375 untimeout(sym_timeout, (caddr_t) ccb, ccb->ccb_h.timeout_ch);
2376 sym_remque(sym_qptr(&ccb->ccb_h.sim_links));
2377 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2378 ccb->ccb_h.sym_hcb_ptr = NULL;
2379 }
2380 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE)
2381 sym_freeze_cam_ccb(ccb);
2382 xpt_done(ccb);
2383 }
2384
2385 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status)
2386 {
2387 sym_set_cam_status(ccb, cam_status);
2388 sym_xpt_done(np, ccb);
2389 }
2390
2391 /*
2392 * SYMBIOS chip clock divisor table.
2393 *
2394 * Divisors are multiplied by 10,000,000 in order to make
2395 * calculations more simple.
2396 */
2397 #define _5M 5000000
2398 static const u32 div_10M[] =
2399 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
2400
2401 /*
2402 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
2403 * 128 transfers. All chips support at least 16 transfers
2404 * bursts. The 825A, 875 and 895 chips support bursts of up
2405 * to 128 transfers and the 895A and 896 support bursts of up
2406 * to 64 transfers. All other chips support up to 16
2407 * transfers bursts.
2408 *
2409 * For PCI 32 bit data transfers each transfer is a DWORD.
2410 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
2411 *
2412 * We use log base 2 (burst length) as internal code, with
2413 * value 0 meaning "burst disabled".
2414 */
2415
2416 /*
2417 * Burst length from burst code.
2418 */
2419 #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
2420
2421 /*
2422 * Burst code from io register bits.
2423 */
2424 #define burst_code(dmode, ctest4, ctest5) \
2425 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
2426
2427 /*
2428 * Set initial io register bits from burst code.
2429 */
2430 static __inline void sym_init_burst(hcb_p np, u_char bc)
2431 {
2432 np->rv_ctest4 &= ~0x80;
2433 np->rv_dmode &= ~(0x3 << 6);
2434 np->rv_ctest5 &= ~0x4;
2435
2436 if (!bc) {
2437 np->rv_ctest4 |= 0x80;
2438 }
2439 else {
2440 --bc;
2441 np->rv_dmode |= ((bc & 0x3) << 6);
2442 np->rv_ctest5 |= (bc & 0x4);
2443 }
2444 }
2445
2446
2447 /*
2448 * Print out the list of targets that have some flag disabled by user.
2449 */
2450 static void sym_print_targets_flag(hcb_p np, int mask, char *msg)
2451 {
2452 int cnt;
2453 int i;
2454
2455 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2456 if (i == np->myaddr)
2457 continue;
2458 if (np->target[i].usrflags & mask) {
2459 if (!cnt++)
2460 printf("%s: %s disabled for targets",
2461 sym_name(np), msg);
2462 printf(" %d", i);
2463 }
2464 }
2465 if (cnt)
2466 printf(".\n");
2467 }
2468
2469 /*
2470 * Save initial settings of some IO registers.
2471 * Assumed to have been set by BIOS.
2472 * We cannot reset the chip prior to reading the
2473 * IO registers, since informations will be lost.
2474 * Since the SCRIPTS processor may be running, this
2475 * is not safe on paper, but it seems to work quite
2476 * well. :)
2477 */
2478 static void sym_save_initial_setting (hcb_p np)
2479 {
2480 np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
2481 np->sv_scntl3 = INB(nc_scntl3) & 0x07;
2482 np->sv_dmode = INB(nc_dmode) & 0xce;
2483 np->sv_dcntl = INB(nc_dcntl) & 0xa8;
2484 np->sv_ctest3 = INB(nc_ctest3) & 0x01;
2485 np->sv_ctest4 = INB(nc_ctest4) & 0x80;
2486 np->sv_gpcntl = INB(nc_gpcntl);
2487 np->sv_stest1 = INB(nc_stest1);
2488 np->sv_stest2 = INB(nc_stest2) & 0x20;
2489 np->sv_stest4 = INB(nc_stest4);
2490 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
2491 np->sv_scntl4 = INB(nc_scntl4);
2492 np->sv_ctest5 = INB(nc_ctest5) & 0x04;
2493 }
2494 else
2495 np->sv_ctest5 = INB(nc_ctest5) & 0x24;
2496 }
2497
2498 /*
2499 * Prepare io register values used by sym_init() according
2500 * to selected and supported features.
2501 */
2502 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
2503 {
2504 u_char burst_max;
2505 u32 period;
2506 int i;
2507
2508 /*
2509 * Wide ?
2510 */
2511 np->maxwide = (np->features & FE_WIDE)? 1 : 0;
2512
2513 /*
2514 * Get the frequency of the chip's clock.
2515 */
2516 if (np->features & FE_QUAD)
2517 np->multiplier = 4;
2518 else if (np->features & FE_DBLR)
2519 np->multiplier = 2;
2520 else
2521 np->multiplier = 1;
2522
2523 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000;
2524 np->clock_khz *= np->multiplier;
2525
2526 if (np->clock_khz != 40000)
2527 sym_getclock(np, np->multiplier);
2528
2529 /*
2530 * Divisor to be used for async (timer pre-scaler).
2531 */
2532 i = np->clock_divn - 1;
2533 while (--i >= 0) {
2534 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
2535 ++i;
2536 break;
2537 }
2538 }
2539 np->rv_scntl3 = i+1;
2540
2541 /*
2542 * The C1010 uses hardwired divisors for async.
2543 * So, we just throw away, the async. divisor.:-)
2544 */
2545 if (np->features & FE_C10)
2546 np->rv_scntl3 = 0;
2547
2548 /*
2549 * Minimum synchronous period factor supported by the chip.
2550 * Btw, 'period' is in tenths of nanoseconds.
2551 */
2552 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
2553 if (period <= 250) np->minsync = 10;
2554 else if (period <= 303) np->minsync = 11;
2555 else if (period <= 500) np->minsync = 12;
2556 else np->minsync = (period + 40 - 1) / 40;
2557
2558 /*
2559 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
2560 */
2561 if (np->minsync < 25 &&
2562 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
2563 np->minsync = 25;
2564 else if (np->minsync < 12 &&
2565 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
2566 np->minsync = 12;
2567
2568 /*
2569 * Maximum synchronous period factor supported by the chip.
2570 */
2571 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
2572 np->maxsync = period > 2540 ? 254 : period / 10;
2573
2574 /*
2575 * If chip is a C1010, guess the sync limits in DT mode.
2576 */
2577 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
2578 if (np->clock_khz == 160000) {
2579 np->minsync_dt = 9;
2580 np->maxsync_dt = 50;
2581 np->maxoffs_dt = 62;
2582 }
2583 }
2584
2585 /*
2586 * 64 bit addressing (895A/896/1010) ?
2587 */
2588 if (np->features & FE_DAC)
2589 #ifdef __LP64__
2590 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
2591 #else
2592 np->rv_ccntl1 |= (DDAC);
2593 #endif
2594
2595 /*
2596 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
2597 */
2598 if (np->features & FE_NOPM)
2599 np->rv_ccntl0 |= (ENPMJ);
2600
2601 /*
2602 * C1010 Errata.
2603 * In dual channel mode, contention occurs if internal cycles
2604 * are used. Disable internal cycles.
2605 */
2606 if (np->device_id == PCI_ID_LSI53C1010 &&
2607 np->revision_id < 0x2)
2608 np->rv_ccntl0 |= DILS;
2609
2610 /*
2611 * Select burst length (dwords)
2612 */
2613 burst_max = SYM_SETUP_BURST_ORDER;
2614 if (burst_max == 255)
2615 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
2616 np->sv_ctest5);
2617 if (burst_max > 7)
2618 burst_max = 7;
2619 if (burst_max > np->maxburst)
2620 burst_max = np->maxburst;
2621
2622 /*
2623 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
2624 * This chip and the 860 Rev 1 may wrongly use PCI cache line
2625 * based transactions on LOAD/STORE instructions. So we have
2626 * to prevent these chips from using such PCI transactions in
2627 * this driver. The generic ncr driver that does not use
2628 * LOAD/STORE instructions does not need this work-around.
2629 */
2630 if ((np->device_id == PCI_ID_SYM53C810 &&
2631 np->revision_id >= 0x10 && np->revision_id <= 0x11) ||
2632 (np->device_id == PCI_ID_SYM53C860 &&
2633 np->revision_id <= 0x1))
2634 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
2635
2636 /*
2637 * Select all supported special features.
2638 * If we are using on-board RAM for scripts, prefetch (PFEN)
2639 * does not help, but burst op fetch (BOF) does.
2640 * Disabling PFEN makes sure BOF will be used.
2641 */
2642 if (np->features & FE_ERL)
2643 np->rv_dmode |= ERL; /* Enable Read Line */
2644 if (np->features & FE_BOF)
2645 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
2646 if (np->features & FE_ERMP)
2647 np->rv_dmode |= ERMP; /* Enable Read Multiple */
2648 #if 1
2649 if ((np->features & FE_PFEN) && !np->ram_ba)
2650 #else
2651 if (np->features & FE_PFEN)
2652 #endif
2653 np->rv_dcntl |= PFEN; /* Prefetch Enable */
2654 if (np->features & FE_CLSE)
2655 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
2656 if (np->features & FE_WRIE)
2657 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
2658 if (np->features & FE_DFS)
2659 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
2660
2661 /*
2662 * Select some other
2663 */
2664 if (SYM_SETUP_PCI_PARITY)
2665 np->rv_ctest4 |= MPEE; /* Master parity checking */
2666 if (SYM_SETUP_SCSI_PARITY)
2667 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
2668
2669 /*
2670 * Get parity checking, host ID and verbose mode from NVRAM
2671 */
2672 np->myaddr = 255;
2673 sym_nvram_setup_host (np, nvram);
2674
2675 /*
2676 * Get SCSI addr of host adapter (set by bios?).
2677 */
2678 if (np->myaddr == 255) {
2679 np->myaddr = INB(nc_scid) & 0x07;
2680 if (!np->myaddr)
2681 np->myaddr = SYM_SETUP_HOST_ID;
2682 }
2683
2684 /*
2685 * Prepare initial io register bits for burst length
2686 */
2687 sym_init_burst(np, burst_max);
2688
2689 /*
2690 * Set SCSI BUS mode.
2691 * - LVD capable chips (895/895A/896/1010) report the
2692 * current BUS mode through the STEST4 IO register.
2693 * - For previous generation chips (825/825A/875),
2694 * user has to tell us how to check against HVD,
2695 * since a 100% safe algorithm is not possible.
2696 */
2697 np->scsi_mode = SMODE_SE;
2698 if (np->features & (FE_ULTRA2|FE_ULTRA3))
2699 np->scsi_mode = (np->sv_stest4 & SMODE);
2700 else if (np->features & FE_DIFF) {
2701 if (SYM_SETUP_SCSI_DIFF == 1) {
2702 if (np->sv_scntl3) {
2703 if (np->sv_stest2 & 0x20)
2704 np->scsi_mode = SMODE_HVD;
2705 }
2706 else if (nvram->type == SYM_SYMBIOS_NVRAM) {
2707 if (!(INB(nc_gpreg) & 0x08))
2708 np->scsi_mode = SMODE_HVD;
2709 }
2710 }
2711 else if (SYM_SETUP_SCSI_DIFF == 2)
2712 np->scsi_mode = SMODE_HVD;
2713 }
2714 if (np->scsi_mode == SMODE_HVD)
2715 np->rv_stest2 |= 0x20;
2716
2717 /*
2718 * Set LED support from SCRIPTS.
2719 * Ignore this feature for boards known to use a
2720 * specific GPIO wiring and for the 895A, 896
2721 * and 1010 that drive the LED directly.
2722 */
2723 if ((SYM_SETUP_SCSI_LED ||
2724 (nvram->type == SYM_SYMBIOS_NVRAM ||
2725 (nvram->type == SYM_TEKRAM_NVRAM &&
2726 np->device_id == PCI_ID_SYM53C895))) &&
2727 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
2728 np->features |= FE_LED0;
2729
2730 /*
2731 * Set irq mode.
2732 */
2733 switch(SYM_SETUP_IRQ_MODE & 3) {
2734 case 2:
2735 np->rv_dcntl |= IRQM;
2736 break;
2737 case 1:
2738 np->rv_dcntl |= (np->sv_dcntl & IRQM);
2739 break;
2740 default:
2741 break;
2742 }
2743
2744 /*
2745 * Configure targets according to driver setup.
2746 * If NVRAM present get targets setup from NVRAM.
2747 */
2748 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2749 tcb_p tp = &np->target[i];
2750
2751 #ifdef FreeBSD_New_Tran_Settings
2752 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2;
2753 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2;
2754 #endif
2755 tp->tinfo.user.period = np->minsync;
2756 if (np->features & FE_ULTRA3)
2757 tp->tinfo.user.period = np->minsync_dt;
2758 tp->tinfo.user.offset = np->maxoffs;
2759 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT;
2760 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
2761 tp->usrtags = SYM_SETUP_MAX_TAG;
2762
2763 sym_nvram_setup_target (np, i, nvram);
2764
2765 /*
2766 * For now, guess PPR/DT support from the period
2767 * and BUS width.
2768 */
2769 if (np->features & FE_ULTRA3) {
2770 if (tp->tinfo.user.period <= 9 &&
2771 tp->tinfo.user.width == BUS_16_BIT) {
2772 tp->tinfo.user.options |= PPR_OPT_DT;
2773 tp->tinfo.user.offset = np->maxoffs_dt;
2774 #ifdef FreeBSD_New_Tran_Settings
2775 tp->tinfo.user.spi_version = 3;
2776 #endif
2777 }
2778 }
2779
2780 if (!tp->usrtags)
2781 tp->usrflags &= ~SYM_TAGS_ENABLED;
2782 }
2783
2784 /*
2785 * Let user know about the settings.
2786 */
2787 i = nvram->type;
2788 printf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np),
2789 i == SYM_SYMBIOS_NVRAM ? "Symbios" :
2790 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"),
2791 np->myaddr,
2792 (np->features & FE_ULTRA3) ? 80 :
2793 (np->features & FE_ULTRA2) ? 40 :
2794 (np->features & FE_ULTRA) ? 20 : 10,
2795 sym_scsi_bus_mode(np->scsi_mode),
2796 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
2797 /*
2798 * Tell him more on demand.
2799 */
2800 if (sym_verbose) {
2801 printf("%s: %s IRQ line driver%s\n",
2802 sym_name(np),
2803 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
2804 np->ram_ba ? ", using on-chip SRAM" : "");
2805 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
2806 if (np->features & FE_NOPM)
2807 printf("%s: handling phase mismatch from SCRIPTS.\n",
2808 sym_name(np));
2809 }
2810 /*
2811 * And still more.
2812 */
2813 if (sym_verbose > 1) {
2814 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
2815 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2816 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
2817 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
2818
2819 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
2820 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2821 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
2822 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
2823 }
2824 /*
2825 * Let user be aware of targets that have some disable flags set.
2826 */
2827 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT");
2828 if (sym_verbose)
2829 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED,
2830 "SCAN FOR LUNS");
2831
2832 return 0;
2833 }
2834
2835 /*
2836 * Prepare the next negotiation message if needed.
2837 *
2838 * Fill in the part of message buffer that contains the
2839 * negotiation and the nego_status field of the CCB.
2840 * Returns the size of the message in bytes.
2841 */
2842
2843 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr)
2844 {
2845 tcb_p tp = &np->target[cp->target];
2846 int msglen = 0;
2847
2848 /*
2849 * Early C1010 chips need a work-around for DT
2850 * data transfer to work.
2851 */
2852 if (!(np->features & FE_U3EN))
2853 tp->tinfo.goal.options = 0;
2854 /*
2855 * negotiate using PPR ?
2856 */
2857 if (tp->tinfo.goal.options & PPR_OPT_MASK)
2858 nego = NS_PPR;
2859 /*
2860 * negotiate wide transfers ?
2861 */
2862 else if (tp->tinfo.current.width != tp->tinfo.goal.width)
2863 nego = NS_WIDE;
2864 /*
2865 * negotiate synchronous transfers?
2866 */
2867 else if (tp->tinfo.current.period != tp->tinfo.goal.period ||
2868 tp->tinfo.current.offset != tp->tinfo.goal.offset)
2869 nego = NS_SYNC;
2870
2871 switch (nego) {
2872 case NS_SYNC:
2873 msgptr[msglen++] = M_EXTENDED;
2874 msgptr[msglen++] = 3;
2875 msgptr[msglen++] = M_X_SYNC_REQ;
2876 msgptr[msglen++] = tp->tinfo.goal.period;
2877 msgptr[msglen++] = tp->tinfo.goal.offset;
2878 break;
2879 case NS_WIDE:
2880 msgptr[msglen++] = M_EXTENDED;
2881 msgptr[msglen++] = 2;
2882 msgptr[msglen++] = M_X_WIDE_REQ;
2883 msgptr[msglen++] = tp->tinfo.goal.width;
2884 break;
2885 case NS_PPR:
2886 msgptr[msglen++] = M_EXTENDED;
2887 msgptr[msglen++] = 6;
2888 msgptr[msglen++] = M_X_PPR_REQ;
2889 msgptr[msglen++] = tp->tinfo.goal.period;
2890 msgptr[msglen++] = 0;
2891 msgptr[msglen++] = tp->tinfo.goal.offset;
2892 msgptr[msglen++] = tp->tinfo.goal.width;
2893 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT;
2894 break;
2895 };
2896
2897 cp->nego_status = nego;
2898
2899 if (nego) {
2900 tp->nego_cp = cp; /* Keep track a nego will be performed */
2901 if (DEBUG_FLAGS & DEBUG_NEGO) {
2902 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" :
2903 nego == NS_WIDE ? "wide msgout" :
2904 "ppr msgout", msgptr);
2905 };
2906 };
2907
2908 return msglen;
2909 }
2910
2911 /*
2912 * Insert a job into the start queue.
2913 */
2914 static void sym_put_start_queue(hcb_p np, ccb_p cp)
2915 {
2916 u_short qidx;
2917
2918 #ifdef SYM_CONF_IARB_SUPPORT
2919 /*
2920 * If the previously queued CCB is not yet done,
2921 * set the IARB hint. The SCRIPTS will go with IARB
2922 * for this job when starting the previous one.
2923 * We leave devices a chance to win arbitration by
2924 * not using more than 'iarb_max' consecutive
2925 * immediate arbitrations.
2926 */
2927 if (np->last_cp && np->iarb_count < np->iarb_max) {
2928 np->last_cp->host_flags |= HF_HINT_IARB;
2929 ++np->iarb_count;
2930 }
2931 else
2932 np->iarb_count = 0;
2933 np->last_cp = cp;
2934 #endif
2935
2936 /*
2937 * Insert first the idle task and then our job.
2938 * The MB should ensure proper ordering.
2939 */
2940 qidx = np->squeueput + 2;
2941 if (qidx >= MAX_QUEUE*2) qidx = 0;
2942
2943 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
2944 MEMORY_BARRIER();
2945 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
2946
2947 np->squeueput = qidx;
2948
2949 if (DEBUG_FLAGS & DEBUG_QUEUE)
2950 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
2951
2952 /*
2953 * Script processor may be waiting for reselect.
2954 * Wake it up.
2955 */
2956 MEMORY_BARRIER();
2957 OUTB (nc_istat, SIGP|np->istat_sem);
2958 }
2959
2960
2961 /*
2962 * Soft reset the chip.
2963 *
2964 * Raising SRST when the chip is running may cause
2965 * problems on dual function chips (see below).
2966 * On the other hand, LVD devices need some delay
2967 * to settle and report actual BUS mode in STEST4.
2968 */
2969 static void sym_chip_reset (hcb_p np)
2970 {
2971 OUTB (nc_istat, SRST);
2972 UDELAY (10);
2973 OUTB (nc_istat, 0);
2974 UDELAY(2000); /* For BUS MODE to settle */
2975 }
2976
2977 /*
2978 * Soft reset the chip.
2979 *
2980 * Some 896 and 876 chip revisions may hang-up if we set
2981 * the SRST (soft reset) bit at the wrong time when SCRIPTS
2982 * are running.
2983 * So, we need to abort the current operation prior to
2984 * soft resetting the chip.
2985 */
2986 static void sym_soft_reset (hcb_p np)
2987 {
2988 u_char istat;
2989 int i;
2990
2991 OUTB (nc_istat, CABRT);
2992 for (i = 1000000 ; i ; --i) {
2993 istat = INB (nc_istat);
2994 if (istat & SIP) {
2995 INW (nc_sist);
2996 continue;
2997 }
2998 if (istat & DIP) {
2999 OUTB (nc_istat, 0);
3000 INB (nc_dstat);
3001 break;
3002 }
3003 }
3004 if (!i)
3005 printf("%s: unable to abort current chip operation.\n",
3006 sym_name(np));
3007 sym_chip_reset (np);
3008 }
3009
3010 /*
3011 * Start reset process.
3012 *
3013 * The interrupt handler will reinitialize the chip.
3014 */
3015 static void sym_start_reset(hcb_p np)
3016 {
3017 (void) sym_reset_scsi_bus(np, 1);
3018 }
3019
3020 static int sym_reset_scsi_bus(hcb_p np, int enab_int)
3021 {
3022 u32 term;
3023 int retv = 0;
3024
3025 sym_soft_reset(np); /* Soft reset the chip */
3026 if (enab_int)
3027 OUTW (nc_sien, RST);
3028 /*
3029 * Enable Tolerant, reset IRQD if present and
3030 * properly set IRQ mode, prior to resetting the bus.
3031 */
3032 OUTB (nc_stest3, TE);
3033 OUTB (nc_dcntl, (np->rv_dcntl & IRQM));
3034 OUTB (nc_scntl1, CRST);
3035 UDELAY (200);
3036
3037 if (!SYM_SETUP_SCSI_BUS_CHECK)
3038 goto out;
3039 /*
3040 * Check for no terminators or SCSI bus shorts to ground.
3041 * Read SCSI data bus, data parity bits and control signals.
3042 * We are expecting RESET to be TRUE and other signals to be
3043 * FALSE.
3044 */
3045 term = INB(nc_sstat0);
3046 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
3047 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
3048 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
3049 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
3050 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
3051
3052 if (!(np->features & FE_WIDE))
3053 term &= 0x3ffff;
3054
3055 if (term != (2<<7)) {
3056 printf("%s: suspicious SCSI data while resetting the BUS.\n",
3057 sym_name(np));
3058 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
3059 "0x%lx, expecting 0x%lx\n",
3060 sym_name(np),
3061 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
3062 (u_long)term, (u_long)(2<<7));
3063 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
3064 retv = 1;
3065 }
3066 out:
3067 OUTB (nc_scntl1, 0);
3068 /* MDELAY(100); */
3069 return retv;
3070 }
3071
3072 /*
3073 * The chip may have completed jobs. Look at the DONE QUEUE.
3074 *
3075 * On architectures that may reorder LOAD/STORE operations,
3076 * a memory barrier may be needed after the reading of the
3077 * so-called `flag' and prior to dealing with the data.
3078 */
3079 static int sym_wakeup_done (hcb_p np)
3080 {
3081 ccb_p cp;
3082 int i, n;
3083 u32 dsa;
3084
3085 n = 0;
3086 i = np->dqueueget;
3087 while (1) {
3088 dsa = scr_to_cpu(np->dqueue[i]);
3089 if (!dsa)
3090 break;
3091 np->dqueue[i] = 0;
3092 if ((i = i+2) >= MAX_QUEUE*2)
3093 i = 0;
3094
3095 cp = sym_ccb_from_dsa(np, dsa);
3096 if (cp) {
3097 MEMORY_BARRIER();
3098 sym_complete_ok (np, cp);
3099 ++n;
3100 }
3101 else
3102 printf ("%s: bad DSA (%x) in done queue.\n",
3103 sym_name(np), (u_int) dsa);
3104 }
3105 np->dqueueget = i;
3106
3107 return n;
3108 }
3109
3110 /*
3111 * Complete all active CCBs with error.
3112 * Used on CHIP/SCSI RESET.
3113 */
3114 static void sym_flush_busy_queue (hcb_p np, int cam_status)
3115 {
3116 /*
3117 * Move all active CCBs to the COMP queue
3118 * and flush this queue.
3119 */
3120 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
3121 sym_que_init(&np->busy_ccbq);
3122 sym_flush_comp_queue(np, cam_status);
3123 }
3124
3125 /*
3126 * Start chip.
3127 *
3128 * 'reason' means:
3129 * 0: initialisation.
3130 * 1: SCSI BUS RESET delivered or received.
3131 * 2: SCSI BUS MODE changed.
3132 */
3133 static void sym_init (hcb_p np, int reason)
3134 {
3135 int i;
3136 u32 phys;
3137
3138 /*
3139 * Reset chip if asked, otherwise just clear fifos.
3140 */
3141 if (reason == 1)
3142 sym_soft_reset(np);
3143 else {
3144 OUTB (nc_stest3, TE|CSF);
3145 OUTONB (nc_ctest3, CLF);
3146 }
3147
3148 /*
3149 * Clear Start Queue
3150 */
3151 phys = np->squeue_ba;
3152 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3153 np->squeue[i] = cpu_to_scr(np->idletask_ba);
3154 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
3155 }
3156 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3157
3158 /*
3159 * Start at first entry.
3160 */
3161 np->squeueput = 0;
3162
3163 /*
3164 * Clear Done Queue
3165 */
3166 phys = np->dqueue_ba;
3167 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3168 np->dqueue[i] = 0;
3169 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
3170 }
3171 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3172
3173 /*
3174 * Start at first entry.
3175 */
3176 np->dqueueget = 0;
3177
3178 /*
3179 * Install patches in scripts.
3180 * This also let point to first position the start
3181 * and done queue pointers used from SCRIPTS.
3182 */
3183 np->fw_patch(np);
3184
3185 /*
3186 * Wakeup all pending jobs.
3187 */
3188 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET);
3189
3190 /*
3191 * Init chip.
3192 */
3193 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */
3194 UDELAY (2000); /* The 895 needs time for the bus mode to settle */
3195
3196 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
3197 /* full arb., ena parity, par->ATN */
3198 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
3199
3200 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
3201
3202 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
3203 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
3204 OUTB (nc_istat , SIGP ); /* Signal Process */
3205 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
3206 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
3207
3208 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
3209 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
3210 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
3211
3212 /* Extended Sreq/Sack filtering not supported on the C10 */
3213 if (np->features & FE_C10)
3214 OUTB (nc_stest2, np->rv_stest2);
3215 else
3216 OUTB (nc_stest2, EXT|np->rv_stest2);
3217
3218 OUTB (nc_stest3, TE); /* TolerANT enable */
3219 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
3220
3221 /*
3222 * For now, disable AIP generation on C1010-66.
3223 */
3224 if (np->device_id == PCI_ID_LSI53C1010_2)
3225 OUTB (nc_aipcntl1, DISAIP);
3226
3227 /*
3228 * C10101 Errata.
3229 * Errant SGE's when in narrow. Write bits 4 & 5 of
3230 * STEST1 register to disable SGE. We probably should do
3231 * that from SCRIPTS for each selection/reselection, but
3232 * I just don't want. :)
3233 */
3234 if (np->device_id == PCI_ID_LSI53C1010 &&
3235 /* np->revision_id < 0xff */ 1)
3236 OUTB (nc_stest1, INB(nc_stest1) | 0x30);
3237
3238 /*
3239 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
3240 * Disable overlapped arbitration for some dual function devices,
3241 * regardless revision id (kind of post-chip-design feature. ;-))
3242 */
3243 if (np->device_id == PCI_ID_SYM53C875)
3244 OUTB (nc_ctest0, (1<<5));
3245 else if (np->device_id == PCI_ID_SYM53C896)
3246 np->rv_ccntl0 |= DPR;
3247
3248 /*
3249 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
3250 * and/or hardware phase mismatch, since only such chips
3251 * seem to support those IO registers.
3252 */
3253 if (np->features & (FE_DAC|FE_NOPM)) {
3254 OUTB (nc_ccntl0, np->rv_ccntl0);
3255 OUTB (nc_ccntl1, np->rv_ccntl1);
3256 }
3257
3258 /*
3259 * If phase mismatch handled by scripts (895A/896/1010),
3260 * set PM jump addresses.
3261 */
3262 if (np->features & FE_NOPM) {
3263 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle));
3264 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle));
3265 }
3266
3267 /*
3268 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
3269 * Also set GPIO5 and clear GPIO6 if hardware LED control.
3270 */
3271 if (np->features & FE_LED0)
3272 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01);
3273 else if (np->features & FE_LEDC)
3274 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20);
3275
3276 /*
3277 * enable ints
3278 */
3279 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
3280 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID);
3281
3282 /*
3283 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
3284 * Try to eat the spurious SBMC interrupt that may occur when
3285 * we reset the chip but not the SCSI BUS (at initialization).
3286 */
3287 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
3288 OUTONW (nc_sien, SBMC);
3289 if (reason == 0) {
3290 MDELAY(100);
3291 INW (nc_sist);
3292 }
3293 np->scsi_mode = INB (nc_stest4) & SMODE;
3294 }
3295
3296 /*
3297 * Fill in target structure.
3298 * Reinitialize usrsync.
3299 * Reinitialize usrwide.
3300 * Prepare sync negotiation according to actual SCSI bus mode.
3301 */
3302 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
3303 tcb_p tp = &np->target[i];
3304
3305 tp->to_reset = 0;
3306 tp->head.sval = 0;
3307 tp->head.wval = np->rv_scntl3;
3308 tp->head.uval = 0;
3309
3310 tp->tinfo.current.period = 0;
3311 tp->tinfo.current.offset = 0;
3312 tp->tinfo.current.width = BUS_8_BIT;
3313 tp->tinfo.current.options = 0;
3314 }
3315
3316 /*
3317 * Download SCSI SCRIPTS to on-chip RAM if present,
3318 * and start script processor.
3319 */
3320 if (np->ram_ba) {
3321 if (sym_verbose > 1)
3322 printf ("%s: Downloading SCSI SCRIPTS.\n",
3323 sym_name(np));
3324 if (np->ram_ws == 8192) {
3325 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz);
3326 OUTL (nc_mmws, np->scr_ram_seg);
3327 OUTL (nc_mmrs, np->scr_ram_seg);
3328 OUTL (nc_sfs, np->scr_ram_seg);
3329 phys = SCRIPTB_BA (np, start64);
3330 }
3331 else
3332 phys = SCRIPTA_BA (np, init);
3333 OUTRAM_OFF(0, np->scripta0, np->scripta_sz);
3334 }
3335 else
3336 phys = SCRIPTA_BA (np, init);
3337
3338 np->istat_sem = 0;
3339
3340 OUTL (nc_dsa, np->hcb_ba);
3341 OUTL_DSP (phys);
3342
3343 /*
3344 * Notify the XPT about the RESET condition.
3345 */
3346 if (reason != 0)
3347 xpt_async(AC_BUS_RESET, np->path, NULL);
3348 }
3349
3350 /*
3351 * Get clock factor and sync divisor for a given
3352 * synchronous factor period.
3353 */
3354 static int
3355 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
3356 {
3357 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
3358 int div = np->clock_divn; /* Number of divisors supported */
3359 u32 fak; /* Sync factor in sxfer */
3360 u32 per; /* Period in tenths of ns */
3361 u32 kpc; /* (per * clk) */
3362 int ret;
3363
3364 /*
3365 * Compute the synchronous period in tenths of nano-seconds
3366 */
3367 if (dt && sfac <= 9) per = 125;
3368 else if (sfac <= 10) per = 250;
3369 else if (sfac == 11) per = 303;
3370 else if (sfac == 12) per = 500;
3371 else per = 40 * sfac;
3372 ret = per;
3373
3374 kpc = per * clk;
3375 if (dt)
3376 kpc <<= 1;
3377
3378 /*
3379 * For earliest C10 revision 0, we cannot use extra
3380 * clocks for the setting of the SCSI clocking.
3381 * Note that this limits the lowest sync data transfer
3382 * to 5 Mega-transfers per second and may result in
3383 * using higher clock divisors.
3384 */
3385 #if 1
3386 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
3387 /*
3388 * Look for the lowest clock divisor that allows an
3389 * output speed not faster than the period.
3390 */
3391 while (div > 0) {
3392 --div;
3393 if (kpc > (div_10M[div] << 2)) {
3394 ++div;
3395 break;
3396 }
3397 }
3398 fak = 0; /* No extra clocks */
3399 if (div == np->clock_divn) { /* Are we too fast ? */
3400 ret = -1;
3401 }
3402 *divp = div;
3403 *fakp = fak;
3404 return ret;
3405 }
3406 #endif
3407
3408 /*
3409 * Look for the greatest clock divisor that allows an
3410 * input speed faster than the period.
3411 */
3412 while (div-- > 0)
3413 if (kpc >= (div_10M[div] << 2)) break;
3414
3415 /*
3416 * Calculate the lowest clock factor that allows an output
3417 * speed not faster than the period, and the max output speed.
3418 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
3419 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
3420 */
3421 if (dt) {
3422 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
3423 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
3424 }
3425 else {
3426 fak = (kpc - 1) / div_10M[div] + 1 - 4;
3427 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
3428 }
3429
3430 /*
3431 * Check against our hardware limits, or bugs :).
3432 */
3433 if (fak < 0) {fak = 0; ret = -1;}
3434 if (fak > 2) {fak = 2; ret = -1;}
3435
3436 /*
3437 * Compute and return sync parameters.
3438 */
3439 *divp = div;
3440 *fakp = fak;
3441
3442 return ret;
3443 }
3444
3445 /*
3446 * Tell the SCSI layer about the new transfer parameters.
3447 */
3448 static void
3449 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid)
3450 {
3451 struct ccb_trans_settings cts;
3452 struct cam_path *path;
3453 int sts;
3454 tcb_p tp = &np->target[target];
3455
3456 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target,
3457 CAM_LUN_WILDCARD);
3458 if (sts != CAM_REQ_CMP)
3459 return;
3460
3461 bzero(&cts, sizeof(cts));
3462
3463 #ifdef FreeBSD_New_Tran_Settings
3464 #define cts__scsi (cts.proto_specific.scsi)
3465 #define cts__spi (cts.xport_specific.spi)
3466
3467 cts.type = CTS_TYPE_CURRENT_SETTINGS;
3468 cts.protocol = PROTO_SCSI;
3469 cts.transport = XPORT_SPI;
3470 cts.protocol_version = tp->tinfo.current.scsi_version;
3471 cts.transport_version = tp->tinfo.current.spi_version;
3472
3473 cts__spi.valid = spi_valid;
3474 if (spi_valid & CTS_SPI_VALID_SYNC_RATE)
3475 cts__spi.sync_period = tp->tinfo.current.period;
3476 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET)
3477 cts__spi.sync_offset = tp->tinfo.current.offset;
3478 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH)
3479 cts__spi.bus_width = tp->tinfo.current.width;
3480 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS)
3481 cts__spi.ppr_options = tp->tinfo.current.options;
3482 #undef cts__spi
3483 #undef cts__scsi
3484 #else
3485 cts.valid = spi_valid;
3486 if (spi_valid & CCB_TRANS_SYNC_RATE_VALID)
3487 cts.sync_period = tp->tinfo.current.period;
3488 if (spi_valid & CCB_TRANS_SYNC_OFFSET_VALID)
3489 cts.sync_offset = tp->tinfo.current.offset;
3490 if (spi_valid & CCB_TRANS_BUS_WIDTH_VALID)
3491 cts.bus_width = tp->tinfo.current.width;
3492 #endif
3493 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1);
3494 xpt_async(AC_TRANSFER_NEG, path, &cts);
3495 xpt_free_path(path);
3496 }
3497
3498 #ifdef FreeBSD_New_Tran_Settings
3499 #define SYM_SPI_VALID_WDTR \
3500 CTS_SPI_VALID_BUS_WIDTH | \
3501 CTS_SPI_VALID_SYNC_RATE | \
3502 CTS_SPI_VALID_SYNC_OFFSET
3503 #define SYM_SPI_VALID_SDTR \
3504 CTS_SPI_VALID_SYNC_RATE | \
3505 CTS_SPI_VALID_SYNC_OFFSET
3506 #define SYM_SPI_VALID_PPR \
3507 CTS_SPI_VALID_PPR_OPTIONS | \
3508 CTS_SPI_VALID_BUS_WIDTH | \
3509 CTS_SPI_VALID_SYNC_RATE | \
3510 CTS_SPI_VALID_SYNC_OFFSET
3511 #else
3512 #define SYM_SPI_VALID_WDTR \
3513 CCB_TRANS_BUS_WIDTH_VALID | \
3514 CCB_TRANS_SYNC_RATE_VALID | \
3515 CCB_TRANS_SYNC_OFFSET_VALID
3516 #define SYM_SPI_VALID_SDTR \
3517 CCB_TRANS_SYNC_RATE_VALID | \
3518 CCB_TRANS_SYNC_OFFSET_VALID
3519 #define SYM_SPI_VALID_PPR \
3520 CCB_TRANS_BUS_WIDTH_VALID | \
3521 CCB_TRANS_SYNC_RATE_VALID | \
3522 CCB_TRANS_SYNC_OFFSET_VALID
3523 #endif
3524
3525 /*
3526 * We received a WDTR.
3527 * Let everything be aware of the changes.
3528 */
3529 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide)
3530 {
3531 tcb_p tp = &np->target[cp->target];
3532
3533 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0);
3534
3535 /*
3536 * Tell the SCSI layer about the new transfer parameters.
3537 */
3538 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3539 tp->tinfo.current.offset = 0;
3540 tp->tinfo.current.period = 0;
3541 tp->tinfo.current.options = 0;
3542
3543 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR);
3544 }
3545
3546 /*
3547 * We received a SDTR.
3548 * Let everything be aware of the changes.
3549 */
3550 static void
3551 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak)
3552 {
3553 tcb_p tp = &np->target[cp->target];
3554 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0;
3555
3556 sym_settrans(np, cp, 0, ofs, per, wide, div, fak);
3557
3558 /*
3559 * Tell the SCSI layer about the new transfer parameters.
3560 */
3561 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3562 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3563 tp->tinfo.goal.options = tp->tinfo.current.options = 0;
3564
3565 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR);
3566 }
3567
3568 /*
3569 * We received a PPR.
3570 * Let everything be aware of the changes.
3571 */
3572 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3573 u_char per, u_char wide, u_char div, u_char fak)
3574 {
3575 tcb_p tp = &np->target[cp->target];
3576
3577 sym_settrans(np, cp, dt, ofs, per, wide, div, fak);
3578
3579 /*
3580 * Tell the SCSI layer about the new transfer parameters.
3581 */
3582 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3583 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3584 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3585 tp->tinfo.goal.options = tp->tinfo.current.options = dt;
3586
3587 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR);
3588 }
3589
3590 /*
3591 * Switch trans mode for current job and it's target.
3592 */
3593 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3594 u_char per, u_char wide, u_char div, u_char fak)
3595 {
3596 SYM_QUEHEAD *qp;
3597 union ccb *ccb;
3598 tcb_p tp;
3599 u_char target = INB (nc_sdid) & 0x0f;
3600 u_char sval, wval, uval;
3601
3602 assert (cp);
3603 if (!cp) return;
3604 ccb = cp->cam_ccb;
3605 assert (ccb);
3606 if (!ccb) return;
3607 assert (target == (cp->target & 0xf));
3608 tp = &np->target[target];
3609
3610 sval = tp->head.sval;
3611 wval = tp->head.wval;
3612 uval = tp->head.uval;
3613
3614 #if 0
3615 printf("XXXX sval=%x wval=%x uval=%x (%x)\n",
3616 sval, wval, uval, np->rv_scntl3);
3617 #endif
3618 /*
3619 * Set the offset.
3620 */
3621 if (!(np->features & FE_C10))
3622 sval = (sval & ~0x1f) | ofs;
3623 else
3624 sval = (sval & ~0x3f) | ofs;
3625
3626 /*
3627 * Set the sync divisor and extra clock factor.
3628 */
3629 if (ofs != 0) {
3630 wval = (wval & ~0x70) | ((div+1) << 4);
3631 if (!(np->features & FE_C10))
3632 sval = (sval & ~0xe0) | (fak << 5);
3633 else {
3634 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
3635 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
3636 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
3637 }
3638 }
3639
3640 /*
3641 * Set the bus width.
3642 */
3643 wval = wval & ~EWS;
3644 if (wide != 0)
3645 wval |= EWS;
3646
3647 /*
3648 * Set misc. ultra enable bits.
3649 */
3650 if (np->features & FE_C10) {
3651 uval = uval & ~(U3EN|AIPCKEN);
3652 if (dt) {
3653 assert(np->features & FE_U3EN);
3654 uval |= U3EN;
3655 }
3656 }
3657 else {
3658 wval = wval & ~ULTRA;
3659 if (per <= 12) wval |= ULTRA;
3660 }
3661
3662 /*
3663 * Stop there if sync parameters are unchanged.
3664 */
3665 if (tp->head.sval == sval &&
3666 tp->head.wval == wval &&
3667 tp->head.uval == uval)
3668 return;
3669 tp->head.sval = sval;
3670 tp->head.wval = wval;
3671 tp->head.uval = uval;
3672
3673 /*
3674 * Disable extended Sreq/Sack filtering if per < 50.
3675 * Not supported on the C1010.
3676 */
3677 if (per < 50 && !(np->features & FE_C10))
3678 OUTOFFB (nc_stest2, EXT);
3679
3680 /*
3681 * set actual value and sync_status
3682 */
3683 OUTB (nc_sxfer, tp->head.sval);
3684 OUTB (nc_scntl3, tp->head.wval);
3685
3686 if (np->features & FE_C10) {
3687 OUTB (nc_scntl4, tp->head.uval);
3688 }
3689
3690 /*
3691 * patch ALL busy ccbs of this target.
3692 */
3693 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3694 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3695 if (cp->target != target)
3696 continue;
3697 cp->phys.select.sel_scntl3 = tp->head.wval;
3698 cp->phys.select.sel_sxfer = tp->head.sval;
3699 if (np->features & FE_C10) {
3700 cp->phys.select.sel_scntl4 = tp->head.uval;
3701 }
3702 }
3703 }
3704
3705 /*
3706 * log message for real hard errors
3707 *
3708 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc).
3709 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
3710 *
3711 * exception register:
3712 * ds: dstat
3713 * si: sist
3714 *
3715 * SCSI bus lines:
3716 * so: control lines as driven by chip.
3717 * si: control lines as seen by chip.
3718 * sd: scsi data lines as seen by chip.
3719 *
3720 * wide/fastmode:
3721 * sxfer: (see the manual)
3722 * scntl3: (see the manual)
3723 *
3724 * current script command:
3725 * dsp: script address (relative to start of script).
3726 * dbc: first word of script command.
3727 *
3728 * First 24 register of the chip:
3729 * r0..rf
3730 */
3731 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat)
3732 {
3733 u32 dsp;
3734 int script_ofs;
3735 int script_size;
3736 char *script_name;
3737 u_char *script_base;
3738 int i;
3739
3740 dsp = INL (nc_dsp);
3741
3742 if (dsp > np->scripta_ba &&
3743 dsp <= np->scripta_ba + np->scripta_sz) {
3744 script_ofs = dsp - np->scripta_ba;
3745 script_size = np->scripta_sz;
3746 script_base = (u_char *) np->scripta0;
3747 script_name = "scripta";
3748 }
3749 else if (np->scriptb_ba < dsp &&
3750 dsp <= np->scriptb_ba + np->scriptb_sz) {
3751 script_ofs = dsp - np->scriptb_ba;
3752 script_size = np->scriptb_sz;
3753 script_base = (u_char *) np->scriptb0;
3754 script_name = "scriptb";
3755 } else {
3756 script_ofs = dsp;
3757 script_size = 0;
3758 script_base = 0;
3759 script_name = "mem";
3760 }
3761
3762 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
3763 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
3764 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl),
3765 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer),
3766 (unsigned)INB (nc_scntl3), script_name, script_ofs,
3767 (unsigned)INL (nc_dbc));
3768
3769 if (((script_ofs & 3) == 0) &&
3770 (unsigned)script_ofs < script_size) {
3771 printf ("%s: script cmd = %08x\n", sym_name(np),
3772 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
3773 }
3774
3775 printf ("%s: regdump:", sym_name(np));
3776 for (i=0; i<24;i++)
3777 printf (" %02x", (unsigned)INB_OFF(i));
3778 printf (".\n");
3779
3780 /*
3781 * PCI BUS error, read the PCI ststus register.
3782 */
3783 if (dstat & (MDPE|BF)) {
3784 u_short pci_sts;
3785 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2);
3786 if (pci_sts & 0xf900) {
3787 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2);
3788 printf("%s: PCI STATUS = 0x%04x\n",
3789 sym_name(np), pci_sts & 0xf900);
3790 }
3791 }
3792 }
3793
3794 /*
3795 * chip interrupt handler
3796 *
3797 * In normal situations, interrupt conditions occur one at
3798 * a time. But when something bad happens on the SCSI BUS,
3799 * the chip may raise several interrupt flags before
3800 * stopping and interrupting the CPU. The additionnal
3801 * interrupt flags are stacked in some extra registers
3802 * after the SIP and/or DIP flag has been raised in the
3803 * ISTAT. After the CPU has read the interrupt condition
3804 * flag from SIST or DSTAT, the chip unstacks the other
3805 * interrupt flags and sets the corresponding bits in
3806 * SIST or DSTAT. Since the chip starts stacking once the
3807 * SIP or DIP flag is set, there is a small window of time
3808 * where the stacking does not occur.
3809 *
3810 * Typically, multiple interrupt conditions may happen in
3811 * the following situations:
3812 *
3813 * - SCSI parity error + Phase mismatch (PAR|MA)
3814 * When a parity error is detected in input phase
3815 * and the device switches to msg-in phase inside a
3816 * block MOV.
3817 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
3818 * When a stupid device does not want to handle the
3819 * recovery of an SCSI parity error.
3820 * - Some combinations of STO, PAR, UDC, ...
3821 * When using non compliant SCSI stuff, when user is
3822 * doing non compliant hot tampering on the BUS, when
3823 * something really bad happens to a device, etc ...
3824 *
3825 * The heuristic suggested by SYMBIOS to handle
3826 * multiple interrupts is to try unstacking all
3827 * interrupts conditions and to handle them on some
3828 * priority based on error severity.
3829 * This will work when the unstacking has been
3830 * successful, but we cannot be 100 % sure of that,
3831 * since the CPU may have been faster to unstack than
3832 * the chip is able to stack. Hmmm ... But it seems that
3833 * such a situation is very unlikely to happen.
3834 *
3835 * If this happen, for example STO caught by the CPU
3836 * then UDC happenning before the CPU have restarted
3837 * the SCRIPTS, the driver may wrongly complete the
3838 * same command on UDC, since the SCRIPTS didn't restart
3839 * and the DSA still points to the same command.
3840 * We avoid this situation by setting the DSA to an
3841 * invalid value when the CCB is completed and before
3842 * restarting the SCRIPTS.
3843 *
3844 * Another issue is that we need some section of our
3845 * recovery procedures to be somehow uninterruptible but
3846 * the SCRIPTS processor does not provides such a
3847 * feature. For this reason, we handle recovery preferently
3848 * from the C code and check against some SCRIPTS critical
3849 * sections from the C code.
3850 *
3851 * Hopefully, the interrupt handling of the driver is now
3852 * able to resist to weird BUS error conditions, but donnot
3853 * ask me for any guarantee that it will never fail. :-)
3854 * Use at your own decision and risk.
3855 */
3856
3857 static void sym_intr1 (hcb_p np)
3858 {
3859 u_char istat, istatc;
3860 u_char dstat;
3861 u_short sist;
3862
3863 /*
3864 * interrupt on the fly ?
3865 *
3866 * A `dummy read' is needed to ensure that the
3867 * clear of the INTF flag reaches the device
3868 * before the scanning of the DONE queue.
3869 */
3870 istat = INB (nc_istat);
3871 if (istat & INTF) {
3872 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem);
3873 istat = INB (nc_istat); /* DUMMY READ */
3874 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F ");
3875 (void)sym_wakeup_done (np);
3876 };
3877
3878 if (!(istat & (SIP|DIP)))
3879 return;
3880
3881 #if 0 /* We should never get this one */
3882 if (istat & CABRT)
3883 OUTB (nc_istat, CABRT);
3884 #endif
3885
3886 /*
3887 * PAR and MA interrupts may occur at the same time,
3888 * and we need to know of both in order to handle
3889 * this situation properly. We try to unstack SCSI
3890 * interrupts for that reason. BTW, I dislike a LOT
3891 * such a loop inside the interrupt routine.
3892 * Even if DMA interrupt stacking is very unlikely to
3893 * happen, we also try unstacking these ones, since
3894 * this has no performance impact.
3895 */
3896 sist = 0;
3897 dstat = 0;
3898 istatc = istat;
3899 do {
3900 if (istatc & SIP)
3901 sist |= INW (nc_sist);
3902 if (istatc & DIP)
3903 dstat |= INB (nc_dstat);
3904 istatc = INB (nc_istat);
3905 istat |= istatc;
3906 } while (istatc & (SIP|DIP));
3907
3908 if (DEBUG_FLAGS & DEBUG_TINY)
3909 printf ("<%d|%x:%x|%x:%x>",
3910 (int)INB(nc_scr0),
3911 dstat,sist,
3912 (unsigned)INL(nc_dsp),
3913 (unsigned)INL(nc_dbc));
3914 /*
3915 * On paper, a memory barrier may be needed here.
3916 * And since we are paranoid ... :)
3917 */
3918 MEMORY_BARRIER();
3919
3920 /*
3921 * First, interrupts we want to service cleanly.
3922 *
3923 * Phase mismatch (MA) is the most frequent interrupt
3924 * for chip earlier than the 896 and so we have to service
3925 * it as quickly as possible.
3926 * A SCSI parity error (PAR) may be combined with a phase
3927 * mismatch condition (MA).
3928 * Programmed interrupts (SIR) are used to call the C code
3929 * from SCRIPTS.
3930 * The single step interrupt (SSI) is not used in this
3931 * driver.
3932 */
3933 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) &&
3934 !(dstat & (MDPE|BF|ABRT|IID))) {
3935 if (sist & PAR) sym_int_par (np, sist);
3936 else if (sist & MA) sym_int_ma (np);
3937 else if (dstat & SIR) sym_int_sir (np);
3938 else if (dstat & SSI) OUTONB_STD ();
3939 else goto unknown_int;
3940 return;
3941 };
3942
3943 /*
3944 * Now, interrupts that donnot happen in normal
3945 * situations and that we may need to recover from.
3946 *
3947 * On SCSI RESET (RST), we reset everything.
3948 * On SCSI BUS MODE CHANGE (SBMC), we complete all
3949 * active CCBs with RESET status, prepare all devices
3950 * for negotiating again and restart the SCRIPTS.
3951 * On STO and UDC, we complete the CCB with the corres-
3952 * ponding status and restart the SCRIPTS.
3953 */
3954 if (sist & RST) {
3955 xpt_print_path(np->path);
3956 printf("SCSI BUS reset detected.\n");
3957 sym_init (np, 1);
3958 return;
3959 };
3960
3961 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
3962 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
3963
3964 if (!(sist & (GEN|HTH|SGE)) &&
3965 !(dstat & (MDPE|BF|ABRT|IID))) {
3966 if (sist & SBMC) sym_int_sbmc (np);
3967 else if (sist & STO) sym_int_sto (np);
3968 else if (sist & UDC) sym_int_udc (np);
3969 else goto unknown_int;
3970 return;
3971 };
3972
3973 /*
3974 * Now, interrupts we are not able to recover cleanly.
3975 *
3976 * Log message for hard errors.
3977 * Reset everything.
3978 */
3979
3980 sym_log_hard_error(np, sist, dstat);
3981
3982 if ((sist & (GEN|HTH|SGE)) ||
3983 (dstat & (MDPE|BF|ABRT|IID))) {
3984 sym_start_reset(np);
3985 return;
3986 };
3987
3988 unknown_int:
3989 /*
3990 * We just miss the cause of the interrupt. :(
3991 * Print a message. The timeout will do the real work.
3992 */
3993 printf( "%s: unknown interrupt(s) ignored, "
3994 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n",
3995 sym_name(np), istat, dstat, sist);
3996 }
3997
3998 static void sym_intr(void *arg)
3999 {
4000 if (DEBUG_FLAGS & DEBUG_TINY) printf ("[");
4001 sym_intr1((hcb_p) arg);
4002 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]");
4003 }
4004
4005 static void sym_poll(struct cam_sim *sim)
4006 {
4007 int s = splcam();
4008 sym_intr(cam_sim_softc(sim));
4009 splx(s);
4010 }
4011
4012
4013 /*
4014 * generic recovery from scsi interrupt
4015 *
4016 * The doc says that when the chip gets an SCSI interrupt,
4017 * it tries to stop in an orderly fashion, by completing
4018 * an instruction fetch that had started or by flushing
4019 * the DMA fifo for a write to memory that was executing.
4020 * Such a fashion is not enough to know if the instruction
4021 * that was just before the current DSP value has been
4022 * executed or not.
4023 *
4024 * There are some small SCRIPTS sections that deal with
4025 * the start queue and the done queue that may break any
4026 * assomption from the C code if we are interrupted
4027 * inside, so we reset if this happens. Btw, since these
4028 * SCRIPTS sections are executed while the SCRIPTS hasn't
4029 * started SCSI operations, it is very unlikely to happen.
4030 *
4031 * All the driver data structures are supposed to be
4032 * allocated from the same 4 GB memory window, so there
4033 * is a 1 to 1 relationship between DSA and driver data
4034 * structures. Since we are careful :) to invalidate the
4035 * DSA when we complete a command or when the SCRIPTS
4036 * pushes a DSA into a queue, we can trust it when it
4037 * points to a CCB.
4038 */
4039 static void sym_recover_scsi_int (hcb_p np, u_char hsts)
4040 {
4041 u32 dsp = INL (nc_dsp);
4042 u32 dsa = INL (nc_dsa);
4043 ccb_p cp = sym_ccb_from_dsa(np, dsa);
4044
4045 /*
4046 * If we haven't been interrupted inside the SCRIPTS
4047 * critical pathes, we can safely restart the SCRIPTS
4048 * and trust the DSA value if it matches a CCB.
4049 */
4050 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) &&
4051 dsp < SCRIPTA_BA (np, getjob_end) + 1)) &&
4052 (!(dsp > SCRIPTA_BA (np, ungetjob) &&
4053 dsp < SCRIPTA_BA (np, reselect) + 1)) &&
4054 (!(dsp > SCRIPTB_BA (np, sel_for_abort) &&
4055 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) &&
4056 (!(dsp > SCRIPTA_BA (np, done) &&
4057 dsp < SCRIPTA_BA (np, done_end) + 1))) {
4058 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
4059 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
4060 /*
4061 * If we have a CCB, let the SCRIPTS call us back for
4062 * the handling of the error with SCRATCHA filled with
4063 * STARTPOS. This way, we will be able to freeze the
4064 * device queue and requeue awaiting IOs.
4065 */
4066 if (cp) {
4067 cp->host_status = hsts;
4068 OUTL_DSP (SCRIPTA_BA (np, complete_error));
4069 }
4070 /*
4071 * Otherwise just restart the SCRIPTS.
4072 */
4073 else {
4074 OUTL (nc_dsa, 0xffffff);
4075 OUTL_DSP (SCRIPTA_BA (np, start));
4076 }
4077 }
4078 else
4079 goto reset_all;
4080
4081 return;
4082
4083 reset_all:
4084 sym_start_reset(np);
4085 }
4086
4087 /*
4088 * chip exception handler for selection timeout
4089 */
4090 static void sym_int_sto (hcb_p np)
4091 {
4092 u32 dsp = INL (nc_dsp);
4093
4094 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T");
4095
4096 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8)
4097 sym_recover_scsi_int(np, HS_SEL_TIMEOUT);
4098 else
4099 sym_start_reset(np);
4100 }
4101
4102 /*
4103 * chip exception handler for unexpected disconnect
4104 */
4105 static void sym_int_udc (hcb_p np)
4106 {
4107 printf ("%s: unexpected disconnect\n", sym_name(np));
4108 sym_recover_scsi_int(np, HS_UNEXPECTED);
4109 }
4110
4111 /*
4112 * chip exception handler for SCSI bus mode change
4113 *
4114 * spi2-r12 11.2.3 says a transceiver mode change must
4115 * generate a reset event and a device that detects a reset
4116 * event shall initiate a hard reset. It says also that a
4117 * device that detects a mode change shall set data transfer
4118 * mode to eight bit asynchronous, etc...
4119 * So, just reinitializing all except chip should be enough.
4120 */
4121 static void sym_int_sbmc (hcb_p np)
4122 {
4123 u_char scsi_mode = INB (nc_stest4) & SMODE;
4124
4125 /*
4126 * Notify user.
4127 */
4128 xpt_print_path(np->path);
4129 printf("SCSI BUS mode change from %s to %s.\n",
4130 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode));
4131
4132 /*
4133 * Should suspend command processing for a few seconds and
4134 * reinitialize all except the chip.
4135 */
4136 sym_init (np, 2);
4137 }
4138
4139 /*
4140 * chip exception handler for SCSI parity error.
4141 *
4142 * When the chip detects a SCSI parity error and is
4143 * currently executing a (CH)MOV instruction, it does
4144 * not interrupt immediately, but tries to finish the
4145 * transfer of the current scatter entry before
4146 * interrupting. The following situations may occur:
4147 *
4148 * - The complete scatter entry has been transferred
4149 * without the device having changed phase.
4150 * The chip will then interrupt with the DSP pointing
4151 * to the instruction that follows the MOV.
4152 *
4153 * - A phase mismatch occurs before the MOV finished
4154 * and phase errors are to be handled by the C code.
4155 * The chip will then interrupt with both PAR and MA
4156 * conditions set.
4157 *
4158 * - A phase mismatch occurs before the MOV finished and
4159 * phase errors are to be handled by SCRIPTS.
4160 * The chip will load the DSP with the phase mismatch
4161 * JUMP address and interrupt the host processor.
4162 */
4163 static void sym_int_par (hcb_p np, u_short sist)
4164 {
4165 u_char hsts = INB (HS_PRT);
4166 u32 dsp = INL (nc_dsp);
4167 u32 dbc = INL (nc_dbc);
4168 u32 dsa = INL (nc_dsa);
4169 u_char sbcl = INB (nc_sbcl);
4170 u_char cmd = dbc >> 24;
4171 int phase = cmd & 7;
4172 ccb_p cp = sym_ccb_from_dsa(np, dsa);
4173
4174 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n",
4175 sym_name(np), hsts, dbc, sbcl);
4176
4177 /*
4178 * Check that the chip is connected to the SCSI BUS.
4179 */
4180 if (!(INB (nc_scntl1) & ISCON)) {
4181 sym_recover_scsi_int(np, HS_UNEXPECTED);
4182 return;
4183 }
4184
4185 /*
4186 * If the nexus is not clearly identified, reset the bus.
4187 * We will try to do better later.
4188 */
4189 if (!cp)
4190 goto reset_all;
4191
4192 /*
4193 * Check instruction was a MOV, direction was INPUT and
4194 * ATN is asserted.
4195 */
4196 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
4197 goto reset_all;
4198
4199 /*
4200 * Keep track of the parity error.
4201 */
4202 OUTONB (HF_PRT, HF_EXT_ERR);
4203 cp->xerr_status |= XE_PARITY_ERR;
4204
4205 /*
4206 * Prepare the message to send to the device.
4207 */
4208 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
4209
4210 /*
4211 * If the old phase was DATA IN phase, we have to deal with
4212 * the 3 situations described above.
4213 * For other input phases (MSG IN and STATUS), the device
4214 * must resend the whole thing that failed parity checking
4215 * or signal error. So, jumping to dispatcher should be OK.
4216 */
4217 if (phase == 1 || phase == 5) {
4218 /* Phase mismatch handled by SCRIPTS */
4219 if (dsp == SCRIPTB_BA (np, pm_handle))
4220 OUTL_DSP (dsp);
4221 /* Phase mismatch handled by the C code */
4222 else if (sist & MA)
4223 sym_int_ma (np);
4224 /* No phase mismatch occurred */
4225 else {
4226 OUTL (nc_temp, dsp);
4227 OUTL_DSP (SCRIPTA_BA (np, dispatch));
4228 }
4229 }
4230 else
4231 OUTL_DSP (SCRIPTA_BA (np, clrack));
4232 return;
4233
4234 reset_all:
4235 sym_start_reset(np);
4236 }
4237
4238 /*
4239 * chip exception handler for phase errors.
4240 *
4241 * We have to construct a new transfer descriptor,
4242 * to transfer the rest of the current block.
4243 */
4244 static void sym_int_ma (hcb_p np)
4245 {
4246 u32 dbc;
4247 u32 rest;
4248 u32 dsp;
4249 u32 dsa;
4250 u32 nxtdsp;
4251 u32 *vdsp;
4252 u32 oadr, olen;
4253 u32 *tblp;
4254 u32 newcmd;
4255 u_int delta;
4256 u_char cmd;
4257 u_char hflags, hflags0;
4258 struct sym_pmc *pm;
4259 ccb_p cp;
4260
4261 dsp = INL (nc_dsp);
4262 dbc = INL (nc_dbc);
4263 dsa = INL (nc_dsa);
4264
4265 cmd = dbc >> 24;
4266 rest = dbc & 0xffffff;
4267 delta = 0;
4268
4269 /*
4270 * locate matching cp if any.
4271 */
4272 cp = sym_ccb_from_dsa(np, dsa);
4273
4274 /*
4275 * Donnot take into account dma fifo and various buffers in
4276 * INPUT phase since the chip flushes everything before
4277 * raising the MA interrupt for interrupted INPUT phases.
4278 * For DATA IN phase, we will check for the SWIDE later.
4279 */
4280 if ((cmd & 7) != 1 && (cmd & 7) != 5) {
4281 u_char ss0, ss2;
4282
4283 if (np->features & FE_DFBC)
4284 delta = INW (nc_dfbc);
4285 else {
4286 u32 dfifo;
4287
4288 /*
4289 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership.
4290 */
4291 dfifo = INL(nc_dfifo);
4292
4293 /*
4294 * Calculate remaining bytes in DMA fifo.
4295 * (CTEST5 = dfifo >> 16)
4296 */
4297 if (dfifo & (DFS << 16))
4298 delta = ((((dfifo >> 8) & 0x300) |
4299 (dfifo & 0xff)) - rest) & 0x3ff;
4300 else
4301 delta = ((dfifo & 0xff) - rest) & 0x7f;
4302 }
4303
4304 /*
4305 * The data in the dma fifo has not been transfered to
4306 * the target -> add the amount to the rest
4307 * and clear the data.
4308 * Check the sstat2 register in case of wide transfer.
4309 */
4310 rest += delta;
4311 ss0 = INB (nc_sstat0);
4312 if (ss0 & OLF) rest++;
4313 if (!(np->features & FE_C10))
4314 if (ss0 & ORF) rest++;
4315 if (cp && (cp->phys.select.sel_scntl3 & EWS)) {
4316 ss2 = INB (nc_sstat2);
4317 if (ss2 & OLF1) rest++;
4318 if (!(np->features & FE_C10))
4319 if (ss2 & ORF1) rest++;
4320 };
4321
4322 /*
4323 * Clear fifos.
4324 */
4325 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */
4326 OUTB (nc_stest3, TE|CSF); /* scsi fifo */
4327 }
4328
4329 /*
4330 * log the information
4331 */
4332 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
4333 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7,
4334 (unsigned) rest, (unsigned) delta);
4335
4336 /*
4337 * try to find the interrupted script command,
4338 * and the address at which to continue.
4339 */
4340 vdsp = 0;
4341 nxtdsp = 0;
4342 if (dsp > np->scripta_ba &&
4343 dsp <= np->scripta_ba + np->scripta_sz) {
4344 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8));
4345 nxtdsp = dsp;
4346 }
4347 else if (dsp > np->scriptb_ba &&
4348 dsp <= np->scriptb_ba + np->scriptb_sz) {
4349 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8));
4350 nxtdsp = dsp;
4351 }
4352
4353 /*
4354 * log the information
4355 */
4356 if (DEBUG_FLAGS & DEBUG_PHASE) {
4357 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
4358 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd);
4359 };
4360
4361 if (!vdsp) {
4362 printf ("%s: interrupted SCRIPT address not found.\n",
4363 sym_name (np));
4364 goto reset_all;
4365 }
4366
4367 if (!cp) {
4368 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n",
4369 sym_name (np));
4370 goto reset_all;
4371 }
4372
4373 /*
4374 * get old startaddress and old length.
4375 */
4376 oadr = scr_to_cpu(vdsp[1]);
4377
4378 if (cmd & 0x10) { /* Table indirect */
4379 tblp = (u32 *) ((char*) &cp->phys + oadr);
4380 olen = scr_to_cpu(tblp[0]);
4381 oadr = scr_to_cpu(tblp[1]);
4382 } else {
4383 tblp = (u32 *) 0;
4384 olen = scr_to_cpu(vdsp[0]) & 0xffffff;
4385 };
4386
4387 if (DEBUG_FLAGS & DEBUG_PHASE) {
4388 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
4389 (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
4390 tblp,
4391 (unsigned) olen,
4392 (unsigned) oadr);
4393 };
4394
4395 /*
4396 * check cmd against assumed interrupted script command.
4397 * If dt data phase, the MOVE instruction hasn't bit 4 of
4398 * the phase.
4399 */
4400 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) {
4401 PRINT_ADDR(cp);
4402 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
4403 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24);
4404
4405 goto reset_all;
4406 };
4407
4408 /*
4409 * if old phase not dataphase, leave here.
4410 */
4411 if (cmd & 2) {
4412 PRINT_ADDR(cp);
4413 printf ("phase change %x-%x %d@%08x resid=%d.\n",
4414 cmd&7, INB(nc_sbcl)&7, (unsigned)olen,
4415 (unsigned)oadr, (unsigned)rest);
4416 goto unexpected_phase;
4417 };
4418
4419 /*
4420 * Choose the correct PM save area.
4421 *
4422 * Look at the PM_SAVE SCRIPT if you want to understand
4423 * this stuff. The equivalent code is implemented in
4424 * SCRIPTS for the 895A, 896 and 1010 that are able to
4425 * handle PM from the SCRIPTS processor.
4426 */
4427 hflags0 = INB (HF_PRT);
4428 hflags = hflags0;
4429
4430 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) {
4431 if (hflags & HF_IN_PM0)
4432 nxtdsp = scr_to_cpu(cp->phys.pm0.ret);
4433 else if (hflags & HF_IN_PM1)
4434 nxtdsp = scr_to_cpu(cp->phys.pm1.ret);
4435
4436 if (hflags & HF_DP_SAVED)
4437 hflags ^= HF_ACT_PM;
4438 }
4439
4440 if (!(hflags & HF_ACT_PM)) {
4441 pm = &cp->phys.pm0;
4442 newcmd = SCRIPTA_BA (np, pm0_data);
4443 }
4444 else {
4445 pm = &cp->phys.pm1;
4446 newcmd = SCRIPTA_BA (np, pm1_data);
4447 }
4448
4449 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED);
4450 if (hflags != hflags0)
4451 OUTB (HF_PRT, hflags);
4452
4453 /*
4454 * fillin the phase mismatch context
4455 */
4456 pm->sg.addr = cpu_to_scr(oadr + olen - rest);
4457 pm->sg.size = cpu_to_scr(rest);
4458 pm->ret = cpu_to_scr(nxtdsp);
4459
4460 /*
4461 * If we have a SWIDE,
4462 * - prepare the address to write the SWIDE from SCRIPTS,
4463 * - compute the SCRIPTS address to restart from,
4464 * - move current data pointer context by one byte.
4465 */
4466 nxtdsp = SCRIPTA_BA (np, dispatch);
4467 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) &&
4468 (INB (nc_scntl2) & WSR)) {
4469 u32 tmp;
4470
4471 /*
4472 * Set up the table indirect for the MOVE
4473 * of the residual byte and adjust the data
4474 * pointer context.
4475 */
4476 tmp = scr_to_cpu(pm->sg.addr);
4477 cp->phys.wresid.addr = cpu_to_scr(tmp);
4478 pm->sg.addr = cpu_to_scr(tmp + 1);
4479 tmp = scr_to_cpu(pm->sg.size);
4480 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1);
4481 pm->sg.size = cpu_to_scr(tmp - 1);
4482
4483 /*
4484 * If only the residual byte is to be moved,
4485 * no PM context is needed.
4486 */
4487 if ((tmp&0xffffff) == 1)
4488 newcmd = pm->ret;
4489
4490 /*
4491 * Prepare the address of SCRIPTS that will
4492 * move the residual byte to memory.
4493 */
4494 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper);
4495 }
4496
4497 if (DEBUG_FLAGS & DEBUG_PHASE) {
4498 PRINT_ADDR(cp);
4499 printf ("PM %x %x %x / %x %x %x.\n",
4500 hflags0, hflags, newcmd,
4501 (unsigned)scr_to_cpu(pm->sg.addr),
4502 (unsigned)scr_to_cpu(pm->sg.size),
4503 (unsigned)scr_to_cpu(pm->ret));
4504 }
4505
4506 /*
4507 * Restart the SCRIPTS processor.
4508 */
4509 OUTL (nc_temp, newcmd);
4510 OUTL_DSP (nxtdsp);
4511 return;
4512
4513 /*
4514 * Unexpected phase changes that occurs when the current phase
4515 * is not a DATA IN or DATA OUT phase are due to error conditions.
4516 * Such event may only happen when the SCRIPTS is using a
4517 * multibyte SCSI MOVE.
4518 *
4519 * Phase change Some possible cause
4520 *
4521 * COMMAND --> MSG IN SCSI parity error detected by target.
4522 * COMMAND --> STATUS Bad command or refused by target.
4523 * MSG OUT --> MSG IN Message rejected by target.
4524 * MSG OUT --> COMMAND Bogus target that discards extended
4525 * negotiation messages.
4526 *
4527 * The code below does not care of the new phase and so
4528 * trusts the target. Why to annoy it ?
4529 * If the interrupted phase is COMMAND phase, we restart at
4530 * dispatcher.
4531 * If a target does not get all the messages after selection,
4532 * the code assumes blindly that the target discards extended
4533 * messages and clears the negotiation status.
4534 * If the target does not want all our response to negotiation,
4535 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
4536 * bloat for such a should_not_happen situation).
4537 * In all other situation, we reset the BUS.
4538 * Are these assumptions reasonnable ? (Wait and see ...)
4539 */
4540 unexpected_phase:
4541 dsp -= 8;
4542 nxtdsp = 0;
4543
4544 switch (cmd & 7) {
4545 case 2: /* COMMAND phase */
4546 nxtdsp = SCRIPTA_BA (np, dispatch);
4547 break;
4548 #if 0
4549 case 3: /* STATUS phase */
4550 nxtdsp = SCRIPTA_BA (np, dispatch);
4551 break;
4552 #endif
4553 case 6: /* MSG OUT phase */
4554 /*
4555 * If the device may want to use untagged when we want
4556 * tagged, we prepare an IDENTIFY without disc. granted,
4557 * since we will not be able to handle reselect.
4558 * Otherwise, we just don't care.
4559 */
4560 if (dsp == SCRIPTA_BA (np, send_ident)) {
4561 if (cp->tag != NO_TAG && olen - rest <= 3) {
4562 cp->host_status = HS_BUSY;
4563 np->msgout[0] = M_IDENTIFY | cp->lun;
4564 nxtdsp = SCRIPTB_BA (np, ident_break_atn);
4565 }
4566 else
4567 nxtdsp = SCRIPTB_BA (np, ident_break);
4568 }
4569 else if (dsp == SCRIPTB_BA (np, send_wdtr) ||
4570 dsp == SCRIPTB_BA (np, send_sdtr) ||
4571 dsp == SCRIPTB_BA (np, send_ppr)) {
4572 nxtdsp = SCRIPTB_BA (np, nego_bad_phase);
4573 }
4574 break;
4575 #if 0
4576 case 7: /* MSG IN phase */
4577 nxtdsp = SCRIPTA_BA (np, clrack);
4578 break;
4579 #endif
4580 }
4581
4582 if (nxtdsp) {
4583 OUTL_DSP (nxtdsp);
4584 return;
4585 }
4586
4587 reset_all:
4588 sym_start_reset(np);
4589 }
4590
4591 /*
4592 * Dequeue from the START queue all CCBs that match
4593 * a given target/lun/task condition (-1 means all),
4594 * and move them from the BUSY queue to the COMP queue
4595 * with CAM_REQUEUE_REQ status condition.
4596 * This function is used during error handling/recovery.
4597 * It is called with SCRIPTS not running.
4598 */
4599 static int
4600 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task)
4601 {
4602 int j;
4603 ccb_p cp;
4604
4605 /*
4606 * Make sure the starting index is within range.
4607 */
4608 assert((i >= 0) && (i < 2*MAX_QUEUE));
4609
4610 /*
4611 * Walk until end of START queue and dequeue every job
4612 * that matches the target/lun/task condition.
4613 */
4614 j = i;
4615 while (i != np->squeueput) {
4616 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i]));
4617 assert(cp);
4618 #ifdef SYM_CONF_IARB_SUPPORT
4619 /* Forget hints for IARB, they may be no longer relevant */
4620 cp->host_flags &= ~HF_HINT_IARB;
4621 #endif
4622 if ((target == -1 || cp->target == target) &&
4623 (lun == -1 || cp->lun == lun) &&
4624 (task == -1 || cp->tag == task)) {
4625 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ);
4626 sym_remque(&cp->link_ccbq);
4627 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
4628 }
4629 else {
4630 if (i != j)
4631 np->squeue[j] = np->squeue[i];
4632 if ((j += 2) >= MAX_QUEUE*2) j = 0;
4633 }
4634 if ((i += 2) >= MAX_QUEUE*2) i = 0;
4635 }
4636 if (i != j) /* Copy back the idle task if needed */
4637 np->squeue[j] = np->squeue[i];
4638 np->squeueput = j; /* Update our current start queue pointer */
4639
4640 return (i - j) / 2;
4641 }
4642
4643 /*
4644 * Complete all CCBs queued to the COMP queue.
4645 *
4646 * These CCBs are assumed:
4647 * - Not to be referenced either by devices or
4648 * SCRIPTS-related queues and datas.
4649 * - To have to be completed with an error condition
4650 * or requeued.
4651 *
4652 * The device queue freeze count is incremented
4653 * for each CCB that does not prevent this.
4654 * This function is called when all CCBs involved
4655 * in error handling/recovery have been reaped.
4656 */
4657 static void
4658 sym_flush_comp_queue(hcb_p np, int cam_status)
4659 {
4660 SYM_QUEHEAD *qp;
4661 ccb_p cp;
4662
4663 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) {
4664 union ccb *ccb;
4665 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
4666 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
4667 /* Leave quiet CCBs waiting for resources */
4668 if (cp->host_status == HS_WAIT)
4669 continue;
4670 ccb = cp->cam_ccb;
4671 if (cam_status)
4672 sym_set_cam_status(ccb, cam_status);
4673 sym_free_ccb(np, cp);
4674 sym_freeze_cam_ccb(ccb);
4675 sym_xpt_done(np, ccb);
4676 }
4677 }
4678
4679 /*
4680 * chip handler for bad SCSI status condition
4681 *
4682 * In case of bad SCSI status, we unqueue all the tasks
4683 * currently queued to the controller but not yet started
4684 * and then restart the SCRIPTS processor immediately.
4685 *
4686 * QUEUE FULL and BUSY conditions are handled the same way.
4687 * Basically all the not yet started tasks are requeued in
4688 * device queue and the queue is frozen until a completion.
4689 *
4690 * For CHECK CONDITION and COMMAND TERMINATED status, we use
4691 * the CCB of the failed command to prepare a REQUEST SENSE
4692 * SCSI command and queue it to the controller queue.
4693 *
4694 * SCRATCHA is assumed to have been loaded with STARTPOS
4695 * before the SCRIPTS called the C code.
4696 */
4697 static void sym_sir_bad_scsi_status(hcb_p np, int num, ccb_p cp)
4698 {
4699 tcb_p tp = &np->target[cp->target];
4700 u32 startp;
4701 u_char s_status = cp->ssss_status;
4702 u_char h_flags = cp->host_flags;
4703 int msglen;
4704 int nego;
4705 int i;
4706
4707 /*
4708 * Compute the index of the next job to start from SCRIPTS.
4709 */
4710 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
4711
4712 /*
4713 * The last CCB queued used for IARB hint may be
4714 * no longer relevant. Forget it.
4715 */
4716 #ifdef SYM_CONF_IARB_SUPPORT
4717 if (np->last_cp)
4718 np->last_cp = NULL;
4719 #endif
4720
4721 /*
4722 * Now deal with the SCSI status.
4723 */
4724 switch(s_status) {
4725 case S_BUSY:
4726 case S_QUEUE_FULL:
4727 if (sym_verbose >= 2) {
4728 PRINT_ADDR(cp);
4729 printf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n");
4730 }
4731 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */
4732 sym_complete_error (np, cp);
4733 break;
4734 case S_TERMINATED:
4735 case S_CHECK_COND:
4736 /*
4737 * If we get an SCSI error when requesting sense, give up.
4738 */
4739 if (h_flags & HF_SENSE) {
4740 sym_complete_error (np, cp);
4741 break;
4742 }
4743
4744 /*
4745 * Dequeue all queued CCBs for that device not yet started,
4746 * and restart the SCRIPTS processor immediately.
4747 */
4748 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
4749 OUTL_DSP (SCRIPTA_BA (np, start));
4750
4751 /*
4752 * Save some info of the actual IO.
4753 * Compute the data residual.
4754 */
4755 cp->sv_scsi_status = cp->ssss_status;
4756 cp->sv_xerr_status = cp->xerr_status;
4757 cp->sv_resid = sym_compute_residual(np, cp);
4758
4759 /*
4760 * Prepare all needed data structures for
4761 * requesting sense data.
4762 */
4763
4764 /*
4765 * identify message
4766 */
4767 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun;
4768 msglen = 1;
4769
4770 /*
4771 * If we are currently using anything different from
4772 * async. 8 bit data transfers with that target,
4773 * start a negotiation, since the device may want
4774 * to report us a UNIT ATTENTION condition due to
4775 * a cause we currently ignore, and we donnot want
4776 * to be stuck with WIDE and/or SYNC data transfer.
4777 *
4778 * cp->nego_status is filled by sym_prepare_nego().
4779 */
4780 cp->nego_status = 0;
4781 nego = 0;
4782 if (tp->tinfo.current.options & PPR_OPT_MASK)
4783 nego = NS_PPR;
4784 else if (tp->tinfo.current.width != BUS_8_BIT)
4785 nego = NS_WIDE;
4786 else if (tp->tinfo.current.offset != 0)
4787 nego = NS_SYNC;
4788 if (nego)
4789 msglen +=
4790 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]);
4791 /*
4792 * Message table indirect structure.
4793 */
4794 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2));
4795 cp->phys.smsg.size = cpu_to_scr(msglen);
4796
4797 /*
4798 * sense command
4799 */
4800 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd));
4801 cp->phys.cmd.size = cpu_to_scr(6);
4802
4803 /*
4804 * patch requested size into sense command
4805 */
4806 cp->sensecmd[0] = 0x03;
4807 cp->sensecmd[1] = cp->lun << 5;
4808 #ifdef FreeBSD_New_Tran_Settings
4809 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7)
4810 cp->sensecmd[1] = 0;
4811 #endif
4812 cp->sensecmd[4] = SYM_SNS_BBUF_LEN;
4813 cp->data_len = SYM_SNS_BBUF_LEN;
4814
4815 /*
4816 * sense data
4817 */
4818 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN);
4819 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf));
4820 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN);
4821
4822 /*
4823 * requeue the command.
4824 */
4825 startp = SCRIPTB_BA (np, sdata_in);
4826
4827 cp->phys.head.savep = cpu_to_scr(startp);
4828 cp->phys.head.goalp = cpu_to_scr(startp + 16);
4829 cp->phys.head.lastp = cpu_to_scr(startp);
4830 cp->startp = cpu_to_scr(startp);
4831
4832 cp->actualquirks = SYM_QUIRK_AUTOSAVE;
4833 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
4834 cp->ssss_status = S_ILLEGAL;
4835 cp->host_flags = (HF_SENSE|HF_DATA_IN);
4836 cp->xerr_status = 0;
4837 cp->extra_bytes = 0;
4838
4839 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select));
4840
4841 /*
4842 * Requeue the command.
4843 */
4844 sym_put_start_queue(np, cp);
4845
4846 /*
4847 * Give back to upper layer everything we have dequeued.
4848 */
4849 sym_flush_comp_queue(np, 0);
4850 break;
4851 }
4852 }
4853
4854 /*
4855 * After a device has accepted some management message
4856 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when
4857 * a device signals a UNIT ATTENTION condition, some
4858 * tasks are thrown away by the device. We are required
4859 * to reflect that on our tasks list since the device
4860 * will never complete these tasks.
4861 *
4862 * This function move from the BUSY queue to the COMP
4863 * queue all disconnected CCBs for a given target that
4864 * match the following criteria:
4865 * - lun=-1 means any logical UNIT otherwise a given one.
4866 * - task=-1 means any task, otherwise a given one.
4867 */
4868 static int
4869 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task)
4870 {
4871 SYM_QUEHEAD qtmp, *qp;
4872 int i = 0;
4873 ccb_p cp;
4874
4875 /*
4876 * Move the entire BUSY queue to our temporary queue.
4877 */
4878 sym_que_init(&qtmp);
4879 sym_que_splice(&np->busy_ccbq, &qtmp);
4880 sym_que_init(&np->busy_ccbq);
4881
4882 /*
4883 * Put all CCBs that matches our criteria into
4884 * the COMP queue and put back other ones into
4885 * the BUSY queue.
4886 */
4887 while ((qp = sym_remque_head(&qtmp)) != 0) {
4888 union ccb *ccb;
4889 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
4890 ccb = cp->cam_ccb;
4891 if (cp->host_status != HS_DISCONNECT ||
4892 cp->target != target ||
4893 (lun != -1 && cp->lun != lun) ||
4894 (task != -1 &&
4895 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) {
4896 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
4897 continue;
4898 }
4899 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
4900
4901 /* Preserve the software timeout condition */
4902 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT)
4903 sym_set_cam_status(ccb, cam_status);
4904 ++i;
4905 #if 0
4906 printf("XXXX TASK @%p CLEARED\n", cp);
4907 #endif
4908 }
4909 return i;
4910 }
4911
4912 /*
4913 * chip handler for TASKS recovery
4914 *
4915 * We cannot safely abort a command, while the SCRIPTS
4916 * processor is running, since we just would be in race
4917 * with it.
4918 *
4919 * As long as we have tasks to abort, we keep the SEM
4920 * bit set in the ISTAT. When this bit is set, the
4921 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED)
4922 * each time it enters the scheduler.
4923 *
4924 * If we have to reset a target, clear tasks of a unit,
4925 * or to perform the abort of a disconnected job, we
4926 * restart the SCRIPTS for selecting the target. Once
4927 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED).
4928 * If it loses arbitration, the SCRIPTS will interrupt again
4929 * the next time it will enter its scheduler, and so on ...
4930 *
4931 * On SIR_TARGET_SELECTED, we scan for the more
4932 * appropriate thing to do:
4933 *
4934 * - If nothing, we just sent a M_ABORT message to the
4935 * target to get rid of the useless SCSI bus ownership.
4936 * According to the specs, no tasks shall be affected.
4937 * - If the target is to be reset, we send it a M_RESET
4938 * message.
4939 * - If a logical UNIT is to be cleared , we send the
4940 * IDENTIFY(lun) + M_ABORT.
4941 * - If an untagged task is to be aborted, we send the
4942 * IDENTIFY(lun) + M_ABORT.
4943 * - If a tagged task is to be aborted, we send the
4944 * IDENTIFY(lun) + task attributes + M_ABORT_TAG.
4945 *
4946 * Once our 'kiss of death' :) message has been accepted
4947 * by the target, the SCRIPTS interrupts again
4948 * (SIR_ABORT_SENT). On this interrupt, we complete
4949 * all the CCBs that should have been aborted by the
4950 * target according to our message.
4951 */
4952 static void sym_sir_task_recovery(hcb_p np, int num)
4953 {
4954 SYM_QUEHEAD *qp;
4955 ccb_p cp;
4956 tcb_p tp;
4957 int target=-1, lun=-1, task;
4958 int i, k;
4959
4960 switch(num) {
4961 /*
4962 * The SCRIPTS processor stopped before starting
4963 * the next command in order to allow us to perform
4964 * some task recovery.
4965 */
4966 case SIR_SCRIPT_STOPPED:
4967 /*
4968 * Do we have any target to reset or unit to clear ?
4969 */
4970 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
4971 tp = &np->target[i];
4972 if (tp->to_reset ||
4973 (tp->lun0p && tp->lun0p->to_clear)) {
4974 target = i;
4975 break;
4976 }
4977 if (!tp->lunmp)
4978 continue;
4979 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
4980 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
4981 target = i;
4982 break;
4983 }
4984 }
4985 if (target != -1)
4986 break;
4987 }
4988
4989 /*
4990 * If not, walk the busy queue for any
4991 * disconnected CCB to be aborted.
4992 */
4993 if (target == -1) {
4994 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
4995 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq);
4996 if (cp->host_status != HS_DISCONNECT)
4997 continue;
4998 if (cp->to_abort) {
4999 target = cp->target;
5000 break;
5001 }
5002 }
5003 }
5004
5005 /*
5006 * If some target is to be selected,
5007 * prepare and start the selection.
5008 */
5009 if (target != -1) {
5010 tp = &np->target[target];
5011 np->abrt_sel.sel_id = target;
5012 np->abrt_sel.sel_scntl3 = tp->head.wval;
5013 np->abrt_sel.sel_sxfer = tp->head.sval;
5014 OUTL(nc_dsa, np->hcb_ba);
5015 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort));
5016 return;
5017 }
5018
5019 /*
5020 * Now look for a CCB to abort that haven't started yet.
5021 * Btw, the SCRIPTS processor is still stopped, so
5022 * we are not in race.
5023 */
5024 i = 0;
5025 cp = NULL;
5026 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
5027 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5028 if (cp->host_status != HS_BUSY &&
5029 cp->host_status != HS_NEGOTIATE)
5030 continue;
5031 if (!cp->to_abort)
5032 continue;
5033 #ifdef SYM_CONF_IARB_SUPPORT
5034 /*
5035 * If we are using IMMEDIATE ARBITRATION, we donnot
5036 * want to cancel the last queued CCB, since the
5037 * SCRIPTS may have anticipated the selection.
5038 */
5039 if (cp == np->last_cp) {
5040 cp->to_abort = 0;
5041 continue;
5042 }
5043 #endif
5044 i = 1; /* Means we have found some */
5045 break;
5046 }
5047 if (!i) {
5048 /*
5049 * We are done, so we donnot need
5050 * to synchronize with the SCRIPTS anylonger.
5051 * Remove the SEM flag from the ISTAT.
5052 */
5053 np->istat_sem = 0;
5054 OUTB (nc_istat, SIGP);
5055 break;
5056 }
5057 /*
5058 * Compute index of next position in the start
5059 * queue the SCRIPTS intends to start and dequeue
5060 * all CCBs for that device that haven't been started.
5061 */
5062 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
5063 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
5064
5065 /*
5066 * Make sure at least our IO to abort has been dequeued.
5067 */
5068 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ);
5069
5070 /*
5071 * Keep track in cam status of the reason of the abort.
5072 */
5073 if (cp->to_abort == 2)
5074 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT);
5075 else
5076 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED);
5077
5078 /*
5079 * Complete with error everything that we have dequeued.
5080 */
5081 sym_flush_comp_queue(np, 0);
5082 break;
5083 /*
5084 * The SCRIPTS processor has selected a target
5085 * we may have some manual recovery to perform for.
5086 */
5087 case SIR_TARGET_SELECTED:
5088 target = (INB (nc_sdid) & 0xf);
5089 tp = &np->target[target];
5090
5091 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg));
5092
5093 /*
5094 * If the target is to be reset, prepare a
5095 * M_RESET message and clear the to_reset flag
5096 * since we donnot expect this operation to fail.
5097 */
5098 if (tp->to_reset) {
5099 np->abrt_msg[0] = M_RESET;
5100 np->abrt_tbl.size = 1;
5101 tp->to_reset = 0;
5102 break;
5103 }
5104
5105 /*
5106 * Otherwise, look for some logical unit to be cleared.
5107 */
5108 if (tp->lun0p && tp->lun0p->to_clear)
5109 lun = 0;
5110 else if (tp->lunmp) {
5111 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
5112 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
5113 lun = k;
5114 break;
5115 }
5116 }
5117 }
5118
5119 /*
5120 * If a logical unit is to be cleared, prepare
5121 * an IDENTIFY(lun) + ABORT MESSAGE.
5122 */
5123 if (lun != -1) {
5124 lcb_p lp = sym_lp(np, tp, lun);
5125 lp->to_clear = 0; /* We donnot expect to fail here */
5126 np->abrt_msg[0] = M_IDENTIFY | lun;
5127 np->abrt_msg[1] = M_ABORT;
5128 np->abrt_tbl.size = 2;
5129 break;
5130 }
5131
5132 /*
5133 * Otherwise, look for some disconnected job to
5134 * abort for this target.
5135 */
5136 i = 0;
5137 cp = NULL;
5138 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
5139 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5140 if (cp->host_status != HS_DISCONNECT)
5141 continue;
5142 if (cp->target != target)
5143 continue;
5144 if (!cp->to_abort)
5145 continue;
5146 i = 1; /* Means we have some */
5147 break;
5148 }
5149
5150 /*
5151 * If we have none, probably since the device has
5152 * completed the command before we won abitration,
5153 * send a M_ABORT message without IDENTIFY.
5154 * According to the specs, the device must just
5155 * disconnect the BUS and not abort any task.
5156 */
5157 if (!i) {
5158 np->abrt_msg[0] = M_ABORT;
5159 np->abrt_tbl.size = 1;
5160 break;
5161 }
5162
5163 /*
5164 * We have some task to abort.
5165 * Set the IDENTIFY(lun)
5166 */
5167 np->abrt_msg[0] = M_IDENTIFY | cp->lun;
5168
5169 /*
5170 * If we want to abort an untagged command, we
5171 * will send an IDENTIFY + M_ABORT.
5172 * Otherwise (tagged command), we will send
5173 * an IDENTIFY + task attributes + ABORT TAG.
5174 */
5175 if (cp->tag == NO_TAG) {
5176 np->abrt_msg[1] = M_ABORT;
5177 np->abrt_tbl.size = 2;
5178 }
5179 else {
5180 np->abrt_msg[1] = cp->scsi_smsg[1];
5181 np->abrt_msg[2] = cp->scsi_smsg[2];
5182 np->abrt_msg[3] = M_ABORT_TAG;
5183 np->abrt_tbl.size = 4;
5184 }
5185 /*
5186 * Keep track of software timeout condition, since the
5187 * peripheral driver may not count retries on abort
5188 * conditions not due to timeout.
5189 */
5190 if (cp->to_abort == 2)
5191 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT);
5192 cp->to_abort = 0; /* We donnot expect to fail here */
5193 break;
5194
5195 /*
5196 * The target has accepted our message and switched
5197 * to BUS FREE phase as we expected.
5198 */
5199 case SIR_ABORT_SENT:
5200 target = (INB (nc_sdid) & 0xf);
5201 tp = &np->target[target];
5202
5203 /*
5204 ** If we didn't abort anything, leave here.
5205 */
5206 if (np->abrt_msg[0] == M_ABORT)
5207 break;
5208
5209 /*
5210 * If we sent a M_RESET, then a hardware reset has
5211 * been performed by the target.
5212 * - Reset everything to async 8 bit
5213 * - Tell ourself to negotiate next time :-)
5214 * - Prepare to clear all disconnected CCBs for
5215 * this target from our task list (lun=task=-1)
5216 */
5217 lun = -1;
5218 task = -1;
5219 if (np->abrt_msg[0] == M_RESET) {
5220 tp->head.sval = 0;
5221 tp->head.wval = np->rv_scntl3;
5222 tp->head.uval = 0;
5223 tp->tinfo.current.period = 0;
5224 tp->tinfo.current.offset = 0;
5225 tp->tinfo.current.width = BUS_8_BIT;
5226 tp->tinfo.current.options = 0;
5227 }
5228
5229 /*
5230 * Otherwise, check for the LUN and TASK(s)
5231 * concerned by the cancelation.
5232 * If it is not ABORT_TAG then it is CLEAR_QUEUE
5233 * or an ABORT message :-)
5234 */
5235 else {
5236 lun = np->abrt_msg[0] & 0x3f;
5237 if (np->abrt_msg[1] == M_ABORT_TAG)
5238 task = np->abrt_msg[2];
5239 }
5240
5241 /*
5242 * Complete all the CCBs the device should have
5243 * aborted due to our 'kiss of death' message.
5244 */
5245 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
5246 (void) sym_dequeue_from_squeue(np, i, target, lun, -1);
5247 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task);
5248 sym_flush_comp_queue(np, 0);
5249
5250 /*
5251 * If we sent a BDR, make uper layer aware of that.
5252 */
5253 if (np->abrt_msg[0] == M_RESET)
5254 xpt_async(AC_SENT_BDR, np->path, NULL);
5255 break;
5256 }
5257
5258 /*
5259 * Print to the log the message we intend to send.
5260 */
5261 if (num == SIR_TARGET_SELECTED) {
5262 PRINT_TARGET(np, target);
5263 sym_printl_hex("control msgout:", np->abrt_msg,
5264 np->abrt_tbl.size);
5265 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size);
5266 }
5267
5268 /*
5269 * Let the SCRIPTS processor continue.
5270 */
5271 OUTONB_STD ();
5272 }
5273
5274 /*
5275 * Gerard's alchemy:) that deals with with the data
5276 * pointer for both MDP and the residual calculation.
5277 *
5278 * I didn't want to bloat the code by more than 200
5279 * lignes for the handling of both MDP and the residual.
5280 * This has been achieved by using a data pointer
5281 * representation consisting in an index in the data
5282 * array (dp_sg) and a negative offset (dp_ofs) that
5283 * have the following meaning:
5284 *
5285 * - dp_sg = SYM_CONF_MAX_SG
5286 * we are at the end of the data script.
5287 * - dp_sg < SYM_CONF_MAX_SG
5288 * dp_sg points to the next entry of the scatter array
5289 * we want to transfer.
5290 * - dp_ofs < 0
5291 * dp_ofs represents the residual of bytes of the
5292 * previous entry scatter entry we will send first.
5293 * - dp_ofs = 0
5294 * no residual to send first.
5295 *
5296 * The function sym_evaluate_dp() accepts an arbitray
5297 * offset (basically from the MDP message) and returns
5298 * the corresponding values of dp_sg and dp_ofs.
5299 */
5300
5301 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs)
5302 {
5303 u32 dp_scr;
5304 int dp_ofs, dp_sg, dp_sgmin;
5305 int tmp;
5306 struct sym_pmc *pm;
5307
5308 /*
5309 * Compute the resulted data pointer in term of a script
5310 * address within some DATA script and a signed byte offset.
5311 */
5312 dp_scr = scr;
5313 dp_ofs = *ofs;
5314 if (dp_scr == SCRIPTA_BA (np, pm0_data))
5315 pm = &cp->phys.pm0;
5316 else if (dp_scr == SCRIPTA_BA (np, pm1_data))
5317 pm = &cp->phys.pm1;
5318 else
5319 pm = NULL;
5320
5321 if (pm) {
5322 dp_scr = scr_to_cpu(pm->ret);
5323 dp_ofs -= scr_to_cpu(pm->sg.size);
5324 }
5325
5326 /*
5327 * If we are auto-sensing, then we are done.
5328 */
5329 if (cp->host_flags & HF_SENSE) {
5330 *ofs = dp_ofs;
5331 return 0;
5332 }
5333
5334 /*
5335 * Deduce the index of the sg entry.
5336 * Keep track of the index of the first valid entry.
5337 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the
5338 * end of the data.
5339 */
5340 tmp = scr_to_cpu(cp->phys.head.goalp);
5341 dp_sg = SYM_CONF_MAX_SG;
5342 if (dp_scr != tmp)
5343 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4);
5344 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
5345
5346 /*
5347 * Move to the sg entry the data pointer belongs to.
5348 *
5349 * If we are inside the data area, we expect result to be:
5350 *
5351 * Either,
5352 * dp_ofs = 0 and dp_sg is the index of the sg entry
5353 * the data pointer belongs to (or the end of the data)
5354 * Or,
5355 * dp_ofs < 0 and dp_sg is the index of the sg entry
5356 * the data pointer belongs to + 1.
5357 */
5358 if (dp_ofs < 0) {
5359 int n;
5360 while (dp_sg > dp_sgmin) {
5361 --dp_sg;
5362 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
5363 n = dp_ofs + (tmp & 0xffffff);
5364 if (n > 0) {
5365 ++dp_sg;
5366 break;
5367 }
5368 dp_ofs = n;
5369 }
5370 }
5371 else if (dp_ofs > 0) {
5372 while (dp_sg < SYM_CONF_MAX_SG) {
5373 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
5374 dp_ofs -= (tmp & 0xffffff);
5375 ++dp_sg;
5376 if (dp_ofs <= 0)
5377 break;
5378 }
5379 }
5380
5381 /*
5382 * Make sure the data pointer is inside the data area.
5383 * If not, return some error.
5384 */
5385 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0))
5386 goto out_err;
5387 else if (dp_sg > SYM_CONF_MAX_SG ||
5388 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0))
5389 goto out_err;
5390
5391 /*
5392 * Save the extreme pointer if needed.
5393 */
5394 if (dp_sg > cp->ext_sg ||
5395 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) {
5396 cp->ext_sg = dp_sg;
5397 cp->ext_ofs = dp_ofs;
5398 }
5399
5400 /*
5401 * Return data.
5402 */
5403 *ofs = dp_ofs;
5404 return dp_sg;
5405
5406 out_err:
5407 return -1;
5408 }
5409
5410 /*
5411 * chip handler for MODIFY DATA POINTER MESSAGE
5412 *
5413 * We also call this function on IGNORE WIDE RESIDUE
5414 * messages that do not match a SWIDE full condition.
5415 * Btw, we assume in that situation that such a message
5416 * is equivalent to a MODIFY DATA POINTER (offset=-1).
5417 */
5418
5419 static void sym_modify_dp(hcb_p np, tcb_p tp, ccb_p cp, int ofs)
5420 {
5421 int dp_ofs = ofs;
5422 u32 dp_scr = INL (nc_temp);
5423 u32 dp_ret;
5424 u32 tmp;
5425 u_char hflags;
5426 int dp_sg;
5427 struct sym_pmc *pm;
5428
5429 /*
5430 * Not supported for auto-sense.
5431 */
5432 if (cp->host_flags & HF_SENSE)
5433 goto out_reject;
5434
5435 /*
5436 * Apply our alchemy:) (see comments in sym_evaluate_dp()),
5437 * to the resulted data pointer.
5438 */
5439 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs);
5440 if (dp_sg < 0)
5441 goto out_reject;
5442
5443 /*
5444 * And our alchemy:) allows to easily calculate the data
5445 * script address we want to return for the next data phase.
5446 */
5447 dp_ret = cpu_to_scr(cp->phys.head.goalp);
5448 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4);
5449
5450 /*
5451 * If offset / scatter entry is zero we donnot need
5452 * a context for the new current data pointer.
5453 */
5454 if (dp_ofs == 0) {
5455 dp_scr = dp_ret;
5456 goto out_ok;
5457 }
5458
5459 /*
5460 * Get a context for the new current data pointer.
5461 */
5462 hflags = INB (HF_PRT);
5463
5464 if (hflags & HF_DP_SAVED)
5465 hflags ^= HF_ACT_PM;
5466
5467 if (!(hflags & HF_ACT_PM)) {
5468 pm = &cp->phys.pm0;
5469 dp_scr = SCRIPTA_BA (np, pm0_data);
5470 }
5471 else {
5472 pm = &cp->phys.pm1;
5473 dp_scr = SCRIPTA_BA (np, pm1_data);
5474 }
5475
5476 hflags &= ~(HF_DP_SAVED);
5477
5478 OUTB (HF_PRT, hflags);
5479
5480 /*
5481 * Set up the new current data pointer.
5482 * ofs < 0 there, and for the next data phase, we
5483 * want to transfer part of the data of the sg entry
5484 * corresponding to index dp_sg-1 prior to returning
5485 * to the main data script.
5486 */
5487 pm->ret = cpu_to_scr(dp_ret);
5488 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr);
5489 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs;
5490 pm->sg.addr = cpu_to_scr(tmp);
5491 pm->sg.size = cpu_to_scr(-dp_ofs);
5492
5493 out_ok:
5494 OUTL (nc_temp, dp_scr);
5495 OUTL_DSP (SCRIPTA_BA (np, clrack));
5496 return;
5497
5498 out_reject:
5499 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5500 }
5501
5502
5503 /*
5504 * chip calculation of the data residual.
5505 *
5506 * As I used to say, the requirement of data residual
5507 * in SCSI is broken, useless and cannot be achieved
5508 * without huge complexity.
5509 * But most OSes and even the official CAM require it.
5510 * When stupidity happens to be so widely spread inside
5511 * a community, it gets hard to convince.
5512 *
5513 * Anyway, I don't care, since I am not going to use
5514 * any software that considers this data residual as
5515 * a relevant information. :)
5516 */
5517
5518 static int sym_compute_residual(hcb_p np, ccb_p cp)
5519 {
5520 int dp_sg, dp_sgmin, resid = 0;
5521 int dp_ofs = 0;
5522
5523 /*
5524 * Check for some data lost or just thrown away.
5525 * We are not required to be quite accurate in this
5526 * situation. Btw, if we are odd for output and the
5527 * device claims some more data, it may well happen
5528 * than our residual be zero. :-)
5529 */
5530 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) {
5531 if (cp->xerr_status & XE_EXTRA_DATA)
5532 resid -= cp->extra_bytes;
5533 if (cp->xerr_status & XE_SODL_UNRUN)
5534 ++resid;
5535 if (cp->xerr_status & XE_SWIDE_OVRUN)
5536 --resid;
5537 }
5538
5539 /*
5540 * If all data has been transferred,
5541 * there is no residual.
5542 */
5543 if (cp->phys.head.lastp == cp->phys.head.goalp)
5544 return resid;
5545
5546 /*
5547 * If no data transfer occurs, or if the data
5548 * pointer is weird, return full residual.
5549 */
5550 if (cp->startp == cp->phys.head.lastp ||
5551 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp),
5552 &dp_ofs) < 0) {
5553 return cp->data_len;
5554 }
5555
5556 /*
5557 * If we were auto-sensing, then we are done.
5558 */
5559 if (cp->host_flags & HF_SENSE) {
5560 return -dp_ofs;
5561 }
5562
5563 /*
5564 * We are now full comfortable in the computation
5565 * of the data residual (2's complement).
5566 */
5567 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
5568 resid = -cp->ext_ofs;
5569 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) {
5570 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
5571 resid += (tmp & 0xffffff);
5572 }
5573
5574 /*
5575 * Hopefully, the result is not too wrong.
5576 */
5577 return resid;
5578 }
5579
5580 /*
5581 * Print out the content of a SCSI message.
5582 */
5583
5584 static int sym_show_msg (u_char * msg)
5585 {
5586 u_char i;
5587 printf ("%x",*msg);
5588 if (*msg==M_EXTENDED) {
5589 for (i=1;i<8;i++) {
5590 if (i-1>msg[1]) break;
5591 printf ("-%x",msg[i]);
5592 };
5593 return (i+1);
5594 } else if ((*msg & 0xf0) == 0x20) {
5595 printf ("-%x",msg[1]);
5596 return (2);
5597 };
5598 return (1);
5599 }
5600
5601 static void sym_print_msg (ccb_p cp, char *label, u_char *msg)
5602 {
5603 PRINT_ADDR(cp);
5604 if (label)
5605 printf ("%s: ", label);
5606
5607 (void) sym_show_msg (msg);
5608 printf (".\n");
5609 }
5610
5611 /*
5612 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER.
5613 *
5614 * When we try to negotiate, we append the negotiation message
5615 * to the identify and (maybe) simple tag message.
5616 * The host status field is set to HS_NEGOTIATE to mark this
5617 * situation.
5618 *
5619 * If the target doesn't answer this message immediately
5620 * (as required by the standard), the SIR_NEGO_FAILED interrupt
5621 * will be raised eventually.
5622 * The handler removes the HS_NEGOTIATE status, and sets the
5623 * negotiated value to the default (async / nowide).
5624 *
5625 * If we receive a matching answer immediately, we check it
5626 * for validity, and set the values.
5627 *
5628 * If we receive a Reject message immediately, we assume the
5629 * negotiation has failed, and fall back to standard values.
5630 *
5631 * If we receive a negotiation message while not in HS_NEGOTIATE
5632 * state, it's a target initiated negotiation. We prepare a
5633 * (hopefully) valid answer, set our parameters, and send back
5634 * this answer to the target.
5635 *
5636 * If the target doesn't fetch the answer (no message out phase),
5637 * we assume the negotiation has failed, and fall back to default
5638 * settings (SIR_NEGO_PROTO interrupt).
5639 *
5640 * When we set the values, we adjust them in all ccbs belonging
5641 * to this target, in the controller's register, and in the "phys"
5642 * field of the controller's struct sym_hcb.
5643 */
5644
5645 /*
5646 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message.
5647 */
5648 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp)
5649 {
5650 u_char chg, ofs, per, fak, div;
5651 int req = 1;
5652
5653 /*
5654 * Synchronous request message received.
5655 */
5656 if (DEBUG_FLAGS & DEBUG_NEGO) {
5657 sym_print_msg(cp, "sync msgin", np->msgin);
5658 };
5659
5660 /*
5661 * request or answer ?
5662 */
5663 if (INB (HS_PRT) == HS_NEGOTIATE) {
5664 OUTB (HS_PRT, HS_BUSY);
5665 if (cp->nego_status && cp->nego_status != NS_SYNC)
5666 goto reject_it;
5667 req = 0;
5668 }
5669
5670 /*
5671 * get requested values.
5672 */
5673 chg = 0;
5674 per = np->msgin[3];
5675 ofs = np->msgin[4];
5676
5677 /*
5678 * check values against our limits.
5679 */
5680 if (ofs) {
5681 if (ofs > np->maxoffs)
5682 {chg = 1; ofs = np->maxoffs;}
5683 if (req) {
5684 if (ofs > tp->tinfo.user.offset)
5685 {chg = 1; ofs = tp->tinfo.user.offset;}
5686 }
5687 }
5688
5689 if (ofs) {
5690 if (per < np->minsync)
5691 {chg = 1; per = np->minsync;}
5692 if (req) {
5693 if (per < tp->tinfo.user.period)
5694 {chg = 1; per = tp->tinfo.user.period;}
5695 }
5696 }
5697
5698 div = fak = 0;
5699 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0)
5700 goto reject_it;
5701
5702 if (DEBUG_FLAGS & DEBUG_NEGO) {
5703 PRINT_ADDR(cp);
5704 printf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n",
5705 ofs, per, div, fak, chg);
5706 }
5707
5708 /*
5709 * This was an answer message
5710 */
5711 if (req == 0) {
5712 if (chg) /* Answer wasn't acceptable. */
5713 goto reject_it;
5714 sym_setsync (np, cp, ofs, per, div, fak);
5715 OUTL_DSP (SCRIPTA_BA (np, clrack));
5716 return;
5717 }
5718
5719 /*
5720 * It was a request. Set value and
5721 * prepare an answer message
5722 */
5723 sym_setsync (np, cp, ofs, per, div, fak);
5724
5725 np->msgout[0] = M_EXTENDED;
5726 np->msgout[1] = 3;
5727 np->msgout[2] = M_X_SYNC_REQ;
5728 np->msgout[3] = per;
5729 np->msgout[4] = ofs;
5730
5731 cp->nego_status = NS_SYNC;
5732
5733 if (DEBUG_FLAGS & DEBUG_NEGO) {
5734 sym_print_msg(cp, "sync msgout", np->msgout);
5735 }
5736
5737 np->msgin [0] = M_NOOP;
5738
5739 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp));
5740 return;
5741 reject_it:
5742 sym_setsync (np, cp, 0, 0, 0, 0);
5743 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5744 }
5745
5746 /*
5747 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message.
5748 */
5749 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp)
5750 {
5751 u_char chg, ofs, per, fak, dt, div, wide;
5752 int req = 1;
5753
5754 /*
5755 * Synchronous request message received.
5756 */
5757 if (DEBUG_FLAGS & DEBUG_NEGO) {
5758 sym_print_msg(cp, "ppr msgin", np->msgin);
5759 };
5760
5761 /*
5762 * get requested values.
5763 */
5764 chg = 0;
5765 per = np->msgin[3];
5766 ofs = np->msgin[5];
5767 wide = np->msgin[6];
5768 dt = np->msgin[7] & PPR_OPT_DT;
5769
5770 /*
5771 * request or answer ?
5772 */
5773 if (INB (HS_PRT) == HS_NEGOTIATE) {
5774 OUTB (HS_PRT, HS_BUSY);
5775 if (cp->nego_status && cp->nego_status != NS_PPR)
5776 goto reject_it;
5777 req = 0;
5778 }
5779
5780 /*
5781 * check values against our limits.
5782 */
5783 if (wide > np->maxwide)
5784 {chg = 1; wide = np->maxwide;}
5785 if (!wide || !(np->features & FE_ULTRA3))
5786 dt &= ~PPR_OPT_DT;
5787 if (req) {
5788 if (wide > tp->tinfo.user.width)
5789 {chg = 1; wide = tp->tinfo.user.width;}
5790 }
5791
5792 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */
5793 dt &= ~PPR_OPT_DT;
5794
5795 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1;
5796
5797 if (ofs) {
5798 if (dt) {
5799 if (ofs > np->maxoffs_dt)
5800 {chg = 1; ofs = np->maxoffs_dt;}
5801 }
5802 else if (ofs > np->maxoffs)
5803 {chg = 1; ofs = np->maxoffs;}
5804 if (req) {
5805 if (ofs > tp->tinfo.user.offset)
5806 {chg = 1; ofs = tp->tinfo.user.offset;}
5807 }
5808 }
5809
5810 if (ofs) {
5811 if (dt) {
5812 if (per < np->minsync_dt)
5813 {chg = 1; per = np->minsync_dt;}
5814 }
5815 else if (per < np->minsync)
5816 {chg = 1; per = np->minsync;}
5817 if (req) {
5818 if (per < tp->tinfo.user.period)
5819 {chg = 1; per = tp->tinfo.user.period;}
5820 }
5821 }
5822
5823 div = fak = 0;
5824 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0)
5825 goto reject_it;
5826
5827 if (DEBUG_FLAGS & DEBUG_NEGO) {
5828 PRINT_ADDR(cp);
5829 printf ("ppr: "
5830 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n",
5831 dt, ofs, per, wide, div, fak, chg);
5832 }
5833
5834 /*
5835 * It was an answer.
5836 */
5837 if (req == 0) {
5838 if (chg) /* Answer wasn't acceptable */
5839 goto reject_it;
5840 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak);
5841 OUTL_DSP (SCRIPTA_BA (np, clrack));
5842 return;
5843 }
5844
5845 /*
5846 * It was a request. Set value and
5847 * prepare an answer message
5848 */
5849 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak);
5850
5851 np->msgout[0] = M_EXTENDED;
5852 np->msgout[1] = 6;
5853 np->msgout[2] = M_X_PPR_REQ;
5854 np->msgout[3] = per;
5855 np->msgout[4] = 0;
5856 np->msgout[5] = ofs;
5857 np->msgout[6] = wide;
5858 np->msgout[7] = dt;
5859
5860 cp->nego_status = NS_PPR;
5861
5862 if (DEBUG_FLAGS & DEBUG_NEGO) {
5863 sym_print_msg(cp, "ppr msgout", np->msgout);
5864 }
5865
5866 np->msgin [0] = M_NOOP;
5867
5868 OUTL_DSP (SCRIPTB_BA (np, ppr_resp));
5869 return;
5870 reject_it:
5871 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0);
5872 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5873 /*
5874 * If it was a device response that should result in
5875 * ST, we may want to try a legacy negotiation later.
5876 */
5877 if (!req && !dt) {
5878 tp->tinfo.goal.options = 0;
5879 tp->tinfo.goal.width = wide;
5880 tp->tinfo.goal.period = per;
5881 tp->tinfo.goal.offset = ofs;
5882 }
5883 }
5884
5885 /*
5886 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message.
5887 */
5888 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp)
5889 {
5890 u_char chg, wide;
5891 int req = 1;
5892
5893 /*
5894 * Wide request message received.
5895 */
5896 if (DEBUG_FLAGS & DEBUG_NEGO) {
5897 sym_print_msg(cp, "wide msgin", np->msgin);
5898 };
5899
5900 /*
5901 * Is it a request from the device?
5902 */
5903 if (INB (HS_PRT) == HS_NEGOTIATE) {
5904 OUTB (HS_PRT, HS_BUSY);
5905 if (cp->nego_status && cp->nego_status != NS_WIDE)
5906 goto reject_it;
5907 req = 0;
5908 }
5909
5910 /*
5911 * get requested values.
5912 */
5913 chg = 0;
5914 wide = np->msgin[3];
5915
5916 /*
5917 * check values against driver limits.
5918 */
5919 if (wide > np->maxwide)
5920 {chg = 1; wide = np->maxwide;}
5921 if (req) {
5922 if (wide > tp->tinfo.user.width)
5923 {chg = 1; wide = tp->tinfo.user.width;}
5924 }
5925
5926 if (DEBUG_FLAGS & DEBUG_NEGO) {
5927 PRINT_ADDR(cp);
5928 printf ("wdtr: wide=%d chg=%d.\n", wide, chg);
5929 }
5930
5931 /*
5932 * This was an answer message
5933 */
5934 if (req == 0) {
5935 if (chg) /* Answer wasn't acceptable. */
5936 goto reject_it;
5937 sym_setwide (np, cp, wide);
5938
5939 /*
5940 * Negotiate for SYNC immediately after WIDE response.
5941 * This allows to negotiate for both WIDE and SYNC on
5942 * a single SCSI command (Suggested by Justin Gibbs).
5943 */
5944 if (tp->tinfo.goal.offset) {
5945 np->msgout[0] = M_EXTENDED;
5946 np->msgout[1] = 3;
5947 np->msgout[2] = M_X_SYNC_REQ;
5948 np->msgout[3] = tp->tinfo.goal.period;
5949 np->msgout[4] = tp->tinfo.goal.offset;
5950
5951 if (DEBUG_FLAGS & DEBUG_NEGO) {
5952 sym_print_msg(cp, "sync msgout", np->msgout);
5953 }
5954
5955 cp->nego_status = NS_SYNC;
5956 OUTB (HS_PRT, HS_NEGOTIATE);
5957 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp));
5958 return;
5959 }
5960
5961 OUTL_DSP (SCRIPTA_BA (np, clrack));
5962 return;
5963 };
5964
5965 /*
5966 * It was a request, set value and
5967 * prepare an answer message
5968 */
5969 sym_setwide (np, cp, wide);
5970
5971 np->msgout[0] = M_EXTENDED;
5972 np->msgout[1] = 2;
5973 np->msgout[2] = M_X_WIDE_REQ;
5974 np->msgout[3] = wide;
5975
5976 np->msgin [0] = M_NOOP;
5977
5978 cp->nego_status = NS_WIDE;
5979
5980 if (DEBUG_FLAGS & DEBUG_NEGO) {
5981 sym_print_msg(cp, "wide msgout", np->msgout);
5982 }
5983
5984 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp));
5985 return;
5986 reject_it:
5987 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
5988 }
5989
5990 /*
5991 * Reset SYNC or WIDE to default settings.
5992 *
5993 * Called when a negotiation does not succeed either
5994 * on rejection or on protocol error.
5995 *
5996 * If it was a PPR that made problems, we may want to
5997 * try a legacy negotiation later.
5998 */
5999 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp)
6000 {
6001 /*
6002 * any error in negotiation:
6003 * fall back to default mode.
6004 */
6005 switch (cp->nego_status) {
6006 case NS_PPR:
6007 #if 0
6008 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0);
6009 #else
6010 tp->tinfo.goal.options = 0;
6011 if (tp->tinfo.goal.period < np->minsync)
6012 tp->tinfo.goal.period = np->minsync;
6013 if (tp->tinfo.goal.offset > np->maxoffs)
6014 tp->tinfo.goal.offset = np->maxoffs;
6015 #endif
6016 break;
6017 case NS_SYNC:
6018 sym_setsync (np, cp, 0, 0, 0, 0);
6019 break;
6020 case NS_WIDE:
6021 sym_setwide (np, cp, 0);
6022 break;
6023 };
6024 np->msgin [0] = M_NOOP;
6025 np->msgout[0] = M_NOOP;
6026 cp->nego_status = 0;
6027 }
6028
6029 /*
6030 * chip handler for MESSAGE REJECT received in response to
6031 * a WIDE or SYNCHRONOUS negotiation.
6032 */
6033 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp)
6034 {
6035 sym_nego_default(np, tp, cp);
6036 OUTB (HS_PRT, HS_BUSY);
6037 }
6038
6039 /*
6040 * chip exception handler for programmed interrupts.
6041 */
6042 static void sym_int_sir (hcb_p np)
6043 {
6044 u_char num = INB (nc_dsps);
6045 u32 dsa = INL (nc_dsa);
6046 ccb_p cp = sym_ccb_from_dsa(np, dsa);
6047 u_char target = INB (nc_sdid) & 0x0f;
6048 tcb_p tp = &np->target[target];
6049 int tmp;
6050
6051 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num);
6052
6053 switch (num) {
6054 /*
6055 * Command has been completed with error condition
6056 * or has been auto-sensed.
6057 */
6058 case SIR_COMPLETE_ERROR:
6059 sym_complete_error(np, cp);
6060 return;
6061 /*
6062 * The C code is currently trying to recover from something.
6063 * Typically, user want to abort some command.
6064 */
6065 case SIR_SCRIPT_STOPPED:
6066 case SIR_TARGET_SELECTED:
6067 case SIR_ABORT_SENT:
6068 sym_sir_task_recovery(np, num);
6069 return;
6070 /*
6071 * The device didn't go to MSG OUT phase after having
6072 * been selected with ATN. We donnot want to handle
6073 * that.
6074 */
6075 case SIR_SEL_ATN_NO_MSG_OUT:
6076 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n",
6077 sym_name (np), target);
6078 goto out_stuck;
6079 /*
6080 * The device didn't switch to MSG IN phase after
6081 * having reseleted the initiator.
6082 */
6083 case SIR_RESEL_NO_MSG_IN:
6084 printf ("%s:%d: No MSG IN phase after reselection.\n",
6085 sym_name (np), target);
6086 goto out_stuck;
6087 /*
6088 * After reselection, the device sent a message that wasn't
6089 * an IDENTIFY.
6090 */
6091 case SIR_RESEL_NO_IDENTIFY:
6092 printf ("%s:%d: No IDENTIFY after reselection.\n",
6093 sym_name (np), target);
6094 goto out_stuck;
6095 /*
6096 * The device reselected a LUN we donnot know about.
6097 */
6098 case SIR_RESEL_BAD_LUN:
6099 np->msgout[0] = M_RESET;
6100 goto out;
6101 /*
6102 * The device reselected for an untagged nexus and we
6103 * haven't any.
6104 */
6105 case SIR_RESEL_BAD_I_T_L:
6106 np->msgout[0] = M_ABORT;
6107 goto out;
6108 /*
6109 * The device reselected for a tagged nexus that we donnot
6110 * have.
6111 */
6112 case SIR_RESEL_BAD_I_T_L_Q:
6113 np->msgout[0] = M_ABORT_TAG;
6114 goto out;
6115 /*
6116 * The SCRIPTS let us know that the device has grabbed
6117 * our message and will abort the job.
6118 */
6119 case SIR_RESEL_ABORTED:
6120 np->lastmsg = np->msgout[0];
6121 np->msgout[0] = M_NOOP;
6122 printf ("%s:%d: message %x sent on bad reselection.\n",
6123 sym_name (np), target, np->lastmsg);
6124 goto out;
6125 /*
6126 * The SCRIPTS let us know that a message has been
6127 * successfully sent to the device.
6128 */
6129 case SIR_MSG_OUT_DONE:
6130 np->lastmsg = np->msgout[0];
6131 np->msgout[0] = M_NOOP;
6132 /* Should we really care of that */
6133 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) {
6134 if (cp) {
6135 cp->xerr_status &= ~XE_PARITY_ERR;
6136 if (!cp->xerr_status)
6137 OUTOFFB (HF_PRT, HF_EXT_ERR);
6138 }
6139 }
6140 goto out;
6141 /*
6142 * The device didn't send a GOOD SCSI status.
6143 * We may have some work to do prior to allow
6144 * the SCRIPTS processor to continue.
6145 */
6146 case SIR_BAD_SCSI_STATUS:
6147 if (!cp)
6148 goto out;
6149 sym_sir_bad_scsi_status(np, num, cp);
6150 return;
6151 /*
6152 * We are asked by the SCRIPTS to prepare a
6153 * REJECT message.
6154 */
6155 case SIR_REJECT_TO_SEND:
6156 sym_print_msg(cp, "M_REJECT to send for ", np->msgin);
6157 np->msgout[0] = M_REJECT;
6158 goto out;
6159 /*
6160 * We have been ODD at the end of a DATA IN
6161 * transfer and the device didn't send a
6162 * IGNORE WIDE RESIDUE message.
6163 * It is a data overrun condition.
6164 */
6165 case SIR_SWIDE_OVERRUN:
6166 if (cp) {
6167 OUTONB (HF_PRT, HF_EXT_ERR);
6168 cp->xerr_status |= XE_SWIDE_OVRUN;
6169 }
6170 goto out;
6171 /*
6172 * We have been ODD at the end of a DATA OUT
6173 * transfer.
6174 * It is a data underrun condition.
6175 */
6176 case SIR_SODL_UNDERRUN:
6177 if (cp) {
6178 OUTONB (HF_PRT, HF_EXT_ERR);
6179 cp->xerr_status |= XE_SODL_UNRUN;
6180 }
6181 goto out;
6182 /*
6183 * The device wants us to tranfer more data than
6184 * expected or in the wrong direction.
6185 * The number of extra bytes is in scratcha.
6186 * It is a data overrun condition.
6187 */
6188 case SIR_DATA_OVERRUN:
6189 if (cp) {
6190 OUTONB (HF_PRT, HF_EXT_ERR);
6191 cp->xerr_status |= XE_EXTRA_DATA;
6192 cp->extra_bytes += INL (nc_scratcha);
6193 }
6194 goto out;
6195 /*
6196 * The device switched to an illegal phase (4/5).
6197 */
6198 case SIR_BAD_PHASE:
6199 if (cp) {
6200 OUTONB (HF_PRT, HF_EXT_ERR);
6201 cp->xerr_status |= XE_BAD_PHASE;
6202 }
6203 goto out;
6204 /*
6205 * We received a message.
6206 */
6207 case SIR_MSG_RECEIVED:
6208 if (!cp)
6209 goto out_stuck;
6210 switch (np->msgin [0]) {
6211 /*
6212 * We received an extended message.
6213 * We handle MODIFY DATA POINTER, SDTR, WDTR
6214 * and reject all other extended messages.
6215 */
6216 case M_EXTENDED:
6217 switch (np->msgin [2]) {
6218 case M_X_MODIFY_DP:
6219 if (DEBUG_FLAGS & DEBUG_POINTER)
6220 sym_print_msg(cp,"modify DP",np->msgin);
6221 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) +
6222 (np->msgin[5]<<8) + (np->msgin[6]);
6223 sym_modify_dp(np, tp, cp, tmp);
6224 return;
6225 case M_X_SYNC_REQ:
6226 sym_sync_nego(np, tp, cp);
6227 return;
6228 case M_X_PPR_REQ:
6229 sym_ppr_nego(np, tp, cp);
6230 return;
6231 case M_X_WIDE_REQ:
6232 sym_wide_nego(np, tp, cp);
6233 return;
6234 default:
6235 goto out_reject;
6236 }
6237 break;
6238 /*
6239 * We received a 1/2 byte message not handled from SCRIPTS.
6240 * We are only expecting MESSAGE REJECT and IGNORE WIDE
6241 * RESIDUE messages that haven't been anticipated by
6242 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE
6243 * WIDE RESIDUE messages are aliased as MODIFY DP (-1).
6244 */
6245 case M_IGN_RESIDUE:
6246 if (DEBUG_FLAGS & DEBUG_POINTER)
6247 sym_print_msg(cp,"ign wide residue", np->msgin);
6248 sym_modify_dp(np, tp, cp, -1);
6249 return;
6250 case M_REJECT:
6251 if (INB (HS_PRT) == HS_NEGOTIATE)
6252 sym_nego_rejected(np, tp, cp);
6253 else {
6254 PRINT_ADDR(cp);
6255 printf ("M_REJECT received (%x:%x).\n",
6256 scr_to_cpu(np->lastmsg), np->msgout[0]);
6257 }
6258 goto out_clrack;
6259 break;
6260 default:
6261 goto out_reject;
6262 }
6263 break;
6264 /*
6265 * We received an unknown message.
6266 * Ignore all MSG IN phases and reject it.
6267 */
6268 case SIR_MSG_WEIRD:
6269 sym_print_msg(cp, "WEIRD message received", np->msgin);
6270 OUTL_DSP (SCRIPTB_BA (np, msg_weird));
6271 return;
6272 /*
6273 * Negotiation failed.
6274 * Target does not send us the reply.
6275 * Remove the HS_NEGOTIATE status.
6276 */
6277 case SIR_NEGO_FAILED:
6278 OUTB (HS_PRT, HS_BUSY);
6279 /*
6280 * Negotiation failed.
6281 * Target does not want answer message.
6282 */
6283 case SIR_NEGO_PROTO:
6284 sym_nego_default(np, tp, cp);
6285 goto out;
6286 };
6287
6288 out:
6289 OUTONB_STD ();
6290 return;
6291 out_reject:
6292 OUTL_DSP (SCRIPTB_BA (np, msg_bad));
6293 return;
6294 out_clrack:
6295 OUTL_DSP (SCRIPTA_BA (np, clrack));
6296 return;
6297 out_stuck:
6298 return;
6299 }
6300
6301 /*
6302 * Acquire a control block
6303 */
6304 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order)
6305 {
6306 tcb_p tp = &np->target[tn];
6307 lcb_p lp = sym_lp(np, tp, ln);
6308 u_short tag = NO_TAG;
6309 SYM_QUEHEAD *qp;
6310 ccb_p cp = (ccb_p) NULL;
6311
6312 /*
6313 * Look for a free CCB
6314 */
6315 if (sym_que_empty(&np->free_ccbq))
6316 (void) sym_alloc_ccb(np);
6317 qp = sym_remque_head(&np->free_ccbq);
6318 if (!qp)
6319 goto out;
6320 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
6321
6322 /*
6323 * If the LCB is not yet available and the LUN
6324 * has been probed ok, try to allocate the LCB.
6325 */
6326 if (!lp && sym_is_bit(tp->lun_map, ln)) {
6327 lp = sym_alloc_lcb(np, tn, ln);
6328 if (!lp)
6329 goto out_free;
6330 }
6331
6332 /*
6333 * If the LCB is not available here, then the
6334 * logical unit is not yet discovered. For those
6335 * ones only accept 1 SCSI IO per logical unit,
6336 * since we cannot allow disconnections.
6337 */
6338 if (!lp) {
6339 if (!sym_is_bit(tp->busy0_map, ln))
6340 sym_set_bit(tp->busy0_map, ln);
6341 else
6342 goto out_free;
6343 } else {
6344 /*
6345 * If we have been asked for a tagged command.
6346 */
6347 if (tag_order) {
6348 /*
6349 * Debugging purpose.
6350 */
6351 assert(lp->busy_itl == 0);
6352 /*
6353 * Allocate resources for tags if not yet.
6354 */
6355 if (!lp->cb_tags) {
6356 sym_alloc_lcb_tags(np, tn, ln);
6357 if (!lp->cb_tags)
6358 goto out_free;
6359 }
6360 /*
6361 * Get a tag for this SCSI IO and set up
6362 * the CCB bus address for reselection,
6363 * and count it for this LUN.
6364 * Toggle reselect path to tagged.
6365 */
6366 if (lp->busy_itlq < SYM_CONF_MAX_TASK) {
6367 tag = lp->cb_tags[lp->ia_tag];
6368 if (++lp->ia_tag == SYM_CONF_MAX_TASK)
6369 lp->ia_tag = 0;
6370 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba);
6371 ++lp->busy_itlq;
6372 lp->head.resel_sa =
6373 cpu_to_scr(SCRIPTA_BA (np, resel_tag));
6374 }
6375 else
6376 goto out_free;
6377 }
6378 /*
6379 * This command will not be tagged.
6380 * If we already have either a tagged or untagged
6381 * one, refuse to overlap this untagged one.
6382 */
6383 else {
6384 /*
6385 * Debugging purpose.
6386 */
6387 assert(lp->busy_itl == 0 && lp->busy_itlq == 0);
6388 /*
6389 * Count this nexus for this LUN.
6390 * Set up the CCB bus address for reselection.
6391 * Toggle reselect path to untagged.
6392 */
6393 if (++lp->busy_itl == 1) {
6394 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
6395 lp->head.resel_sa =
6396 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag));
6397 }
6398 else
6399 goto out_free;
6400 }
6401 }
6402 /*
6403 * Put the CCB into the busy queue.
6404 */
6405 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
6406
6407 /*
6408 * Remember all informations needed to free this CCB.
6409 */
6410 cp->to_abort = 0;
6411 cp->tag = tag;
6412 cp->target = tn;
6413 cp->lun = ln;
6414
6415 if (DEBUG_FLAGS & DEBUG_TAGS) {
6416 PRINT_LUN(np, tn, ln);
6417 printf ("ccb @%p using tag %d.\n", cp, tag);
6418 }
6419
6420 out:
6421 return cp;
6422 out_free:
6423 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
6424 return NULL;
6425 }
6426
6427 /*
6428 * Release one control block
6429 */
6430 static void sym_free_ccb (hcb_p np, ccb_p cp)
6431 {
6432 tcb_p tp = &np->target[cp->target];
6433 lcb_p lp = sym_lp(np, tp, cp->lun);
6434
6435 if (DEBUG_FLAGS & DEBUG_TAGS) {
6436 PRINT_LUN(np, cp->target, cp->lun);
6437 printf ("ccb @%p freeing tag %d.\n", cp, cp->tag);
6438 }
6439
6440 /*
6441 * If LCB available,
6442 */
6443 if (lp) {
6444 /*
6445 * If tagged, release the tag, set the relect path
6446 */
6447 if (cp->tag != NO_TAG) {
6448 /*
6449 * Free the tag value.
6450 */
6451 lp->cb_tags[lp->if_tag] = cp->tag;
6452 if (++lp->if_tag == SYM_CONF_MAX_TASK)
6453 lp->if_tag = 0;
6454 /*
6455 * Make the reselect path invalid,
6456 * and uncount this CCB.
6457 */
6458 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba);
6459 --lp->busy_itlq;
6460 } else { /* Untagged */
6461 /*
6462 * Make the reselect path invalid,
6463 * and uncount this CCB.
6464 */
6465 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
6466 --lp->busy_itl;
6467 }
6468 /*
6469 * If no JOB active, make the LUN reselect path invalid.
6470 */
6471 if (lp->busy_itlq == 0 && lp->busy_itl == 0)
6472 lp->head.resel_sa =
6473 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun));
6474 }
6475 /*
6476 * Otherwise, we only accept 1 IO per LUN.
6477 * Clear the bit that keeps track of this IO.
6478 */
6479 else
6480 sym_clr_bit(tp->busy0_map, cp->lun);
6481
6482 /*
6483 * We donnot queue more than 1 ccb per target
6484 * with negotiation at any time. If this ccb was
6485 * used for negotiation, clear this info in the tcb.
6486 */
6487 if (cp == tp->nego_cp)
6488 tp->nego_cp = NULL;
6489
6490 #ifdef SYM_CONF_IARB_SUPPORT
6491 /*
6492 * If we just complete the last queued CCB,
6493 * clear this info that is no longer relevant.
6494 */
6495 if (cp == np->last_cp)
6496 np->last_cp = NULL;
6497 #endif
6498
6499 /*
6500 * Unmap user data from DMA map if needed.
6501 */
6502 if (cp->dmamapped) {
6503 bus_dmamap_unload(np->data_dmat, cp->dmamap);
6504 cp->dmamapped = 0;
6505 }
6506
6507 /*
6508 * Make this CCB available.
6509 */
6510 cp->cam_ccb = NULL;
6511 cp->host_status = HS_IDLE;
6512 sym_remque(&cp->link_ccbq);
6513 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
6514 }
6515
6516 /*
6517 * Allocate a CCB from memory and initialize its fixed part.
6518 */
6519 static ccb_p sym_alloc_ccb(hcb_p np)
6520 {
6521 ccb_p cp = NULL;
6522 int hcode;
6523
6524 /*
6525 * Prevent from allocating more CCBs than we can
6526 * queue to the controller.
6527 */
6528 if (np->actccbs >= SYM_CONF_MAX_START)
6529 return NULL;
6530
6531 /*
6532 * Allocate memory for this CCB.
6533 */
6534 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB");
6535 if (!cp)
6536 goto out_free;
6537
6538 /*
6539 * Allocate a bounce buffer for sense data.
6540 */
6541 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF");
6542 if (!cp->sns_bbuf)
6543 goto out_free;
6544
6545 /*
6546 * Allocate a map for the DMA of user data.
6547 */
6548 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap))
6549 goto out_free;
6550 /*
6551 * Count it.
6552 */
6553 np->actccbs++;
6554
6555 /*
6556 * Compute the bus address of this ccb.
6557 */
6558 cp->ccb_ba = vtobus(cp);
6559
6560 /*
6561 * Insert this ccb into the hashed list.
6562 */
6563 hcode = CCB_HASH_CODE(cp->ccb_ba);
6564 cp->link_ccbh = np->ccbh[hcode];
6565 np->ccbh[hcode] = cp;
6566
6567 /*
6568 * Initialize the start and restart actions.
6569 */
6570 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle));
6571 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
6572
6573 /*
6574 * Initilialyze some other fields.
6575 */
6576 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2]));
6577
6578 /*
6579 * Chain into free ccb queue.
6580 */
6581 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
6582
6583 return cp;
6584 out_free:
6585 if (cp) {
6586 if (cp->sns_bbuf)
6587 sym_mfree_dma(cp->sns_bbuf,SYM_SNS_BBUF_LEN,"SNS_BBUF");
6588 sym_mfree_dma(cp, sizeof(*cp), "CCB");
6589 }
6590 return NULL;
6591 }
6592
6593 /*
6594 * Look up a CCB from a DSA value.
6595 */
6596 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa)
6597 {
6598 int hcode;
6599 ccb_p cp;
6600
6601 hcode = CCB_HASH_CODE(dsa);
6602 cp = np->ccbh[hcode];
6603 while (cp) {
6604 if (cp->ccb_ba == dsa)
6605 break;
6606 cp = cp->link_ccbh;
6607 }
6608
6609 return cp;
6610 }
6611
6612 /*
6613 * Target control block initialisation.
6614 * Nothing important to do at the moment.
6615 */
6616 static void sym_init_tcb (hcb_p np, u_char tn)
6617 {
6618 /*
6619 * Check some alignments required by the chip.
6620 */
6621 assert (((offsetof(struct sym_reg, nc_sxfer) ^
6622 offsetof(struct sym_tcb, head.sval)) &3) == 0);
6623 assert (((offsetof(struct sym_reg, nc_scntl3) ^
6624 offsetof(struct sym_tcb, head.wval)) &3) == 0);
6625 }
6626
6627 /*
6628 * Lun control block allocation and initialization.
6629 */
6630 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln)
6631 {
6632 tcb_p tp = &np->target[tn];
6633 lcb_p lp = sym_lp(np, tp, ln);
6634
6635 /*
6636 * Already done, just return.
6637 */
6638 if (lp)
6639 return lp;
6640 /*
6641 * Check against some race.
6642 */
6643 assert(!sym_is_bit(tp->busy0_map, ln));
6644
6645 /*
6646 * Initialize the target control block if not yet.
6647 */
6648 sym_init_tcb (np, tn);
6649
6650 /*
6651 * Allocate the LCB bus address array.
6652 * Compute the bus address of this table.
6653 */
6654 if (ln && !tp->luntbl) {
6655 int i;
6656
6657 tp->luntbl = sym_calloc_dma(256, "LUNTBL");
6658 if (!tp->luntbl)
6659 goto fail;
6660 for (i = 0 ; i < 64 ; i++)
6661 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
6662 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl));
6663 }
6664
6665 /*
6666 * Allocate the table of pointers for LUN(s) > 0, if needed.
6667 */
6668 if (ln && !tp->lunmp) {
6669 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p),
6670 "LUNMP");
6671 if (!tp->lunmp)
6672 goto fail;
6673 }
6674
6675 /*
6676 * Allocate the lcb.
6677 * Make it available to the chip.
6678 */
6679 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB");
6680 if (!lp)
6681 goto fail;
6682 if (ln) {
6683 tp->lunmp[ln] = lp;
6684 tp->luntbl[ln] = cpu_to_scr(vtobus(lp));
6685 }
6686 else {
6687 tp->lun0p = lp;
6688 tp->head.lun0_sa = cpu_to_scr(vtobus(lp));
6689 }
6690
6691 /*
6692 * Let the itl task point to error handling.
6693 */
6694 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
6695
6696 /*
6697 * Set the reselect pattern to our default. :)
6698 */
6699 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun));
6700
6701 /*
6702 * Set user capabilities.
6703 */
6704 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
6705
6706 fail:
6707 return lp;
6708 }
6709
6710 /*
6711 * Allocate LCB resources for tagged command queuing.
6712 */
6713 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln)
6714 {
6715 tcb_p tp = &np->target[tn];
6716 lcb_p lp = sym_lp(np, tp, ln);
6717 int i;
6718
6719 /*
6720 * If LCB not available, try to allocate it.
6721 */
6722 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln)))
6723 return;
6724
6725 /*
6726 * Allocate the task table and and the tag allocation
6727 * circular buffer. We want both or none.
6728 */
6729 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
6730 if (!lp->itlq_tbl)
6731 return;
6732 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS");
6733 if (!lp->cb_tags) {
6734 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
6735 lp->itlq_tbl = 0;
6736 return;
6737 }
6738
6739 /*
6740 * Initialize the task table with invalid entries.
6741 */
6742 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
6743 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba);
6744
6745 /*
6746 * Fill up the tag buffer with tag numbers.
6747 */
6748 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
6749 lp->cb_tags[i] = i;
6750
6751 /*
6752 * Make the task table available to SCRIPTS,
6753 * And accept tagged commands now.
6754 */
6755 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl));
6756 }
6757
6758 /*
6759 * Test the pci bus snoop logic :-(
6760 *
6761 * Has to be called with interrupts disabled.
6762 */
6763 #ifndef SYM_CONF_IOMAPPED
6764 static int sym_regtest (hcb_p np)
6765 {
6766 register volatile u32 data;
6767 /*
6768 * chip registers may NOT be cached.
6769 * write 0xffffffff to a read only register area,
6770 * and try to read it back.
6771 */
6772 data = 0xffffffff;
6773 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data);
6774 data = INL_OFF(offsetof(struct sym_reg, nc_dstat));
6775 #if 1
6776 if (data == 0xffffffff) {
6777 #else
6778 if ((data & 0xe2f0fffd) != 0x02000080) {
6779 #endif
6780 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
6781 (unsigned) data);
6782 return (0x10);
6783 };
6784 return (0);
6785 }
6786 #endif
6787
6788 static int sym_snooptest (hcb_p np)
6789 {
6790 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat;
6791 int i, err=0;
6792 #ifndef SYM_CONF_IOMAPPED
6793 err |= sym_regtest (np);
6794 if (err) return (err);
6795 #endif
6796 restart_test:
6797 /*
6798 * Enable Master Parity Checking as we intend
6799 * to enable it for normal operations.
6800 */
6801 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE));
6802 /*
6803 * init
6804 */
6805 pc = SCRIPTB0_BA (np, snooptest);
6806 host_wr = 1;
6807 sym_wr = 2;
6808 /*
6809 * Set memory and register.
6810 */
6811 np->cache = cpu_to_scr(host_wr);
6812 OUTL (nc_temp, sym_wr);
6813 /*
6814 * Start script (exchange values)
6815 */
6816 OUTL (nc_dsa, np->hcb_ba);
6817 OUTL_DSP (pc);
6818 /*
6819 * Wait 'til done (with timeout)
6820 */
6821 for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
6822 if (INB(nc_istat) & (INTF|SIP|DIP))
6823 break;
6824 if (i>=SYM_SNOOP_TIMEOUT) {
6825 printf ("CACHE TEST FAILED: timeout.\n");
6826 return (0x20);
6827 };
6828 /*
6829 * Check for fatal DMA errors.
6830 */
6831 dstat = INB (nc_dstat);
6832 #if 1 /* Band aiding for broken hardwares that fail PCI parity */
6833 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) {
6834 printf ("%s: PCI DATA PARITY ERROR DETECTED - "
6835 "DISABLING MASTER DATA PARITY CHECKING.\n",
6836 sym_name(np));
6837 np->rv_ctest4 &= ~MPEE;
6838 goto restart_test;
6839 }
6840 #endif
6841 if (dstat & (MDPE|BF|IID)) {
6842 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat);
6843 return (0x80);
6844 }
6845 /*
6846 * Save termination position.
6847 */
6848 pc = INL (nc_dsp);
6849 /*
6850 * Read memory and register.
6851 */
6852 host_rd = scr_to_cpu(np->cache);
6853 sym_rd = INL (nc_scratcha);
6854 sym_bk = INL (nc_temp);
6855
6856 /*
6857 * Check termination position.
6858 */
6859 if (pc != SCRIPTB0_BA (np, snoopend)+8) {
6860 printf ("CACHE TEST FAILED: script execution failed.\n");
6861 printf ("start=%08lx, pc=%08lx, end=%08lx\n",
6862 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc,
6863 (u_long) SCRIPTB0_BA (np, snoopend) +8);
6864 return (0x40);
6865 };
6866 /*
6867 * Show results.
6868 */
6869 if (host_wr != sym_rd) {
6870 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n",
6871 (int) host_wr, (int) sym_rd);
6872 err |= 1;
6873 };
6874 if (host_rd != sym_wr) {
6875 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n",
6876 (int) sym_wr, (int) host_rd);
6877 err |= 2;
6878 };
6879 if (sym_bk != sym_wr) {
6880 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n",
6881 (int) sym_wr, (int) sym_bk);
6882 err |= 4;
6883 };
6884
6885 return (err);
6886 }
6887
6888 /*
6889 * Determine the chip's clock frequency.
6890 *
6891 * This is essential for the negotiation of the synchronous
6892 * transfer rate.
6893 *
6894 * Note: we have to return the correct value.
6895 * THERE IS NO SAFE DEFAULT VALUE.
6896 *
6897 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
6898 * 53C860 and 53C875 rev. 1 support fast20 transfers but
6899 * do not have a clock doubler and so are provided with a
6900 * 80 MHz clock. All other fast20 boards incorporate a doubler
6901 * and so should be delivered with a 40 MHz clock.
6902 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base
6903 * clock and provide a clock quadrupler (160 Mhz).
6904 */
6905
6906 /*
6907 * Select SCSI clock frequency
6908 */
6909 static void sym_selectclock(hcb_p np, u_char scntl3)
6910 {
6911 /*
6912 * If multiplier not present or not selected, leave here.
6913 */
6914 if (np->multiplier <= 1) {
6915 OUTB(nc_scntl3, scntl3);
6916 return;
6917 }
6918
6919 if (sym_verbose >= 2)
6920 printf ("%s: enabling clock multiplier\n", sym_name(np));
6921
6922 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */
6923 /*
6924 * Wait for the LCKFRQ bit to be set if supported by the chip.
6925 * Otherwise wait 20 micro-seconds.
6926 */
6927 if (np->features & FE_LCKFRQ) {
6928 int i = 20;
6929 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0)
6930 UDELAY (20);
6931 if (!i)
6932 printf("%s: the chip cannot lock the frequency\n",
6933 sym_name(np));
6934 } else
6935 UDELAY (20);
6936 OUTB(nc_stest3, HSC); /* Halt the scsi clock */
6937 OUTB(nc_scntl3, scntl3);
6938 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
6939 OUTB(nc_stest3, 0x00); /* Restart scsi clock */
6940 }
6941
6942 /*
6943 * calculate SCSI clock frequency (in KHz)
6944 */
6945 static unsigned getfreq (hcb_p np, int gen)
6946 {
6947 unsigned int ms = 0;
6948 unsigned int f;
6949
6950 /*
6951 * Measure GEN timer delay in order
6952 * to calculate SCSI clock frequency
6953 *
6954 * This code will never execute too
6955 * many loop iterations (if DELAY is
6956 * reasonably correct). It could get
6957 * too low a delay (too high a freq.)
6958 * if the CPU is slow executing the
6959 * loop for some reason (an NMI, for
6960 * example). For this reason we will
6961 * if multiple measurements are to be
6962 * performed trust the higher delay
6963 * (lower frequency returned).
6964 */
6965 OUTW (nc_sien , 0); /* mask all scsi interrupts */
6966 (void) INW (nc_sist); /* clear pending scsi interrupt */
6967 OUTB (nc_dien , 0); /* mask all dma interrupts */
6968 (void) INW (nc_sist); /* another one, just to be sure :) */
6969 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */
6970 OUTB (nc_stime1, 0); /* disable general purpose timer */
6971 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
6972 while (!(INW(nc_sist) & GEN) && ms++ < 100000)
6973 UDELAY (1000); /* count ms */
6974 OUTB (nc_stime1, 0); /* disable general purpose timer */
6975 /*
6976 * set prescaler to divide by whatever 0 means
6977 * 0 ought to choose divide by 2, but appears
6978 * to set divide by 3.5 mode in my 53c810 ...
6979 */
6980 OUTB (nc_scntl3, 0);
6981
6982 /*
6983 * adjust for prescaler, and convert into KHz
6984 */
6985 f = ms ? ((1 << gen) * 4340) / ms : 0;
6986
6987 if (sym_verbose >= 2)
6988 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n",
6989 sym_name(np), gen, ms, f);
6990
6991 return f;
6992 }
6993
6994 static unsigned sym_getfreq (hcb_p np)
6995 {
6996 u_int f1, f2;
6997 int gen = 11;
6998
6999 (void) getfreq (np, gen); /* throw away first result */
7000 f1 = getfreq (np, gen);
7001 f2 = getfreq (np, gen);
7002 if (f1 > f2) f1 = f2; /* trust lower result */
7003 return f1;
7004 }
7005
7006 /*
7007 * Get/probe chip SCSI clock frequency
7008 */
7009 static void sym_getclock (hcb_p np, int mult)
7010 {
7011 unsigned char scntl3 = np->sv_scntl3;
7012 unsigned char stest1 = np->sv_stest1;
7013 unsigned f1;
7014
7015 /*
7016 * For the C10 core, assume 40 MHz.
7017 */
7018 if (np->features & FE_C10) {
7019 np->multiplier = mult;
7020 np->clock_khz = 40000 * mult;
7021 return;
7022 }
7023
7024 np->multiplier = 1;
7025 f1 = 40000;
7026 /*
7027 * True with 875/895/896/895A with clock multiplier selected
7028 */
7029 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
7030 if (sym_verbose >= 2)
7031 printf ("%s: clock multiplier found\n", sym_name(np));
7032 np->multiplier = mult;
7033 }
7034
7035 /*
7036 * If multiplier not found or scntl3 not 7,5,3,
7037 * reset chip and get frequency from general purpose timer.
7038 * Otherwise trust scntl3 BIOS setting.
7039 */
7040 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
7041 OUTB (nc_stest1, 0); /* make sure doubler is OFF */
7042 f1 = sym_getfreq (np);
7043
7044 if (sym_verbose)
7045 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1);
7046
7047 if (f1 < 45000) f1 = 40000;
7048 else if (f1 < 55000) f1 = 50000;
7049 else f1 = 80000;
7050
7051 if (f1 < 80000 && mult > 1) {
7052 if (sym_verbose >= 2)
7053 printf ("%s: clock multiplier assumed\n",
7054 sym_name(np));
7055 np->multiplier = mult;
7056 }
7057 } else {
7058 if ((scntl3 & 7) == 3) f1 = 40000;
7059 else if ((scntl3 & 7) == 5) f1 = 80000;
7060 else f1 = 160000;
7061
7062 f1 /= np->multiplier;
7063 }
7064
7065 /*
7066 * Compute controller synchronous parameters.
7067 */
7068 f1 *= np->multiplier;
7069 np->clock_khz = f1;
7070 }
7071
7072 /*
7073 * Get/probe PCI clock frequency
7074 */
7075 static int sym_getpciclock (hcb_p np)
7076 {
7077 int f = 0;
7078
7079 /*
7080 * For the C1010-33, this doesn't work.
7081 * For the C1010-66, this will be tested when I'll have
7082 * such a beast to play with.
7083 */
7084 if (!(np->features & FE_C10)) {
7085 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
7086 f = (int) sym_getfreq (np);
7087 OUTB (nc_stest1, 0);
7088 }
7089 np->pciclk_khz = f;
7090
7091 return f;
7092 }
7093
7094 /*============= DRIVER ACTION/COMPLETION ====================*/
7095
7096 /*
7097 * Print something that tells about extended errors.
7098 */
7099 static void sym_print_xerr(ccb_p cp, int x_status)
7100 {
7101 if (x_status & XE_PARITY_ERR) {
7102 PRINT_ADDR(cp);
7103 printf ("unrecovered SCSI parity error.\n");
7104 }
7105 if (x_status & XE_EXTRA_DATA) {
7106 PRINT_ADDR(cp);
7107 printf ("extraneous data discarded.\n");
7108 }
7109 if (x_status & XE_BAD_PHASE) {
7110 PRINT_ADDR(cp);
7111 printf ("illegal scsi phase (4/5).\n");
7112 }
7113 if (x_status & XE_SODL_UNRUN) {
7114 PRINT_ADDR(cp);
7115 printf ("ODD transfer in DATA OUT phase.\n");
7116 }
7117 if (x_status & XE_SWIDE_OVRUN) {
7118 PRINT_ADDR(cp);
7119 printf ("ODD transfer in DATA IN phase.\n");
7120 }
7121 }
7122
7123 /*
7124 * Choose the more appropriate CAM status if
7125 * the IO encountered an extended error.
7126 */
7127 static int sym_xerr_cam_status(int cam_status, int x_status)
7128 {
7129 if (x_status) {
7130 if (x_status & XE_PARITY_ERR)
7131 cam_status = CAM_UNCOR_PARITY;
7132 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN))
7133 cam_status = CAM_DATA_RUN_ERR;
7134 else if (x_status & XE_BAD_PHASE)
7135 cam_status = CAM_REQ_CMP_ERR;
7136 else
7137 cam_status = CAM_REQ_CMP_ERR;
7138 }
7139 return cam_status;
7140 }
7141
7142 /*
7143 * Complete execution of a SCSI command with extented
7144 * error, SCSI status error, or having been auto-sensed.
7145 *
7146 * The SCRIPTS processor is not running there, so we
7147 * can safely access IO registers and remove JOBs from
7148 * the START queue.
7149 * SCRATCHA is assumed to have been loaded with STARTPOS
7150 * before the SCRIPTS called the C code.
7151 */
7152 static void sym_complete_error (hcb_p np, ccb_p cp)
7153 {
7154 struct ccb_scsiio *csio;
7155 u_int cam_status;
7156 int i;
7157
7158 /*
7159 * Paranoid check. :)
7160 */
7161 if (!cp || !cp->cam_ccb)
7162 return;
7163
7164 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) {
7165 printf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp,
7166 cp->host_status, cp->ssss_status, cp->host_flags,
7167 cp->target, cp->lun);
7168 MDELAY(100);
7169 }
7170
7171 /*
7172 * Get CAM command pointer.
7173 */
7174 csio = &cp->cam_ccb->csio;
7175
7176 /*
7177 * Check for extended errors.
7178 */
7179 if (cp->xerr_status) {
7180 if (sym_verbose)
7181 sym_print_xerr(cp, cp->xerr_status);
7182 if (cp->host_status == HS_COMPLETE)
7183 cp->host_status = HS_COMP_ERR;
7184 }
7185
7186 /*
7187 * Calculate the residual.
7188 */
7189 csio->sense_resid = 0;
7190 csio->resid = sym_compute_residual(np, cp);
7191
7192 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */
7193 csio->resid = 0; /* throw them away. :) */
7194 cp->sv_resid = 0;
7195 }
7196
7197 if (cp->host_flags & HF_SENSE) { /* Auto sense */
7198 csio->scsi_status = cp->sv_scsi_status; /* Restore status */
7199 csio->sense_resid = csio->resid; /* Swap residuals */
7200 csio->resid = cp->sv_resid;
7201 cp->sv_resid = 0;
7202 if (sym_verbose && cp->sv_xerr_status)
7203 sym_print_xerr(cp, cp->sv_xerr_status);
7204 if (cp->host_status == HS_COMPLETE &&
7205 cp->ssss_status == S_GOOD &&
7206 cp->xerr_status == 0) {
7207 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR,
7208 cp->sv_xerr_status);
7209 cam_status |= CAM_AUTOSNS_VALID;
7210 /*
7211 * Bounce back the sense data to user and
7212 * fix the residual.
7213 */
7214 bzero(&csio->sense_data, csio->sense_len);
7215 bcopy(cp->sns_bbuf, &csio->sense_data,
7216 MIN(csio->sense_len, SYM_SNS_BBUF_LEN));
7217 csio->sense_resid += csio->sense_len;
7218 csio->sense_resid -= SYM_SNS_BBUF_LEN;
7219 #if 0
7220 /*
7221 * If the device reports a UNIT ATTENTION condition
7222 * due to a RESET condition, we should consider all
7223 * disconnect CCBs for this unit as aborted.
7224 */
7225 if (1) {
7226 u_char *p;
7227 p = (u_char *) csio->sense_data;
7228 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29)
7229 sym_clear_tasks(np, CAM_REQ_ABORTED,
7230 cp->target,cp->lun, -1);
7231 }
7232 #endif
7233 }
7234 else
7235 cam_status = CAM_AUTOSENSE_FAIL;
7236 }
7237 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */
7238 csio->scsi_status = cp->ssss_status;
7239 cam_status = CAM_SCSI_STATUS_ERROR;
7240 }
7241 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */
7242 cam_status = CAM_SEL_TIMEOUT;
7243 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/
7244 cam_status = CAM_UNEXP_BUSFREE;
7245 else { /* Extended error */
7246 if (sym_verbose) {
7247 PRINT_ADDR(cp);
7248 printf ("COMMAND FAILED (%x %x %x).\n",
7249 cp->host_status, cp->ssss_status,
7250 cp->xerr_status);
7251 }
7252 csio->scsi_status = cp->ssss_status;
7253 /*
7254 * Set the most appropriate value for CAM status.
7255 */
7256 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR,
7257 cp->xerr_status);
7258 }
7259
7260 /*
7261 * Dequeue all queued CCBs for that device
7262 * not yet started by SCRIPTS.
7263 */
7264 i = (INL (nc_scratcha) - np->squeue_ba) / 4;
7265 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
7266
7267 /*
7268 * Restart the SCRIPTS processor.
7269 */
7270 OUTL_DSP (SCRIPTA_BA (np, start));
7271
7272 /*
7273 * Synchronize DMA map if needed.
7274 */
7275 if (cp->dmamapped) {
7276 bus_dmamap_sync(np->data_dmat, cp->dmamap,
7277 (cp->dmamapped == SYM_DMA_READ ?
7278 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE));
7279 }
7280 /*
7281 * Add this one to the COMP queue.
7282 * Complete all those commands with either error
7283 * or requeue condition.
7284 */
7285 sym_set_cam_status((union ccb *) csio, cam_status);
7286 sym_remque(&cp->link_ccbq);
7287 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq);
7288 sym_flush_comp_queue(np, 0);
7289 }
7290
7291 /*
7292 * Complete execution of a successful SCSI command.
7293 *
7294 * Only successful commands go to the DONE queue,
7295 * since we need to have the SCRIPTS processor
7296 * stopped on any error condition.
7297 * The SCRIPTS processor is running while we are
7298 * completing successful commands.
7299 */
7300 static void sym_complete_ok (hcb_p np, ccb_p cp)
7301 {
7302 struct ccb_scsiio *csio;
7303 tcb_p tp;
7304 lcb_p lp;
7305
7306 /*
7307 * Paranoid check. :)
7308 */
7309 if (!cp || !cp->cam_ccb)
7310 return;
7311 assert (cp->host_status == HS_COMPLETE);
7312
7313 /*
7314 * Get command, target and lun pointers.
7315 */
7316 csio = &cp->cam_ccb->csio;
7317 tp = &np->target[cp->target];
7318 lp = sym_lp(np, tp, cp->lun);
7319
7320 /*
7321 * Assume device discovered on first success.
7322 */
7323 if (!lp)
7324 sym_set_bit(tp->lun_map, cp->lun);
7325
7326 /*
7327 * If all data have been transferred, given than no
7328 * extended error did occur, there is no residual.
7329 */
7330 csio->resid = 0;
7331 if (cp->phys.head.lastp != cp->phys.head.goalp)
7332 csio->resid = sym_compute_residual(np, cp);
7333
7334 /*
7335 * Wrong transfer residuals may be worse than just always
7336 * returning zero. User can disable this feature from
7337 * sym_conf.h. Residual support is enabled by default.
7338 */
7339 if (!SYM_CONF_RESIDUAL_SUPPORT)
7340 csio->resid = 0;
7341
7342 /*
7343 * Synchronize DMA map if needed.
7344 */
7345 if (cp->dmamapped) {
7346 bus_dmamap_sync(np->data_dmat, cp->dmamap,
7347 (cp->dmamapped == SYM_DMA_READ ?
7348 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE));
7349 }
7350 /*
7351 * Set status and complete the command.
7352 */
7353 csio->scsi_status = cp->ssss_status;
7354 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP);
7355 sym_free_ccb (np, cp);
7356 sym_xpt_done(np, (union ccb *) csio);
7357 }
7358
7359 /*
7360 * Our timeout handler.
7361 */
7362 static void sym_timeout1(void *arg)
7363 {
7364 union ccb *ccb = (union ccb *) arg;
7365 hcb_p np = ccb->ccb_h.sym_hcb_ptr;
7366
7367 /*
7368 * Check that the CAM CCB is still queued.
7369 */
7370 if (!np)
7371 return;
7372
7373 switch(ccb->ccb_h.func_code) {
7374 case XPT_SCSI_IO:
7375 (void) sym_abort_scsiio(np, ccb, 1);
7376 break;
7377 default:
7378 break;
7379 }
7380 }
7381
7382 static void sym_timeout(void *arg)
7383 {
7384 int s = splcam();
7385 sym_timeout1(arg);
7386 splx(s);
7387 }
7388
7389 /*
7390 * Abort an SCSI IO.
7391 */
7392 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out)
7393 {
7394 ccb_p cp;
7395 SYM_QUEHEAD *qp;
7396
7397 /*
7398 * Look up our CCB control block.
7399 */
7400 cp = NULL;
7401 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
7402 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq);
7403 if (cp2->cam_ccb == ccb) {
7404 cp = cp2;
7405 break;
7406 }
7407 }
7408 if (!cp || cp->host_status == HS_WAIT)
7409 return -1;
7410
7411 /*
7412 * If a previous abort didn't succeed in time,
7413 * perform a BUS reset.
7414 */
7415 if (cp->to_abort) {
7416 sym_reset_scsi_bus(np, 1);
7417 return 0;
7418 }
7419
7420 /*
7421 * Mark the CCB for abort and allow time for.
7422 */
7423 cp->to_abort = timed_out ? 2 : 1;
7424 ccb->ccb_h.timeout_ch = timeout(sym_timeout, (caddr_t) ccb, 10*hz);
7425
7426 /*
7427 * Tell the SCRIPTS processor to stop and synchronize with us.
7428 */
7429 np->istat_sem = SEM;
7430 OUTB (nc_istat, SIGP|SEM);
7431 return 0;
7432 }
7433
7434 /*
7435 * Reset a SCSI device (all LUNs of a target).
7436 */
7437 static void sym_reset_dev(hcb_p np, union ccb *ccb)
7438 {
7439 tcb_p tp;
7440 struct ccb_hdr *ccb_h = &ccb->ccb_h;
7441
7442 if (ccb_h->target_id == np->myaddr ||
7443 ccb_h->target_id >= SYM_CONF_MAX_TARGET ||
7444 ccb_h->target_lun >= SYM_CONF_MAX_LUN) {
7445 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE);
7446 return;
7447 }
7448
7449 tp = &np->target[ccb_h->target_id];
7450
7451 tp->to_reset = 1;
7452 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
7453
7454 np->istat_sem = SEM;
7455 OUTB (nc_istat, SIGP|SEM);
7456 }
7457
7458 /*
7459 * SIM action entry point.
7460 */
7461 static void sym_action(struct cam_sim *sim, union ccb *ccb)
7462 {
7463 int s = splcam();
7464 sym_action1(sim, ccb);
7465 splx(s);
7466 }
7467
7468 static void sym_action1(struct cam_sim *sim, union ccb *ccb)
7469 {
7470 hcb_p np;
7471 tcb_p tp;
7472 lcb_p lp;
7473 ccb_p cp;
7474 int tmp;
7475 u_char idmsg, *msgptr;
7476 u_int msglen;
7477 struct ccb_scsiio *csio;
7478 struct ccb_hdr *ccb_h;
7479
7480 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n"));
7481
7482 /*
7483 * Retrieve our controller data structure.
7484 */
7485 np = (hcb_p) cam_sim_softc(sim);
7486
7487 /*
7488 * The common case is SCSI IO.
7489 * We deal with other ones elsewhere.
7490 */
7491 if (ccb->ccb_h.func_code != XPT_SCSI_IO) {
7492 sym_action2(sim, ccb);
7493 return;
7494 }
7495 csio = &ccb->csio;
7496 ccb_h = &csio->ccb_h;
7497
7498 /*
7499 * Work around races.
7500 */
7501 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
7502 xpt_done(ccb);
7503 return;
7504 }
7505
7506 /*
7507 * Minimal checkings, so that we will not
7508 * go outside our tables.
7509 */
7510 if (ccb_h->target_id == np->myaddr ||
7511 ccb_h->target_id >= SYM_CONF_MAX_TARGET ||
7512 ccb_h->target_lun >= SYM_CONF_MAX_LUN) {
7513 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE);
7514 return;
7515 }
7516
7517 /*
7518 * Retreive the target and lun descriptors.
7519 */
7520 tp = &np->target[ccb_h->target_id];
7521 lp = sym_lp(np, tp, ccb_h->target_lun);
7522
7523 /*
7524 * Complete the 1st INQUIRY command with error
7525 * condition if the device is flagged NOSCAN
7526 * at BOOT in the NVRAM. This may speed up
7527 * the boot and maintain coherency with BIOS
7528 * device numbering. Clearing the flag allows
7529 * user to rescan skipped devices later.
7530 * We also return error for devices not flagged
7531 * for SCAN LUNS in the NVRAM since some mono-lun
7532 * devices behave badly when asked for some non
7533 * zero LUN. Btw, this is an absolute hack.:-)
7534 */
7535 if (!(ccb_h->flags & CAM_CDB_PHYS) &&
7536 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ?
7537 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) {
7538 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) ||
7539 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) &&
7540 ccb_h->target_lun != 0)) {
7541 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED;
7542 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE);
7543 return;
7544 }
7545 }
7546
7547 /*
7548 * Get a control block for this IO.
7549 */
7550 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0);
7551 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp);
7552 if (!cp) {
7553 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL);
7554 return;
7555 }
7556
7557 /*
7558 * Keep track of the IO in our CCB.
7559 */
7560 cp->cam_ccb = ccb;
7561
7562 /*
7563 * Build the IDENTIFY message.
7564 */
7565 idmsg = M_IDENTIFY | cp->lun;
7566 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED)))
7567 idmsg |= 0x40;
7568
7569 msgptr = cp->scsi_smsg;
7570 msglen = 0;
7571 msgptr[msglen++] = idmsg;
7572
7573 /*
7574 * Build the tag message if present.
7575 */
7576 if (cp->tag != NO_TAG) {
7577 u_char order = csio->tag_action;
7578
7579 switch(order) {
7580 case M_ORDERED_TAG:
7581 break;
7582 case M_HEAD_TAG:
7583 break;
7584 default:
7585 order = M_SIMPLE_TAG;
7586 }
7587 msgptr[msglen++] = order;
7588
7589 /*
7590 * For less than 128 tags, actual tags are numbered
7591 * 1,3,5,..2*MAXTAGS+1,since we may have to deal
7592 * with devices that have problems with #TAG 0 or too
7593 * great #TAG numbers. For more tags (up to 256),
7594 * we use directly our tag number.
7595 */
7596 #if SYM_CONF_MAX_TASK > (512/4)
7597 msgptr[msglen++] = cp->tag;
7598 #else
7599 msgptr[msglen++] = (cp->tag << 1) + 1;
7600 #endif
7601 }
7602
7603 /*
7604 * Build a negotiation message if needed.
7605 * (nego_status is filled by sym_prepare_nego())
7606 */
7607 cp->nego_status = 0;
7608 if (tp->tinfo.current.width != tp->tinfo.goal.width ||
7609 tp->tinfo.current.period != tp->tinfo.goal.period ||
7610 tp->tinfo.current.offset != tp->tinfo.goal.offset ||
7611 tp->tinfo.current.options != tp->tinfo.goal.options) {
7612 if (!tp->nego_cp && lp)
7613 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen);
7614 }
7615
7616 /*
7617 * Fill in our ccb
7618 */
7619
7620 /*
7621 * Startqueue
7622 */
7623 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select));
7624 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa));
7625
7626 /*
7627 * select
7628 */
7629 cp->phys.select.sel_id = cp->target;
7630 cp->phys.select.sel_scntl3 = tp->head.wval;
7631 cp->phys.select.sel_sxfer = tp->head.sval;
7632 cp->phys.select.sel_scntl4 = tp->head.uval;
7633
7634 /*
7635 * message
7636 */
7637 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg));
7638 cp->phys.smsg.size = cpu_to_scr(msglen);
7639
7640 /*
7641 * command
7642 */
7643 if (sym_setup_cdb(np, csio, cp) < 0) {
7644 sym_free_ccb(np, cp);
7645 sym_xpt_done(np, ccb);
7646 return;
7647 }
7648
7649 /*
7650 * status
7651 */
7652 #if 0 /* Provision */
7653 cp->actualquirks = tp->quirks;
7654 #endif
7655 cp->actualquirks = SYM_QUIRK_AUTOSAVE;
7656 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
7657 cp->ssss_status = S_ILLEGAL;
7658 cp->xerr_status = 0;
7659 cp->host_flags = 0;
7660 cp->extra_bytes = 0;
7661
7662 /*
7663 * extreme data pointer.
7664 * shall be positive, so -1 is lower than lowest.:)
7665 */
7666 cp->ext_sg = -1;
7667 cp->ext_ofs = 0;
7668
7669 /*
7670 * Build the data descriptor block
7671 * and start the IO.
7672 */
7673 sym_setup_data_and_start(np, csio, cp);
7674 }
7675
7676 /*
7677 * Setup buffers and pointers that address the CDB.
7678 * I bet, physical CDBs will never be used on the planet,
7679 * since they can be bounced without significant overhead.
7680 */
7681 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp)
7682 {
7683 struct ccb_hdr *ccb_h;
7684 u32 cmd_ba;
7685 int cmd_len;
7686
7687 ccb_h = &csio->ccb_h;
7688
7689 /*
7690 * CDB is 16 bytes max.
7691 */
7692 if (csio->cdb_len > sizeof(cp->cdb_buf)) {
7693 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7694 return -1;
7695 }
7696 cmd_len = csio->cdb_len;
7697
7698 if (ccb_h->flags & CAM_CDB_POINTER) {
7699 /* CDB is a pointer */
7700 if (!(ccb_h->flags & CAM_CDB_PHYS)) {
7701 /* CDB pointer is virtual */
7702 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len);
7703 cmd_ba = CCB_BA (cp, cdb_buf[0]);
7704 } else {
7705 /* CDB pointer is physical */
7706 #if 0
7707 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff;
7708 #else
7709 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7710 return -1;
7711 #endif
7712 }
7713 } else {
7714 /* CDB is in the CAM ccb (buffer) */
7715 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len);
7716 cmd_ba = CCB_BA (cp, cdb_buf[0]);
7717 }
7718
7719 cp->phys.cmd.addr = cpu_to_scr(cmd_ba);
7720 cp->phys.cmd.size = cpu_to_scr(cmd_len);
7721
7722 return 0;
7723 }
7724
7725 /*
7726 * Set up data pointers used by SCRIPTS.
7727 */
7728 static void __inline
7729 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir)
7730 {
7731 u32 lastp, goalp;
7732
7733 /*
7734 * No segments means no data.
7735 */
7736 if (!cp->segments)
7737 dir = CAM_DIR_NONE;
7738
7739 /*
7740 * Set the data pointer.
7741 */
7742 switch(dir) {
7743 case CAM_DIR_OUT:
7744 goalp = SCRIPTA_BA (np, data_out2) + 8;
7745 lastp = goalp - 8 - (cp->segments * (2*4));
7746 break;
7747 case CAM_DIR_IN:
7748 cp->host_flags |= HF_DATA_IN;
7749 goalp = SCRIPTA_BA (np, data_in2) + 8;
7750 lastp = goalp - 8 - (cp->segments * (2*4));
7751 break;
7752 case CAM_DIR_NONE:
7753 default:
7754 lastp = goalp = SCRIPTB_BA (np, no_data);
7755 break;
7756 }
7757
7758 cp->phys.head.lastp = cpu_to_scr(lastp);
7759 cp->phys.head.goalp = cpu_to_scr(goalp);
7760 cp->phys.head.savep = cpu_to_scr(lastp);
7761 cp->startp = cp->phys.head.savep;
7762 }
7763
7764
7765 /*
7766 * Call back routine for the DMA map service.
7767 * If bounce buffers are used (why ?), we may sleep and then
7768 * be called there in another context.
7769 */
7770 static void
7771 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error)
7772 {
7773 ccb_p cp;
7774 hcb_p np;
7775 union ccb *ccb;
7776 int s;
7777
7778 s = splcam();
7779
7780 cp = (ccb_p) arg;
7781 ccb = cp->cam_ccb;
7782 np = (hcb_p) cp->arg;
7783
7784 /*
7785 * Deal with weird races.
7786 */
7787 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG)
7788 goto out_abort;
7789
7790 /*
7791 * Deal with weird errors.
7792 */
7793 if (error) {
7794 cp->dmamapped = 0;
7795 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED);
7796 goto out_abort;
7797 }
7798
7799 /*
7800 * Build the data descriptor for the chip.
7801 */
7802 if (nsegs) {
7803 int retv;
7804 /* 896 rev 1 requires to be careful about boundaries */
7805 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1)
7806 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs);
7807 else
7808 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs);
7809 if (retv < 0) {
7810 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG);
7811 goto out_abort;
7812 }
7813 }
7814
7815 /*
7816 * Synchronize the DMA map only if we have
7817 * actually mapped the data.
7818 */
7819 if (cp->dmamapped) {
7820 bus_dmamap_sync(np->data_dmat, cp->dmamap,
7821 (cp->dmamapped == SYM_DMA_READ ?
7822 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
7823 }
7824
7825 /*
7826 * Set host status to busy state.
7827 * May have been set back to HS_WAIT to avoid a race.
7828 */
7829 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
7830
7831 /*
7832 * Set data pointers.
7833 */
7834 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK));
7835
7836 /*
7837 * Enqueue this IO in our pending queue.
7838 */
7839 sym_enqueue_cam_ccb(np, ccb);
7840
7841 /*
7842 * When `#ifed 1', the code below makes the driver
7843 * panic on the first attempt to write to a SCSI device.
7844 * It is the first test we want to do after a driver
7845 * change that does not seem obviously safe. :)
7846 */
7847 #if 0
7848 switch (cp->cdb_buf[0]) {
7849 case 0x0A: case 0x2A: case 0xAA:
7850 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX\n");
7851 MDELAY(10000);
7852 break;
7853 default:
7854 break;
7855 }
7856 #endif
7857 /*
7858 * Activate this job.
7859 */
7860 sym_put_start_queue(np, cp);
7861 out:
7862 splx(s);
7863 return;
7864 out_abort:
7865 sym_free_ccb(np, cp);
7866 sym_xpt_done(np, ccb);
7867 goto out;
7868 }
7869
7870 /*
7871 * How complex it gets to deal with the data in CAM.
7872 * The Bus Dma stuff makes things still more complex.
7873 */
7874 static void
7875 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp)
7876 {
7877 struct ccb_hdr *ccb_h;
7878 int dir, retv;
7879
7880 ccb_h = &csio->ccb_h;
7881
7882 /*
7883 * Now deal with the data.
7884 */
7885 cp->data_len = csio->dxfer_len;
7886 cp->arg = np;
7887
7888 /*
7889 * No direction means no data.
7890 */
7891 dir = (ccb_h->flags & CAM_DIR_MASK);
7892 if (dir == CAM_DIR_NONE) {
7893 sym_execute_ccb(cp, NULL, 0, 0);
7894 return;
7895 }
7896
7897 if (!(ccb_h->flags & CAM_SCATTER_VALID)) {
7898 /* Single buffer */
7899 if (!(ccb_h->flags & CAM_DATA_PHYS)) {
7900 /* Buffer is virtual */
7901 int s;
7902
7903 cp->dmamapped = (dir == CAM_DIR_IN) ?
7904 SYM_DMA_READ : SYM_DMA_WRITE;
7905 s = splsoftvm();
7906 retv = bus_dmamap_load(np->data_dmat, cp->dmamap,
7907 csio->data_ptr, csio->dxfer_len,
7908 sym_execute_ccb, cp, 0);
7909 if (retv == EINPROGRESS) {
7910 cp->host_status = HS_WAIT;
7911 xpt_freeze_simq(np->sim, 1);
7912 csio->ccb_h.status |= CAM_RELEASE_SIMQ;
7913 }
7914 splx(s);
7915 } else {
7916 /* Buffer is physical */
7917 struct bus_dma_segment seg;
7918
7919 seg.ds_addr = (bus_addr_t) csio->data_ptr;
7920 sym_execute_ccb(cp, &seg, 1, 0);
7921 }
7922 } else {
7923 /* Scatter/gather list */
7924 struct bus_dma_segment *segs;
7925
7926 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) {
7927 /* The SG list pointer is physical */
7928 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7929 goto out_abort;
7930 }
7931
7932 if (!(ccb_h->flags & CAM_DATA_PHYS)) {
7933 /* SG buffer pointers are virtual */
7934 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID);
7935 goto out_abort;
7936 }
7937
7938 /* SG buffer pointers are physical */
7939 segs = (struct bus_dma_segment *)csio->data_ptr;
7940 sym_execute_ccb(cp, segs, csio->sglist_cnt, 0);
7941 }
7942 return;
7943 out_abort:
7944 sym_free_ccb(np, cp);
7945 sym_xpt_done(np, (union ccb *) csio);
7946 }
7947
7948 /*
7949 * Move the scatter list to our data block.
7950 */
7951 static int
7952 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
7953 bus_dma_segment_t *psegs, int nsegs)
7954 {
7955 struct sym_tblmove *data;
7956 bus_dma_segment_t *psegs2;
7957
7958 if (nsegs > SYM_CONF_MAX_SG)
7959 return -1;
7960
7961 data = &cp->phys.data[SYM_CONF_MAX_SG-1];
7962 psegs2 = &psegs[nsegs-1];
7963 cp->segments = nsegs;
7964
7965 while (1) {
7966 data->addr = cpu_to_scr(psegs2->ds_addr);
7967 data->size = cpu_to_scr(psegs2->ds_len);
7968 if (DEBUG_FLAGS & DEBUG_SCATTER) {
7969 printf ("%s scatter: paddr=%lx len=%ld\n",
7970 sym_name(np), (long) psegs2->ds_addr,
7971 (long) psegs2->ds_len);
7972 }
7973 if (psegs2 != psegs) {
7974 --data;
7975 --psegs2;
7976 continue;
7977 }
7978 break;
7979 }
7980 return 0;
7981 }
7982
7983
7984 /*
7985 * Scatter a SG list with physical addresses into bus addressable chunks.
7986 * We need to ensure 16MB boundaries not to be crossed during DMA of
7987 * each segment, due to some chips being flawed.
7988 */
7989 #define BOUND_MASK ((1UL<<24)-1)
7990 static int
7991 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs)
7992 {
7993 u_long ps, pe, pn;
7994 u_long k;
7995 int s, t;
7996
7997 s = SYM_CONF_MAX_SG - 1;
7998 t = nsegs - 1;
7999 ps = psegs[t].ds_addr;
8000 pe = ps + psegs[t].ds_len;
8001
8002 while (s >= 0) {
8003 pn = (pe - 1) & ~BOUND_MASK;
8004 if (pn <= ps)
8005 pn = ps;
8006 k = pe - pn;
8007 if (DEBUG_FLAGS & DEBUG_SCATTER) {
8008 printf ("%s scatter: paddr=%lx len=%ld\n",
8009 sym_name(np), pn, k);
8010 }
8011 cp->phys.data[s].addr = cpu_to_scr(pn);
8012 cp->phys.data[s].size = cpu_to_scr(k);
8013 --s;
8014 if (pn == ps) {
8015 if (--t < 0)
8016 break;
8017 ps = psegs[t].ds_addr;
8018 pe = ps + psegs[t].ds_len;
8019 }
8020 else
8021 pe = pn;
8022 }
8023
8024 cp->segments = SYM_CONF_MAX_SG - 1 - s;
8025
8026 return t >= 0 ? -1 : 0;
8027 }
8028 #undef BOUND_MASK
8029
8030 /*
8031 * SIM action for non performance critical stuff.
8032 */
8033 static void sym_action2(struct cam_sim *sim, union ccb *ccb)
8034 {
8035 hcb_p np;
8036 tcb_p tp;
8037 lcb_p lp;
8038 struct ccb_hdr *ccb_h;
8039
8040 /*
8041 * Retrieve our controller data structure.
8042 */
8043 np = (hcb_p) cam_sim_softc(sim);
8044
8045 ccb_h = &ccb->ccb_h;
8046
8047 switch (ccb_h->func_code) {
8048 case XPT_SET_TRAN_SETTINGS:
8049 {
8050 struct ccb_trans_settings *cts;
8051
8052 cts = &ccb->cts;
8053 tp = &np->target[ccb_h->target_id];
8054
8055 /*
8056 * Update SPI transport settings in TARGET control block.
8057 * Update SCSI device settings in LUN control block.
8058 */
8059 lp = sym_lp(np, tp, ccb_h->target_lun);
8060 #ifdef FreeBSD_New_Tran_Settings
8061 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
8062 #else
8063 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
8064 #endif
8065 sym_update_trans(np, tp, &tp->tinfo.goal, cts);
8066 if (lp)
8067 sym_update_dflags(np, &lp->current_flags, cts);
8068 }
8069 #ifdef FreeBSD_New_Tran_Settings
8070 if (cts->type == CTS_TYPE_USER_SETTINGS) {
8071 #else
8072 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
8073 #endif
8074 sym_update_trans(np, tp, &tp->tinfo.user, cts);
8075 if (lp)
8076 sym_update_dflags(np, &lp->user_flags, cts);
8077 }
8078
8079 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8080 break;
8081 }
8082 case XPT_GET_TRAN_SETTINGS:
8083 {
8084 struct ccb_trans_settings *cts;
8085 struct sym_trans *tip;
8086 u_char dflags;
8087
8088 cts = &ccb->cts;
8089 tp = &np->target[ccb_h->target_id];
8090 lp = sym_lp(np, tp, ccb_h->target_lun);
8091
8092 #ifdef FreeBSD_New_Tran_Settings
8093 #define cts__scsi (&cts->proto_specific.scsi)
8094 #define cts__spi (&cts->xport_specific.spi)
8095 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
8096 tip = &tp->tinfo.current;
8097 dflags = lp ? lp->current_flags : 0;
8098 }
8099 else {
8100 tip = &tp->tinfo.user;
8101 dflags = lp ? lp->user_flags : tp->usrflags;
8102 }
8103
8104 cts->protocol = PROTO_SCSI;
8105 cts->transport = XPORT_SPI;
8106 cts->protocol_version = tip->scsi_version;
8107 cts->transport_version = tip->spi_version;
8108
8109 cts__spi->sync_period = tip->period;
8110 cts__spi->sync_offset = tip->offset;
8111 cts__spi->bus_width = tip->width;
8112 cts__spi->ppr_options = tip->options;
8113
8114 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE
8115 | CTS_SPI_VALID_SYNC_OFFSET
8116 | CTS_SPI_VALID_BUS_WIDTH
8117 | CTS_SPI_VALID_PPR_OPTIONS;
8118
8119 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
8120 if (dflags & SYM_DISC_ENABLED)
8121 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
8122 cts__spi->valid |= CTS_SPI_VALID_DISC;
8123
8124 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB;
8125 if (dflags & SYM_TAGS_ENABLED)
8126 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
8127 cts__scsi->valid |= CTS_SCSI_VALID_TQ;
8128 #undef cts__spi
8129 #undef cts__scsi
8130 #else
8131 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
8132 tip = &tp->tinfo.current;
8133 dflags = lp ? lp->current_flags : 0;
8134 }
8135 else {
8136 tip = &tp->tinfo.user;
8137 dflags = lp ? lp->user_flags : tp->usrflags;
8138 }
8139
8140 cts->sync_period = tip->period;
8141 cts->sync_offset = tip->offset;
8142 cts->bus_width = tip->width;
8143
8144 cts->valid = CCB_TRANS_SYNC_RATE_VALID
8145 | CCB_TRANS_SYNC_OFFSET_VALID
8146 | CCB_TRANS_BUS_WIDTH_VALID;
8147
8148 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
8149
8150 if (dflags & SYM_DISC_ENABLED)
8151 cts->flags |= CCB_TRANS_DISC_ENB;
8152
8153 if (dflags & SYM_TAGS_ENABLED)
8154 cts->flags |= CCB_TRANS_TAG_ENB;
8155
8156 cts->valid |= CCB_TRANS_DISC_VALID;
8157 cts->valid |= CCB_TRANS_TQ_VALID;
8158 #endif
8159 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8160 break;
8161 }
8162 case XPT_CALC_GEOMETRY:
8163 {
8164 cam_calc_geometry(&ccb->ccg, /*extended*/1);
8165 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8166 break;
8167 }
8168 case XPT_PATH_INQ:
8169 {
8170 struct ccb_pathinq *cpi = &ccb->cpi;
8171 cpi->version_num = 1;
8172 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE;
8173 if ((np->features & FE_WIDE) != 0)
8174 cpi->hba_inquiry |= PI_WIDE_16;
8175 cpi->target_sprt = 0;
8176 cpi->hba_misc = 0;
8177 if (np->usrflags & SYM_SCAN_TARGETS_HILO)
8178 cpi->hba_misc |= PIM_SCANHILO;
8179 if (np->usrflags & SYM_AVOID_BUS_RESET)
8180 cpi->hba_misc |= PIM_NOBUSRESET;
8181 cpi->hba_eng_cnt = 0;
8182 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7;
8183 /* Semantic problem:)LUN number max = max number of LUNs - 1 */
8184 cpi->max_lun = SYM_CONF_MAX_LUN-1;
8185 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN)
8186 cpi->max_lun = SYM_SETUP_MAX_LUN-1;
8187 cpi->bus_id = cam_sim_bus(sim);
8188 cpi->initiator_id = np->myaddr;
8189 cpi->base_transfer_speed = 3300;
8190 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
8191 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN);
8192 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
8193 cpi->unit_number = cam_sim_unit(sim);
8194
8195 #ifdef FreeBSD_New_Tran_Settings
8196 cpi->protocol = PROTO_SCSI;
8197 cpi->protocol_version = SCSI_REV_2;
8198 cpi->transport = XPORT_SPI;
8199 cpi->transport_version = 2;
8200 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST;
8201 if (np->features & FE_ULTRA3) {
8202 cpi->transport_version = 3;
8203 cpi->xport_specific.spi.ppr_options =
8204 SID_SPI_CLOCK_DT_ST;
8205 }
8206 #endif
8207 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8208 break;
8209 }
8210 case XPT_ABORT:
8211 {
8212 union ccb *abort_ccb = ccb->cab.abort_ccb;
8213 switch(abort_ccb->ccb_h.func_code) {
8214 case XPT_SCSI_IO:
8215 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) {
8216 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8217 break;
8218 }
8219 default:
8220 sym_xpt_done2(np, ccb, CAM_UA_ABORT);
8221 break;
8222 }
8223 break;
8224 }
8225 case XPT_RESET_DEV:
8226 {
8227 sym_reset_dev(np, ccb);
8228 break;
8229 }
8230 case XPT_RESET_BUS:
8231 {
8232 sym_reset_scsi_bus(np, 0);
8233 if (sym_verbose) {
8234 xpt_print_path(np->path);
8235 printf("SCSI BUS reset delivered.\n");
8236 }
8237 sym_init (np, 1);
8238 sym_xpt_done2(np, ccb, CAM_REQ_CMP);
8239 break;
8240 }
8241 case XPT_ACCEPT_TARGET_IO:
8242 case XPT_CONT_TARGET_IO:
8243 case XPT_EN_LUN:
8244 case XPT_NOTIFY_ACK:
8245 case XPT_IMMED_NOTIFY:
8246 case XPT_TERM_IO:
8247 default:
8248 sym_xpt_done2(np, ccb, CAM_REQ_INVALID);
8249 break;
8250 }
8251 }
8252
8253 /*
8254 * Asynchronous notification handler.
8255 */
8256 static void
8257 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg)
8258 {
8259 hcb_p np;
8260 struct cam_sim *sim;
8261 u_int tn;
8262 tcb_p tp;
8263 int s;
8264
8265 s = splcam();
8266
8267 sim = (struct cam_sim *) cb_arg;
8268 np = (hcb_p) cam_sim_softc(sim);
8269
8270 switch (code) {
8271 case AC_LOST_DEVICE:
8272 tn = xpt_path_target_id(path);
8273 if (tn >= SYM_CONF_MAX_TARGET)
8274 break;
8275
8276 tp = &np->target[tn];
8277
8278 tp->to_reset = 0;
8279 tp->head.sval = 0;
8280 tp->head.wval = np->rv_scntl3;
8281 tp->head.uval = 0;
8282
8283 tp->tinfo.current.period = tp->tinfo.goal.period = 0;
8284 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0;
8285 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT;
8286 tp->tinfo.current.options = tp->tinfo.goal.options = 0;
8287
8288 break;
8289 default:
8290 break;
8291 }
8292
8293 splx(s);
8294 }
8295
8296 /*
8297 * Update transfer settings of a target.
8298 */
8299 static void sym_update_trans(hcb_p np, tcb_p tp, struct sym_trans *tip,
8300 struct ccb_trans_settings *cts)
8301 {
8302 /*
8303 * Update the infos.
8304 */
8305 #ifdef FreeBSD_New_Tran_Settings
8306 #define cts__spi (&cts->xport_specific.spi)
8307 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0)
8308 tip->width = cts__spi->bus_width;
8309 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)
8310 tip->offset = cts__spi->sync_offset;
8311 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0)
8312 tip->period = cts__spi->sync_period;
8313 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0)
8314 tip->options = (cts__spi->ppr_options & PPR_OPT_DT);
8315 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED &&
8316 cts->protocol_version != PROTO_VERSION_UNKNOWN)
8317 tip->scsi_version = cts->protocol_version;
8318 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED &&
8319 cts->transport_version != XPORT_VERSION_UNKNOWN)
8320 tip->spi_version = cts->transport_version;
8321 #undef cts__spi
8322 #else
8323 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0)
8324 tip->width = cts->bus_width;
8325 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)
8326 tip->offset = cts->sync_offset;
8327 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
8328 tip->period = cts->sync_period;
8329 #endif
8330 /*
8331 * Scale against driver configuration limits.
8332 */
8333 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE;
8334 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS;
8335 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC;
8336
8337 /*
8338 * Scale against actual controller BUS width.
8339 */
8340 if (tip->width > np->maxwide)
8341 tip->width = np->maxwide;
8342
8343 #ifdef FreeBSD_New_Tran_Settings
8344 /*
8345 * Only accept DT if controller supports and SYNC/WIDE asked.
8346 */
8347 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) ||
8348 !(tip->width == BUS_16_BIT && tip->offset)) {
8349 tip->options &= ~PPR_OPT_DT;
8350 }
8351 #else
8352 /*
8353 * For now, only assume DT if period <= 9, BUS 16 and offset != 0.
8354 */
8355 tip->options = 0;
8356 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3) &&
8357 tip->period <= 9 && tip->width == BUS_16_BIT && tip->offset) {
8358 tip->options |= PPR_OPT_DT;
8359 }
8360 #endif
8361
8362 /*
8363 * Scale period factor and offset against controller limits.
8364 */
8365 if (tip->options & PPR_OPT_DT) {
8366 if (tip->period < np->minsync_dt)
8367 tip->period = np->minsync_dt;
8368 if (tip->period > np->maxsync_dt)
8369 tip->period = np->maxsync_dt;
8370 if (tip->offset > np->maxoffs_dt)
8371 tip->offset = np->maxoffs_dt;
8372 }
8373 else {
8374 if (tip->period < np->minsync)
8375 tip->period = np->minsync;
8376 if (tip->period > np->maxsync)
8377 tip->period = np->maxsync;
8378 if (tip->offset > np->maxoffs)
8379 tip->offset = np->maxoffs;
8380 }
8381 }
8382
8383 /*
8384 * Update flags for a device (logical unit).
8385 */
8386 static void
8387 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts)
8388 {
8389 #ifdef FreeBSD_New_Tran_Settings
8390 #define cts__scsi (&cts->proto_specific.scsi)
8391 #define cts__spi (&cts->xport_specific.spi)
8392 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) {
8393 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0)
8394 *flags |= SYM_DISC_ENABLED;
8395 else
8396 *flags &= ~SYM_DISC_ENABLED;
8397 }
8398
8399 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
8400 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0)
8401 *flags |= SYM_TAGS_ENABLED;
8402 else
8403 *flags &= ~SYM_TAGS_ENABLED;
8404 }
8405 #undef cts__spi
8406 #undef cts__scsi
8407 #else
8408 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
8409 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
8410 *flags |= SYM_DISC_ENABLED;
8411 else
8412 *flags &= ~SYM_DISC_ENABLED;
8413 }
8414
8415 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
8416 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
8417 *flags |= SYM_TAGS_ENABLED;
8418 else
8419 *flags &= ~SYM_TAGS_ENABLED;
8420 }
8421 #endif
8422 }
8423
8424
8425 /*============= DRIVER INITIALISATION ==================*/
8426
8427
8428 static device_method_t sym_pci_methods[] = {
8429 DEVMETHOD(device_probe, sym_pci_probe),
8430 DEVMETHOD(device_attach, sym_pci_attach),
8431 { 0, 0 }
8432 };
8433
8434 static driver_t sym_pci_driver = {
8435 "sym",
8436 sym_pci_methods,
8437 1 /* no softc */
8438 };
8439
8440 static devclass_t sym_devclass;
8441
8442 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, 0, 0);
8443 MODULE_DEPEND(sym, cam, 1, 1, 1);
8444 MODULE_DEPEND(sym, pci, 1, 1, 1);
8445
8446
8447 static const struct sym_pci_chip sym_pci_dev_table[] = {
8448 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64,
8449 FE_ERL}
8450 ,
8451 #ifdef SYM_DEBUG_GENERIC_SUPPORT
8452 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1,
8453 FE_BOF}
8454 ,
8455 #else
8456 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1,
8457 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF}
8458 ,
8459 #endif
8460 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64,
8461 FE_BOF|FE_ERL}
8462 ,
8463 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64,
8464 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF}
8465 ,
8466 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2,
8467 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF}
8468 ,
8469 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1,
8470 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN}
8471 ,
8472 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2,
8473 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8474 FE_RAM|FE_DIFF}
8475 ,
8476 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2,
8477 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8478 FE_RAM|FE_DIFF}
8479 ,
8480 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2,
8481 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8482 FE_RAM|FE_DIFF}
8483 ,
8484 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2,
8485 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8486 FE_RAM|FE_DIFF}
8487 ,
8488 #ifdef SYM_DEBUG_GENERIC_SUPPORT
8489 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2,
8490 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|
8491 FE_RAM|FE_LCKFRQ}
8492 ,
8493 #else
8494 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2,
8495 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8496 FE_RAM|FE_LCKFRQ}
8497 ,
8498 #endif
8499 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4,
8500 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8501 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
8502 ,
8503 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4,
8504 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8505 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
8506 ,
8507 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8,
8508 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
8509 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
8510 FE_C10}
8511 ,
8512 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8,
8513 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
8514 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
8515 FE_C10|FE_U3EN}
8516 ,
8517 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8,
8518 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
8519 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
8520 FE_C10|FE_U3EN}
8521 ,
8522 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4,
8523 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
8524 FE_RAM|FE_IO256|FE_LEDC}
8525 };
8526
8527 #define sym_pci_num_devs \
8528 (sizeof(sym_pci_dev_table) / sizeof(sym_pci_dev_table[0]))
8529
8530 /*
8531 * Look up the chip table.
8532 *
8533 * Return a pointer to the chip entry if found,
8534 * zero otherwise.
8535 */
8536 static const struct sym_pci_chip *
8537 sym_find_pci_chip(device_t dev)
8538 {
8539 const struct sym_pci_chip *chip;
8540 int i;
8541 u_short device_id;
8542 u_char revision;
8543
8544 if (pci_get_vendor(dev) != PCI_VENDOR_NCR)
8545 return NULL;
8546
8547 device_id = pci_get_device(dev);
8548 revision = pci_get_revid(dev);
8549
8550 for (i = 0; i < sym_pci_num_devs; i++) {
8551 chip = &sym_pci_dev_table[i];
8552 if (device_id != chip->device_id)
8553 continue;
8554 if (revision > chip->revision_id)
8555 continue;
8556 return chip;
8557 }
8558
8559 return NULL;
8560 }
8561
8562 /*
8563 * Tell upper layer if the chip is supported.
8564 */
8565 static int
8566 sym_pci_probe(device_t dev)
8567 {
8568 const struct sym_pci_chip *chip;
8569
8570 chip = sym_find_pci_chip(dev);
8571 if (chip && sym_find_firmware(chip)) {
8572 device_set_desc(dev, chip->name);
8573 return (chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)?
8574 BUS_PROBE_LOW_PRIORITY : BUS_PROBE_DEFAULT;
8575 }
8576 return ENXIO;
8577 }
8578
8579 /*
8580 * Attach a sym53c8xx device.
8581 */
8582 static int
8583 sym_pci_attach(device_t dev)
8584 {
8585 const struct sym_pci_chip *chip;
8586 u_short command;
8587 u_char cachelnsz;
8588 struct sym_hcb *np = NULL;
8589 struct sym_nvram nvram;
8590 const struct sym_fw *fw = NULL;
8591 int i;
8592 bus_dma_tag_t bus_dmat;
8593
8594 /*
8595 * I expected to be told about a parent
8596 * DMA tag, but didn't find any.
8597 */
8598 bus_dmat = NULL;
8599
8600 /*
8601 * Only probed devices should be attached.
8602 * We just enjoy being paranoid. :)
8603 */
8604 chip = sym_find_pci_chip(dev);
8605 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL)
8606 return (ENXIO);
8607 device_set_softc(dev, np);
8608
8609 /*
8610 * Allocate immediately the host control block,
8611 * since we are only expecting to succeed. :)
8612 * We keep track in the HCB of all the resources that
8613 * are to be released on error.
8614 */
8615 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB");
8616 if (np)
8617 np->bus_dmat = bus_dmat;
8618 else
8619 goto attach_failed;
8620
8621 /*
8622 * Copy some useful infos to the HCB.
8623 */
8624 np->hcb_ba = vtobus(np);
8625 np->verbose = bootverbose;
8626 np->device = dev;
8627 np->device_id = pci_get_device(dev);
8628 np->revision_id = pci_get_revid(dev);
8629 np->features = chip->features;
8630 np->clock_divn = chip->nr_divisor;
8631 np->maxoffs = chip->offset_max;
8632 np->maxburst = chip->burst_max;
8633 np->scripta_sz = fw->a_size;
8634 np->scriptb_sz = fw->b_size;
8635 np->fw_setup = fw->setup;
8636 np->fw_patch = fw->patch;
8637 np->fw_name = fw->name;
8638
8639 #ifdef __amd64__
8640 np->target = sym_calloc_dma(SYM_CONF_MAX_TARGET * sizeof(*(np->target)),
8641 "TARGET");
8642 if (!np->target)
8643 goto attach_failed;
8644 #endif
8645
8646 /*
8647 * Initialize the CCB free and busy queues.
8648 */
8649 sym_que_init(&np->free_ccbq);
8650 sym_que_init(&np->busy_ccbq);
8651 sym_que_init(&np->comp_ccbq);
8652 sym_que_init(&np->cam_ccbq);
8653
8654 /*
8655 * Allocate a tag for the DMA of user data.
8656 */
8657 if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24),
8658 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
8659 NULL, NULL,
8660 BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG,
8661 (1<<24), 0, busdma_lock_mutex, &Giant,
8662 &np->data_dmat)) {
8663 device_printf(dev, "failed to create DMA tag.\n");
8664 goto attach_failed;
8665 }
8666 /*
8667 * Read and apply some fix-ups to the PCI COMMAND
8668 * register. We want the chip to be enabled for:
8669 * - BUS mastering
8670 * - PCI parity checking (reporting would also be fine)
8671 * - Write And Invalidate.
8672 */
8673 command = pci_read_config(dev, PCIR_COMMAND, 2);
8674 command |= PCIM_CMD_BUSMASTEREN;
8675 command |= PCIM_CMD_PERRESPEN;
8676 command |= /* PCIM_CMD_MWIEN */ 0x0010;
8677 pci_write_config(dev, PCIR_COMMAND, command, 2);
8678
8679 /*
8680 * Let the device know about the cache line size,
8681 * if it doesn't yet.
8682 */
8683 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
8684 if (!cachelnsz) {
8685 cachelnsz = 8;
8686 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1);
8687 }
8688
8689 /*
8690 * Alloc/get/map/retrieve everything that deals with MMIO.
8691 */
8692 if ((command & PCIM_CMD_MEMEN) != 0) {
8693 int regs_id = SYM_PCI_MMIO;
8694 np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
8695 ®s_id, RF_ACTIVE);
8696 }
8697 if (!np->mmio_res) {
8698 device_printf(dev, "failed to allocate MMIO resources\n");
8699 goto attach_failed;
8700 }
8701 np->mmio_bsh = rman_get_bushandle(np->mmio_res);
8702 np->mmio_tag = rman_get_bustag(np->mmio_res);
8703 np->mmio_ba = rman_get_start(np->mmio_res);
8704
8705 /*
8706 * Allocate the IRQ.
8707 */
8708 i = 0;
8709 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
8710 RF_ACTIVE | RF_SHAREABLE);
8711 if (!np->irq_res) {
8712 device_printf(dev, "failed to allocate IRQ resource\n");
8713 goto attach_failed;
8714 }
8715
8716 #ifdef SYM_CONF_IOMAPPED
8717 /*
8718 * User want us to use normal IO with PCI.
8719 * Alloc/get/map/retrieve everything that deals with IO.
8720 */
8721 if ((command & PCI_COMMAND_IO_ENABLE) != 0) {
8722 int regs_id = SYM_PCI_IO;
8723 np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
8724 ®s_id, RF_ACTIVE);
8725 }
8726 if (!np->io_res) {
8727 device_printf(dev, "failed to allocate IO resources\n");
8728 goto attach_failed;
8729 }
8730 np->io_bsh = rman_get_bushandle(np->io_res);
8731 np->io_tag = rman_get_bustag(np->io_res);
8732 np->io_port = rman_get_start(np->io_res);
8733
8734 #endif /* SYM_CONF_IOMAPPED */
8735
8736 /*
8737 * If the chip has RAM.
8738 * Alloc/get/map/retrieve the corresponding resources.
8739 */
8740 if ((np->features & (FE_RAM|FE_RAM8K)) &&
8741 (command & PCIM_CMD_MEMEN) != 0) {
8742 int regs_id = SYM_PCI_RAM;
8743 if (np->features & FE_64BIT)
8744 regs_id = SYM_PCI_RAM64;
8745 np->ram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
8746 ®s_id, RF_ACTIVE);
8747 if (!np->ram_res) {
8748 device_printf(dev,"failed to allocate RAM resources\n");
8749 goto attach_failed;
8750 }
8751 np->ram_id = regs_id;
8752 np->ram_bsh = rman_get_bushandle(np->ram_res);
8753 np->ram_tag = rman_get_bustag(np->ram_res);
8754 np->ram_ba = rman_get_start(np->ram_res);
8755 }
8756
8757 /*
8758 * Save setting of some IO registers, so we will
8759 * be able to probe specific implementations.
8760 */
8761 sym_save_initial_setting (np);
8762
8763 /*
8764 * Reset the chip now, since it has been reported
8765 * that SCSI clock calibration may not work properly
8766 * if the chip is currently active.
8767 */
8768 sym_chip_reset (np);
8769
8770 /*
8771 * Try to read the user set-up.
8772 */
8773 (void) sym_read_nvram(np, &nvram);
8774
8775 /*
8776 * Prepare controller and devices settings, according
8777 * to chip features, user set-up and driver set-up.
8778 */
8779 (void) sym_prepare_setting(np, &nvram);
8780
8781 /*
8782 * Check the PCI clock frequency.
8783 * Must be performed after prepare_setting since it destroys
8784 * STEST1 that is used to probe for the clock doubler.
8785 */
8786 i = sym_getpciclock(np);
8787 if (i > 37000)
8788 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i);
8789
8790 /*
8791 * Allocate the start queue.
8792 */
8793 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE");
8794 if (!np->squeue)
8795 goto attach_failed;
8796 np->squeue_ba = vtobus(np->squeue);
8797
8798 /*
8799 * Allocate the done queue.
8800 */
8801 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE");
8802 if (!np->dqueue)
8803 goto attach_failed;
8804 np->dqueue_ba = vtobus(np->dqueue);
8805
8806 /*
8807 * Allocate the target bus address array.
8808 */
8809 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL");
8810 if (!np->targtbl)
8811 goto attach_failed;
8812 np->targtbl_ba = vtobus(np->targtbl);
8813
8814 /*
8815 * Allocate SCRIPTS areas.
8816 */
8817 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0");
8818 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0");
8819 if (!np->scripta0 || !np->scriptb0)
8820 goto attach_failed;
8821
8822 /*
8823 * Allocate some CCB. We need at least ONE.
8824 */
8825 if (!sym_alloc_ccb(np))
8826 goto attach_failed;
8827
8828 /*
8829 * Calculate BUS addresses where we are going
8830 * to load the SCRIPTS.
8831 */
8832 np->scripta_ba = vtobus(np->scripta0);
8833 np->scriptb_ba = vtobus(np->scriptb0);
8834 np->scriptb0_ba = np->scriptb_ba;
8835
8836 if (np->ram_ba) {
8837 np->scripta_ba = np->ram_ba;
8838 if (np->features & FE_RAM8K) {
8839 np->ram_ws = 8192;
8840 np->scriptb_ba = np->scripta_ba + 4096;
8841 #ifdef __LP64__
8842 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32);
8843 #endif
8844 }
8845 else
8846 np->ram_ws = 4096;
8847 }
8848
8849 /*
8850 * Copy scripts to controller instance.
8851 */
8852 bcopy(fw->a_base, np->scripta0, np->scripta_sz);
8853 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz);
8854
8855 /*
8856 * Setup variable parts in scripts and compute
8857 * scripts bus addresses used from the C code.
8858 */
8859 np->fw_setup(np, fw);
8860
8861 /*
8862 * Bind SCRIPTS with physical addresses usable by the
8863 * SCRIPTS processor (as seen from the BUS = BUS addresses).
8864 */
8865 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz);
8866 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz);
8867
8868 #ifdef SYM_CONF_IARB_SUPPORT
8869 /*
8870 * If user wants IARB to be set when we win arbitration
8871 * and have other jobs, compute the max number of consecutive
8872 * settings of IARB hints before we leave devices a chance to
8873 * arbitrate for reselection.
8874 */
8875 #ifdef SYM_SETUP_IARB_MAX
8876 np->iarb_max = SYM_SETUP_IARB_MAX;
8877 #else
8878 np->iarb_max = 4;
8879 #endif
8880 #endif
8881
8882 /*
8883 * Prepare the idle and invalid task actions.
8884 */
8885 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8886 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
8887 np->idletask_ba = vtobus(&np->idletask);
8888
8889 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8890 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
8891 np->notask_ba = vtobus(&np->notask);
8892
8893 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8894 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l));
8895 np->bad_itl_ba = vtobus(&np->bad_itl);
8896
8897 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle));
8898 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q));
8899 np->bad_itlq_ba = vtobus(&np->bad_itlq);
8900
8901 /*
8902 * Allocate and prepare the lun JUMP table that is used
8903 * for a target prior the probing of devices (bad lun table).
8904 * A private table will be allocated for the target on the
8905 * first INQUIRY response received.
8906 */
8907 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL");
8908 if (!np->badluntbl)
8909 goto attach_failed;
8910
8911 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun));
8912 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */
8913 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
8914
8915 /*
8916 * Prepare the bus address array that contains the bus
8917 * address of each target control block.
8918 * For now, assume all logical units are wrong. :)
8919 */
8920 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
8921 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i]));
8922 np->target[i].head.luntbl_sa =
8923 cpu_to_scr(vtobus(np->badluntbl));
8924 np->target[i].head.lun0_sa =
8925 cpu_to_scr(vtobus(&np->badlun_sa));
8926 }
8927
8928 /*
8929 * Now check the cache handling of the pci chipset.
8930 */
8931 if (sym_snooptest (np)) {
8932 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n");
8933 goto attach_failed;
8934 };
8935
8936 /*
8937 * Now deal with CAM.
8938 * Hopefully, we will succeed with that one.:)
8939 */
8940 if (!sym_cam_attach(np))
8941 goto attach_failed;
8942
8943 /*
8944 * Sigh! we are done.
8945 */
8946 return 0;
8947
8948 /*
8949 * We have failed.
8950 * We will try to free all the resources we have
8951 * allocated, but if we are a boot device, this
8952 * will not help that much.;)
8953 */
8954 attach_failed:
8955 if (np)
8956 sym_pci_free(np);
8957 return ENXIO;
8958 }
8959
8960 /*
8961 * Free everything that have been allocated for this device.
8962 */
8963 static void sym_pci_free(hcb_p np)
8964 {
8965 SYM_QUEHEAD *qp;
8966 ccb_p cp;
8967 tcb_p tp;
8968 lcb_p lp;
8969 int target, lun;
8970 int s;
8971
8972 /*
8973 * First free CAM resources.
8974 */
8975 s = splcam();
8976 sym_cam_free(np);
8977 splx(s);
8978
8979 /*
8980 * Now every should be quiet for us to
8981 * free other resources.
8982 */
8983 if (np->ram_res)
8984 bus_release_resource(np->device, SYS_RES_MEMORY,
8985 np->ram_id, np->ram_res);
8986 if (np->mmio_res)
8987 bus_release_resource(np->device, SYS_RES_MEMORY,
8988 SYM_PCI_MMIO, np->mmio_res);
8989 if (np->io_res)
8990 bus_release_resource(np->device, SYS_RES_IOPORT,
8991 SYM_PCI_IO, np->io_res);
8992 if (np->irq_res)
8993 bus_release_resource(np->device, SYS_RES_IRQ,
8994 0, np->irq_res);
8995
8996 if (np->scriptb0)
8997 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0");
8998 if (np->scripta0)
8999 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0");
9000 if (np->squeue)
9001 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE");
9002 if (np->dqueue)
9003 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE");
9004
9005 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) {
9006 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
9007 bus_dmamap_destroy(np->data_dmat, cp->dmamap);
9008 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF");
9009 sym_mfree_dma(cp, sizeof(*cp), "CCB");
9010 }
9011
9012 if (np->badluntbl)
9013 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL");
9014
9015 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) {
9016 tp = &np->target[target];
9017 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) {
9018 lp = sym_lp(np, tp, lun);
9019 if (!lp)
9020 continue;
9021 if (lp->itlq_tbl)
9022 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4,
9023 "ITLQ_TBL");
9024 if (lp->cb_tags)
9025 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK,
9026 "CB_TAGS");
9027 sym_mfree_dma(lp, sizeof(*lp), "LCB");
9028 }
9029 #if SYM_CONF_MAX_LUN > 1
9030 if (tp->lunmp)
9031 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p),
9032 "LUNMP");
9033 #endif
9034 }
9035 #ifdef __amd64__
9036 if (np->target)
9037 sym_mfree_dma(np->target,
9038 SYM_CONF_MAX_TARGET * sizeof(*(np->target)), "TARGET");
9039 #endif
9040 if (np->targtbl)
9041 sym_mfree_dma(np->targtbl, 256, "TARGTBL");
9042 if (np->data_dmat)
9043 bus_dma_tag_destroy(np->data_dmat);
9044 device_set_softc(np->device, NULL);
9045 sym_mfree_dma(np, sizeof(*np), "HCB");
9046 }
9047
9048 /*
9049 * Allocate CAM resources and register a bus to CAM.
9050 */
9051 static int sym_cam_attach(hcb_p np)
9052 {
9053 struct cam_devq *devq = NULL;
9054 struct cam_sim *sim = NULL;
9055 struct cam_path *path = NULL;
9056 struct ccb_setasync csa;
9057 int err, s;
9058
9059 s = splcam();
9060
9061 /*
9062 * Establish our interrupt handler.
9063 */
9064 err = bus_setup_intr(np->device, np->irq_res,
9065 INTR_TYPE_CAM | INTR_ENTROPY, sym_intr, np,
9066 &np->intr);
9067 if (err) {
9068 device_printf(np->device, "bus_setup_intr() failed: %d\n",
9069 err);
9070 goto fail;
9071 }
9072
9073 /*
9074 * Create the device queue for our sym SIM.
9075 */
9076 devq = cam_simq_alloc(SYM_CONF_MAX_START);
9077 if (!devq)
9078 goto fail;
9079
9080 /*
9081 * Construct our SIM entry.
9082 */
9083 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np,
9084 device_get_unit(np->device),
9085 1, SYM_SETUP_MAX_TAG, devq);
9086 if (!sim)
9087 goto fail;
9088 devq = 0;
9089
9090 if (xpt_bus_register(sim, 0) != CAM_SUCCESS)
9091 goto fail;
9092 np->sim = sim;
9093 sim = 0;
9094
9095 if (xpt_create_path(&path, 0,
9096 cam_sim_path(np->sim), CAM_TARGET_WILDCARD,
9097 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
9098 goto fail;
9099 }
9100 np->path = path;
9101
9102 /*
9103 * Establish our async notification handler.
9104 */
9105 xpt_setup_ccb(&csa.ccb_h, np->path, 5);
9106 csa.ccb_h.func_code = XPT_SASYNC_CB;
9107 csa.event_enable = AC_LOST_DEVICE;
9108 csa.callback = sym_async;
9109 csa.callback_arg = np->sim;
9110 xpt_action((union ccb *)&csa);
9111
9112 /*
9113 * Start the chip now, without resetting the BUS, since
9114 * it seems that this must stay under control of CAM.
9115 * With LVD/SE capable chips and BUS in SE mode, we may
9116 * get a spurious SMBC interrupt.
9117 */
9118 sym_init (np, 0);
9119
9120 splx(s);
9121 return 1;
9122 fail:
9123 if (sim)
9124 cam_sim_free(sim, FALSE);
9125 if (devq)
9126 cam_simq_free(devq);
9127
9128 sym_cam_free(np);
9129
9130 splx(s);
9131 return 0;
9132 }
9133
9134 /*
9135 * Free everything that deals with CAM.
9136 */
9137 static void sym_cam_free(hcb_p np)
9138 {
9139 if (np->intr) {
9140 bus_teardown_intr(np->device, np->irq_res, np->intr);
9141 np->intr = NULL;
9142 }
9143
9144 if (np->sim) {
9145 xpt_bus_deregister(cam_sim_path(np->sim));
9146 cam_sim_free(np->sim, /*free_devq*/ TRUE);
9147 np->sim = NULL;
9148 }
9149 if (np->path) {
9150 xpt_free_path(np->path);
9151 np->path = NULL;
9152 }
9153 }
9154
9155 /*============ OPTIONNAL NVRAM SUPPORT =================*/
9156
9157 /*
9158 * Get host setup from NVRAM.
9159 */
9160 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram)
9161 {
9162 #ifdef SYM_CONF_NVRAM_SUPPORT
9163 /*
9164 * Get parity checking, host ID, verbose mode
9165 * and miscellaneous host flags from NVRAM.
9166 */
9167 switch(nvram->type) {
9168 case SYM_SYMBIOS_NVRAM:
9169 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE))
9170 np->rv_scntl0 &= ~0x0a;
9171 np->myaddr = nvram->data.Symbios.host_id & 0x0f;
9172 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS)
9173 np->verbose += 1;
9174 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO)
9175 np->usrflags |= SYM_SCAN_TARGETS_HILO;
9176 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET)
9177 np->usrflags |= SYM_AVOID_BUS_RESET;
9178 break;
9179 case SYM_TEKRAM_NVRAM:
9180 np->myaddr = nvram->data.Tekram.host_id & 0x0f;
9181 break;
9182 default:
9183 break;
9184 }
9185 #endif
9186 }
9187
9188 /*
9189 * Get target setup from NVRAM.
9190 */
9191 #ifdef SYM_CONF_NVRAM_SUPPORT
9192 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram);
9193 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram);
9194 #endif
9195
9196 static void
9197 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp)
9198 {
9199 #ifdef SYM_CONF_NVRAM_SUPPORT
9200 switch(nvp->type) {
9201 case SYM_SYMBIOS_NVRAM:
9202 sym_Symbios_setup_target (np, target, &nvp->data.Symbios);
9203 break;
9204 case SYM_TEKRAM_NVRAM:
9205 sym_Tekram_setup_target (np, target, &nvp->data.Tekram);
9206 break;
9207 default:
9208 break;
9209 }
9210 #endif
9211 }
9212
9213 #ifdef SYM_CONF_NVRAM_SUPPORT
9214 /*
9215 * Get target set-up from Symbios format NVRAM.
9216 */
9217 static void
9218 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram)
9219 {
9220 tcb_p tp = &np->target[target];
9221 Symbios_target *tn = &nvram->target[target];
9222
9223 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0;
9224 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT;
9225 tp->usrtags =
9226 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0;
9227
9228 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE))
9229 tp->usrflags &= ~SYM_DISC_ENABLED;
9230 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME))
9231 tp->usrflags |= SYM_SCAN_BOOT_DISABLED;
9232 if (!(tn->flags & SYMBIOS_SCAN_LUNS))
9233 tp->usrflags |= SYM_SCAN_LUNS_DISABLED;
9234 }
9235
9236 /*
9237 * Get target set-up from Tekram format NVRAM.
9238 */
9239 static void
9240 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram)
9241 {
9242 tcb_p tp = &np->target[target];
9243 struct Tekram_target *tn = &nvram->target[target];
9244 int i;
9245
9246 if (tn->flags & TEKRAM_SYNC_NEGO) {
9247 i = tn->sync_index & 0xf;
9248 tp->tinfo.user.period = Tekram_sync[i];
9249 }
9250
9251 tp->tinfo.user.width =
9252 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT;
9253
9254 if (tn->flags & TEKRAM_TAGGED_COMMANDS) {
9255 tp->usrtags = 2 << nvram->max_tags_index;
9256 }
9257
9258 if (tn->flags & TEKRAM_DISCONNECT_ENABLE)
9259 tp->usrflags |= SYM_DISC_ENABLED;
9260
9261 /* If any device does not support parity, we will not use this option */
9262 if (!(tn->flags & TEKRAM_PARITY_CHECK))
9263 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */
9264 }
9265
9266 #ifdef SYM_CONF_DEBUG_NVRAM
9267 /*
9268 * Dump Symbios format NVRAM for debugging purpose.
9269 */
9270 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram)
9271 {
9272 int i;
9273
9274 /* display Symbios nvram host data */
9275 printf("%s: HOST ID=%d%s%s%s%s%s%s\n",
9276 sym_name(np), nvram->host_id & 0x0f,
9277 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"",
9278 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"",
9279 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"",
9280 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"",
9281 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"",
9282 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :"");
9283
9284 /* display Symbios nvram drive data */
9285 for (i = 0 ; i < 15 ; i++) {
9286 struct Symbios_target *tn = &nvram->target[i];
9287 printf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n",
9288 sym_name(np), i,
9289 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "",
9290 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "",
9291 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "",
9292 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "",
9293 tn->bus_width,
9294 tn->sync_period / 4,
9295 tn->timeout);
9296 }
9297 }
9298
9299 /*
9300 * Dump TEKRAM format NVRAM for debugging purpose.
9301 */
9302 static const u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120};
9303 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram)
9304 {
9305 int i, tags, boot_delay;
9306 char *rem;
9307
9308 /* display Tekram nvram host data */
9309 tags = 2 << nvram->max_tags_index;
9310 boot_delay = 0;
9311 if (nvram->boot_delay_index < 6)
9312 boot_delay = Tekram_boot_delay[nvram->boot_delay_index];
9313 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) {
9314 default:
9315 case 0: rem = ""; break;
9316 case 1: rem = " REMOVABLE=boot device"; break;
9317 case 2: rem = " REMOVABLE=all"; break;
9318 }
9319
9320 printf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n",
9321 sym_name(np), nvram->host_id & 0x0f,
9322 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"",
9323 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"",
9324 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"",
9325 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"",
9326 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"",
9327 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"",
9328 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"",
9329 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"",
9330 rem, boot_delay, tags);
9331
9332 /* display Tekram nvram drive data */
9333 for (i = 0; i <= 15; i++) {
9334 int sync, j;
9335 struct Tekram_target *tn = &nvram->target[i];
9336 j = tn->sync_index & 0xf;
9337 sync = Tekram_sync[j];
9338 printf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n",
9339 sym_name(np), i,
9340 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "",
9341 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "",
9342 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "",
9343 (tn->flags & TEKRAM_START_CMD) ? " START" : "",
9344 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "",
9345 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "",
9346 sync);
9347 }
9348 }
9349 #endif /* SYM_CONF_DEBUG_NVRAM */
9350 #endif /* SYM_CONF_NVRAM_SUPPORT */
9351
9352
9353 /*
9354 * Try reading Symbios or Tekram NVRAM
9355 */
9356 #ifdef SYM_CONF_NVRAM_SUPPORT
9357 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram);
9358 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram);
9359 #endif
9360
9361 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp)
9362 {
9363 #ifdef SYM_CONF_NVRAM_SUPPORT
9364 /*
9365 * Try to read SYMBIOS nvram.
9366 * Try to read TEKRAM nvram if Symbios nvram not found.
9367 */
9368 if (SYM_SETUP_SYMBIOS_NVRAM &&
9369 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) {
9370 nvp->type = SYM_SYMBIOS_NVRAM;
9371 #ifdef SYM_CONF_DEBUG_NVRAM
9372 sym_display_Symbios_nvram(np, &nvp->data.Symbios);
9373 #endif
9374 }
9375 else if (SYM_SETUP_TEKRAM_NVRAM &&
9376 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) {
9377 nvp->type = SYM_TEKRAM_NVRAM;
9378 #ifdef SYM_CONF_DEBUG_NVRAM
9379 sym_display_Tekram_nvram(np, &nvp->data.Tekram);
9380 #endif
9381 }
9382 else
9383 nvp->type = 0;
9384 #else
9385 nvp->type = 0;
9386 #endif
9387 return nvp->type;
9388 }
9389
9390
9391 #ifdef SYM_CONF_NVRAM_SUPPORT
9392 /*
9393 * 24C16 EEPROM reading.
9394 *
9395 * GPOI0 - data in/data out
9396 * GPIO1 - clock
9397 * Symbios NVRAM wiring now also used by Tekram.
9398 */
9399
9400 #define SET_BIT 0
9401 #define CLR_BIT 1
9402 #define SET_CLK 2
9403 #define CLR_CLK 3
9404
9405 /*
9406 * Set/clear data/clock bit in GPIO0
9407 */
9408 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg,
9409 int bit_mode)
9410 {
9411 UDELAY (5);
9412 switch (bit_mode){
9413 case SET_BIT:
9414 *gpreg |= write_bit;
9415 break;
9416 case CLR_BIT:
9417 *gpreg &= 0xfe;
9418 break;
9419 case SET_CLK:
9420 *gpreg |= 0x02;
9421 break;
9422 case CLR_CLK:
9423 *gpreg &= 0xfd;
9424 break;
9425
9426 }
9427 OUTB (nc_gpreg, *gpreg);
9428 UDELAY (5);
9429 }
9430
9431 /*
9432 * Send START condition to NVRAM to wake it up.
9433 */
9434 static void S24C16_start(hcb_p np, u_char *gpreg)
9435 {
9436 S24C16_set_bit(np, 1, gpreg, SET_BIT);
9437 S24C16_set_bit(np, 0, gpreg, SET_CLK);
9438 S24C16_set_bit(np, 0, gpreg, CLR_BIT);
9439 S24C16_set_bit(np, 0, gpreg, CLR_CLK);
9440 }
9441
9442 /*
9443 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!!
9444 */
9445 static void S24C16_stop(hcb_p np, u_char *gpreg)
9446 {
9447 S24C16_set_bit(np, 0, gpreg, SET_CLK);
9448 S24C16_set_bit(np, 1, gpreg, SET_BIT);
9449 }
9450
9451 /*
9452 * Read or write a bit to the NVRAM,
9453 * read if GPIO0 input else write if GPIO0 output
9454 */
9455 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit,
9456 u_char *gpreg)
9457 {
9458 S24C16_set_bit(np, write_bit, gpreg, SET_BIT);
9459 S24C16_set_bit(np, 0, gpreg, SET_CLK);
9460 if (read_bit)
9461 *read_bit = INB (nc_gpreg);
9462 S24C16_set_bit(np, 0, gpreg, CLR_CLK);
9463 S24C16_set_bit(np, 0, gpreg, CLR_BIT);
9464 }
9465
9466 /*
9467 * Output an ACK to the NVRAM after reading,
9468 * change GPIO0 to output and when done back to an input
9469 */
9470 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg,
9471 u_char *gpcntl)
9472 {
9473 OUTB (nc_gpcntl, *gpcntl & 0xfe);
9474 S24C16_do_bit(np, 0, write_bit, gpreg);
9475 OUTB (nc_gpcntl, *gpcntl);
9476 }
9477
9478 /*
9479 * Input an ACK from NVRAM after writing,
9480 * change GPIO0 to input and when done back to an output
9481 */
9482 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg,
9483 u_char *gpcntl)
9484 {
9485 OUTB (nc_gpcntl, *gpcntl | 0x01);
9486 S24C16_do_bit(np, read_bit, 1, gpreg);
9487 OUTB (nc_gpcntl, *gpcntl);
9488 }
9489
9490 /*
9491 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK,
9492 * GPIO0 must already be set as an output
9493 */
9494 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data,
9495 u_char *gpreg, u_char *gpcntl)
9496 {
9497 int x;
9498
9499 for (x = 0; x < 8; x++)
9500 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg);
9501
9502 S24C16_read_ack(np, ack_data, gpreg, gpcntl);
9503 }
9504
9505 /*
9506 * READ a byte from the NVRAM and then send an ACK to say we have got it,
9507 * GPIO0 must already be set as an input
9508 */
9509 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data,
9510 u_char *gpreg, u_char *gpcntl)
9511 {
9512 int x;
9513 u_char read_bit;
9514
9515 *read_data = 0;
9516 for (x = 0; x < 8; x++) {
9517 S24C16_do_bit(np, &read_bit, 1, gpreg);
9518 *read_data |= ((read_bit & 0x01) << (7 - x));
9519 }
9520
9521 S24C16_write_ack(np, ack_data, gpreg, gpcntl);
9522 }
9523
9524 /*
9525 * Read 'len' bytes starting at 'offset'.
9526 */
9527 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len)
9528 {
9529 u_char gpcntl, gpreg;
9530 u_char old_gpcntl, old_gpreg;
9531 u_char ack_data;
9532 int retv = 1;
9533 int x;
9534
9535 /* save current state of GPCNTL and GPREG */
9536 old_gpreg = INB (nc_gpreg);
9537 old_gpcntl = INB (nc_gpcntl);
9538 gpcntl = old_gpcntl & 0x1c;
9539
9540 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */
9541 OUTB (nc_gpreg, old_gpreg);
9542 OUTB (nc_gpcntl, gpcntl);
9543
9544 /* this is to set NVRAM into a known state with GPIO0/1 both low */
9545 gpreg = old_gpreg;
9546 S24C16_set_bit(np, 0, &gpreg, CLR_CLK);
9547 S24C16_set_bit(np, 0, &gpreg, CLR_BIT);
9548
9549 /* now set NVRAM inactive with GPIO0/1 both high */
9550 S24C16_stop(np, &gpreg);
9551
9552 /* activate NVRAM */
9553 S24C16_start(np, &gpreg);
9554
9555 /* write device code and random address MSB */
9556 S24C16_write_byte(np, &ack_data,
9557 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl);
9558 if (ack_data & 0x01)
9559 goto out;
9560
9561 /* write random address LSB */
9562 S24C16_write_byte(np, &ack_data,
9563 offset & 0xff, &gpreg, &gpcntl);
9564 if (ack_data & 0x01)
9565 goto out;
9566
9567 /* regenerate START state to set up for reading */
9568 S24C16_start(np, &gpreg);
9569
9570 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */
9571 S24C16_write_byte(np, &ack_data,
9572 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl);
9573 if (ack_data & 0x01)
9574 goto out;
9575
9576 /* now set up GPIO0 for inputting data */
9577 gpcntl |= 0x01;
9578 OUTB (nc_gpcntl, gpcntl);
9579
9580 /* input all requested data - only part of total NVRAM */
9581 for (x = 0; x < len; x++)
9582 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl);
9583
9584 /* finally put NVRAM back in inactive mode */
9585 gpcntl &= 0xfe;
9586 OUTB (nc_gpcntl, gpcntl);
9587 S24C16_stop(np, &gpreg);
9588 retv = 0;
9589 out:
9590 /* return GPIO0/1 to original states after having accessed NVRAM */
9591 OUTB (nc_gpcntl, old_gpcntl);
9592 OUTB (nc_gpreg, old_gpreg);
9593
9594 return retv;
9595 }
9596
9597 #undef SET_BIT /* 0 */
9598 #undef CLR_BIT /* 1 */
9599 #undef SET_CLK /* 2 */
9600 #undef CLR_CLK /* 3 */
9601
9602 /*
9603 * Try reading Symbios NVRAM.
9604 * Return 0 if OK.
9605 */
9606 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram)
9607 {
9608 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0};
9609 u_char *data = (u_char *) nvram;
9610 int len = sizeof(*nvram);
9611 u_short csum;
9612 int x;
9613
9614 /* probe the 24c16 and read the SYMBIOS 24c16 area */
9615 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len))
9616 return 1;
9617
9618 /* check valid NVRAM signature, verify byte count and checksum */
9619 if (nvram->type != 0 ||
9620 bcmp(nvram->trailer, Symbios_trailer, 6) ||
9621 nvram->byte_count != len - 12)
9622 return 1;
9623
9624 /* verify checksum */
9625 for (x = 6, csum = 0; x < len - 6; x++)
9626 csum += data[x];
9627 if (csum != nvram->checksum)
9628 return 1;
9629
9630 return 0;
9631 }
9632
9633 /*
9634 * 93C46 EEPROM reading.
9635 *
9636 * GPOI0 - data in
9637 * GPIO1 - data out
9638 * GPIO2 - clock
9639 * GPIO4 - chip select
9640 *
9641 * Used by Tekram.
9642 */
9643
9644 /*
9645 * Pulse clock bit in GPIO0
9646 */
9647 static void T93C46_Clk(hcb_p np, u_char *gpreg)
9648 {
9649 OUTB (nc_gpreg, *gpreg | 0x04);
9650 UDELAY (2);
9651 OUTB (nc_gpreg, *gpreg);
9652 }
9653
9654 /*
9655 * Read bit from NVRAM
9656 */
9657 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg)
9658 {
9659 UDELAY (2);
9660 T93C46_Clk(np, gpreg);
9661 *read_bit = INB (nc_gpreg);
9662 }
9663
9664 /*
9665 * Write bit to GPIO0
9666 */
9667 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg)
9668 {
9669 if (write_bit & 0x01)
9670 *gpreg |= 0x02;
9671 else
9672 *gpreg &= 0xfd;
9673
9674 *gpreg |= 0x10;
9675
9676 OUTB (nc_gpreg, *gpreg);
9677 UDELAY (2);
9678
9679 T93C46_Clk(np, gpreg);
9680 }
9681
9682 /*
9683 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!!
9684 */
9685 static void T93C46_Stop(hcb_p np, u_char *gpreg)
9686 {
9687 *gpreg &= 0xef;
9688 OUTB (nc_gpreg, *gpreg);
9689 UDELAY (2);
9690
9691 T93C46_Clk(np, gpreg);
9692 }
9693
9694 /*
9695 * Send read command and address to NVRAM
9696 */
9697 static void T93C46_Send_Command(hcb_p np, u_short write_data,
9698 u_char *read_bit, u_char *gpreg)
9699 {
9700 int x;
9701
9702 /* send 9 bits, start bit (1), command (2), address (6) */
9703 for (x = 0; x < 9; x++)
9704 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg);
9705
9706 *read_bit = INB (nc_gpreg);
9707 }
9708
9709 /*
9710 * READ 2 bytes from the NVRAM
9711 */
9712 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg)
9713 {
9714 int x;
9715 u_char read_bit;
9716
9717 *nvram_data = 0;
9718 for (x = 0; x < 16; x++) {
9719 T93C46_Read_Bit(np, &read_bit, gpreg);
9720
9721 if (read_bit & 0x01)
9722 *nvram_data |= (0x01 << (15 - x));
9723 else
9724 *nvram_data &= ~(0x01 << (15 - x));
9725 }
9726 }
9727
9728 /*
9729 * Read Tekram NvRAM data.
9730 */
9731 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg)
9732 {
9733 u_char read_bit;
9734 int x;
9735
9736 for (x = 0; x < len; x++) {
9737
9738 /* output read command and address */
9739 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg);
9740 if (read_bit & 0x01)
9741 return 1; /* Bad */
9742 T93C46_Read_Word(np, &data[x], gpreg);
9743 T93C46_Stop(np, gpreg);
9744 }
9745
9746 return 0;
9747 }
9748
9749 /*
9750 * Try reading 93C46 Tekram NVRAM.
9751 */
9752 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram)
9753 {
9754 u_char gpcntl, gpreg;
9755 u_char old_gpcntl, old_gpreg;
9756 int retv = 1;
9757
9758 /* save current state of GPCNTL and GPREG */
9759 old_gpreg = INB (nc_gpreg);
9760 old_gpcntl = INB (nc_gpcntl);
9761
9762 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in,
9763 1/2/4 out */
9764 gpreg = old_gpreg & 0xe9;
9765 OUTB (nc_gpreg, gpreg);
9766 gpcntl = (old_gpcntl & 0xe9) | 0x09;
9767 OUTB (nc_gpcntl, gpcntl);
9768
9769 /* input all of NVRAM, 64 words */
9770 retv = T93C46_Read_Data(np, (u_short *) nvram,
9771 sizeof(*nvram) / sizeof(short), &gpreg);
9772
9773 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */
9774 OUTB (nc_gpcntl, old_gpcntl);
9775 OUTB (nc_gpreg, old_gpreg);
9776
9777 return retv;
9778 }
9779
9780 /*
9781 * Try reading Tekram NVRAM.
9782 * Return 0 if OK.
9783 */
9784 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram)
9785 {
9786 u_char *data = (u_char *) nvram;
9787 int len = sizeof(*nvram);
9788 u_short csum;
9789 int x;
9790
9791 switch (np->device_id) {
9792 case PCI_ID_SYM53C885:
9793 case PCI_ID_SYM53C895:
9794 case PCI_ID_SYM53C896:
9795 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS,
9796 data, len);
9797 break;
9798 case PCI_ID_SYM53C875:
9799 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS,
9800 data, len);
9801 if (!x)
9802 break;
9803 default:
9804 x = sym_read_T93C46_nvram(np, nvram);
9805 break;
9806 }
9807 if (x)
9808 return 1;
9809
9810 /* verify checksum */
9811 for (x = 0, csum = 0; x < len - 1; x += 2)
9812 csum += data[x] + (data[x+1] << 8);
9813 if (csum != 0x1234)
9814 return 1;
9815
9816 return 0;
9817 }
9818
9819 #endif /* SYM_CONF_NVRAM_SUPPORT */
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