FreeBSD/Linux Kernel Cross Reference
sys/dev/tc/tcdsreg.h
1 /* $OpenBSD: tcdsreg.h,v 1.3 2007/05/26 00:36:03 krw Exp $ */
2 /* $NetBSD: tcdsreg.h,v 1.1 2000/07/04 02:22:20 nisimura Exp $ */
3
4 /*
5 * Copyright (c) 1994, 1995 Carnegie-Mellon University.
6 * All rights reserved.
7 *
8 * Authors: Keith Bostic, Chris G. Demetriou
9 *
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
15 *
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 *
20 * Carnegie Mellon requests users of this software to return to
21 *
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
26 *
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
29 */
30
31 /*
32 * Offsets to the SCSI chips
33 */
34 #define TCDS_SCSI0_OFFSET 0x080000
35 #define TCDS_SCSI1_OFFSET 0x080100
36
37 /*
38 * TCDS register offsets, bit masks.
39 */
40 #define TCDS_EEPROM 0x000000 /* EEPROM offset */
41 #define TCDS_EEPROM_IDS 0x000008 /* SCSI IDs offset in EEPROM */
42
43 #define TCDS_CIR 0x040000 /* CIR offset */
44
45 /*
46 * TCDS CIR control bits.
47 */
48 #define TCDS_CIR_GPO_0 0x00000001 /* Not used */
49 #define TCDS_CIR_GPO_1 0x00000002 /* Not used */
50 #define TCDS_CIR_GPO_2 0x00000004 /* Not used */
51 #define TCDS_CIR_STD 0x00000008 /* Serial transmit disable */
52 #define TCDS_CIR_GPI_0 0x00000010 /* Not used */
53 #define TCDS_CIR_GPI_1 0x00000020 /* Not used */
54 #define TCDS_CIR_GPI_2 0x00000040 /* 1 = 25MHz, 0 = 40MHz */
55 #define TCDS_CIR_GPI_3 0x00000080 /* Not used */
56 #define TCDS_CIR_SCSI0_DMAENA 0x00000100 /* SCSI 0 DMA enable */
57 #define TCDS_CIR_SCSI1_DMAENA 0x00000200 /* SCSI 1 DMA enable */
58 #define TCDS_CIR_SCSI0_RESET 0x00000400 /* SCSI 0 reset */
59 #define TCDS_CIR_SCSI1_RESET 0x00000800 /* SCSI 1 reset */
60 #define TCDS_CIR_SCSI0_DMA_TEST 0x00001000 /* SCSI 0 DMA buf parity test */
61 #define TCDS_CIR_SCSI1_DMA_TEST 0x00002000 /* SCSI 1 DMA buf parity test */
62 #define TCDS_CIR_DB_PAR 0x00004000 /* DB parity test mode */
63 #define TCDS_CIR_TC_PAR 0x00008000 /* TC parity test mode */
64 #define TCDS_CIR_ALLCONTROL 0x0000ffff /* all control bits */
65
66 /* TCDS CIR interrupt bits. */
67 #define TCDS_CIR_SCSI0_DREQ 0x00010000 /* SCSI 0 DREQ */
68 #define TCDS_CIR_SCSI1_DREQ 0x00020000 /* SCSI 1 DREQ */
69 #define TCDS_CIR_SCSI0_INT 0x00040000 /* SCSI 0 interrupt */
70 #define TCDS_CIR_SCSI1_INT 0x00080000 /* SCSI 1 interrupt */
71 #define TCDS_CIR_SCSI0_PREFETCH 0x00100000 /* SCSI 0 prefetch */
72 #define TCDS_CIR_SCSI1_PREFETCH 0x00200000 /* SCSI 1 prefetch */
73 #define TCDS_CIR_SCSI0_DMA 0x00400000 /* SCSI 0 DMA error */
74 #define TCDS_CIR_SCSI1_DMA 0x00800000 /* SCSI 1 DMA error */
75 #define TCDS_CIR_SCSI0_DB 0x01000000 /* SCSI 0 DB parity */
76 #define TCDS_CIR_SCSI1_DB 0x02000000 /* SCSI 1 DB parity */
77 #define TCDS_CIR_SCSI0_DMAB_PAR 0x04000000 /* SCSI 0 DMA buffer parity */
78 #define TCDS_CIR_SCSI1_DMAB_PAR 0x08000000 /* SCSI 1 DMA buffer parity */
79 #define TCDS_CIR_SCSI0_DMAR_PAR 0x10000000 /* SCSI 0 DMA read parity */
80 #define TCDS_CIR_SCSI1_DMAR_PAR 0x20000000 /* SCSI 1 DMA read parity */
81 #define TCDS_CIR_TCIOW_PAR 0x40000000 /* TC I/O write parity */
82 #define TCDS_CIR_TCIOA_PAR 0x80000000 /* TC I/O address parity */
83 #define TCDS_CIR_ALLINTR 0xffff0000 /* all interrupt bits */
84
85 #define TCDS_CIR_CLR(c, b) c = ((c | TCDS_CIR_ALLINTR) & ~b)
86 #define TCDS_CIR_SET(c, b) c = ((c | TCDS_CIR_ALLINTR) | b)
87
88 /* TCDS IMER masks and enables, for interrupts in the CIR. */
89 #define TCDS_IMER_SCSI0_MASK 0x04 /* SCSI 0 intr/enable mask */
90 #define TCDS_IMER_SCSI1_MASK 0x08 /* SCSI 1 intr/enable mask */
91 #define TCDS_IMER_SCSI0_ENB (TCDS_IMER_SCSI0_MASK << 16)
92 #define TCDS_IMER_SCSI1_ENB (TCDS_IMER_SCSI1_MASK << 16)
93 #define TCDS_IMER 0x040004 /* IMER offset */
94
95 #define TCDS_SCSI0_DMA_ADDR 0x041000 /* DMA address */
96 #define TCDS_SCSI0_DMA_INTR 0x041004 /* DMA interrupt control */
97 #define TCDS_SCSI0_DMA_DUD0 0x041008 /* DMA unaligned data[0] */
98 #define TCDS_SCSI0_DMA_DUD1 0x04100c /* DMA unaligned data[1] */
99
100 #define TCDS_SCSI1_DMA_ADDR 0x041100 /* DMA address */
101 #define TCDS_SCSI1_DMA_INTR 0x041104 /* DMA interrupt control */
102 #define TCDS_SCSI1_DMA_DUD0 0x041108 /* DMA unaligned data[0] */
103 #define TCDS_SCSI1_DMA_DUD1 0x04110c /* DMA unaligned data[1] */
104
105 #define TCDS_DIC_ADDRMASK 0x03 /* DMA address bits <1:0> */
106 #define TCDS_DIC_READ_PREFETCH 0x40 /* DMA read prefetch enable */
107 #define TCDS_DIC_WRITE 0x80 /* DMA write */
108
109 #define TCDS_DUD0_VALID00 0x00000001 /* byte 00 valid mask (zero) */
110 #define TCDS_DUD0_VALID01 0x00000002 /* byte 01 valid mask */
111 #define TCDS_DUD0_VALID10 0x00000004 /* byte 10 valid mask */
112 #define TCDS_DUD0_VALID11 0x00000008 /* byte 11 valid mask */
113 #define TCDS_DUD0_VALIDBITS 0x0000000f /* bits that show valid bytes */
114
115 #define TCDS_DUD1_VALID00 0x01000000 /* byte 00 valid mask */
116 #define TCDS_DUD1_VALID01 0x02000000 /* byte 01 valid mask */
117 #define TCDS_DUD1_VALID10 0x04000000 /* byte 10 valid mask */
118 #define TCDS_DUD1_VALID11 0x08000000 /* byte 11 valid mask (zero) */
119 #define TCDS_DUD1_VALIDBITS 0x0f000000 /* bits that show valid bytes */
120
121 #define TCDS_DUD_BYTE00 0x000000ff /* byte 00 mask */
122 #define TCDS_DUD_BYTE01 0x0000ff00 /* byte 01 mask */
123 #define TCDS_DUD_BYTE10 0x00ff0000 /* byte 10 mask */
124 #define TCDS_DUD_BYTE11 0xff000000 /* byte 11 mask */
125
126 #if 0
127 int tcds_scsi_iserr(struct dma_softc *);
128 int tcds_scsi_isintr(int, int);
129 void tcds_dma_disable(int);
130 void tcds_dma_enable(int);
131 void tcds_dma_init(struct dma_softc *, int);
132 void tcds_scsi_disable(int);
133 void tcds_scsi_enable(int);
134 void tcds_scsi_reset(int);
135
136 /*
137 * XXX
138 * Start of MACH #defines, minimal changes to port to NetBSD.
139 *
140 * The following register is the SCSI control interrupt register. It
141 * starts, stops and resets scsi DMA. It takes over the SCSI functions
142 * that were handled by the ASIC on the 3min.
143 */
144 #define KN15AA_SYS_SCSI 0x1d0000000
145 #define KN15AA_REG_SCSI_CIR (KN15AA_SYS_SCSI + 0x80000)
146 #define SCSI_CIR_AIOPAR 0x80000000 /* TC IO Address parity error */
147 #define SCSI_CIR_WDIOPAR 0x40000000 /* TC IO write data parity error */
148 #define SCSI_CIR_DMARPAR1 0x20000000 /* SCSI[1] TC DMA read data parity */
149 #define SCSI_CIR_DMARPAR0 0x10000000 /* SCSI[0] TC DMA read data parity */
150 #define SCSI_CIR_DMABUFPAR1 0x08000000 /* SCSI[1] DMA buffer parity error */
151 #define SCSI_CIR_DMABUFPAR0 0x04000000 /* SCSI[0] DMA buffer parity error */
152 #define SCSI_CIR_DBPAR1 0x02000000 /* SCSI[1] DB parity error */
153 #define SCSI_CIR_DBPAR0 0x01000000 /* SCSI[0] DB parity error */
154 #define SCSI_CIR_DMAERR1 0x00800000 /* SCSI[1] DMA error */
155 #define SCSI_CIR_DMAERR0 0x00400000 /* SCSI[0] DMA error */
156 #if fmm50
157 #define SCSI_CIR_xxx0 0x00200000 /* RESERVED */
158 #define SCSI_CIR_xxx1 0x00100000 /* RESERVED */
159 #else
160 #define SCSI_CIR_PREF1 0x00200000 /* 53C94 prefetch interrupt */
161 #define SCSI_CIR_PREF0 0x00100000 /* 53C94 prefetch interrupt */
162 #endif
163 #define SCSI_CIR_53C94_INT1 0x00080000 /* SCSI[1] 53C94 Interrupt */
164 #define SCSI_CIR_53C94_INT0 0x00040000 /* SCSI[0] 53C94 Interrupt */
165 #define SCSI_CIR_53C94_DREQ1 0x00020000 /* SCSI[1] 53C94 DREQ */
166 #define SCSI_CIR_53C94_DREQ0 0x00010000 /* SCSI[0] 53C94 DREQ */
167 #define SCSI_CIR_TC_PAR_TEST 0x00008000 /* TC parity test mode */
168 #define SCSI_CIR_DB_PAR_TEST 0x00004000 /* DB parity test mode */
169 #define SCSI_CIR_DBUF_PAR_TEST1 0x00002000 /* SCSI[1] DMA buffer parity test */
170 #define SCSI_CIR_DBUF_PAR_TEST0 0x00001000 /* SCSI[0] DMA buffer parity test */
171 #define SCSI_CIR_RESET1 0x00000800 /* SCSI[1] ~Reset,enable(0)/disable(1) */
172 #define SCSI_CIR_RESET0 0x00000400 /* SCSI[0] ~Reset,enable(0)/disable(1) */
173 #define SCSI_CIR_DMAENA1 0x00000200 /* SCSI[1] DMA enable */
174 #define SCSI_CIR_DMAENA0 0x00000100 /* SCSI[1] DMA enable */
175 #define SCSI_CIR_GPI3 0x00000080 /* General purpose input <3> */
176 #define SCSI_CIR_GPI2 0x00000040 /* General purpose input <2> */
177 #define SCSI_CIR_GPI1 0x00000020 /* General purpose input <1> */
178 #define SCSI_CIR_GPI0 0x00000010 /* General purpose input <0> */
179 #define SCSI_CIR_TXDIS 0x00000008 /* TXDIS- serial transmit disable */
180 #define SCSI_CIR_GPO2 0x00000004 /* General purpose output <2> */
181 #define SCSI_CIR_GPO1 0x00000002 /* General purpose output <1> */
182 #define SCSI_CIR_GPO0 0x00000001 /* General purpose output <0> */
183 #define SCSI_CIR_ERROR (SCSI_CIR_AIOPAR | SCSI_CIR_WDIOPAR | SCSI_CIR_DMARPAR1 | SCSI_CIR_DMARPAR0 | SCSI_CIR_DMABUFPAR1 | SCSI_CIR_DMABUFPAR0 | SCSI_CIR_DBPAR1 |SCSI_CIR_DBPAR0 | SCSI_CIR_DMAERR1 | SCSI_CIR_DMAERR0 )
184
185 #define KN15AA_REG_SCSI_DMAPTR0 (KN15AA_SYS_SCSI + 0x82000)
186 #define KN15AA_REG_SCSI_DMAPTR1 (KN15AA_SYS_SCSI + 0x82200)
187
188 #define KN15AA_REG_SCSI_DIC0 (KN15AA_SYS_SCSI + 0x82008)
189 #define KN15AA_REG_SCSI_DIC1 (KN15AA_SYS_SCSI + 0x82208)
190 #define SCSI_DIC_DMADIR 0x00000080 /* DMA direction read(0)/write(1) */
191 #define SCSI_DIC_PREFENA 0x00000040 /* DMA read prefetch dis(0)/ena(1) */
192 #define SCSI_DIC_DMAADDR1 0x00000002 /* DMA address <1> */
193 #define SCSI_DIC_DMAADDR0 0x00000001 /* DMA address <0> */
194 #define SCSI_DIC_ADDR_MASK (SCSI_DIC_DMAADDR0 |SCSI_DIC_DMAADDR1)
195
196 #define KN15AA_REG_SCSI_94REG0 (KN15AA_SYS_SCSI + 0x100000)
197 #define KN15AA_REG_SCSI_94REG1 (KN15AA_SYS_SCSI + 0x100200)
198
199 #define KN15AA_REG_SCSI_IMER (KN15AA_SYS_SCSI + 0x80008)
200
201 /* these are the bits that were unaligned at the beginning of the dma */
202 #define KN15AA_REG_SCSI_DUDB0 (KN15AA_SYS_SCSI + 0x82010)
203 #define KN15AA_REG_SCSI_DUDB1 (KN15AA_SYS_SCSI + 0x82210)
204 # define SCSI_DUDB_MASK01 0x00000001 /* Mask bit for byte[01] */
205 # define SCSI_DUDB_MASK10 0x00000002 /* Mask bit for byte[10] */
206 # define SCSI_DUDB_MASK11 0x00000004 /* Mask bit for byte[11] */
207
208 /* these are the bits that were unaligned at the end of the dma */
209 #define KN15AA_REG_SCSI_DUDE0 (KN15AA_SYS_SCSI + 0x82018)
210 #define KN15AA_REG_SCSI_DUDE1 (KN15AA_SYS_SCSI + 0x82218)
211 # define SCSI_DUDE_MASK00 0x1000000 /* Mask bit for byte[00] */
212 # define SCSI_DUDE_MASK01 0x2000000 /* Mask bit for byte[01] */
213 # define SCSI_DUDE_MASK10 0x4000000 /* Mask bit for byte[10] */
214
215 #define SCSI_CIR ALPHA_PHYS_TO_K0SEG(KN15AA_REG_SCSI_CIR)
216 #define SCSI_IMER ALPHA_PHYS_TO_K0SEG(KN15AA_REG_SCSI_IMER)
217
218 #endif
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