The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/tc/zs_ioasic.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /* $NetBSD: zs_ioasic.c,v 1.21 2003/03/06 00:38:28 matt Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the
    9  * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *        This product includes software developed by the NetBSD
   22  *        Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * Zilog Z8530 Dual UART driver (machine-dependent part).  This driver
   42  * handles Z8530 chips attached to the DECstation/Alpha IOASIC.  Modified
   43  * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe.  NetBSD/pmax
   44  * adaption by Mattias Drochner.  Merge work by Tohru Nishimura.
   45  *
   46  * Runs two serial lines per chip using slave drivers.
   47  * Plain tty/async lines use the zstty slave.
   48  */
   49 
   50 #include <sys/cdefs.h>
   51 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.21 2003/03/06 00:38:28 matt Exp $");
   52 
   53 #include "opt_ddb.h"
   54 #include "opt_kgdb.h"
   55 #include "zskbd.h"
   56 
   57 #include <sys/param.h>
   58 #include <sys/systm.h>
   59 #include <sys/conf.h>
   60 #include <sys/device.h>
   61 #include <sys/malloc.h>
   62 #include <sys/file.h>
   63 #include <sys/ioctl.h>
   64 #include <sys/kernel.h>
   65 #include <sys/proc.h>
   66 #include <sys/tty.h>
   67 #include <sys/time.h>
   68 #include <sys/syslog.h>
   69 
   70 #include <machine/autoconf.h>
   71 #include <machine/intr.h>
   72 #include <machine/z8530var.h>
   73 
   74 #include <dev/cons.h>
   75 #include <dev/ic/z8530reg.h>
   76 
   77 #include <dev/tc/tcvar.h>
   78 #include <dev/tc/ioasicreg.h>
   79 #include <dev/tc/ioasicvar.h>
   80 
   81 #include <dev/tc/zs_ioasicvar.h>
   82 
   83 #if defined(__alpha__) || defined(alpha)
   84 #include <machine/rpb.h>
   85 #endif
   86 #if defined(pmax)
   87 #include <pmax/pmax/pmaxtype.h>
   88 #endif
   89 
   90 /*
   91  * Helpers for console support.
   92  */
   93 void    zs_ioasic_cninit __P((tc_addr_t, tc_offset_t, int));
   94 int     zs_ioasic_cngetc __P((dev_t));
   95 void    zs_ioasic_cnputc __P((dev_t, int));
   96 void    zs_ioasic_cnpollc __P((dev_t, int));
   97 
   98 struct consdev zs_ioasic_cons = {
   99         NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc,
  100         zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL,
  101 };
  102 
  103 tc_offset_t zs_ioasic_console_offset;
  104 int zs_ioasic_console_channel;
  105 int zs_ioasic_console;
  106 struct zs_chanstate zs_ioasic_conschanstate_store;
  107 
  108 int     zs_ioasic_isconsole __P((tc_offset_t, int));
  109 int     zs_getc __P((struct zs_chanstate *));
  110 void    zs_putc __P((struct zs_chanstate *, int));
  111 
  112 /*
  113  * Some warts needed by z8530tty.c
  114  */
  115 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
  116 
  117 /*
  118  * ZS chips are feeded a 7.372 MHz clock.
  119  */
  120 #define PCLK    (9600 * 768)    /* PCLK pin input clock rate */
  121 
  122 /* The layout of this is hardware-dependent (padding, order). */
  123 struct zshan {
  124 #if defined(__alpha__) || defined(alpha)
  125         volatile u_int  zc_csr;         /* ctrl,status, and indirect access */
  126         u_int           zc_pad0;
  127         volatile u_int  zc_data;        /* data */
  128         u_int           sc_pad1;
  129 #endif
  130 #if defined(pmax)
  131         volatile u_int16_t zc_csr;      /* ctrl,status, and indirect access */
  132         unsigned : 16;
  133         volatile u_int16_t zc_data;     /* data */
  134         unsigned : 16;
  135 #endif
  136 };
  137 
  138 struct zsdevice {
  139         /* Yes, they are backwards. */
  140         struct  zshan zs_chan_b;
  141         struct  zshan zs_chan_a;
  142 };
  143 
  144 static u_char zs_ioasic_init_reg[16] = {
  145         0,      /* 0: CMD (reset, etc.) */
  146         0,      /* 1: No interrupts yet. */
  147         0xf0,   /* 2: IVECT */
  148         ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
  149         ZSWR4_CLK_X16 | ZSWR4_ONESB,
  150         ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
  151         0,      /* 6: TXSYNC/SYNCLO */
  152         0,      /* 7: RXSYNC/SYNCHI */
  153         0,      /* 8: alias for data port */
  154         ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT,
  155         0,      /*10: Misc. TX/RX control bits */
  156         ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
  157         22,     /*12: BAUDLO (default=9600) */
  158         0,      /*13: BAUDHI (default=9600) */
  159         ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
  160         ZSWR15_BREAK_IE,
  161 };
  162 
  163 struct zshan *zs_ioasic_get_chan_addr __P((tc_addr_t, int));
  164 
  165 struct zshan *
  166 zs_ioasic_get_chan_addr(zsaddr, channel)
  167         tc_addr_t zsaddr;
  168         int channel;
  169 {
  170         struct zsdevice *addr;
  171         struct zshan *zc;
  172 
  173 #if defined(__alpha__) || defined(alpha)
  174         addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr);
  175 #endif
  176 #if defined(pmax)
  177         addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr);
  178 #endif
  179 
  180         if (channel == 0)
  181                 zc = &addr->zs_chan_a;
  182         else
  183                 zc = &addr->zs_chan_b;
  184 
  185         return (zc);
  186 }
  187 
  188 
  189 /****************************************************************
  190  * Autoconfig
  191  ****************************************************************/
  192 
  193 /* Definition of the driver for autoconfig. */
  194 int     zs_ioasic_match __P((struct device *, struct cfdata *, void *));
  195 void    zs_ioasic_attach __P((struct device *, struct device *, void *));
  196 int     zs_ioasic_print __P((void *, const char *name));
  197 int     zs_ioasic_submatch __P((struct device *, struct cfdata *, void *));
  198 
  199 CFATTACH_DECL(zsc_ioasic, sizeof(struct zsc_softc),
  200     zs_ioasic_match, zs_ioasic_attach, NULL, NULL);
  201 
  202 /* Interrupt handlers. */
  203 int     zs_ioasic_hardintr __P((void *));
  204 void    zs_ioasic_softintr __P((void *));
  205 
  206 /*
  207  * Is the zs chip present?
  208  */
  209 int
  210 zs_ioasic_match(parent, cf, aux)
  211         struct device *parent;
  212         struct cfdata *cf;
  213         void *aux;
  214 {
  215         struct ioasicdev_attach_args *d = aux;
  216         tc_addr_t zs_addr;
  217 
  218         /*
  219          * Make sure that we're looking for the right kind of device.
  220          */
  221         if (strncmp(d->iada_modname, "z8530   ", TC_ROM_LLEN) != 0 &&
  222             strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0)
  223                 return (0);
  224 
  225         /*
  226          * Check user-specified offset against the ioasic offset.
  227          * Allow it to be wildcarded.
  228          */
  229         if (cf->cf_loc[IOASICCF_OFFSET] != IOASICCF_OFFSET_DEFAULT &&
  230             cf->cf_loc[IOASICCF_OFFSET] != d->iada_offset)
  231                 return (0);
  232 
  233         /*
  234          * Find out the device address, and check it for validity.
  235          */
  236         zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr);
  237         if (tc_badaddr(zs_addr))
  238                 return (0);
  239 
  240         return (1);
  241 }
  242 
  243 /*
  244  * Attach a found zs.
  245  */
  246 void
  247 zs_ioasic_attach(parent, self, aux)
  248         struct device *parent;
  249         struct device *self;
  250         void *aux;
  251 {
  252         struct zsc_softc *zs = (void *) self;
  253         struct zsc_attach_args zs_args;
  254         struct zs_chanstate *cs;
  255         struct ioasicdev_attach_args *d = aux;
  256         struct zshan *zc;
  257         int s, channel;
  258         u_long zflg;
  259 
  260         printf("\n");
  261 
  262         /*
  263          * Initialize software state for each channel.
  264          */
  265         for (channel = 0; channel < 2; channel++) {
  266                 zs_args.channel = channel;
  267                 zs_args.hwflags = 0;
  268 
  269                 if (zs_ioasic_isconsole(d->iada_offset, channel)) {
  270                         cs = &zs_ioasic_conschanstate_store;
  271                         zs_args.hwflags |= ZS_HWFLAG_CONSOLE;
  272                 } else {
  273                         cs = malloc(sizeof(struct zs_chanstate),
  274                                         M_DEVBUF, M_NOWAIT|M_ZERO);
  275                         zc = zs_ioasic_get_chan_addr(d->iada_addr, channel);
  276                         cs->cs_reg_csr = (void *)&zc->zc_csr;
  277 
  278                         bcopy(zs_ioasic_init_reg, cs->cs_creg, 16);
  279                         bcopy(zs_ioasic_init_reg, cs->cs_preg, 16);
  280 
  281                         cs->cs_defcflag = zs_def_cflag;
  282                         cs->cs_defspeed = 9600;         /* XXX */
  283                         (void) zs_set_modes(cs, cs->cs_defcflag);
  284                 }
  285 
  286                 zs->zsc_cs[channel] = cs;
  287                 zs->zsc_addroffset = d->iada_offset; /* cookie only */
  288                 cs->cs_channel = channel;
  289                 cs->cs_ops = &zsops_null;
  290                 cs->cs_brg_clk = PCLK / 16;
  291 
  292                 /*
  293                  * DCD and CTS interrupts are only meaningful on
  294                  * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1.
  295                  *
  296                  * XXX This is sorta gross.
  297                  */
  298                 if (d->iada_offset == 0x00100000 && channel == 1) {
  299                         cs->cs_creg[15] |= ZSWR15_DCD_IE;
  300                         cs->cs_preg[15] |= ZSWR15_DCD_IE;
  301                         zflg = ZIP_FLAGS_DCDCTS;
  302                 } else
  303                         zflg = 0;
  304                 if (channel == 1)
  305                         zflg |= ZIP_FLAGS_DTRRTS;
  306                 (u_long)cs->cs_private = zflg;
  307 
  308                 /*
  309                  * Clear the master interrupt enable.
  310                  * The INTENA is common to both channels,
  311                  * so just do it on the A channel.
  312                  */
  313                 if (channel == 0) {
  314                         zs_write_reg(cs, 9, 0);
  315                 }
  316 
  317                 /*
  318                  * Set up the flow/modem control channel pointer to
  319                  * deal with the weird wiring on the TC Alpha and
  320                  * DECstation.
  321                  */
  322                 if (channel == 1)
  323                         cs->cs_ctl_chan = zs->zsc_cs[0];
  324                 else
  325                         cs->cs_ctl_chan = NULL;
  326 
  327                 /*
  328                  * Look for a child driver for this channel.
  329                  * The child attach will setup the hardware.
  330                  */
  331                 if (config_found_sm(self, (void *)&zs_args,
  332                                 zs_ioasic_print, zs_ioasic_submatch) == NULL) {
  333                         /* No sub-driver.  Just reset it. */
  334                         u_char reset = (channel == 0) ?
  335                                 ZSWR9_A_RESET : ZSWR9_B_RESET;
  336                         s = splhigh();
  337                         zs_write_reg(cs, 9, reset);
  338                         splx(s);
  339                 }
  340         }
  341 
  342         /*
  343          * Set up the ioasic interrupt handler.
  344          */
  345         ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY,
  346             zs_ioasic_hardintr, zs);
  347         zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL,
  348             zs_ioasic_softintr, zs);
  349         if (zs->zsc_sih == NULL)
  350                 panic("zs_ioasic_attach: unable to register softintr");
  351 
  352         /*
  353          * Set the master interrupt enable and interrupt vector.  The
  354          * Sun does this only on one channel.  The old Alpha SCC driver
  355          * did it on both.  We'll do it on both.
  356          */
  357         s = splhigh();
  358         /* interrupt vector */
  359         zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]);
  360         zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]);
  361 
  362         /* master interrupt control (enable) */
  363         zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]);
  364         zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]);
  365 #if defined(__alpha__) || defined(alpha)
  366         /* ioasic interrupt enable */
  367         *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |=
  368                     IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0;
  369         tc_mb();
  370 #endif
  371         splx(s);
  372 }
  373 
  374 int
  375 zs_ioasic_print(aux, name)
  376         void *aux;
  377         const char *name;
  378 {
  379         struct zsc_attach_args *args = aux;
  380 
  381         if (name != NULL)
  382                 aprint_normal("%s:", name);
  383 
  384         if (args->channel != -1)
  385                 aprint_normal(" channel %d", args->channel);
  386 
  387         return (UNCONF);
  388 }
  389 
  390 int
  391 zs_ioasic_submatch(parent, cf, aux)
  392         struct device *parent;
  393         struct cfdata *cf;
  394         void *aux;
  395 {
  396         struct zsc_softc *zs = (void *)parent;
  397         struct zsc_attach_args *pa = aux;
  398         char *defname = "";
  399 
  400         if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT &&
  401             cf->cf_loc[ZSCCF_CHANNEL] != pa->channel)
  402                 return (0);
  403         if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) {
  404                 if (pa->channel == 0) {
  405 #if defined(pmax)
  406                         if (systype == DS_MAXINE)
  407                                 return (0);
  408 #endif
  409                         if (zs->zsc_addroffset == 0x100000)
  410                                 defname = "vsms";
  411                         else
  412                                 defname = "lkkbd";
  413                 }
  414                 else if (zs->zsc_addroffset == 0x100000)
  415                         defname = "zstty";
  416 #if defined(pmax)
  417                 else if (systype == DS_MAXINE)
  418                         return (0);
  419 #endif
  420 #if defined(__alpha__) || defined(alpha)
  421                 else if (cputype == ST_DEC_3000_300)
  422                         return (0);
  423 #endif
  424                 else
  425                         defname = "zstty"; /* 3min/3max+, DEC3000/500 */
  426 
  427                 if (strcmp(cf->cf_name, defname))
  428                         return (0);
  429         }
  430         return (config_match(parent, cf, aux));
  431 }
  432 
  433 /*
  434  * Hardware interrupt handler.
  435  */
  436 int
  437 zs_ioasic_hardintr(arg)
  438         void *arg;
  439 {
  440         struct zsc_softc *zsc = arg;
  441 
  442         /*
  443          * Call the upper-level MI hardware interrupt handler.
  444          */
  445         zsc_intr_hard(zsc);
  446 
  447         /*
  448          * Check to see if we need to schedule any software-level
  449          * processing interrupts.
  450          */
  451         if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq)
  452                 softintr_schedule(zsc->zsc_sih);
  453 
  454         return (1);
  455 }
  456 
  457 /*
  458  * Software-level interrupt (character processing, lower priority).
  459  */
  460 void
  461 zs_ioasic_softintr(arg)
  462         void *arg;
  463 {
  464         struct zsc_softc *zsc = arg;
  465         int s;
  466 
  467         s = spltty();
  468         (void) zsc_intr_soft(zsc);
  469         splx(s);
  470 }
  471 
  472 /*
  473  * MD functions for setting the baud rate and control modes.
  474  */
  475 int
  476 zs_set_speed(cs, bps)
  477         struct zs_chanstate *cs;
  478         int bps;        /* bits per second */
  479 {
  480         int tconst, real_bps;
  481 
  482         if (bps == 0)
  483                 return (0);
  484 
  485 #ifdef DIAGNOSTIC
  486         if (cs->cs_brg_clk == 0)
  487                 panic("zs_set_speed");
  488 #endif
  489 
  490         tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
  491         if (tconst < 0)
  492                 return (EINVAL);
  493 
  494         /* Convert back to make sure we can do it. */
  495         real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
  496 
  497         /* XXX - Allow some tolerance here? */
  498         if (real_bps != bps)
  499                 return (EINVAL);
  500 
  501         cs->cs_preg[12] = tconst;
  502         cs->cs_preg[13] = tconst >> 8;
  503 
  504         /* Caller will stuff the pending registers. */
  505         return (0);
  506 }
  507 
  508 int
  509 zs_set_modes(cs, cflag)
  510         struct zs_chanstate *cs;
  511         int cflag;      /* bits per second */
  512 {
  513         u_long privflags = (u_long)cs->cs_private;
  514         int s;
  515 
  516         /*
  517          * Output hardware flow control on the chip is horrendous:
  518          * if carrier detect drops, the receiver is disabled, and if
  519          * CTS drops, the transmitter is stoped IN MID CHARACTER!
  520          * Therefore, NEVER set the HFC bit, and instead use the
  521          * status interrupt to detect CTS changes.
  522          */
  523         s = splzs();
  524         if ((cflag & (CLOCAL | MDMBUF)) != 0)
  525                 cs->cs_rr0_dcd = 0;
  526         else
  527                 cs->cs_rr0_dcd = ZSRR0_DCD;
  528         if ((cflag & CRTSCTS) != 0) {
  529                 cs->cs_wr5_dtr = ZSWR5_DTR;
  530                 cs->cs_wr5_rts = ZSWR5_RTS;
  531                 cs->cs_rr0_cts = ZSRR0_CTS;
  532         } else if ((cflag & CDTRCTS) != 0) {
  533                 cs->cs_wr5_dtr = 0;
  534                 cs->cs_wr5_rts = ZSWR5_DTR;
  535                 cs->cs_rr0_cts = ZSRR0_CTS;
  536         } else if ((cflag & MDMBUF) != 0) {
  537                 cs->cs_wr5_dtr = 0;
  538                 cs->cs_wr5_rts = ZSWR5_DTR;
  539                 cs->cs_rr0_cts = ZSRR0_DCD;
  540         } else {
  541                 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
  542                 cs->cs_wr5_rts = 0;
  543                 cs->cs_rr0_cts = 0;
  544         }
  545 
  546         if ((privflags & ZIP_FLAGS_DCDCTS) == 0) {
  547                 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD);
  548                 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD);
  549         }
  550         if ((privflags & ZIP_FLAGS_DTRRTS) == 0) {
  551                 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR);
  552                 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR);
  553         }
  554         splx(s);
  555 
  556         /* Caller will stuff the pending registers. */
  557         return (0);
  558 }
  559 
  560 /*
  561  * Functions to read and write individual registers in a channel.
  562  * The ZS chip requires a 1.6 uSec. recovery time between accesses,
  563  * and the Alpha TC hardware does NOT take care of this for you.
  564  * The delay is now handled inside the chip access functions.
  565  * These could be inlines, but with the delay, speed is moot.
  566  */
  567 #if defined(pmax)
  568 #undef  DELAY
  569 #define DELAY(x)
  570 #endif
  571 
  572 u_int
  573 zs_read_reg(cs, reg)
  574         struct zs_chanstate *cs;
  575         u_int reg;
  576 {
  577         struct zshan *zc = (void *)cs->cs_reg_csr;
  578         unsigned val;
  579 
  580         zc->zc_csr = reg << 8;
  581         tc_wmb();
  582         DELAY(5);
  583         val = (zc->zc_csr >> 8) & 0xff;
  584         /* tc_mb(); */
  585         DELAY(5);
  586         return (val);
  587 }
  588 
  589 void
  590 zs_write_reg(cs, reg, val)
  591         struct zs_chanstate *cs;
  592         u_int reg, val;
  593 {
  594         struct zshan *zc = (void *)cs->cs_reg_csr;
  595    
  596         zc->zc_csr = reg << 8;
  597         tc_wmb();
  598         DELAY(5);
  599         zc->zc_csr = val << 8;
  600         tc_wmb();
  601         DELAY(5);
  602 }
  603 
  604 u_int
  605 zs_read_csr(cs)
  606         struct zs_chanstate *cs;
  607 {
  608         struct zshan *zc = (void *)cs->cs_reg_csr;
  609         unsigned val;
  610 
  611         val = (zc->zc_csr >> 8) & 0xff;
  612         /* tc_mb(); */
  613         DELAY(5);
  614         return (val);
  615 }
  616 
  617 void
  618 zs_write_csr(cs, val)
  619         struct zs_chanstate *cs;
  620         u_int val;
  621 {
  622         struct zshan *zc = (void *)cs->cs_reg_csr;
  623 
  624         zc->zc_csr = val << 8;
  625         tc_wmb();
  626         DELAY(5);
  627 }
  628 
  629 u_int
  630 zs_read_data(cs)
  631         struct zs_chanstate *cs;
  632 {
  633         struct zshan *zc = (void *)cs->cs_reg_csr;
  634         unsigned val;
  635 
  636         val = (zc->zc_data) >> 8 & 0xff;
  637         /* tc_mb(); */
  638         DELAY(5);
  639         return (val);
  640 }
  641 
  642 void
  643 zs_write_data(cs, val)
  644         struct zs_chanstate *cs;
  645         u_int val;
  646 {
  647         struct zshan *zc = (void *)cs->cs_reg_csr;
  648 
  649         zc->zc_data = val << 8;
  650         tc_wmb();
  651         DELAY(5);
  652 }
  653 
  654 /****************************************************************
  655  * Console support functions
  656  ****************************************************************/
  657 
  658 /*
  659  * Handle user request to enter kernel debugger.
  660  */
  661 void
  662 zs_abort(cs)
  663         struct zs_chanstate *cs;
  664 {
  665         int rr0;
  666 
  667         /* Wait for end of break. */
  668         /* XXX - Limit the wait? */
  669         do {
  670                 rr0 = zs_read_csr(cs);
  671         } while (rr0 & ZSRR0_BREAK);
  672 
  673 #if defined(KGDB)
  674         zskgdb(cs);
  675 #elif defined(DDB)
  676         Debugger();
  677 #else
  678         printf("zs_abort: ignoring break on console\n");
  679 #endif
  680 }
  681 
  682 /*
  683  * Polled input char.
  684  */
  685 int
  686 zs_getc(cs)
  687         struct zs_chanstate *cs;
  688 {
  689         int s, c, rr0;
  690 
  691         s = splhigh();
  692         /* Wait for a character to arrive. */
  693         do {
  694                 rr0 = zs_read_csr(cs);
  695         } while ((rr0 & ZSRR0_RX_READY) == 0);
  696 
  697         c = zs_read_data(cs);
  698         splx(s);
  699 
  700         /*
  701          * This is used by the kd driver to read scan codes,
  702          * so don't translate '\r' ==> '\n' here...
  703          */
  704         return (c);
  705 }
  706 
  707 /*
  708  * Polled output char.
  709  */
  710 void
  711 zs_putc(cs, c)
  712         struct zs_chanstate *cs;
  713         int c;
  714 {
  715         register int s, rr0;
  716 
  717         s = splhigh();
  718         /* Wait for transmitter to become ready. */
  719         do {
  720                 rr0 = zs_read_csr(cs);
  721         } while ((rr0 & ZSRR0_TX_READY) == 0);
  722 
  723         zs_write_data(cs, c);
  724 
  725         /* Wait for the character to be transmitted. */
  726         do {
  727                 rr0 = zs_read_csr(cs);
  728         } while ((rr0 & ZSRR0_TX_READY) == 0);
  729         splx(s);
  730 }
  731 
  732 /*****************************************************************/
  733 
  734 /*
  735  * zs_ioasic_cninit --
  736  *      Initialize the serial channel for either a keyboard or
  737  *      a serial console.
  738  */
  739 void
  740 zs_ioasic_cninit(ioasic_addr, zs_offset, channel)
  741         tc_addr_t ioasic_addr;
  742         tc_offset_t zs_offset;
  743         int channel;
  744 {
  745         struct zs_chanstate *cs;
  746         tc_addr_t zs_addr;
  747         struct zshan *zc;
  748         u_long zflg;
  749 
  750         /*
  751          * Initialize the console finder helpers.
  752          */
  753         zs_ioasic_console_offset = zs_offset;
  754         zs_ioasic_console_channel = channel;
  755         zs_ioasic_console = 1;
  756 
  757         /*
  758          * Pointer to channel state.
  759          */
  760         cs = &zs_ioasic_conschanstate_store;
  761 
  762         /*
  763          * Compute the physical address of the chip, "map" it via
  764          * K0SEG, and then get the address of the actual channel.
  765          */
  766 #if defined(__alpha__) || defined(alpha)
  767         zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset);
  768 #endif
  769 #if defined(pmax)
  770         zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset);
  771 #endif
  772         zc = zs_ioasic_get_chan_addr(zs_addr, channel);
  773 
  774         /* Setup temporary chanstate. */
  775         cs->cs_reg_csr = (void *)&zc->zc_csr;
  776 
  777         cs->cs_channel = channel;
  778         cs->cs_ops = &zsops_null;
  779         cs->cs_brg_clk = PCLK / 16;
  780 
  781         /* Initialize the pending registers. */
  782         bcopy(zs_ioasic_init_reg, cs->cs_preg, 16);
  783         /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */
  784 
  785         /*
  786          * DCD and CTS interrupts are only meaningful on
  787          * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1.
  788          *
  789          * XXX This is sorta gross.
  790          */
  791         if (zs_offset == 0x00100000 && channel == 1)
  792                 zflg = ZIP_FLAGS_DCDCTS;
  793         else
  794                 zflg = 0;
  795         if (channel == 1)
  796                 zflg |= ZIP_FLAGS_DTRRTS;
  797         (u_long)cs->cs_private = zflg;
  798 
  799         /* Clear the master interrupt enable. */
  800         zs_write_reg(cs, 9, 0);
  801 
  802         /* Reset the whole SCC chip. */
  803         zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
  804 
  805         /* Copy "pending" to "current" and H/W. */
  806         zs_loadchannelregs(cs);
  807 }
  808 
  809 /*
  810  * zs_ioasic_cnattach --
  811  *      Initialize and attach a serial console.
  812  */
  813 void
  814 zs_ioasic_cnattach(ioasic_addr, zs_offset, channel)
  815         tc_addr_t ioasic_addr;
  816         tc_offset_t zs_offset;
  817         int channel;
  818 {
  819         struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;
  820         extern const struct cdevsw zstty_cdevsw;
  821 
  822         zs_ioasic_cninit(ioasic_addr, zs_offset, channel);
  823         cs->cs_defspeed = 9600;
  824         cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
  825 
  826         /* Point the console at the SCC. */
  827         cn_tab = &zs_ioasic_cons;
  828         cn_tab->cn_pri = CN_REMOTE;
  829         cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw),
  830                                  (zs_offset == 0x100000) ? 0 : 1);
  831 }
  832 
  833 /*
  834  * zs_ioasic_lk201_cnattach --
  835  *      Initialize and attach a keyboard.
  836  */
  837 int
  838 zs_ioasic_lk201_cnattach(ioasic_addr, zs_offset, channel)
  839         tc_addr_t ioasic_addr;
  840         tc_offset_t zs_offset;
  841         int channel;
  842 {
  843 #if (NZSKBD > 0)
  844         struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;
  845 
  846         zs_ioasic_cninit(ioasic_addr, zs_offset, channel);
  847         cs->cs_defspeed = 4800;
  848         cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
  849         return (zskbd_cnattach(cs));
  850 #else
  851         return (ENXIO);
  852 #endif
  853 }
  854 
  855 int
  856 zs_ioasic_isconsole(offset, channel)
  857         tc_offset_t offset;
  858         int channel;
  859 {
  860 
  861         if (zs_ioasic_console &&
  862             offset == zs_ioasic_console_offset &&
  863             channel == zs_ioasic_console_channel)
  864                 return (1);
  865 
  866         return (0);
  867 }
  868 
  869 /*
  870  * Polled console input putchar.
  871  */
  872 int
  873 zs_ioasic_cngetc(dev)
  874         dev_t dev;
  875 {
  876 
  877         return (zs_getc(&zs_ioasic_conschanstate_store));
  878 }
  879 
  880 /*
  881  * Polled console output putchar.
  882  */
  883 void
  884 zs_ioasic_cnputc(dev, c)
  885         dev_t dev;
  886         int c;
  887 {
  888 
  889         zs_putc(&zs_ioasic_conschanstate_store, c);
  890 }
  891 
  892 /*
  893  * Set polling/no polling on console.
  894  */
  895 void
  896 zs_ioasic_cnpollc(dev, onoff)
  897         dev_t dev;
  898         int onoff;
  899 {
  900 
  901         /* XXX ??? */
  902 }

Cache object: f00fb196fc52b85df78c1a5f7b473b95


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.