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sys/dev/tc/zs_ioasic.c
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1 /* $NetBSD: zs_ioasic.c,v 1.37 2008/04/28 20:23:58 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 35 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 36 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 37 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 38 * 39 * Runs two serial lines per chip using slave drivers. 40 * Plain tty/async lines use the zstty slave. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.37 2008/04/28 20:23:58 martin Exp $"); 45 46 #include "opt_ddb.h" 47 #include "opt_kgdb.h" 48 #include "zskbd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/file.h> 56 #include <sys/ioctl.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> 59 #include <sys/tty.h> 60 #include <sys/time.h> 61 #include <sys/syslog.h> 62 #include <sys/intr.h> 63 64 #include <machine/autoconf.h> 65 #include <machine/z8530var.h> 66 67 #include <dev/cons.h> 68 #include <dev/ic/z8530reg.h> 69 70 #include <dev/tc/tcvar.h> 71 #include <dev/tc/ioasicreg.h> 72 #include <dev/tc/ioasicvar.h> 73 74 #include <dev/tc/zs_ioasicvar.h> 75 76 #if defined(__alpha__) || defined(alpha) 77 #include <machine/rpb.h> 78 #endif 79 #if defined(pmax) 80 #include <pmax/pmax/pmaxtype.h> 81 #endif 82 83 /* 84 * Helpers for console support. 85 */ 86 static void zs_ioasic_cninit(tc_addr_t, tc_offset_t, int); 87 static int zs_ioasic_cngetc(dev_t); 88 static void zs_ioasic_cnputc(dev_t, int); 89 static void zs_ioasic_cnpollc(dev_t, int); 90 91 struct consdev zs_ioasic_cons = { 92 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 93 zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL, 94 }; 95 96 static tc_offset_t zs_ioasic_console_offset; 97 static int zs_ioasic_console_channel; 98 static int zs_ioasic_console; 99 static struct zs_chanstate zs_ioasic_conschanstate_store; 100 101 static int zs_ioasic_isconsole(tc_offset_t, int); 102 static void zs_putc(struct zs_chanstate *, int); 103 104 /* 105 * Some warts needed by z8530tty.c 106 */ 107 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 108 109 /* 110 * ZS chips are feeded a 7.372 MHz clock. 111 */ 112 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zshan { 116 #if defined(__alpha__) || defined(alpha) 117 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 118 u_int zc_pad0; 119 volatile u_int zc_data; /* data */ 120 u_int sc_pad1; 121 #endif 122 #if defined(pmax) 123 volatile uint16_t zc_csr; /* ctrl,status, and indirect access */ 124 unsigned : 16; 125 volatile uint16_t zc_data; /* data */ 126 unsigned : 16; 127 #endif 128 }; 129 130 struct zsdevice { 131 /* Yes, they are backwards. */ 132 struct zshan zs_chan_b; 133 struct zshan zs_chan_a; 134 }; 135 136 static const u_char zs_ioasic_init_reg[16] = { 137 0, /* 0: CMD (reset, etc.) */ 138 0, /* 1: No interrupts yet. */ 139 0xf0, /* 2: IVECT */ 140 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 141 ZSWR4_CLK_X16 | ZSWR4_ONESB, 142 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 143 0, /* 6: TXSYNC/SYNCLO */ 144 0, /* 7: RXSYNC/SYNCHI */ 145 0, /* 8: alias for data port */ 146 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 147 0, /*10: Misc. TX/RX control bits */ 148 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 149 22, /*12: BAUDLO (default=9600) */ 150 0, /*13: BAUDHI (default=9600) */ 151 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 152 ZSWR15_BREAK_IE, 153 }; 154 155 static struct zshan * 156 zs_ioasic_get_chan_addr(tc_addr_t zsaddr, int channel) 157 { 158 struct zsdevice *addr; 159 struct zshan *zc; 160 161 #if defined(__alpha__) || defined(alpha) 162 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 163 #endif 164 #if defined(pmax) 165 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 166 #endif 167 168 if (channel == 0) 169 zc = &addr->zs_chan_a; 170 else 171 zc = &addr->zs_chan_b; 172 173 return (zc); 174 } 175 176 177 /**************************************************************** 178 * Autoconfig 179 ****************************************************************/ 180 181 /* Definition of the driver for autoconfig. */ 182 static int zs_ioasic_match(device_t, cfdata_t, void *); 183 static void zs_ioasic_attach(device_t, device_t, void *); 184 static int zs_ioasic_print(void *, const char *name); 185 static int zs_ioasic_submatch(device_t, struct cfdata *, 186 const int *, void *); 187 188 CFATTACH_DECL_NEW(zsc_ioasic, sizeof(struct zsc_softc), 189 zs_ioasic_match, zs_ioasic_attach, NULL, NULL); 190 191 /* Interrupt handlers. */ 192 static int zs_ioasic_hardintr(void *); 193 static void zs_ioasic_softintr(void *); 194 195 /* 196 * Is the zs chip present? 197 */ 198 static int 199 zs_ioasic_match(device_t parent, cfdata_t cf, void *aux) 200 { 201 struct ioasicdev_attach_args *d = aux; 202 tc_addr_t zs_addr; 203 204 /* 205 * Make sure that we're looking for the right kind of device. 206 */ 207 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 208 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 209 return (0); 210 211 /* 212 * Find out the device address, and check it for validity. 213 */ 214 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 215 if (tc_badaddr(zs_addr)) 216 return (0); 217 218 return (1); 219 } 220 221 /* 222 * Attach a found zs. 223 */ 224 static void 225 zs_ioasic_attach(device_t parent, device_t self, void *aux) 226 { 227 struct zsc_softc *zs = device_private(self); 228 struct zsc_attach_args zs_args; 229 struct zs_chanstate *cs; 230 struct ioasicdev_attach_args *d = aux; 231 struct zshan *zc; 232 int s, channel; 233 u_long zflg; 234 int locs[ZSCCF_NLOCS]; 235 236 zs->zsc_dev = self; 237 aprint_normal("\n"); 238 239 /* 240 * Initialize software state for each channel. 241 */ 242 for (channel = 0; channel < 2; channel++) { 243 zs_args.channel = channel; 244 zs_args.hwflags = 0; 245 246 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 247 cs = &zs_ioasic_conschanstate_store; 248 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 249 } else { 250 cs = malloc(sizeof(struct zs_chanstate), 251 M_DEVBUF, M_NOWAIT|M_ZERO); 252 zs_lock_init(cs); 253 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 254 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 255 256 memcpy(cs->cs_creg, zs_ioasic_init_reg, 16); 257 memcpy(cs->cs_preg, zs_ioasic_init_reg, 16); 258 259 cs->cs_defcflag = zs_def_cflag; 260 cs->cs_defspeed = 9600; /* XXX */ 261 (void)zs_set_modes(cs, cs->cs_defcflag); 262 } 263 264 zs->zsc_cs[channel] = cs; 265 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 266 cs->cs_channel = channel; 267 cs->cs_ops = &zsops_null; 268 cs->cs_brg_clk = PCLK / 16; 269 270 /* 271 * DCD and CTS interrupts are only meaningful on 272 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 273 * 274 * XXX This is sorta gross. 275 */ 276 if (d->iada_offset == 0x00100000 && channel == 1) { 277 cs->cs_creg[15] |= ZSWR15_DCD_IE; 278 cs->cs_preg[15] |= ZSWR15_DCD_IE; 279 zflg = ZIP_FLAGS_DCDCTS; 280 } else 281 zflg = 0; 282 if (channel == 1) 283 zflg |= ZIP_FLAGS_DTRRTS; 284 cs->cs_private = (void *)zflg; 285 286 /* 287 * Clear the master interrupt enable. 288 * The INTENA is common to both channels, 289 * so just do it on the A channel. 290 */ 291 if (channel == 0) { 292 zs_write_reg(cs, 9, 0); 293 } 294 295 /* 296 * Set up the flow/modem control channel pointer to 297 * deal with the weird wiring on the TC Alpha and 298 * DECstation. 299 */ 300 if (channel == 1) 301 cs->cs_ctl_chan = zs->zsc_cs[0]; 302 else 303 cs->cs_ctl_chan = NULL; 304 305 locs[ZSCCF_CHANNEL] = channel; 306 307 /* 308 * Look for a child driver for this channel. 309 * The child attach will setup the hardware. 310 */ 311 if (config_found_sm_loc(self, "zsc", locs, (void *)&zs_args, 312 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 313 /* No sub-driver. Just reset it. */ 314 uint8_t reset = (channel == 0) ? 315 ZSWR9_A_RESET : ZSWR9_B_RESET; 316 s = splhigh(); 317 zs_write_reg(cs, 9, reset); 318 splx(s); 319 } 320 } 321 322 /* 323 * Set up the ioasic interrupt handler. 324 */ 325 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 326 zs_ioasic_hardintr, zs); 327 zs->zsc_sih = softint_establish(SOFTINT_SERIAL, 328 zs_ioasic_softintr, zs); 329 if (zs->zsc_sih == NULL) 330 panic("%s: unable to register softintr", __func__); 331 332 /* 333 * Set the master interrupt enable and interrupt vector. The 334 * Sun does this only on one channel. The old Alpha SCC driver 335 * did it on both. We'll do it on both. 336 */ 337 s = splhigh(); 338 /* interrupt vector */ 339 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 340 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 341 342 /* master interrupt control (enable) */ 343 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 344 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 345 #if defined(__alpha__) || defined(alpha) 346 /* ioasic interrupt enable */ 347 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 348 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 349 tc_mb(); 350 #endif 351 splx(s); 352 } 353 354 static int 355 zs_ioasic_print(void *aux, const char *name) 356 { 357 struct zsc_attach_args *args = aux; 358 359 if (name != NULL) 360 aprint_normal("%s:", name); 361 362 if (args->channel != -1) 363 aprint_normal(" channel %d", args->channel); 364 365 return (UNCONF); 366 } 367 368 static int 369 zs_ioasic_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux) 370 { 371 struct zsc_softc *zs = device_private(parent); 372 struct zsc_attach_args *pa = aux; 373 const char *defname = ""; 374 375 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 376 cf->cf_loc[ZSCCF_CHANNEL] != locs[ZSCCF_CHANNEL]) 377 return (0); 378 379 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 380 if (pa->channel == 0) { 381 #if defined(pmax) 382 if (systype == DS_MAXINE) 383 return (0); 384 #endif 385 if (zs->zsc_addroffset == 0x100000) 386 defname = "vsms"; 387 else 388 defname = "lkkbd"; 389 } 390 else if (zs->zsc_addroffset == 0x100000) 391 defname = "zstty"; 392 #if defined(pmax) 393 else if (systype == DS_MAXINE) 394 return (0); 395 #endif 396 #if defined(__alpha__) || defined(alpha) 397 else if (cputype == ST_DEC_3000_300) 398 return (0); 399 #endif 400 else 401 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 402 403 if (strcmp(cf->cf_name, defname)) 404 return (0); 405 } 406 return (config_match(parent, cf, aux)); 407 } 408 409 /* 410 * Hardware interrupt handler. 411 */ 412 static int 413 zs_ioasic_hardintr(void *arg) 414 { 415 struct zsc_softc *zsc = arg; 416 417 /* 418 * Call the upper-level MI hardware interrupt handler. 419 */ 420 zsc_intr_hard(zsc); 421 422 /* 423 * Check to see if we need to schedule any software-level 424 * processing interrupts. 425 */ 426 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 427 softint_schedule(zsc->zsc_sih); 428 429 return (1); 430 } 431 432 /* 433 * Software-level interrupt (character processing, lower priority). 434 */ 435 static void 436 zs_ioasic_softintr(void *arg) 437 { 438 struct zsc_softc *zsc = arg; 439 int s; 440 441 s = spltty(); 442 (void)zsc_intr_soft(zsc); 443 splx(s); 444 } 445 446 /* 447 * MD functions for setting the baud rate and control modes. 448 */ 449 int 450 zs_set_speed(struct zs_chanstate *cs, int bps /*bits per second*/) 451 { 452 int tconst, real_bps; 453 454 if (bps == 0) 455 return (0); 456 457 #ifdef DIAGNOSTIC 458 if (cs->cs_brg_clk == 0) 459 panic("zs_set_speed"); 460 #endif 461 462 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 463 if (tconst < 0) 464 return (EINVAL); 465 466 /* Convert back to make sure we can do it. */ 467 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 468 469 /* XXX - Allow some tolerance here? */ 470 if (real_bps != bps) 471 return (EINVAL); 472 473 cs->cs_preg[12] = tconst; 474 cs->cs_preg[13] = tconst >> 8; 475 476 /* Caller will stuff the pending registers. */ 477 return (0); 478 } 479 480 int 481 zs_set_modes(struct zs_chanstate *cs, int cflag) 482 { 483 u_long privflags = (u_long)cs->cs_private; 484 int s; 485 486 /* 487 * Output hardware flow control on the chip is horrendous: 488 * if carrier detect drops, the receiver is disabled, and if 489 * CTS drops, the transmitter is stoped IN MID CHARACTER! 490 * Therefore, NEVER set the HFC bit, and instead use the 491 * status interrupt to detect CTS changes. 492 */ 493 s = splzs(); 494 if ((cflag & (CLOCAL | MDMBUF)) != 0) 495 cs->cs_rr0_dcd = 0; 496 else 497 cs->cs_rr0_dcd = ZSRR0_DCD; 498 if ((cflag & CRTSCTS) != 0) { 499 cs->cs_wr5_dtr = ZSWR5_DTR; 500 cs->cs_wr5_rts = ZSWR5_RTS; 501 cs->cs_rr0_cts = ZSRR0_CTS; 502 } else if ((cflag & CDTRCTS) != 0) { 503 cs->cs_wr5_dtr = 0; 504 cs->cs_wr5_rts = ZSWR5_DTR; 505 cs->cs_rr0_cts = ZSRR0_CTS; 506 } else if ((cflag & MDMBUF) != 0) { 507 cs->cs_wr5_dtr = 0; 508 cs->cs_wr5_rts = ZSWR5_DTR; 509 cs->cs_rr0_cts = ZSRR0_DCD; 510 } else { 511 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 512 cs->cs_wr5_rts = 0; 513 cs->cs_rr0_cts = 0; 514 } 515 516 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 517 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 518 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 519 } 520 if ((privflags & ZIP_FLAGS_DTRRTS) == 0) { 521 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR); 522 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR); 523 } 524 splx(s); 525 526 /* Caller will stuff the pending registers. */ 527 return (0); 528 } 529 530 /* 531 * Functions to read and write individual registers in a channel. 532 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 533 * and the Alpha TC hardware does NOT take care of this for you. 534 * The delay is now handled inside the chip access functions. 535 * These could be inlines, but with the delay, speed is moot. 536 */ 537 #if defined(pmax) 538 #undef DELAY 539 #define DELAY(x) 540 #endif 541 542 u_int 543 zs_read_reg(struct zs_chanstate *cs, u_int reg) 544 { 545 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 546 unsigned val; 547 548 zc->zc_csr = reg << 8; 549 tc_wmb(); 550 DELAY(5); 551 val = (zc->zc_csr >> 8) & 0xff; 552 /* tc_mb(); */ 553 DELAY(5); 554 return (val); 555 } 556 557 void 558 zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val) 559 { 560 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 561 562 zc->zc_csr = reg << 8; 563 tc_wmb(); 564 DELAY(5); 565 zc->zc_csr = val << 8; 566 tc_wmb(); 567 DELAY(5); 568 } 569 570 u_int 571 zs_read_csr(struct zs_chanstate *cs) 572 { 573 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 574 unsigned val; 575 576 val = (zc->zc_csr >> 8) & 0xff; 577 /* tc_mb(); */ 578 DELAY(5); 579 return (val); 580 } 581 582 void 583 zs_write_csr(struct zs_chanstate *cs, u_int val) 584 { 585 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 586 587 zc->zc_csr = val << 8; 588 tc_wmb(); 589 DELAY(5); 590 } 591 592 u_int 593 zs_read_data(struct zs_chanstate *cs) 594 { 595 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 596 unsigned val; 597 598 val = (zc->zc_data) >> 8 & 0xff; 599 /* tc_mb(); */ 600 DELAY(5); 601 return (val); 602 } 603 604 void 605 zs_write_data(struct zs_chanstate *cs, u_int val) 606 { 607 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 608 609 zc->zc_data = val << 8; 610 tc_wmb(); 611 DELAY(5); 612 } 613 614 /**************************************************************** 615 * Console support functions 616 ****************************************************************/ 617 618 /* 619 * Handle user request to enter kernel debugger. 620 */ 621 void 622 zs_abort(struct zs_chanstate *cs) 623 { 624 u_int rr0; 625 626 /* Wait for end of break. */ 627 /* XXX - Limit the wait? */ 628 do { 629 rr0 = zs_read_csr(cs); 630 } while (rr0 & ZSRR0_BREAK); 631 632 #if defined(KGDB) 633 zskgdb(cs); 634 #elif defined(DDB) 635 Debugger(); 636 #else 637 printf("zs_abort: ignoring break on console\n"); 638 #endif 639 } 640 641 /* 642 * Polled input char. 643 */ 644 int 645 zs_getc(struct zs_chanstate *cs) 646 { 647 int s, c; 648 u_int rr0; 649 650 s = splhigh(); 651 /* Wait for a character to arrive. */ 652 do { 653 rr0 = zs_read_csr(cs); 654 } while ((rr0 & ZSRR0_RX_READY) == 0); 655 656 c = zs_read_data(cs); 657 splx(s); 658 659 /* 660 * This is used by the kd driver to read scan codes, 661 * so don't translate '\r' ==> '\n' here... 662 */ 663 return (c); 664 } 665 666 /* 667 * Polled output char. 668 */ 669 static void 670 zs_putc(struct zs_chanstate *cs, int c) 671 { 672 int s; 673 u_int rr0; 674 675 s = splhigh(); 676 /* Wait for transmitter to become ready. */ 677 do { 678 rr0 = zs_read_csr(cs); 679 } while ((rr0 & ZSRR0_TX_READY) == 0); 680 681 zs_write_data(cs, c); 682 683 /* Wait for the character to be transmitted. */ 684 do { 685 rr0 = zs_read_csr(cs); 686 } while ((rr0 & ZSRR0_TX_READY) == 0); 687 splx(s); 688 } 689 690 /*****************************************************************/ 691 692 /* 693 * zs_ioasic_cninit -- 694 * Initialize the serial channel for either a keyboard or 695 * a serial console. 696 */ 697 static void 698 zs_ioasic_cninit(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 699 { 700 struct zs_chanstate *cs; 701 tc_addr_t zs_addr; 702 struct zshan *zc; 703 u_long zflg; 704 705 /* 706 * Initialize the console finder helpers. 707 */ 708 zs_ioasic_console_offset = zs_offset; 709 zs_ioasic_console_channel = channel; 710 zs_ioasic_console = 1; 711 712 /* 713 * Pointer to channel state. 714 */ 715 cs = &zs_ioasic_conschanstate_store; 716 717 /* 718 * Compute the physical address of the chip, "map" it via 719 * K0SEG, and then get the address of the actual channel. 720 */ 721 #if defined(__alpha__) || defined(alpha) 722 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 723 #endif 724 #if defined(pmax) 725 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 726 #endif 727 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 728 729 /* Setup temporary chanstate. */ 730 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 731 732 cs->cs_channel = channel; 733 cs->cs_ops = &zsops_null; 734 cs->cs_brg_clk = PCLK / 16; 735 736 /* Initialize the pending registers. */ 737 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 738 /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */ 739 740 /* 741 * DCD and CTS interrupts are only meaningful on 742 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 743 * 744 * XXX This is sorta gross. 745 */ 746 if (zs_offset == 0x00100000 && channel == 1) 747 zflg = ZIP_FLAGS_DCDCTS; 748 else 749 zflg = 0; 750 if (channel == 1) 751 zflg |= ZIP_FLAGS_DTRRTS; 752 cs->cs_private = (void *)zflg; 753 754 /* Clear the master interrupt enable. */ 755 zs_write_reg(cs, 9, 0); 756 757 /* Reset the whole SCC chip. */ 758 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 759 760 /* Copy "pending" to "current" and H/W. */ 761 zs_loadchannelregs(cs); 762 } 763 764 /* 765 * zs_ioasic_cnattach -- 766 * Initialize and attach a serial console. 767 */ 768 void 769 zs_ioasic_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 770 { 771 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 772 extern const struct cdevsw zstty_cdevsw; 773 774 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 775 zs_lock_init(cs); 776 cs->cs_defspeed = 9600; 777 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 778 779 /* Point the console at the SCC. */ 780 cn_tab = &zs_ioasic_cons; 781 cn_tab->cn_pri = CN_REMOTE; 782 cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 783 (zs_offset == 0x100000) ? 0 : 1); 784 } 785 786 /* 787 * zs_ioasic_lk201_cnattach -- 788 * Initialize and attach a keyboard. 789 */ 790 int 791 zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, 792 int channel) 793 { 794 #if (NZSKBD > 0) 795 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 796 797 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 798 zs_lock_init(cs); 799 cs->cs_defspeed = 4800; 800 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 801 return (zskbd_cnattach(cs)); 802 #else 803 return (ENXIO); 804 #endif 805 } 806 807 static int 808 zs_ioasic_isconsole(tc_offset_t offset, int channel) 809 { 810 811 if (zs_ioasic_console && 812 offset == zs_ioasic_console_offset && 813 channel == zs_ioasic_console_channel) 814 return (1); 815 816 return (0); 817 } 818 819 /* 820 * Polled console input putchar. 821 */ 822 static int 823 zs_ioasic_cngetc(dev_t dev) 824 { 825 826 return (zs_getc(&zs_ioasic_conschanstate_store)); 827 } 828 829 /* 830 * Polled console output putchar. 831 */ 832 static void 833 zs_ioasic_cnputc(dev_t dev, int c) 834 { 835 836 zs_putc(&zs_ioasic_conschanstate_store, c); 837 } 838 839 /* 840 * Set polling/no polling on console. 841 */ 842 static void 843 zs_ioasic_cnpollc(dev_t dev, int onoff) 844 { 845 846 /* XXX ??? */ 847 }
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