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sys/dev/ti/if_ti.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD: releng/8.3/sys/dev/ti/if_ti.c 229442 2012-01-03 23:45:44Z yongari $"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/module.h> 91 #include <sys/socket.h> 92 #include <sys/queue.h> 93 #include <sys/conf.h> 94 #include <sys/sf_buf.h> 95 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 104 #include <net/bpf.h> 105 106 #include <netinet/in_systm.h> 107 #include <netinet/in.h> 108 #include <netinet/ip.h> 109 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #ifdef TI_SF_BUF_JUMBO 116 #include <vm/vm.h> 117 #include <vm/vm_page.h> 118 #endif 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 123 #include <sys/tiio.h> 124 #include <dev/ti/if_tireg.h> 125 #include <dev/ti/ti_fw.h> 126 #include <dev/ti/ti_fw2.h> 127 128 #include <sys/sysctl.h> 129 130 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 131 /* 132 * We can only turn on header splitting if we're using extended receive 133 * BDs. 134 */ 135 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 136 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 137 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 138 139 typedef enum { 140 TI_SWAP_HTON, 141 TI_SWAP_NTOH 142 } ti_swap_type; 143 144 /* 145 * Various supported device vendors/types and their names. 146 */ 147 148 static const struct ti_type const ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164 }; 165 166 167 static d_open_t ti_open; 168 static d_close_t ti_close; 169 static d_ioctl_t ti_ioctl2; 170 171 static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178 }; 179 180 static int ti_probe(device_t); 181 static int ti_attach(device_t); 182 static int ti_detach(device_t); 183 static void ti_txeof(struct ti_softc *); 184 static void ti_rxeof(struct ti_softc *); 185 186 static void ti_stats_update(struct ti_softc *); 187 static int ti_encap(struct ti_softc *, struct mbuf **); 188 189 static void ti_intr(void *); 190 static void ti_start(struct ifnet *); 191 static void ti_start_locked(struct ifnet *); 192 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193 static void ti_init(void *); 194 static void ti_init_locked(void *); 195 static void ti_init2(struct ti_softc *); 196 static void ti_stop(struct ti_softc *); 197 static void ti_watchdog(void *); 198 static int ti_shutdown(device_t); 199 static int ti_ifmedia_upd(struct ifnet *); 200 static int ti_ifmedia_upd_locked(struct ti_softc *); 201 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 202 203 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 204 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 205 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 206 207 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 208 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 209 static void ti_setmulti(struct ti_softc *); 210 211 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 212 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 213 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 214 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 215 int); 216 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 217 int, int, int); 218 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219 static void ti_loadfw(struct ti_softc *); 220 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222 static void ti_handle_events(struct ti_softc *); 223 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 224 static int ti_dma_alloc(struct ti_softc *); 225 static void ti_dma_free(struct ti_softc *); 226 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 227 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 228 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 229 bus_dmamap_t *); 230 static int ti_newbuf_std(struct ti_softc *, int); 231 static int ti_newbuf_mini(struct ti_softc *, int); 232 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 233 static int ti_init_rx_ring_std(struct ti_softc *); 234 static void ti_free_rx_ring_std(struct ti_softc *); 235 static int ti_init_rx_ring_jumbo(struct ti_softc *); 236 static void ti_free_rx_ring_jumbo(struct ti_softc *); 237 static int ti_init_rx_ring_mini(struct ti_softc *); 238 static void ti_free_rx_ring_mini(struct ti_softc *); 239 static void ti_free_tx_ring(struct ti_softc *); 240 static int ti_init_tx_ring(struct ti_softc *); 241 static void ti_discard_std(struct ti_softc *, int); 242 #ifndef TI_SF_BUF_JUMBO 243 static void ti_discard_jumbo(struct ti_softc *, int); 244 #endif 245 static void ti_discard_mini(struct ti_softc *, int); 246 247 static int ti_64bitslot_war(struct ti_softc *); 248 static int ti_chipinit(struct ti_softc *); 249 static int ti_gibinit(struct ti_softc *); 250 251 #ifdef TI_JUMBO_HDRSPLIT 252 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 253 int idx); 254 #endif /* TI_JUMBO_HDRSPLIT */ 255 256 static void ti_sysctl_node(struct ti_softc *); 257 258 static device_method_t ti_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, ti_probe), 261 DEVMETHOD(device_attach, ti_attach), 262 DEVMETHOD(device_detach, ti_detach), 263 DEVMETHOD(device_shutdown, ti_shutdown), 264 { 0, 0 } 265 }; 266 267 static driver_t ti_driver = { 268 "ti", 269 ti_methods, 270 sizeof(struct ti_softc) 271 }; 272 273 static devclass_t ti_devclass; 274 275 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 276 MODULE_DEPEND(ti, pci, 1, 1, 1); 277 MODULE_DEPEND(ti, ether, 1, 1, 1); 278 279 /* 280 * Send an instruction or address to the EEPROM, check for ACK. 281 */ 282 static uint32_t 283 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 284 { 285 int i, ack = 0; 286 287 /* 288 * Make sure we're in TX mode. 289 */ 290 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 291 292 /* 293 * Feed in each bit and stobe the clock. 294 */ 295 for (i = 0x80; i; i >>= 1) { 296 if (byte & i) { 297 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 298 } else { 299 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 300 } 301 DELAY(1); 302 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 303 DELAY(1); 304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 305 } 306 307 /* 308 * Turn off TX mode. 309 */ 310 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 311 312 /* 313 * Check for ack. 314 */ 315 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 316 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 318 319 return (ack); 320 } 321 322 /* 323 * Read a byte of data stored in the EEPROM at address 'addr.' 324 * We have to send two address bytes since the EEPROM can hold 325 * more than 256 bytes of data. 326 */ 327 static uint8_t 328 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 329 { 330 int i; 331 uint8_t byte = 0; 332 333 EEPROM_START; 334 335 /* 336 * Send write control code to EEPROM. 337 */ 338 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 339 device_printf(sc->ti_dev, 340 "failed to send write command, status: %x\n", 341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 342 return (1); 343 } 344 345 /* 346 * Send first byte of address of byte we want to read. 347 */ 348 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 349 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 /* 354 * Send second byte address of byte we want to read. 355 */ 356 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 357 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 358 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 359 return (1); 360 } 361 362 EEPROM_STOP; 363 EEPROM_START; 364 /* 365 * Send read control code to EEPROM. 366 */ 367 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 368 device_printf(sc->ti_dev, 369 "failed to send read command, status: %x\n", 370 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 371 return (1); 372 } 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 378 for (i = 0x80; i; i >>= 1) { 379 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 380 DELAY(1); 381 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 382 byte |= i; 383 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 384 DELAY(1); 385 } 386 387 EEPROM_STOP; 388 389 /* 390 * No ACK generated for read, so just return byte. 391 */ 392 393 *dest = byte; 394 395 return (0); 396 } 397 398 /* 399 * Read a sequence of bytes from the EEPROM. 400 */ 401 static int 402 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 403 { 404 int err = 0, i; 405 uint8_t byte = 0; 406 407 for (i = 0; i < cnt; i++) { 408 err = ti_eeprom_getbyte(sc, off + i, &byte); 409 if (err) 410 break; 411 *(dest + i) = byte; 412 } 413 414 return (err ? 1 : 0); 415 } 416 417 /* 418 * NIC memory read function. 419 * Can be used to copy data from NIC local memory. 420 */ 421 static void 422 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 423 { 424 int segptr, segsize, cnt; 425 char *ptr; 426 427 segptr = addr; 428 cnt = len; 429 ptr = buf; 430 431 while (cnt) { 432 if (cnt < TI_WINLEN) 433 segsize = cnt; 434 else 435 segsize = TI_WINLEN - (segptr % TI_WINLEN); 436 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 437 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 438 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 439 segsize / 4); 440 ptr += segsize; 441 segptr += segsize; 442 cnt -= segsize; 443 } 444 } 445 446 447 /* 448 * NIC memory write function. 449 * Can be used to copy data into NIC local memory. 450 */ 451 static void 452 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 453 { 454 int segptr, segsize, cnt; 455 char *ptr; 456 457 segptr = addr; 458 cnt = len; 459 ptr = buf; 460 461 while (cnt) { 462 if (cnt < TI_WINLEN) 463 segsize = cnt; 464 else 465 segsize = TI_WINLEN - (segptr % TI_WINLEN); 466 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 467 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 468 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 469 segsize / 4); 470 ptr += segsize; 471 segptr += segsize; 472 cnt -= segsize; 473 } 474 } 475 476 /* 477 * NIC memory read function. 478 * Can be used to clear a section of NIC local memory. 479 */ 480 static void 481 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 482 { 483 int segptr, segsize, cnt; 484 485 segptr = addr; 486 cnt = len; 487 488 while (cnt) { 489 if (cnt < TI_WINLEN) 490 segsize = cnt; 491 else 492 segsize = TI_WINLEN - (segptr % TI_WINLEN); 493 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 494 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 495 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 496 segptr += segsize; 497 cnt -= segsize; 498 } 499 } 500 501 static int 502 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 503 caddr_t buf, int useraddr, int readdata) 504 { 505 int segptr, segsize, cnt; 506 caddr_t ptr; 507 uint32_t origwin; 508 int resid, segresid; 509 int first_pass; 510 511 TI_LOCK_ASSERT(sc); 512 513 /* 514 * At the moment, we don't handle non-aligned cases, we just bail. 515 * If this proves to be a problem, it will be fixed. 516 */ 517 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 518 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 519 "word-aligned\n", __func__, tigon_addr); 520 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 521 "yet supported\n", __func__); 522 return (EINVAL); 523 } 524 525 segptr = tigon_addr & ~0x3; 526 segresid = tigon_addr - segptr; 527 528 /* 529 * This is the non-aligned amount left over that we'll need to 530 * copy. 531 */ 532 resid = len & 0x3; 533 534 /* Add in the left over amount at the front of the buffer */ 535 resid += segresid; 536 537 cnt = len & ~0x3; 538 /* 539 * If resid + segresid is >= 4, add multiples of 4 to the count and 540 * decrease the residual by that much. 541 */ 542 cnt += resid & ~0x3; 543 resid -= resid & ~0x3; 544 545 ptr = buf; 546 547 first_pass = 1; 548 549 /* 550 * Save the old window base value. 551 */ 552 origwin = CSR_READ_4(sc, TI_WINBASE); 553 554 while (cnt) { 555 bus_size_t ti_offset; 556 557 if (cnt < TI_WINLEN) 558 segsize = cnt; 559 else 560 segsize = TI_WINLEN - (segptr % TI_WINLEN); 561 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 562 563 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 564 565 if (readdata) { 566 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 567 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 568 if (useraddr) { 569 /* 570 * Yeah, this is a little on the kludgy 571 * side, but at least this code is only 572 * used for debugging. 573 */ 574 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 575 segsize, TI_SWAP_NTOH); 576 577 TI_UNLOCK(sc); 578 if (first_pass) { 579 copyout(&sc->ti_membuf2[segresid], ptr, 580 segsize - segresid); 581 first_pass = 0; 582 } else 583 copyout(sc->ti_membuf2, ptr, segsize); 584 TI_LOCK(sc); 585 } else { 586 if (first_pass) { 587 588 ti_bcopy_swap(sc->ti_membuf, 589 sc->ti_membuf2, segsize, 590 TI_SWAP_NTOH); 591 TI_UNLOCK(sc); 592 bcopy(&sc->ti_membuf2[segresid], ptr, 593 segsize - segresid); 594 TI_LOCK(sc); 595 first_pass = 0; 596 } else 597 ti_bcopy_swap(sc->ti_membuf, ptr, 598 segsize, TI_SWAP_NTOH); 599 } 600 601 } else { 602 if (useraddr) { 603 TI_UNLOCK(sc); 604 copyin(ptr, sc->ti_membuf2, segsize); 605 TI_LOCK(sc); 606 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 607 segsize, TI_SWAP_HTON); 608 } else 609 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 610 TI_SWAP_HTON); 611 612 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 613 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 614 } 615 segptr += segsize; 616 ptr += segsize; 617 cnt -= segsize; 618 } 619 620 /* 621 * Handle leftover, non-word-aligned bytes. 622 */ 623 if (resid != 0) { 624 uint32_t tmpval, tmpval2; 625 bus_size_t ti_offset; 626 627 /* 628 * Set the segment pointer. 629 */ 630 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 631 632 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 633 634 /* 635 * First, grab whatever is in our source/destination. 636 * We'll obviously need this for reads, but also for 637 * writes, since we'll be doing read/modify/write. 638 */ 639 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 640 ti_offset, &tmpval, 1); 641 642 /* 643 * Next, translate this from little-endian to big-endian 644 * (at least on i386 boxes). 645 */ 646 tmpval2 = ntohl(tmpval); 647 648 if (readdata) { 649 /* 650 * If we're reading, just copy the leftover number 651 * of bytes from the host byte order buffer to 652 * the user's buffer. 653 */ 654 if (useraddr) { 655 TI_UNLOCK(sc); 656 copyout(&tmpval2, ptr, resid); 657 TI_LOCK(sc); 658 } else 659 bcopy(&tmpval2, ptr, resid); 660 } else { 661 /* 662 * If we're writing, first copy the bytes to be 663 * written into the network byte order buffer, 664 * leaving the rest of the buffer with whatever was 665 * originally in there. Then, swap the bytes 666 * around into host order and write them out. 667 * 668 * XXX KDM the read side of this has been verified 669 * to work, but the write side of it has not been 670 * verified. So user beware. 671 */ 672 if (useraddr) { 673 TI_UNLOCK(sc); 674 copyin(ptr, &tmpval2, resid); 675 TI_LOCK(sc); 676 } else 677 bcopy(ptr, &tmpval2, resid); 678 679 tmpval = htonl(tmpval2); 680 681 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 682 ti_offset, &tmpval, 1); 683 } 684 } 685 686 CSR_WRITE_4(sc, TI_WINBASE, origwin); 687 688 return (0); 689 } 690 691 static int 692 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 693 caddr_t buf, int useraddr, int readdata, int cpu) 694 { 695 uint32_t segptr; 696 int cnt; 697 uint32_t tmpval, tmpval2; 698 caddr_t ptr; 699 700 TI_LOCK_ASSERT(sc); 701 702 /* 703 * At the moment, we don't handle non-aligned cases, we just bail. 704 * If this proves to be a problem, it will be fixed. 705 */ 706 if (tigon_addr & 0x3) { 707 device_printf(sc->ti_dev, "%s: tigon address %#x " 708 "isn't word-aligned\n", __func__, tigon_addr); 709 return (EINVAL); 710 } 711 712 if (len & 0x3) { 713 device_printf(sc->ti_dev, "%s: transfer length %d " 714 "isn't word-aligned\n", __func__, len); 715 return (EINVAL); 716 } 717 718 segptr = tigon_addr; 719 cnt = len; 720 ptr = buf; 721 722 while (cnt) { 723 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 724 725 if (readdata) { 726 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 727 728 tmpval = ntohl(tmpval2); 729 730 /* 731 * Note: I've used this debugging interface 732 * extensively with Alteon's 12.3.15 firmware, 733 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 734 * 735 * When you compile the firmware without 736 * optimization, which is necessary sometimes in 737 * order to properly step through it, you sometimes 738 * read out a bogus value of 0xc0017c instead of 739 * whatever was supposed to be in that scratchpad 740 * location. That value is on the stack somewhere, 741 * but I've never been able to figure out what was 742 * causing the problem. 743 * 744 * The address seems to pop up in random places, 745 * often not in the same place on two subsequent 746 * reads. 747 * 748 * In any case, the underlying data doesn't seem 749 * to be affected, just the value read out. 750 * 751 * KDM, 3/7/2000 752 */ 753 754 if (tmpval2 == 0xc0017c) 755 device_printf(sc->ti_dev, "found 0xc0017c at " 756 "%#x (tmpval2)\n", segptr); 757 758 if (tmpval == 0xc0017c) 759 device_printf(sc->ti_dev, "found 0xc0017c at " 760 "%#x (tmpval)\n", segptr); 761 762 if (useraddr) 763 copyout(&tmpval, ptr, 4); 764 else 765 bcopy(&tmpval, ptr, 4); 766 } else { 767 if (useraddr) 768 copyin(ptr, &tmpval2, 4); 769 else 770 bcopy(ptr, &tmpval2, 4); 771 772 tmpval = htonl(tmpval2); 773 774 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 775 } 776 777 cnt -= 4; 778 segptr += 4; 779 ptr += 4; 780 } 781 782 return (0); 783 } 784 785 static int 786 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 787 { 788 const uint8_t *tmpsrc; 789 uint8_t *tmpdst; 790 size_t tmplen; 791 792 if (len & 0x3) { 793 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 794 return (-1); 795 } 796 797 tmpsrc = src; 798 tmpdst = dst; 799 tmplen = len; 800 801 while (tmplen) { 802 if (swap_type == TI_SWAP_NTOH) 803 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 804 else 805 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 806 tmpsrc += 4; 807 tmpdst += 4; 808 tmplen -= 4; 809 } 810 811 return (0); 812 } 813 814 /* 815 * Load firmware image into the NIC. Check that the firmware revision 816 * is acceptable and see if we want the firmware for the Tigon 1 or 817 * Tigon 2. 818 */ 819 static void 820 ti_loadfw(struct ti_softc *sc) 821 { 822 823 TI_LOCK_ASSERT(sc); 824 825 switch (sc->ti_hwrev) { 826 case TI_HWREV_TIGON: 827 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 828 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 829 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 830 device_printf(sc->ti_dev, "firmware revision mismatch; " 831 "want %d.%d.%d, got %d.%d.%d\n", 832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 833 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 834 tigonFwReleaseMinor, tigonFwReleaseFix); 835 return; 836 } 837 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 838 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 839 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 840 tigonFwRodata); 841 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 842 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 844 break; 845 case TI_HWREV_TIGON_II: 846 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 847 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 848 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 849 device_printf(sc->ti_dev, "firmware revision mismatch; " 850 "want %d.%d.%d, got %d.%d.%d\n", 851 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 852 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 853 tigon2FwReleaseMinor, tigon2FwReleaseFix); 854 return; 855 } 856 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 857 tigon2FwText); 858 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 859 tigon2FwData); 860 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 861 tigon2FwRodata); 862 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 863 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 864 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 865 break; 866 default: 867 device_printf(sc->ti_dev, 868 "can't load firmware: unknown hardware rev\n"); 869 break; 870 } 871 } 872 873 /* 874 * Send the NIC a command via the command ring. 875 */ 876 static void 877 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 878 { 879 int index; 880 881 index = sc->ti_cmd_saved_prodidx; 882 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 883 TI_INC(index, TI_CMD_RING_CNT); 884 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 885 sc->ti_cmd_saved_prodidx = index; 886 } 887 888 /* 889 * Send the NIC an extended command. The 'len' parameter specifies the 890 * number of command slots to include after the initial command. 891 */ 892 static void 893 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 894 { 895 int index; 896 int i; 897 898 index = sc->ti_cmd_saved_prodidx; 899 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 900 TI_INC(index, TI_CMD_RING_CNT); 901 for (i = 0; i < len; i++) { 902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 903 *(uint32_t *)(&arg[i * 4])); 904 TI_INC(index, TI_CMD_RING_CNT); 905 } 906 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 907 sc->ti_cmd_saved_prodidx = index; 908 } 909 910 /* 911 * Handle events that have triggered interrupts. 912 */ 913 static void 914 ti_handle_events(struct ti_softc *sc) 915 { 916 struct ti_event_desc *e; 917 918 if (sc->ti_rdata.ti_event_ring == NULL) 919 return; 920 921 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 922 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 924 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 925 switch (TI_EVENT_EVENT(e)) { 926 case TI_EV_LINKSTAT_CHANGED: 927 sc->ti_linkstat = TI_EVENT_CODE(e); 928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 930 sc->ti_ifp->if_baudrate = IF_Mbps(100); 931 if (bootverbose) 932 device_printf(sc->ti_dev, 933 "10/100 link up\n"); 934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 937 if (bootverbose) 938 device_printf(sc->ti_dev, 939 "gigabit link up\n"); 940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 941 if_link_state_change(sc->ti_ifp, 942 LINK_STATE_DOWN); 943 sc->ti_ifp->if_baudrate = 0; 944 if (bootverbose) 945 device_printf(sc->ti_dev, 946 "link down\n"); 947 } 948 break; 949 case TI_EV_ERROR: 950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 951 device_printf(sc->ti_dev, "invalid command\n"); 952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 953 device_printf(sc->ti_dev, "unknown command\n"); 954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 955 device_printf(sc->ti_dev, "bad config data\n"); 956 break; 957 case TI_EV_FIRMWARE_UP: 958 ti_init2(sc); 959 break; 960 case TI_EV_STATS_UPDATED: 961 ti_stats_update(sc); 962 break; 963 case TI_EV_RESET_JUMBO_RING: 964 case TI_EV_MCAST_UPDATED: 965 /* Who cares. */ 966 break; 967 default: 968 device_printf(sc->ti_dev, "unknown event: %d\n", 969 TI_EVENT_EVENT(e)); 970 break; 971 } 972 /* Advance the consumer index. */ 973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 975 } 976 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 977 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 978 } 979 980 struct ti_dmamap_arg { 981 bus_addr_t ti_busaddr; 982 }; 983 984 static void 985 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 986 { 987 struct ti_dmamap_arg *ctx; 988 989 if (error) 990 return; 991 992 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 993 994 ctx = arg; 995 ctx->ti_busaddr = segs->ds_addr; 996 } 997 998 static int 999 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 1000 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1001 const char *msg) 1002 { 1003 struct ti_dmamap_arg ctx; 1004 int error; 1005 1006 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1007 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1008 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1009 if (error != 0) { 1010 device_printf(sc->ti_dev, 1011 "could not create %s dma tag\n", msg); 1012 return (error); 1013 } 1014 /* Allocate DMA'able memory for ring. */ 1015 error = bus_dmamem_alloc(*tag, (void **)ring, 1016 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1017 if (error != 0) { 1018 device_printf(sc->ti_dev, 1019 "could not allocate DMA'able memory for %s\n", msg); 1020 return (error); 1021 } 1022 /* Load the address of the ring. */ 1023 ctx.ti_busaddr = 0; 1024 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1025 &ctx, BUS_DMA_NOWAIT); 1026 if (error != 0) { 1027 device_printf(sc->ti_dev, 1028 "could not load DMA'able memory for %s\n", msg); 1029 return (error); 1030 } 1031 *paddr = ctx.ti_busaddr; 1032 return (0); 1033 } 1034 1035 static void 1036 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1037 bus_dmamap_t *map) 1038 { 1039 1040 if (*map != NULL) 1041 bus_dmamap_unload(*tag, *map); 1042 if (*map != NULL && *ring != NULL) { 1043 bus_dmamem_free(*tag, *ring, *map); 1044 *ring = NULL; 1045 *map = NULL; 1046 } 1047 if (*tag) { 1048 bus_dma_tag_destroy(*tag); 1049 *tag = NULL; 1050 } 1051 } 1052 1053 static int 1054 ti_dma_alloc(struct ti_softc *sc) 1055 { 1056 bus_addr_t lowaddr; 1057 int i, error; 1058 1059 lowaddr = BUS_SPACE_MAXADDR; 1060 if (sc->ti_dac == 0) 1061 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1062 1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1064 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1065 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1066 &sc->ti_cdata.ti_parent_tag); 1067 if (error != 0) { 1068 device_printf(sc->ti_dev, 1069 "could not allocate parent dma tag\n"); 1070 return (ENOMEM); 1071 } 1072 1073 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1074 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1075 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1076 if (error) 1077 return (error); 1078 1079 /* Producer/consumer status */ 1080 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1081 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1082 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1083 "event ring"); 1084 if (error) 1085 return (error); 1086 1087 /* Event ring */ 1088 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1089 &sc->ti_cdata.ti_event_ring_tag, 1090 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1091 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1092 "event ring"); 1093 if (error) 1094 return (error); 1095 1096 /* Command ring lives in shared memory so no need to create DMA area. */ 1097 1098 /* Standard RX ring */ 1099 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1100 &sc->ti_cdata.ti_rx_std_ring_tag, 1101 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1102 &sc->ti_cdata.ti_rx_std_ring_map, 1103 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1104 if (error) 1105 return (error); 1106 1107 /* Jumbo RX ring */ 1108 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1109 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1110 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1111 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1112 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1113 if (error) 1114 return (error); 1115 1116 /* RX return ring */ 1117 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1118 &sc->ti_cdata.ti_rx_return_ring_tag, 1119 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1120 &sc->ti_cdata.ti_rx_return_ring_map, 1121 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1122 if (error) 1123 return (error); 1124 1125 /* Create DMA tag for standard RX mbufs. */ 1126 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1128 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1129 if (error) { 1130 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1131 return (error); 1132 } 1133 1134 /* Create DMA tag for jumbo RX mbufs. */ 1135 #ifdef TI_SF_BUF_JUMBO 1136 /* 1137 * The VM system will take care of providing aligned pages. Alignment 1138 * is set to 1 here so that busdma resources won't be wasted. 1139 */ 1140 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1141 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1142 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1143 #else 1144 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1146 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1147 #endif 1148 if (error) { 1149 device_printf(sc->ti_dev, 1150 "could not allocate jumbo RX dma tag\n"); 1151 return (error); 1152 } 1153 1154 /* Create DMA tag for TX mbufs. */ 1155 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1156 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1157 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1158 &sc->ti_cdata.ti_tx_tag); 1159 if (error) { 1160 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1161 return (ENOMEM); 1162 } 1163 1164 /* Create DMA maps for RX buffers. */ 1165 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1166 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1167 &sc->ti_cdata.ti_rx_std_maps[i]); 1168 if (error) { 1169 device_printf(sc->ti_dev, 1170 "could not create DMA map for RX\n"); 1171 return (error); 1172 } 1173 } 1174 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1175 &sc->ti_cdata.ti_rx_std_sparemap); 1176 if (error) { 1177 device_printf(sc->ti_dev, 1178 "could not create spare DMA map for RX\n"); 1179 return (error); 1180 } 1181 1182 /* Create DMA maps for jumbo RX buffers. */ 1183 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1184 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1185 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1186 if (error) { 1187 device_printf(sc->ti_dev, 1188 "could not create DMA map for jumbo RX\n"); 1189 return (error); 1190 } 1191 } 1192 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1193 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1194 if (error) { 1195 device_printf(sc->ti_dev, 1196 "could not create spare DMA map for jumbo RX\n"); 1197 return (error); 1198 } 1199 1200 /* Create DMA maps for TX buffers. */ 1201 for (i = 0; i < TI_TX_RING_CNT; i++) { 1202 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1203 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1204 if (error) { 1205 device_printf(sc->ti_dev, 1206 "could not create DMA map for TX\n"); 1207 return (ENOMEM); 1208 } 1209 } 1210 1211 /* Mini ring and TX ring is not available on Tigon 1. */ 1212 if (sc->ti_hwrev == TI_HWREV_TIGON) 1213 return (0); 1214 1215 /* TX ring */ 1216 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1217 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1218 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1219 "TX ring"); 1220 if (error) 1221 return (error); 1222 1223 /* Mini RX ring */ 1224 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1225 &sc->ti_cdata.ti_rx_mini_ring_tag, 1226 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1227 &sc->ti_cdata.ti_rx_mini_ring_map, 1228 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1229 if (error) 1230 return (error); 1231 1232 /* Create DMA tag for mini RX mbufs. */ 1233 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1235 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1236 if (error) { 1237 device_printf(sc->ti_dev, 1238 "could not allocate mini RX dma tag\n"); 1239 return (error); 1240 } 1241 1242 /* Create DMA maps for mini RX buffers. */ 1243 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1244 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1245 &sc->ti_cdata.ti_rx_mini_maps[i]); 1246 if (error) { 1247 device_printf(sc->ti_dev, 1248 "could not create DMA map for mini RX\n"); 1249 return (error); 1250 } 1251 } 1252 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1253 &sc->ti_cdata.ti_rx_mini_sparemap); 1254 if (error) { 1255 device_printf(sc->ti_dev, 1256 "could not create spare DMA map for mini RX\n"); 1257 return (error); 1258 } 1259 1260 return (0); 1261 } 1262 1263 static void 1264 ti_dma_free(struct ti_softc *sc) 1265 { 1266 int i; 1267 1268 /* Destroy DMA maps for RX buffers. */ 1269 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1270 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1271 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1272 sc->ti_cdata.ti_rx_std_maps[i]); 1273 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1274 } 1275 } 1276 if (sc->ti_cdata.ti_rx_std_sparemap) { 1277 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1278 sc->ti_cdata.ti_rx_std_sparemap); 1279 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1280 } 1281 if (sc->ti_cdata.ti_rx_std_tag) { 1282 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1283 sc->ti_cdata.ti_rx_std_tag = NULL; 1284 } 1285 1286 /* Destroy DMA maps for jumbo RX buffers. */ 1287 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1288 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1289 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1290 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1291 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1292 } 1293 } 1294 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1295 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1296 sc->ti_cdata.ti_rx_jumbo_sparemap); 1297 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1298 } 1299 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1300 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1301 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1302 } 1303 1304 /* Destroy DMA maps for mini RX buffers. */ 1305 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1306 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1307 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1308 sc->ti_cdata.ti_rx_mini_maps[i]); 1309 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1310 } 1311 } 1312 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1313 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1314 sc->ti_cdata.ti_rx_mini_sparemap); 1315 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1316 } 1317 if (sc->ti_cdata.ti_rx_mini_tag) { 1318 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1319 sc->ti_cdata.ti_rx_mini_tag = NULL; 1320 } 1321 1322 /* Destroy DMA maps for TX buffers. */ 1323 for (i = 0; i < TI_TX_RING_CNT; i++) { 1324 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1325 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1326 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1327 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1328 } 1329 } 1330 if (sc->ti_cdata.ti_tx_tag) { 1331 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1332 sc->ti_cdata.ti_tx_tag = NULL; 1333 } 1334 1335 /* Destroy standard RX ring. */ 1336 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1337 (void *)&sc->ti_rdata.ti_rx_std_ring, 1338 &sc->ti_cdata.ti_rx_std_ring_map); 1339 /* Destroy jumbo RX ring. */ 1340 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1341 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1342 &sc->ti_cdata.ti_rx_jumbo_ring_map); 1343 /* Destroy mini RX ring. */ 1344 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1345 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1346 &sc->ti_cdata.ti_rx_mini_ring_map); 1347 /* Destroy RX return ring. */ 1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1349 (void *)&sc->ti_rdata.ti_rx_return_ring, 1350 &sc->ti_cdata.ti_rx_return_ring_map); 1351 /* Destroy TX ring. */ 1352 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1353 (void *)&sc->ti_rdata.ti_tx_ring, &sc->ti_cdata.ti_tx_ring_map); 1354 /* Destroy status block. */ 1355 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1356 (void *)&sc->ti_rdata.ti_status, &sc->ti_cdata.ti_status_map); 1357 /* Destroy event ring. */ 1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1359 (void *)&sc->ti_rdata.ti_event_ring, 1360 &sc->ti_cdata.ti_event_ring_map); 1361 /* Destroy GIB */ 1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1363 (void *)&sc->ti_rdata.ti_info, &sc->ti_cdata.ti_gib_map); 1364 1365 /* Destroy the parent tag. */ 1366 if (sc->ti_cdata.ti_parent_tag) { 1367 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1368 sc->ti_cdata.ti_parent_tag = NULL; 1369 } 1370 } 1371 1372 /* 1373 * Intialize a standard receive ring descriptor. 1374 */ 1375 static int 1376 ti_newbuf_std(struct ti_softc *sc, int i) 1377 { 1378 bus_dmamap_t map; 1379 bus_dma_segment_t segs[1]; 1380 struct mbuf *m; 1381 struct ti_rx_desc *r; 1382 int error, nsegs; 1383 1384 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1385 if (m == NULL) 1386 return (ENOBUFS); 1387 m->m_len = m->m_pkthdr.len = MCLBYTES; 1388 m_adj(m, ETHER_ALIGN); 1389 1390 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1391 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1392 if (error != 0) { 1393 m_freem(m); 1394 return (error); 1395 } 1396 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1397 1398 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1399 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1400 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1402 sc->ti_cdata.ti_rx_std_maps[i]); 1403 } 1404 1405 map = sc->ti_cdata.ti_rx_std_maps[i]; 1406 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1407 sc->ti_cdata.ti_rx_std_sparemap = map; 1408 sc->ti_cdata.ti_rx_std_chain[i] = m; 1409 1410 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1411 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1412 r->ti_len = segs[0].ds_len; 1413 r->ti_type = TI_BDTYPE_RECV_BD; 1414 r->ti_flags = 0; 1415 r->ti_vlan_tag = 0; 1416 r->ti_tcp_udp_cksum = 0; 1417 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1418 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1419 r->ti_idx = i; 1420 1421 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1422 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1423 return (0); 1424 } 1425 1426 /* 1427 * Intialize a mini receive ring descriptor. This only applies to 1428 * the Tigon 2. 1429 */ 1430 static int 1431 ti_newbuf_mini(struct ti_softc *sc, int i) 1432 { 1433 bus_dmamap_t map; 1434 bus_dma_segment_t segs[1]; 1435 struct mbuf *m; 1436 struct ti_rx_desc *r; 1437 int error, nsegs; 1438 1439 MGETHDR(m, M_DONTWAIT, MT_DATA); 1440 if (m == NULL) 1441 return (ENOBUFS); 1442 m->m_len = m->m_pkthdr.len = MHLEN; 1443 m_adj(m, ETHER_ALIGN); 1444 1445 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1446 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1447 if (error != 0) { 1448 m_freem(m); 1449 return (error); 1450 } 1451 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1452 1453 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1454 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1455 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1456 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1457 sc->ti_cdata.ti_rx_mini_maps[i]); 1458 } 1459 1460 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1461 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1462 sc->ti_cdata.ti_rx_mini_sparemap = map; 1463 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1464 1465 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1466 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1467 r->ti_len = segs[0].ds_len; 1468 r->ti_type = TI_BDTYPE_RECV_BD; 1469 r->ti_flags = TI_BDFLAG_MINI_RING; 1470 r->ti_vlan_tag = 0; 1471 r->ti_tcp_udp_cksum = 0; 1472 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1473 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1474 r->ti_idx = i; 1475 1476 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1477 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1478 return (0); 1479 } 1480 1481 #ifndef TI_SF_BUF_JUMBO 1482 1483 /* 1484 * Initialize a jumbo receive ring descriptor. This allocates 1485 * a jumbo buffer from the pool managed internally by the driver. 1486 */ 1487 static int 1488 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1489 { 1490 bus_dmamap_t map; 1491 bus_dma_segment_t segs[1]; 1492 struct mbuf *m; 1493 struct ti_rx_desc *r; 1494 int error, nsegs; 1495 1496 (void)dummy; 1497 1498 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1499 if (m == NULL) 1500 return (ENOBUFS); 1501 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1502 m_adj(m, ETHER_ALIGN); 1503 1504 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1505 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1506 if (error != 0) { 1507 m_freem(m); 1508 return (error); 1509 } 1510 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1511 1512 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1513 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1514 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1515 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1516 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1517 } 1518 1519 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1520 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1521 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1522 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1523 1524 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1525 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1526 r->ti_len = segs[0].ds_len; 1527 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1528 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1529 r->ti_vlan_tag = 0; 1530 r->ti_tcp_udp_cksum = 0; 1531 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1532 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1533 r->ti_idx = i; 1534 1535 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1536 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1537 return (0); 1538 } 1539 1540 #else 1541 1542 #if (PAGE_SIZE == 4096) 1543 #define NPAYLOAD 2 1544 #else 1545 #define NPAYLOAD 1 1546 #endif 1547 1548 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1549 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1550 #define NFS_HDR_LEN (UDP_HDR_LEN) 1551 static int HDR_LEN = TCP_HDR_LEN; 1552 1553 /* 1554 * Initialize a jumbo receive ring descriptor. This allocates 1555 * a jumbo buffer from the pool managed internally by the driver. 1556 */ 1557 static int 1558 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1559 { 1560 bus_dmamap_t map; 1561 struct mbuf *cur, *m_new = NULL; 1562 struct mbuf *m[3] = {NULL, NULL, NULL}; 1563 struct ti_rx_desc_ext *r; 1564 vm_page_t frame; 1565 static int color; 1566 /* 1 extra buf to make nobufs easy*/ 1567 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1568 int i; 1569 bus_dma_segment_t segs[4]; 1570 int nsegs; 1571 1572 if (m_old != NULL) { 1573 m_new = m_old; 1574 cur = m_old->m_next; 1575 for (i = 0; i <= NPAYLOAD; i++){ 1576 m[i] = cur; 1577 cur = cur->m_next; 1578 } 1579 } else { 1580 /* Allocate the mbufs. */ 1581 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1582 if (m_new == NULL) { 1583 device_printf(sc->ti_dev, "mbuf allocation failed " 1584 "-- packet dropped!\n"); 1585 goto nobufs; 1586 } 1587 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1588 if (m[NPAYLOAD] == NULL) { 1589 device_printf(sc->ti_dev, "cluster mbuf allocation " 1590 "failed -- packet dropped!\n"); 1591 goto nobufs; 1592 } 1593 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1594 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1595 device_printf(sc->ti_dev, "mbuf allocation failed " 1596 "-- packet dropped!\n"); 1597 goto nobufs; 1598 } 1599 m[NPAYLOAD]->m_len = MCLBYTES; 1600 1601 for (i = 0; i < NPAYLOAD; i++){ 1602 MGET(m[i], M_DONTWAIT, MT_DATA); 1603 if (m[i] == NULL) { 1604 device_printf(sc->ti_dev, "mbuf allocation " 1605 "failed -- packet dropped!\n"); 1606 goto nobufs; 1607 } 1608 frame = vm_page_alloc(NULL, color++, 1609 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1610 VM_ALLOC_WIRED); 1611 if (frame == NULL) { 1612 device_printf(sc->ti_dev, "buffer allocation " 1613 "failed -- packet dropped!\n"); 1614 printf(" index %d page %d\n", idx, i); 1615 goto nobufs; 1616 } 1617 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1618 if (sf[i] == NULL) { 1619 vm_page_lock_queues(); 1620 vm_page_unwire(frame, 0); 1621 vm_page_free(frame); 1622 vm_page_unlock_queues(); 1623 device_printf(sc->ti_dev, "buffer allocation " 1624 "failed -- packet dropped!\n"); 1625 printf(" index %d page %d\n", idx, i); 1626 goto nobufs; 1627 } 1628 } 1629 for (i = 0; i < NPAYLOAD; i++){ 1630 /* Attach the buffer to the mbuf. */ 1631 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1632 m[i]->m_len = PAGE_SIZE; 1633 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1634 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1635 0, EXT_DISPOSABLE); 1636 m[i]->m_next = m[i+1]; 1637 } 1638 /* link the buffers to the header */ 1639 m_new->m_next = m[0]; 1640 m_new->m_data += ETHER_ALIGN; 1641 if (sc->ti_hdrsplit) 1642 m_new->m_len = MHLEN - ETHER_ALIGN; 1643 else 1644 m_new->m_len = HDR_LEN; 1645 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1646 } 1647 1648 /* Set up the descriptor. */ 1649 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1650 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1651 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1652 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1653 segs, &nsegs, 0)) 1654 return (ENOBUFS); 1655 if ((nsegs < 1) || (nsegs > 4)) 1656 return (ENOBUFS); 1657 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1658 r->ti_len0 = m_new->m_len; 1659 1660 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1661 r->ti_len1 = PAGE_SIZE; 1662 1663 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1664 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1665 1666 if (PAGE_SIZE == 4096) { 1667 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1668 r->ti_len3 = MCLBYTES; 1669 } else { 1670 r->ti_len3 = 0; 1671 } 1672 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1673 1674 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1675 1676 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1677 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1678 1679 r->ti_idx = idx; 1680 1681 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1682 return (0); 1683 1684 nobufs: 1685 1686 /* 1687 * Warning! : 1688 * This can only be called before the mbufs are strung together. 1689 * If the mbufs are strung together, m_freem() will free the chain, 1690 * so that the later mbufs will be freed multiple times. 1691 */ 1692 if (m_new) 1693 m_freem(m_new); 1694 1695 for (i = 0; i < 3; i++) { 1696 if (m[i]) 1697 m_freem(m[i]); 1698 if (sf[i]) 1699 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1700 } 1701 return (ENOBUFS); 1702 } 1703 #endif 1704 1705 /* 1706 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1707 * that's 1MB or memory, which is a lot. For now, we fill only the first 1708 * 256 ring entries and hope that our CPU is fast enough to keep up with 1709 * the NIC. 1710 */ 1711 static int 1712 ti_init_rx_ring_std(struct ti_softc *sc) 1713 { 1714 int i; 1715 struct ti_cmd_desc cmd; 1716 1717 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1718 if (ti_newbuf_std(sc, i) != 0) 1719 return (ENOBUFS); 1720 }; 1721 1722 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1723 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1724 1725 return (0); 1726 } 1727 1728 static void 1729 ti_free_rx_ring_std(struct ti_softc *sc) 1730 { 1731 bus_dmamap_t map; 1732 int i; 1733 1734 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1735 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1736 map = sc->ti_cdata.ti_rx_std_maps[i]; 1737 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1738 BUS_DMASYNC_POSTREAD); 1739 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1740 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1741 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1742 } 1743 } 1744 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1745 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1746 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1747 } 1748 1749 static int 1750 ti_init_rx_ring_jumbo(struct ti_softc *sc) 1751 { 1752 struct ti_cmd_desc cmd; 1753 int i; 1754 1755 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1756 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1757 return (ENOBUFS); 1758 }; 1759 1760 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1761 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1762 1763 return (0); 1764 } 1765 1766 static void 1767 ti_free_rx_ring_jumbo(struct ti_softc *sc) 1768 { 1769 bus_dmamap_t map; 1770 int i; 1771 1772 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1773 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1774 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1775 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1776 BUS_DMASYNC_POSTREAD); 1777 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1778 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1779 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1780 } 1781 } 1782 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1783 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1784 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1785 } 1786 1787 static int 1788 ti_init_rx_ring_mini(struct ti_softc *sc) 1789 { 1790 int i; 1791 1792 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1793 if (ti_newbuf_mini(sc, i) != 0) 1794 return (ENOBUFS); 1795 }; 1796 1797 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1798 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1799 1800 return (0); 1801 } 1802 1803 static void 1804 ti_free_rx_ring_mini(struct ti_softc *sc) 1805 { 1806 bus_dmamap_t map; 1807 int i; 1808 1809 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1810 return; 1811 1812 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1813 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1814 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1815 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1816 BUS_DMASYNC_POSTREAD); 1817 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1818 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1819 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1820 } 1821 } 1822 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1823 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1824 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1825 } 1826 1827 static void 1828 ti_free_tx_ring(struct ti_softc *sc) 1829 { 1830 struct ti_txdesc *txd; 1831 int i; 1832 1833 if (sc->ti_rdata.ti_tx_ring == NULL) 1834 return; 1835 1836 for (i = 0; i < TI_TX_RING_CNT; i++) { 1837 txd = &sc->ti_cdata.ti_txdesc[i]; 1838 if (txd->tx_m != NULL) { 1839 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1840 BUS_DMASYNC_POSTWRITE); 1841 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1842 txd->tx_dmamap); 1843 m_freem(txd->tx_m); 1844 txd->tx_m = NULL; 1845 } 1846 } 1847 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1848 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1849 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1850 } 1851 1852 static int 1853 ti_init_tx_ring(struct ti_softc *sc) 1854 { 1855 struct ti_txdesc *txd; 1856 int i; 1857 1858 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1859 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1860 for (i = 0; i < TI_TX_RING_CNT; i++) { 1861 txd = &sc->ti_cdata.ti_txdesc[i]; 1862 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1863 } 1864 sc->ti_txcnt = 0; 1865 sc->ti_tx_saved_considx = 0; 1866 sc->ti_tx_saved_prodidx = 0; 1867 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1868 return (0); 1869 } 1870 1871 /* 1872 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1873 * but we have to support the old way too so that Tigon 1 cards will 1874 * work. 1875 */ 1876 static void 1877 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1878 { 1879 struct ti_cmd_desc cmd; 1880 uint16_t *m; 1881 uint32_t ext[2] = {0, 0}; 1882 1883 m = (uint16_t *)&addr->octet[0]; 1884 1885 switch (sc->ti_hwrev) { 1886 case TI_HWREV_TIGON: 1887 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1888 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1889 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1890 break; 1891 case TI_HWREV_TIGON_II: 1892 ext[0] = htons(m[0]); 1893 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1894 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1895 break; 1896 default: 1897 device_printf(sc->ti_dev, "unknown hwrev\n"); 1898 break; 1899 } 1900 } 1901 1902 static void 1903 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1904 { 1905 struct ti_cmd_desc cmd; 1906 uint16_t *m; 1907 uint32_t ext[2] = {0, 0}; 1908 1909 m = (uint16_t *)&addr->octet[0]; 1910 1911 switch (sc->ti_hwrev) { 1912 case TI_HWREV_TIGON: 1913 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1914 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1915 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1916 break; 1917 case TI_HWREV_TIGON_II: 1918 ext[0] = htons(m[0]); 1919 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1920 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1921 break; 1922 default: 1923 device_printf(sc->ti_dev, "unknown hwrev\n"); 1924 break; 1925 } 1926 } 1927 1928 /* 1929 * Configure the Tigon's multicast address filter. 1930 * 1931 * The actual multicast table management is a bit of a pain, thanks to 1932 * slight brain damage on the part of both Alteon and us. With our 1933 * multicast code, we are only alerted when the multicast address table 1934 * changes and at that point we only have the current list of addresses: 1935 * we only know the current state, not the previous state, so we don't 1936 * actually know what addresses were removed or added. The firmware has 1937 * state, but we can't get our grubby mits on it, and there is no 'delete 1938 * all multicast addresses' command. Hence, we have to maintain our own 1939 * state so we know what addresses have been programmed into the NIC at 1940 * any given time. 1941 */ 1942 static void 1943 ti_setmulti(struct ti_softc *sc) 1944 { 1945 struct ifnet *ifp; 1946 struct ifmultiaddr *ifma; 1947 struct ti_cmd_desc cmd; 1948 struct ti_mc_entry *mc; 1949 uint32_t intrs; 1950 1951 TI_LOCK_ASSERT(sc); 1952 1953 ifp = sc->ti_ifp; 1954 1955 if (ifp->if_flags & IFF_ALLMULTI) { 1956 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1957 return; 1958 } else { 1959 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1960 } 1961 1962 /* Disable interrupts. */ 1963 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1964 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1965 1966 /* First, zot all the existing filters. */ 1967 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1968 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1969 ti_del_mcast(sc, &mc->mc_addr); 1970 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1971 free(mc, M_DEVBUF); 1972 } 1973 1974 /* Now program new ones. */ 1975 if_maddr_rlock(ifp); 1976 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1977 if (ifma->ifma_addr->sa_family != AF_LINK) 1978 continue; 1979 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1980 if (mc == NULL) { 1981 device_printf(sc->ti_dev, 1982 "no memory for mcast filter entry\n"); 1983 continue; 1984 } 1985 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1986 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1987 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1988 ti_add_mcast(sc, &mc->mc_addr); 1989 } 1990 if_maddr_runlock(ifp); 1991 1992 /* Re-enable interrupts. */ 1993 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1994 } 1995 1996 /* 1997 * Check to see if the BIOS has configured us for a 64 bit slot when 1998 * we aren't actually in one. If we detect this condition, we can work 1999 * around it on the Tigon 2 by setting a bit in the PCI state register, 2000 * but for the Tigon 1 we must give up and abort the interface attach. 2001 */ 2002 static int 2003 ti_64bitslot_war(struct ti_softc *sc) 2004 { 2005 2006 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 2007 CSR_WRITE_4(sc, 0x600, 0); 2008 CSR_WRITE_4(sc, 0x604, 0); 2009 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2010 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2011 if (sc->ti_hwrev == TI_HWREV_TIGON) 2012 return (EINVAL); 2013 else { 2014 TI_SETBIT(sc, TI_PCI_STATE, 2015 TI_PCISTATE_32BIT_BUS); 2016 return (0); 2017 } 2018 } 2019 } 2020 2021 return (0); 2022 } 2023 2024 /* 2025 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2026 * self-test results. 2027 */ 2028 static int 2029 ti_chipinit(struct ti_softc *sc) 2030 { 2031 uint32_t cacheline; 2032 uint32_t pci_writemax = 0; 2033 uint32_t hdrsplit; 2034 2035 /* Initialize link to down state. */ 2036 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2037 2038 /* Set endianness before we access any non-PCI registers. */ 2039 #if 0 && BYTE_ORDER == BIG_ENDIAN 2040 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2041 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2042 #else 2043 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2044 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2045 #endif 2046 2047 /* Check the ROM failed bit to see if self-tests passed. */ 2048 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2049 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2050 return (ENODEV); 2051 } 2052 2053 /* Halt the CPU. */ 2054 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2055 2056 /* Figure out the hardware revision. */ 2057 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2058 case TI_REV_TIGON_I: 2059 sc->ti_hwrev = TI_HWREV_TIGON; 2060 break; 2061 case TI_REV_TIGON_II: 2062 sc->ti_hwrev = TI_HWREV_TIGON_II; 2063 break; 2064 default: 2065 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2066 return (ENODEV); 2067 } 2068 2069 /* Do special setup for Tigon 2. */ 2070 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2071 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2072 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2073 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2074 } 2075 2076 /* 2077 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2078 * can't do header splitting. 2079 */ 2080 #ifdef TI_JUMBO_HDRSPLIT 2081 if (sc->ti_hwrev != TI_HWREV_TIGON) 2082 sc->ti_hdrsplit = 1; 2083 else 2084 device_printf(sc->ti_dev, 2085 "can't do header splitting on a Tigon I board\n"); 2086 #endif /* TI_JUMBO_HDRSPLIT */ 2087 2088 /* Set up the PCI state register. */ 2089 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2090 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2091 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2092 } 2093 2094 /* Clear the read/write max DMA parameters. */ 2095 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2096 TI_PCISTATE_READ_MAXDMA)); 2097 2098 /* Get cache line size. */ 2099 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2100 2101 /* 2102 * If the system has set enabled the PCI memory write 2103 * and invalidate command in the command register, set 2104 * the write max parameter accordingly. This is necessary 2105 * to use MWI with the Tigon 2. 2106 */ 2107 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2108 switch (cacheline) { 2109 case 1: 2110 case 4: 2111 case 8: 2112 case 16: 2113 case 32: 2114 case 64: 2115 break; 2116 default: 2117 /* Disable PCI memory write and invalidate. */ 2118 if (bootverbose) 2119 device_printf(sc->ti_dev, "cache line size %d" 2120 " not supported; disabling PCI MWI\n", 2121 cacheline); 2122 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2123 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2124 break; 2125 } 2126 } 2127 2128 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2129 2130 /* This sets the min dma param all the way up (0xff). */ 2131 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2132 2133 if (sc->ti_hdrsplit) 2134 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2135 else 2136 hdrsplit = 0; 2137 2138 /* Configure DMA variables. */ 2139 #if BYTE_ORDER == BIG_ENDIAN 2140 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2141 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2142 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2143 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2144 #else /* BYTE_ORDER */ 2145 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2146 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2147 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2148 #endif /* BYTE_ORDER */ 2149 2150 /* 2151 * Only allow 1 DMA channel to be active at a time. 2152 * I don't think this is a good idea, but without it 2153 * the firmware racks up lots of nicDmaReadRingFull 2154 * errors. This is not compatible with hardware checksums. 2155 */ 2156 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2157 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2158 2159 /* Recommended settings from Tigon manual. */ 2160 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2161 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2162 2163 if (ti_64bitslot_war(sc)) { 2164 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2165 "but we aren't"); 2166 return (EINVAL); 2167 } 2168 2169 return (0); 2170 } 2171 2172 /* 2173 * Initialize the general information block and firmware, and 2174 * start the CPU(s) running. 2175 */ 2176 static int 2177 ti_gibinit(struct ti_softc *sc) 2178 { 2179 struct ifnet *ifp; 2180 struct ti_rcb *rcb; 2181 int i; 2182 2183 TI_LOCK_ASSERT(sc); 2184 2185 ifp = sc->ti_ifp; 2186 2187 /* Disable interrupts for now. */ 2188 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2189 2190 /* Tell the chip where to find the general information block. */ 2191 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2192 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2193 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2194 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2195 2196 /* Load the firmware into SRAM. */ 2197 ti_loadfw(sc); 2198 2199 /* Set up the contents of the general info and ring control blocks. */ 2200 2201 /* Set up the event ring and producer pointer. */ 2202 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2203 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2204 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2205 rcb->ti_flags = 0; 2206 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2207 sc->ti_rdata.ti_status_paddr + 2208 offsetof(struct ti_status, ti_ev_prodidx_r)); 2209 sc->ti_ev_prodidx.ti_idx = 0; 2210 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2211 sc->ti_ev_saved_considx = 0; 2212 2213 /* Set up the command ring and producer mailbox. */ 2214 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2215 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2216 rcb->ti_flags = 0; 2217 rcb->ti_max_len = 0; 2218 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2219 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2220 } 2221 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2222 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2223 sc->ti_cmd_saved_prodidx = 0; 2224 2225 /* 2226 * Assign the address of the stats refresh buffer. 2227 * We re-use the current stats buffer for this to 2228 * conserve memory. 2229 */ 2230 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2231 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2232 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2233 2234 /* Set up the standard receive ring. */ 2235 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2236 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2237 rcb->ti_max_len = TI_FRAMELEN; 2238 rcb->ti_flags = 0; 2239 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2240 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2241 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2242 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2243 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2244 2245 /* Set up the jumbo receive ring. */ 2246 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2247 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2248 2249 #ifndef TI_SF_BUF_JUMBO 2250 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2251 rcb->ti_flags = 0; 2252 #else 2253 rcb->ti_max_len = PAGE_SIZE; 2254 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2255 #endif 2256 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2257 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2258 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2259 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2260 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2261 2262 /* 2263 * Set up the mini ring. Only activated on the 2264 * Tigon 2 but the slot in the config block is 2265 * still there on the Tigon 1. 2266 */ 2267 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2268 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2269 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2270 if (sc->ti_hwrev == TI_HWREV_TIGON) 2271 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2272 else 2273 rcb->ti_flags = 0; 2274 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2275 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2276 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2277 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2278 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2279 2280 /* 2281 * Set up the receive return ring. 2282 */ 2283 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2284 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2285 rcb->ti_flags = 0; 2286 rcb->ti_max_len = TI_RETURN_RING_CNT; 2287 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2288 sc->ti_rdata.ti_status_paddr + 2289 offsetof(struct ti_status, ti_return_prodidx_r)); 2290 2291 /* 2292 * Set up the tx ring. Note: for the Tigon 2, we have the option 2293 * of putting the transmit ring in the host's address space and 2294 * letting the chip DMA it instead of leaving the ring in the NIC's 2295 * memory and accessing it through the shared memory region. We 2296 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2297 * so we have to revert to the shared memory scheme if we detect 2298 * a Tigon 1 chip. 2299 */ 2300 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2301 if (sc->ti_rdata.ti_tx_ring != NULL) 2302 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2303 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2304 if (sc->ti_hwrev == TI_HWREV_TIGON) 2305 rcb->ti_flags = 0; 2306 else 2307 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2308 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2309 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2310 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2311 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2312 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2313 rcb->ti_max_len = TI_TX_RING_CNT; 2314 if (sc->ti_hwrev == TI_HWREV_TIGON) 2315 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2316 else 2317 ti_hostaddr64(&rcb->ti_hostaddr, 2318 sc->ti_rdata.ti_tx_ring_paddr); 2319 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2320 sc->ti_rdata.ti_status_paddr + 2321 offsetof(struct ti_status, ti_tx_considx_r)); 2322 2323 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2325 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2326 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2327 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2328 sc->ti_cdata.ti_event_ring_map, 2329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2330 if (sc->ti_rdata.ti_tx_ring != NULL) 2331 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2332 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2333 2334 /* Set up tunables */ 2335 #if 0 2336 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2337 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2338 (sc->ti_rx_coal_ticks / 10)); 2339 else 2340 #endif 2341 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2342 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2343 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2344 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2345 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2346 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2347 2348 /* Turn interrupts on. */ 2349 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2350 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2351 2352 /* Start CPU. */ 2353 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2354 2355 return (0); 2356 } 2357 2358 /* 2359 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2360 * against our list and return its name if we find a match. 2361 */ 2362 static int 2363 ti_probe(device_t dev) 2364 { 2365 const struct ti_type *t; 2366 2367 t = ti_devs; 2368 2369 while (t->ti_name != NULL) { 2370 if ((pci_get_vendor(dev) == t->ti_vid) && 2371 (pci_get_device(dev) == t->ti_did)) { 2372 device_set_desc(dev, t->ti_name); 2373 return (BUS_PROBE_DEFAULT); 2374 } 2375 t++; 2376 } 2377 2378 return (ENXIO); 2379 } 2380 2381 static int 2382 ti_attach(device_t dev) 2383 { 2384 struct ifnet *ifp; 2385 struct ti_softc *sc; 2386 int error = 0, rid; 2387 u_char eaddr[6]; 2388 2389 sc = device_get_softc(dev); 2390 sc->ti_dev = dev; 2391 2392 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2393 MTX_DEF); 2394 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2395 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2396 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2397 if (ifp == NULL) { 2398 device_printf(dev, "can not if_alloc()\n"); 2399 error = ENOSPC; 2400 goto fail; 2401 } 2402 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2403 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2404 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2405 2406 /* 2407 * Map control/status registers. 2408 */ 2409 pci_enable_busmaster(dev); 2410 2411 rid = PCIR_BAR(0); 2412 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2413 RF_ACTIVE); 2414 2415 if (sc->ti_res == NULL) { 2416 device_printf(dev, "couldn't map memory\n"); 2417 error = ENXIO; 2418 goto fail; 2419 } 2420 2421 sc->ti_btag = rman_get_bustag(sc->ti_res); 2422 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2423 2424 /* Allocate interrupt */ 2425 rid = 0; 2426 2427 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2428 RF_SHAREABLE | RF_ACTIVE); 2429 2430 if (sc->ti_irq == NULL) { 2431 device_printf(dev, "couldn't map interrupt\n"); 2432 error = ENXIO; 2433 goto fail; 2434 } 2435 2436 if (ti_chipinit(sc)) { 2437 device_printf(dev, "chip initialization failed\n"); 2438 error = ENXIO; 2439 goto fail; 2440 } 2441 2442 /* Zero out the NIC's on-board SRAM. */ 2443 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2444 2445 /* Init again -- zeroing memory may have clobbered some registers. */ 2446 if (ti_chipinit(sc)) { 2447 device_printf(dev, "chip initialization failed\n"); 2448 error = ENXIO; 2449 goto fail; 2450 } 2451 2452 /* 2453 * Get station address from the EEPROM. Note: the manual states 2454 * that the MAC address is at offset 0x8c, however the data is 2455 * stored as two longwords (since that's how it's loaded into 2456 * the NIC). This means the MAC address is actually preceded 2457 * by two zero bytes. We need to skip over those. 2458 */ 2459 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2460 device_printf(dev, "failed to read station address\n"); 2461 error = ENXIO; 2462 goto fail; 2463 } 2464 2465 /* Allocate working area for memory dump. */ 2466 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2467 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2468 M_NOWAIT); 2469 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2470 device_printf(dev, "cannot allocate memory buffer\n"); 2471 error = ENOMEM; 2472 goto fail; 2473 } 2474 if ((error = ti_dma_alloc(sc)) != 0) 2475 goto fail; 2476 2477 /* 2478 * We really need a better way to tell a 1000baseTX card 2479 * from a 1000baseSX one, since in theory there could be 2480 * OEMed 1000baseTX cards from lame vendors who aren't 2481 * clever enough to change the PCI ID. For the moment 2482 * though, the AceNIC is the only copper card available. 2483 */ 2484 if (pci_get_vendor(dev) == ALT_VENDORID && 2485 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2486 sc->ti_copper = 1; 2487 /* Ok, it's not the only copper card available. */ 2488 if (pci_get_vendor(dev) == NG_VENDORID && 2489 pci_get_device(dev) == NG_DEVICEID_GA620T) 2490 sc->ti_copper = 1; 2491 2492 /* Set default tunable values. */ 2493 ti_sysctl_node(sc); 2494 2495 /* Set up ifnet structure */ 2496 ifp->if_softc = sc; 2497 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2498 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2499 ifp->if_ioctl = ti_ioctl; 2500 ifp->if_start = ti_start; 2501 ifp->if_init = ti_init; 2502 ifp->if_baudrate = IF_Gbps(1UL); 2503 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2504 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2505 IFQ_SET_READY(&ifp->if_snd); 2506 2507 /* Set up ifmedia support. */ 2508 if (sc->ti_copper) { 2509 /* 2510 * Copper cards allow manual 10/100 mode selection, 2511 * but not manual 1000baseTX mode selection. Why? 2512 * Becuase currently there's no way to specify the 2513 * master/slave setting through the firmware interface, 2514 * so Alteon decided to just bag it and handle it 2515 * via autonegotiation. 2516 */ 2517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2518 ifmedia_add(&sc->ifmedia, 2519 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2521 ifmedia_add(&sc->ifmedia, 2522 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2523 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2524 ifmedia_add(&sc->ifmedia, 2525 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2526 } else { 2527 /* Fiber cards don't support 10/100 modes. */ 2528 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2529 ifmedia_add(&sc->ifmedia, 2530 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2531 } 2532 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2533 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2534 2535 /* 2536 * We're assuming here that card initialization is a sequential 2537 * thing. If it isn't, multiple cards probing at the same time 2538 * could stomp on the list of softcs here. 2539 */ 2540 2541 /* Register the device */ 2542 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2543 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2544 sc->dev->si_drv1 = sc; 2545 2546 /* 2547 * Call MI attach routine. 2548 */ 2549 ether_ifattach(ifp, eaddr); 2550 2551 /* VLAN capability setup. */ 2552 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2553 IFCAP_VLAN_HWTAGGING; 2554 ifp->if_capenable = ifp->if_capabilities; 2555 /* Tell the upper layer we support VLAN over-sized frames. */ 2556 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2557 2558 /* Driver supports link state tracking. */ 2559 ifp->if_capabilities |= IFCAP_LINKSTATE; 2560 ifp->if_capenable |= IFCAP_LINKSTATE; 2561 2562 /* Hook interrupt last to avoid having to lock softc */ 2563 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2564 NULL, ti_intr, sc, &sc->ti_intrhand); 2565 2566 if (error) { 2567 device_printf(dev, "couldn't set up irq\n"); 2568 goto fail; 2569 } 2570 2571 fail: 2572 if (error) 2573 ti_detach(dev); 2574 2575 return (error); 2576 } 2577 2578 /* 2579 * Shutdown hardware and free up resources. This can be called any 2580 * time after the mutex has been initialized. It is called in both 2581 * the error case in attach and the normal detach case so it needs 2582 * to be careful about only freeing resources that have actually been 2583 * allocated. 2584 */ 2585 static int 2586 ti_detach(device_t dev) 2587 { 2588 struct ti_softc *sc; 2589 struct ifnet *ifp; 2590 2591 sc = device_get_softc(dev); 2592 if (sc->dev) 2593 destroy_dev(sc->dev); 2594 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2595 ifp = sc->ti_ifp; 2596 if (device_is_attached(dev)) { 2597 ether_ifdetach(ifp); 2598 TI_LOCK(sc); 2599 ti_stop(sc); 2600 TI_UNLOCK(sc); 2601 } 2602 2603 /* These should only be active if attach succeeded */ 2604 callout_drain(&sc->ti_watchdog); 2605 bus_generic_detach(dev); 2606 ti_dma_free(sc); 2607 ifmedia_removeall(&sc->ifmedia); 2608 2609 if (sc->ti_intrhand) 2610 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2611 if (sc->ti_irq) 2612 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2613 if (sc->ti_res) { 2614 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2615 sc->ti_res); 2616 } 2617 if (ifp) 2618 if_free(ifp); 2619 if (sc->ti_membuf) 2620 free(sc->ti_membuf, M_DEVBUF); 2621 if (sc->ti_membuf2) 2622 free(sc->ti_membuf2, M_DEVBUF); 2623 2624 mtx_destroy(&sc->ti_mtx); 2625 2626 return (0); 2627 } 2628 2629 #ifdef TI_JUMBO_HDRSPLIT 2630 /* 2631 * If hdr_len is 0, that means that header splitting wasn't done on 2632 * this packet for some reason. The two most likely reasons are that 2633 * the protocol isn't a supported protocol for splitting, or this 2634 * packet had a fragment offset that wasn't 0. 2635 * 2636 * The header length, if it is non-zero, will always be the length of 2637 * the headers on the packet, but that length could be longer than the 2638 * first mbuf. So we take the minimum of the two as the actual 2639 * length. 2640 */ 2641 static __inline void 2642 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2643 { 2644 int i = 0; 2645 int lengths[4] = {0, 0, 0, 0}; 2646 struct mbuf *m, *mp; 2647 2648 if (hdr_len != 0) 2649 top->m_len = min(hdr_len, top->m_len); 2650 pkt_len -= top->m_len; 2651 lengths[i++] = top->m_len; 2652 2653 mp = top; 2654 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2655 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2656 pkt_len -= m->m_len; 2657 lengths[i++] = m->m_len; 2658 mp = m; 2659 } 2660 2661 #if 0 2662 if (hdr_len != 0) 2663 printf("got split packet: "); 2664 else 2665 printf("got non-split packet: "); 2666 2667 printf("%d,%d,%d,%d = %d\n", lengths[0], 2668 lengths[1], lengths[2], lengths[3], 2669 lengths[0] + lengths[1] + lengths[2] + 2670 lengths[3]); 2671 #endif 2672 2673 if (pkt_len) 2674 panic("header splitting didn't"); 2675 2676 if (m) { 2677 m_freem(m); 2678 mp->m_next = NULL; 2679 2680 } 2681 if (mp->m_next != NULL) 2682 panic("ti_hdr_split: last mbuf in chain should be null"); 2683 } 2684 #endif /* TI_JUMBO_HDRSPLIT */ 2685 2686 static void 2687 ti_discard_std(struct ti_softc *sc, int i) 2688 { 2689 2690 struct ti_rx_desc *r; 2691 2692 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2693 r->ti_len = MCLBYTES - ETHER_ALIGN; 2694 r->ti_type = TI_BDTYPE_RECV_BD; 2695 r->ti_flags = 0; 2696 r->ti_vlan_tag = 0; 2697 r->ti_tcp_udp_cksum = 0; 2698 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2699 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2700 r->ti_idx = i; 2701 } 2702 2703 static void 2704 ti_discard_mini(struct ti_softc *sc, int i) 2705 { 2706 2707 struct ti_rx_desc *r; 2708 2709 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2710 r->ti_len = MHLEN - ETHER_ALIGN; 2711 r->ti_type = TI_BDTYPE_RECV_BD; 2712 r->ti_flags = TI_BDFLAG_MINI_RING; 2713 r->ti_vlan_tag = 0; 2714 r->ti_tcp_udp_cksum = 0; 2715 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2716 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2717 r->ti_idx = i; 2718 } 2719 2720 #ifndef TI_SF_BUF_JUMBO 2721 static void 2722 ti_discard_jumbo(struct ti_softc *sc, int i) 2723 { 2724 2725 struct ti_rx_desc *r; 2726 2727 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2728 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2729 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2730 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2731 r->ti_vlan_tag = 0; 2732 r->ti_tcp_udp_cksum = 0; 2733 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2734 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2735 r->ti_idx = i; 2736 } 2737 #endif 2738 2739 /* 2740 * Frame reception handling. This is called if there's a frame 2741 * on the receive return list. 2742 * 2743 * Note: we have to be able to handle three possibilities here: 2744 * 1) the frame is from the mini receive ring (can only happen) 2745 * on Tigon 2 boards) 2746 * 2) the frame is from the jumbo recieve ring 2747 * 3) the frame is from the standard receive ring 2748 */ 2749 2750 static void 2751 ti_rxeof(struct ti_softc *sc) 2752 { 2753 struct ifnet *ifp; 2754 #ifdef TI_SF_BUF_JUMBO 2755 bus_dmamap_t map; 2756 #endif 2757 struct ti_cmd_desc cmd; 2758 int jumbocnt, minicnt, stdcnt, ti_len; 2759 2760 TI_LOCK_ASSERT(sc); 2761 2762 ifp = sc->ti_ifp; 2763 2764 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2765 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2766 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2767 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2768 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2769 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2770 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2771 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2772 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2773 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2774 2775 jumbocnt = minicnt = stdcnt = 0; 2776 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2777 struct ti_rx_desc *cur_rx; 2778 uint32_t rxidx; 2779 struct mbuf *m = NULL; 2780 uint16_t vlan_tag = 0; 2781 int have_tag = 0; 2782 2783 cur_rx = 2784 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2785 rxidx = cur_rx->ti_idx; 2786 ti_len = cur_rx->ti_len; 2787 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2788 2789 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2790 have_tag = 1; 2791 vlan_tag = cur_rx->ti_vlan_tag; 2792 } 2793 2794 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2795 jumbocnt++; 2796 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2797 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2798 #ifndef TI_SF_BUF_JUMBO 2799 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2800 ifp->if_ierrors++; 2801 ti_discard_jumbo(sc, rxidx); 2802 continue; 2803 } 2804 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2805 ifp->if_iqdrops++; 2806 ti_discard_jumbo(sc, rxidx); 2807 continue; 2808 } 2809 m->m_len = ti_len; 2810 #else /* !TI_SF_BUF_JUMBO */ 2811 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2812 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2813 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2814 BUS_DMASYNC_POSTREAD); 2815 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2816 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2817 ifp->if_ierrors++; 2818 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2819 continue; 2820 } 2821 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2822 ifp->if_iqdrops++; 2823 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2824 continue; 2825 } 2826 #ifdef TI_JUMBO_HDRSPLIT 2827 if (sc->ti_hdrsplit) 2828 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2829 ti_len, rxidx); 2830 else 2831 #endif /* TI_JUMBO_HDRSPLIT */ 2832 m_adj(m, ti_len - m->m_pkthdr.len); 2833 #endif /* TI_SF_BUF_JUMBO */ 2834 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2835 minicnt++; 2836 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2837 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2838 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2839 ifp->if_ierrors++; 2840 ti_discard_mini(sc, rxidx); 2841 continue; 2842 } 2843 if (ti_newbuf_mini(sc, rxidx) != 0) { 2844 ifp->if_iqdrops++; 2845 ti_discard_mini(sc, rxidx); 2846 continue; 2847 } 2848 m->m_len = ti_len; 2849 } else { 2850 stdcnt++; 2851 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2852 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2853 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2854 ifp->if_ierrors++; 2855 ti_discard_std(sc, rxidx); 2856 continue; 2857 } 2858 if (ti_newbuf_std(sc, rxidx) != 0) { 2859 ifp->if_iqdrops++; 2860 ti_discard_std(sc, rxidx); 2861 continue; 2862 } 2863 m->m_len = ti_len; 2864 } 2865 2866 m->m_pkthdr.len = ti_len; 2867 ifp->if_ipackets++; 2868 m->m_pkthdr.rcvif = ifp; 2869 2870 if (ifp->if_capenable & IFCAP_RXCSUM) { 2871 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2872 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2873 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2874 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2875 } 2876 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2877 m->m_pkthdr.csum_data = 2878 cur_rx->ti_tcp_udp_cksum; 2879 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2880 } 2881 } 2882 2883 /* 2884 * If we received a packet with a vlan tag, 2885 * tag it before passing the packet upward. 2886 */ 2887 if (have_tag) { 2888 m->m_pkthdr.ether_vtag = vlan_tag; 2889 m->m_flags |= M_VLANTAG; 2890 } 2891 TI_UNLOCK(sc); 2892 (*ifp->if_input)(ifp, m); 2893 TI_LOCK(sc); 2894 } 2895 2896 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2897 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2898 /* Only necessary on the Tigon 1. */ 2899 if (sc->ti_hwrev == TI_HWREV_TIGON) 2900 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2901 sc->ti_rx_saved_considx); 2902 2903 if (stdcnt > 0) { 2904 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2905 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2906 TI_UPDATE_STDPROD(sc, sc->ti_std); 2907 } 2908 if (minicnt > 0) { 2909 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2910 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2911 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2912 } 2913 if (jumbocnt > 0) { 2914 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2915 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2916 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2917 } 2918 } 2919 2920 static void 2921 ti_txeof(struct ti_softc *sc) 2922 { 2923 struct ti_txdesc *txd; 2924 struct ti_tx_desc txdesc; 2925 struct ti_tx_desc *cur_tx = NULL; 2926 struct ifnet *ifp; 2927 int idx; 2928 2929 ifp = sc->ti_ifp; 2930 2931 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2932 if (txd == NULL) 2933 return; 2934 2935 if (sc->ti_rdata.ti_tx_ring != NULL) 2936 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2937 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2938 /* 2939 * Go through our tx ring and free mbufs for those 2940 * frames that have been sent. 2941 */ 2942 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2943 TI_INC(idx, TI_TX_RING_CNT)) { 2944 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2945 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2946 sizeof(txdesc), &txdesc); 2947 cur_tx = &txdesc; 2948 } else 2949 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2950 sc->ti_txcnt--; 2951 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2952 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2953 continue; 2954 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2955 BUS_DMASYNC_POSTWRITE); 2956 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2957 2958 ifp->if_opackets++; 2959 m_freem(txd->tx_m); 2960 txd->tx_m = NULL; 2961 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2962 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2963 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2964 } 2965 sc->ti_tx_saved_considx = idx; 2966 if (sc->ti_txcnt == 0) 2967 sc->ti_timer = 0; 2968 } 2969 2970 static void 2971 ti_intr(void *xsc) 2972 { 2973 struct ti_softc *sc; 2974 struct ifnet *ifp; 2975 2976 sc = xsc; 2977 TI_LOCK(sc); 2978 ifp = sc->ti_ifp; 2979 2980 /* Make sure this is really our interrupt. */ 2981 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2982 TI_UNLOCK(sc); 2983 return; 2984 } 2985 2986 /* Ack interrupt and stop others from occuring. */ 2987 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2988 2989 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2990 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2991 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2992 /* Check RX return ring producer/consumer */ 2993 ti_rxeof(sc); 2994 2995 /* Check TX ring producer/consumer */ 2996 ti_txeof(sc); 2997 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2998 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 2999 } 3000 3001 ti_handle_events(sc); 3002 3003 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3004 /* Re-enable interrupts. */ 3005 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3006 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3007 ti_start_locked(ifp); 3008 } 3009 3010 TI_UNLOCK(sc); 3011 } 3012 3013 static void 3014 ti_stats_update(struct ti_softc *sc) 3015 { 3016 struct ifnet *ifp; 3017 struct ti_stats *s; 3018 3019 ifp = sc->ti_ifp; 3020 3021 if (sc->ti_stat_ticks == 0) 3022 return; 3023 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3024 BUS_DMASYNC_POSTREAD); 3025 3026 s = &sc->ti_rdata.ti_info->ti_stats; 3027 ifp->if_collisions += (s->dot3StatsSingleCollisionFrames + 3028 s->dot3StatsMultipleCollisionFrames + 3029 s->dot3StatsExcessiveCollisions + s->dot3StatsLateCollisions) - 3030 ifp->if_collisions; 3031 3032 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3033 BUS_DMASYNC_PREREAD); 3034 } 3035 3036 /* 3037 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3038 * pointers to descriptors. 3039 */ 3040 static int 3041 ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3042 { 3043 struct ti_txdesc *txd; 3044 struct ti_tx_desc *f; 3045 struct ti_tx_desc txdesc; 3046 struct mbuf *m; 3047 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3048 uint16_t csum_flags; 3049 int error, frag, i, nseg; 3050 3051 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3052 return (ENOBUFS); 3053 3054 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3055 *m_head, txsegs, &nseg, 0); 3056 if (error == EFBIG) { 3057 m = m_defrag(*m_head, M_DONTWAIT); 3058 if (m == NULL) { 3059 m_freem(*m_head); 3060 *m_head = NULL; 3061 return (ENOMEM); 3062 } 3063 *m_head = m; 3064 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3065 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3066 if (error) { 3067 m_freem(*m_head); 3068 *m_head = NULL; 3069 return (error); 3070 } 3071 } else if (error != 0) 3072 return (error); 3073 if (nseg == 0) { 3074 m_freem(*m_head); 3075 *m_head = NULL; 3076 return (EIO); 3077 } 3078 3079 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3080 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3081 return (ENOBUFS); 3082 } 3083 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3084 BUS_DMASYNC_PREWRITE); 3085 3086 m = *m_head; 3087 csum_flags = 0; 3088 if (m->m_pkthdr.csum_flags) { 3089 if (m->m_pkthdr.csum_flags & CSUM_IP) 3090 csum_flags |= TI_BDFLAG_IP_CKSUM; 3091 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3092 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3093 if (m->m_flags & M_LASTFRAG) 3094 csum_flags |= TI_BDFLAG_IP_FRAG_END; 3095 else if (m->m_flags & M_FRAG) 3096 csum_flags |= TI_BDFLAG_IP_FRAG; 3097 } 3098 3099 frag = sc->ti_tx_saved_prodidx; 3100 for (i = 0; i < nseg; i++) { 3101 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3102 bzero(&txdesc, sizeof(txdesc)); 3103 f = &txdesc; 3104 } else 3105 f = &sc->ti_rdata.ti_tx_ring[frag]; 3106 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3107 f->ti_len = txsegs[i].ds_len; 3108 f->ti_flags = csum_flags; 3109 if (m->m_flags & M_VLANTAG) { 3110 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3111 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3112 } else { 3113 f->ti_vlan_tag = 0; 3114 } 3115 3116 if (sc->ti_hwrev == TI_HWREV_TIGON) 3117 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3118 sizeof(txdesc), sizeof(txdesc), &txdesc); 3119 TI_INC(frag, TI_TX_RING_CNT); 3120 } 3121 3122 sc->ti_tx_saved_prodidx = frag; 3123 /* set TI_BDFLAG_END on the last descriptor */ 3124 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3125 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3126 txdesc.ti_flags |= TI_BDFLAG_END; 3127 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3128 sizeof(txdesc), &txdesc); 3129 } else 3130 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3131 3132 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3133 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3134 txd->tx_m = m; 3135 sc->ti_txcnt += nseg; 3136 3137 return (0); 3138 } 3139 3140 static void 3141 ti_start(struct ifnet *ifp) 3142 { 3143 struct ti_softc *sc; 3144 3145 sc = ifp->if_softc; 3146 TI_LOCK(sc); 3147 ti_start_locked(ifp); 3148 TI_UNLOCK(sc); 3149 } 3150 3151 /* 3152 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3153 * to the mbuf data regions directly in the transmit descriptors. 3154 */ 3155 static void 3156 ti_start_locked(struct ifnet *ifp) 3157 { 3158 struct ti_softc *sc; 3159 struct mbuf *m_head = NULL; 3160 int enq = 0; 3161 3162 sc = ifp->if_softc; 3163 3164 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3165 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3166 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3167 if (m_head == NULL) 3168 break; 3169 3170 /* 3171 * XXX 3172 * safety overkill. If this is a fragmented packet chain 3173 * with delayed TCP/UDP checksums, then only encapsulate 3174 * it if we have enough descriptors to handle the entire 3175 * chain at once. 3176 * (paranoia -- may not actually be needed) 3177 */ 3178 if (m_head->m_flags & M_FIRSTFRAG && 3179 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3180 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3181 m_head->m_pkthdr.csum_data + 16) { 3182 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3183 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3184 break; 3185 } 3186 } 3187 3188 /* 3189 * Pack the data into the transmit ring. If we 3190 * don't have room, set the OACTIVE flag and wait 3191 * for the NIC to drain the ring. 3192 */ 3193 if (ti_encap(sc, &m_head)) { 3194 if (m_head == NULL) 3195 break; 3196 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3197 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3198 break; 3199 } 3200 3201 enq++; 3202 /* 3203 * If there's a BPF listener, bounce a copy of this frame 3204 * to him. 3205 */ 3206 ETHER_BPF_MTAP(ifp, m_head); 3207 } 3208 3209 if (enq > 0) { 3210 if (sc->ti_rdata.ti_tx_ring != NULL) 3211 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3212 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3213 /* Transmit */ 3214 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3215 3216 /* 3217 * Set a timeout in case the chip goes out to lunch. 3218 */ 3219 sc->ti_timer = 5; 3220 } 3221 } 3222 3223 static void 3224 ti_init(void *xsc) 3225 { 3226 struct ti_softc *sc; 3227 3228 sc = xsc; 3229 TI_LOCK(sc); 3230 ti_init_locked(sc); 3231 TI_UNLOCK(sc); 3232 } 3233 3234 static void 3235 ti_init_locked(void *xsc) 3236 { 3237 struct ti_softc *sc = xsc; 3238 3239 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3240 return; 3241 3242 /* Cancel pending I/O and flush buffers. */ 3243 ti_stop(sc); 3244 3245 /* Init the gen info block, ring control blocks and firmware. */ 3246 if (ti_gibinit(sc)) { 3247 device_printf(sc->ti_dev, "initialization failure\n"); 3248 return; 3249 } 3250 } 3251 3252 static void ti_init2(struct ti_softc *sc) 3253 { 3254 struct ti_cmd_desc cmd; 3255 struct ifnet *ifp; 3256 uint8_t *ea; 3257 struct ifmedia *ifm; 3258 int tmp; 3259 3260 TI_LOCK_ASSERT(sc); 3261 3262 ifp = sc->ti_ifp; 3263 3264 /* Specify MTU and interface index. */ 3265 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3266 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3267 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3268 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3269 3270 /* Load our MAC address. */ 3271 ea = IF_LLADDR(sc->ti_ifp); 3272 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3273 CSR_WRITE_4(sc, TI_GCR_PAR1, 3274 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3275 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3276 3277 /* Enable or disable promiscuous mode as needed. */ 3278 if (ifp->if_flags & IFF_PROMISC) { 3279 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3280 } else { 3281 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3282 } 3283 3284 /* Program multicast filter. */ 3285 ti_setmulti(sc); 3286 3287 /* 3288 * If this is a Tigon 1, we should tell the 3289 * firmware to use software packet filtering. 3290 */ 3291 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3292 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3293 } 3294 3295 /* Init RX ring. */ 3296 if (ti_init_rx_ring_std(sc) != 0) { 3297 /* XXX */ 3298 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3299 return; 3300 } 3301 3302 /* Init jumbo RX ring. */ 3303 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3304 if (ti_init_rx_ring_jumbo(sc) != 0) { 3305 /* XXX */ 3306 device_printf(sc->ti_dev, 3307 "no memory for jumbo Rx buffers.\n"); 3308 return; 3309 } 3310 } 3311 3312 /* 3313 * If this is a Tigon 2, we can also configure the 3314 * mini ring. 3315 */ 3316 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3317 if (ti_init_rx_ring_mini(sc) != 0) { 3318 /* XXX */ 3319 device_printf(sc->ti_dev, 3320 "no memory for mini Rx buffers.\n"); 3321 return; 3322 } 3323 } 3324 3325 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3326 sc->ti_rx_saved_considx = 0; 3327 3328 /* Init TX ring. */ 3329 ti_init_tx_ring(sc); 3330 3331 /* Tell firmware we're alive. */ 3332 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3333 3334 /* Enable host interrupts. */ 3335 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3336 3337 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3338 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3339 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3340 3341 /* 3342 * Make sure to set media properly. We have to do this 3343 * here since we have to issue commands in order to set 3344 * the link negotiation and we can't issue commands until 3345 * the firmware is running. 3346 */ 3347 ifm = &sc->ifmedia; 3348 tmp = ifm->ifm_media; 3349 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3350 ti_ifmedia_upd_locked(sc); 3351 ifm->ifm_media = tmp; 3352 } 3353 3354 /* 3355 * Set media options. 3356 */ 3357 static int 3358 ti_ifmedia_upd(struct ifnet *ifp) 3359 { 3360 struct ti_softc *sc; 3361 int error; 3362 3363 sc = ifp->if_softc; 3364 TI_LOCK(sc); 3365 error = ti_ifmedia_upd(ifp); 3366 TI_UNLOCK(sc); 3367 3368 return (error); 3369 } 3370 3371 static int 3372 ti_ifmedia_upd_locked(struct ti_softc *sc) 3373 { 3374 struct ifmedia *ifm; 3375 struct ti_cmd_desc cmd; 3376 uint32_t flowctl; 3377 3378 ifm = &sc->ifmedia; 3379 3380 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3381 return (EINVAL); 3382 3383 flowctl = 0; 3384 3385 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3386 case IFM_AUTO: 3387 /* 3388 * Transmit flow control doesn't work on the Tigon 1. 3389 */ 3390 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3391 3392 /* 3393 * Transmit flow control can also cause problems on the 3394 * Tigon 2, apparantly with both the copper and fiber 3395 * boards. The symptom is that the interface will just 3396 * hang. This was reproduced with Alteon 180 switches. 3397 */ 3398 #if 0 3399 if (sc->ti_hwrev != TI_HWREV_TIGON) 3400 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3401 #endif 3402 3403 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3404 TI_GLNK_FULL_DUPLEX| flowctl | 3405 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3406 3407 flowctl = TI_LNK_RX_FLOWCTL_Y; 3408 #if 0 3409 if (sc->ti_hwrev != TI_HWREV_TIGON) 3410 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3411 #endif 3412 3413 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3414 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3415 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3416 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3417 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3418 break; 3419 case IFM_1000_SX: 3420 case IFM_1000_T: 3421 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3422 #if 0 3423 if (sc->ti_hwrev != TI_HWREV_TIGON) 3424 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3425 #endif 3426 3427 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3428 flowctl |TI_GLNK_ENB); 3429 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3430 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3431 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3432 } 3433 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3434 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3435 break; 3436 case IFM_100_FX: 3437 case IFM_10_FL: 3438 case IFM_100_TX: 3439 case IFM_10_T: 3440 flowctl = TI_LNK_RX_FLOWCTL_Y; 3441 #if 0 3442 if (sc->ti_hwrev != TI_HWREV_TIGON) 3443 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3444 #endif 3445 3446 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3447 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3448 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3449 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3450 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3451 } else { 3452 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3453 } 3454 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3455 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3456 } else { 3457 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3458 } 3459 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3460 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3461 break; 3462 } 3463 3464 return (0); 3465 } 3466 3467 /* 3468 * Report current media status. 3469 */ 3470 static void 3471 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3472 { 3473 struct ti_softc *sc; 3474 uint32_t media = 0; 3475 3476 sc = ifp->if_softc; 3477 3478 TI_LOCK(sc); 3479 3480 ifmr->ifm_status = IFM_AVALID; 3481 ifmr->ifm_active = IFM_ETHER; 3482 3483 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3484 TI_UNLOCK(sc); 3485 return; 3486 } 3487 3488 ifmr->ifm_status |= IFM_ACTIVE; 3489 3490 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3491 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3492 if (sc->ti_copper) 3493 ifmr->ifm_active |= IFM_1000_T; 3494 else 3495 ifmr->ifm_active |= IFM_1000_SX; 3496 if (media & TI_GLNK_FULL_DUPLEX) 3497 ifmr->ifm_active |= IFM_FDX; 3498 else 3499 ifmr->ifm_active |= IFM_HDX; 3500 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3501 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3502 if (sc->ti_copper) { 3503 if (media & TI_LNK_100MB) 3504 ifmr->ifm_active |= IFM_100_TX; 3505 if (media & TI_LNK_10MB) 3506 ifmr->ifm_active |= IFM_10_T; 3507 } else { 3508 if (media & TI_LNK_100MB) 3509 ifmr->ifm_active |= IFM_100_FX; 3510 if (media & TI_LNK_10MB) 3511 ifmr->ifm_active |= IFM_10_FL; 3512 } 3513 if (media & TI_LNK_FULL_DUPLEX) 3514 ifmr->ifm_active |= IFM_FDX; 3515 if (media & TI_LNK_HALF_DUPLEX) 3516 ifmr->ifm_active |= IFM_HDX; 3517 } 3518 TI_UNLOCK(sc); 3519 } 3520 3521 static int 3522 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3523 { 3524 struct ti_softc *sc = ifp->if_softc; 3525 struct ifreq *ifr = (struct ifreq *) data; 3526 struct ti_cmd_desc cmd; 3527 int mask, error = 0; 3528 3529 switch (command) { 3530 case SIOCSIFMTU: 3531 TI_LOCK(sc); 3532 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3533 error = EINVAL; 3534 else { 3535 ifp->if_mtu = ifr->ifr_mtu; 3536 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3537 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3538 ti_init_locked(sc); 3539 } 3540 } 3541 TI_UNLOCK(sc); 3542 break; 3543 case SIOCSIFFLAGS: 3544 TI_LOCK(sc); 3545 if (ifp->if_flags & IFF_UP) { 3546 /* 3547 * If only the state of the PROMISC flag changed, 3548 * then just use the 'set promisc mode' command 3549 * instead of reinitializing the entire NIC. Doing 3550 * a full re-init means reloading the firmware and 3551 * waiting for it to start up, which may take a 3552 * second or two. 3553 */ 3554 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3555 ifp->if_flags & IFF_PROMISC && 3556 !(sc->ti_if_flags & IFF_PROMISC)) { 3557 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3558 TI_CMD_CODE_PROMISC_ENB, 0); 3559 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3560 !(ifp->if_flags & IFF_PROMISC) && 3561 sc->ti_if_flags & IFF_PROMISC) { 3562 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3563 TI_CMD_CODE_PROMISC_DIS, 0); 3564 } else 3565 ti_init_locked(sc); 3566 } else { 3567 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3568 ti_stop(sc); 3569 } 3570 } 3571 sc->ti_if_flags = ifp->if_flags; 3572 TI_UNLOCK(sc); 3573 break; 3574 case SIOCADDMULTI: 3575 case SIOCDELMULTI: 3576 TI_LOCK(sc); 3577 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3578 ti_setmulti(sc); 3579 TI_UNLOCK(sc); 3580 break; 3581 case SIOCSIFMEDIA: 3582 case SIOCGIFMEDIA: 3583 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3584 break; 3585 case SIOCSIFCAP: 3586 TI_LOCK(sc); 3587 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3588 if ((mask & IFCAP_TXCSUM) != 0 && 3589 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3590 ifp->if_capenable ^= IFCAP_TXCSUM; 3591 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3592 ifp->if_hwassist |= TI_CSUM_FEATURES; 3593 else 3594 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3595 } 3596 if ((mask & IFCAP_RXCSUM) != 0 && 3597 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3598 ifp->if_capenable ^= IFCAP_RXCSUM; 3599 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3600 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3601 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3602 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3603 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3604 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3605 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3606 IFCAP_VLAN_HWTAGGING)) != 0) { 3607 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3608 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3609 ti_init_locked(sc); 3610 } 3611 } 3612 TI_UNLOCK(sc); 3613 VLAN_CAPABILITIES(ifp); 3614 break; 3615 default: 3616 error = ether_ioctl(ifp, command, data); 3617 break; 3618 } 3619 3620 return (error); 3621 } 3622 3623 static int 3624 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3625 { 3626 struct ti_softc *sc; 3627 3628 sc = dev->si_drv1; 3629 if (sc == NULL) 3630 return (ENODEV); 3631 3632 TI_LOCK(sc); 3633 sc->ti_flags |= TI_FLAG_DEBUGING; 3634 TI_UNLOCK(sc); 3635 3636 return (0); 3637 } 3638 3639 static int 3640 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3641 { 3642 struct ti_softc *sc; 3643 3644 sc = dev->si_drv1; 3645 if (sc == NULL) 3646 return (ENODEV); 3647 3648 TI_LOCK(sc); 3649 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3650 TI_UNLOCK(sc); 3651 3652 return (0); 3653 } 3654 3655 /* 3656 * This ioctl routine goes along with the Tigon character device. 3657 */ 3658 static int 3659 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3660 struct thread *td) 3661 { 3662 struct ti_softc *sc; 3663 int error; 3664 3665 sc = dev->si_drv1; 3666 if (sc == NULL) 3667 return (ENODEV); 3668 3669 error = 0; 3670 3671 switch (cmd) { 3672 case TIIOCGETSTATS: 3673 { 3674 struct ti_stats *outstats; 3675 3676 outstats = (struct ti_stats *)addr; 3677 3678 TI_LOCK(sc); 3679 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3680 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3681 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3682 sizeof(struct ti_stats)); 3683 TI_UNLOCK(sc); 3684 break; 3685 } 3686 case TIIOCGETPARAMS: 3687 { 3688 struct ti_params *params; 3689 3690 params = (struct ti_params *)addr; 3691 3692 TI_LOCK(sc); 3693 params->ti_stat_ticks = sc->ti_stat_ticks; 3694 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3695 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3696 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3697 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3698 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3699 params->param_mask = TI_PARAM_ALL; 3700 TI_UNLOCK(sc); 3701 break; 3702 } 3703 case TIIOCSETPARAMS: 3704 { 3705 struct ti_params *params; 3706 3707 params = (struct ti_params *)addr; 3708 3709 TI_LOCK(sc); 3710 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3711 sc->ti_stat_ticks = params->ti_stat_ticks; 3712 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3713 } 3714 3715 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3716 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3717 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3718 sc->ti_rx_coal_ticks); 3719 } 3720 3721 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3722 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3723 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3724 sc->ti_tx_coal_ticks); 3725 } 3726 3727 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3728 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3729 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3730 sc->ti_rx_max_coal_bds); 3731 } 3732 3733 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3734 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3735 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3736 sc->ti_tx_max_coal_bds); 3737 } 3738 3739 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3740 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3741 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3742 sc->ti_tx_buf_ratio); 3743 } 3744 TI_UNLOCK(sc); 3745 break; 3746 } 3747 case TIIOCSETTRACE: { 3748 ti_trace_type trace_type; 3749 3750 trace_type = *(ti_trace_type *)addr; 3751 3752 /* 3753 * Set tracing to whatever the user asked for. Setting 3754 * this register to 0 should have the effect of disabling 3755 * tracing. 3756 */ 3757 TI_LOCK(sc); 3758 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3759 TI_UNLOCK(sc); 3760 break; 3761 } 3762 case TIIOCGETTRACE: { 3763 struct ti_trace_buf *trace_buf; 3764 uint32_t trace_start, cur_trace_ptr, trace_len; 3765 3766 trace_buf = (struct ti_trace_buf *)addr; 3767 3768 TI_LOCK(sc); 3769 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3770 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3771 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3772 #if 0 3773 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3774 "trace_len = %d\n", trace_start, 3775 cur_trace_ptr, trace_len); 3776 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3777 trace_buf->buf_len); 3778 #endif 3779 error = ti_copy_mem(sc, trace_start, min(trace_len, 3780 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3781 if (error == 0) { 3782 trace_buf->fill_len = min(trace_len, 3783 trace_buf->buf_len); 3784 if (cur_trace_ptr < trace_start) 3785 trace_buf->cur_trace_ptr = 3786 trace_start - cur_trace_ptr; 3787 else 3788 trace_buf->cur_trace_ptr = 3789 cur_trace_ptr - trace_start; 3790 } else 3791 trace_buf->fill_len = 0; 3792 TI_UNLOCK(sc); 3793 break; 3794 } 3795 3796 /* 3797 * For debugging, five ioctls are needed: 3798 * ALT_ATTACH 3799 * ALT_READ_TG_REG 3800 * ALT_WRITE_TG_REG 3801 * ALT_READ_TG_MEM 3802 * ALT_WRITE_TG_MEM 3803 */ 3804 case ALT_ATTACH: 3805 /* 3806 * From what I can tell, Alteon's Solaris Tigon driver 3807 * only has one character device, so you have to attach 3808 * to the Tigon board you're interested in. This seems 3809 * like a not-so-good way to do things, since unless you 3810 * subsequently specify the unit number of the device 3811 * you're interested in every ioctl, you'll only be 3812 * able to debug one board at a time. 3813 */ 3814 break; 3815 case ALT_READ_TG_MEM: 3816 case ALT_WRITE_TG_MEM: 3817 { 3818 struct tg_mem *mem_param; 3819 uint32_t sram_end, scratch_end; 3820 3821 mem_param = (struct tg_mem *)addr; 3822 3823 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3824 sram_end = TI_END_SRAM_I; 3825 scratch_end = TI_END_SCRATCH_I; 3826 } else { 3827 sram_end = TI_END_SRAM_II; 3828 scratch_end = TI_END_SCRATCH_II; 3829 } 3830 3831 /* 3832 * For now, we'll only handle accessing regular SRAM, 3833 * nothing else. 3834 */ 3835 TI_LOCK(sc); 3836 if (mem_param->tgAddr >= TI_BEG_SRAM && 3837 mem_param->tgAddr + mem_param->len <= sram_end) { 3838 /* 3839 * In this instance, we always copy to/from user 3840 * space, so the user space argument is set to 1. 3841 */ 3842 error = ti_copy_mem(sc, mem_param->tgAddr, 3843 mem_param->len, mem_param->userAddr, 1, 3844 cmd == ALT_READ_TG_MEM ? 1 : 0); 3845 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3846 mem_param->tgAddr <= scratch_end) { 3847 error = ti_copy_scratch(sc, mem_param->tgAddr, 3848 mem_param->len, mem_param->userAddr, 1, 3849 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3850 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3851 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3852 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3853 if_printf(sc->ti_ifp, 3854 "invalid memory range for Tigon I\n"); 3855 error = EINVAL; 3856 break; 3857 } 3858 error = ti_copy_scratch(sc, mem_param->tgAddr - 3859 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3860 mem_param->userAddr, 1, 3861 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3862 } else { 3863 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3864 "out of supported range\n", 3865 mem_param->tgAddr, mem_param->len); 3866 error = EINVAL; 3867 } 3868 TI_UNLOCK(sc); 3869 break; 3870 } 3871 case ALT_READ_TG_REG: 3872 case ALT_WRITE_TG_REG: 3873 { 3874 struct tg_reg *regs; 3875 uint32_t tmpval; 3876 3877 regs = (struct tg_reg *)addr; 3878 3879 /* 3880 * Make sure the address in question isn't out of range. 3881 */ 3882 if (regs->addr > TI_REG_MAX) { 3883 error = EINVAL; 3884 break; 3885 } 3886 TI_LOCK(sc); 3887 if (cmd == ALT_READ_TG_REG) { 3888 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3889 regs->addr, &tmpval, 1); 3890 regs->data = ntohl(tmpval); 3891 #if 0 3892 if ((regs->addr == TI_CPU_STATE) 3893 || (regs->addr == TI_CPU_CTL_B)) { 3894 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3895 regs->addr, tmpval); 3896 } 3897 #endif 3898 } else { 3899 tmpval = htonl(regs->data); 3900 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3901 regs->addr, &tmpval, 1); 3902 } 3903 TI_UNLOCK(sc); 3904 break; 3905 } 3906 default: 3907 error = ENOTTY; 3908 break; 3909 } 3910 return (error); 3911 } 3912 3913 static void 3914 ti_watchdog(void *arg) 3915 { 3916 struct ti_softc *sc; 3917 struct ifnet *ifp; 3918 3919 sc = arg; 3920 TI_LOCK_ASSERT(sc); 3921 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3922 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3923 return; 3924 3925 /* 3926 * When we're debugging, the chip is often stopped for long periods 3927 * of time, and that would normally cause the watchdog timer to fire. 3928 * Since that impedes debugging, we don't want to do that. 3929 */ 3930 if (sc->ti_flags & TI_FLAG_DEBUGING) 3931 return; 3932 3933 ifp = sc->ti_ifp; 3934 if_printf(ifp, "watchdog timeout -- resetting\n"); 3935 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3936 ti_init_locked(sc); 3937 3938 ifp->if_oerrors++; 3939 } 3940 3941 /* 3942 * Stop the adapter and free any mbufs allocated to the 3943 * RX and TX lists. 3944 */ 3945 static void 3946 ti_stop(struct ti_softc *sc) 3947 { 3948 struct ifnet *ifp; 3949 struct ti_cmd_desc cmd; 3950 3951 TI_LOCK_ASSERT(sc); 3952 3953 ifp = sc->ti_ifp; 3954 3955 /* Disable host interrupts. */ 3956 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3957 /* 3958 * Tell firmware we're shutting down. 3959 */ 3960 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3961 3962 /* Halt and reinitialize. */ 3963 if (ti_chipinit(sc) == 0) { 3964 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3965 /* XXX ignore init errors. */ 3966 ti_chipinit(sc); 3967 } 3968 3969 /* Free the RX lists. */ 3970 ti_free_rx_ring_std(sc); 3971 3972 /* Free jumbo RX list. */ 3973 ti_free_rx_ring_jumbo(sc); 3974 3975 /* Free mini RX list. */ 3976 ti_free_rx_ring_mini(sc); 3977 3978 /* Free TX buffers. */ 3979 ti_free_tx_ring(sc); 3980 3981 sc->ti_ev_prodidx.ti_idx = 0; 3982 sc->ti_return_prodidx.ti_idx = 0; 3983 sc->ti_tx_considx.ti_idx = 0; 3984 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3985 3986 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3987 callout_stop(&sc->ti_watchdog); 3988 } 3989 3990 /* 3991 * Stop all chip I/O so that the kernel's probe routines don't 3992 * get confused by errant DMAs when rebooting. 3993 */ 3994 static int 3995 ti_shutdown(device_t dev) 3996 { 3997 struct ti_softc *sc; 3998 3999 sc = device_get_softc(dev); 4000 TI_LOCK(sc); 4001 ti_chipinit(sc); 4002 TI_UNLOCK(sc); 4003 4004 return (0); 4005 } 4006 4007 static void 4008 ti_sysctl_node(struct ti_softc *sc) 4009 { 4010 struct sysctl_ctx_list *ctx; 4011 struct sysctl_oid_list *child; 4012 char tname[32]; 4013 4014 ctx = device_get_sysctl_ctx(sc->ti_dev); 4015 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 4016 4017 /* Use DAC */ 4018 sc->ti_dac = 1; 4019 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 4020 device_get_unit(sc->ti_dev)); 4021 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 4022 4023 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 4024 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 4025 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4026 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4027 4028 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4029 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4030 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4031 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4032 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4033 &sc->ti_tx_buf_ratio, 0, 4034 "Ratio of NIC memory devoted to TX buffer"); 4035 4036 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4037 &sc->ti_stat_ticks, 0, 4038 "Number of clock ticks for statistics update interval"); 4039 4040 /* Pull in device tunables. */ 4041 sc->ti_rx_coal_ticks = 170; 4042 resource_int_value(device_get_name(sc->ti_dev), 4043 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4044 &sc->ti_rx_coal_ticks); 4045 sc->ti_rx_max_coal_bds = 64; 4046 resource_int_value(device_get_name(sc->ti_dev), 4047 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4048 &sc->ti_rx_max_coal_bds); 4049 4050 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4051 resource_int_value(device_get_name(sc->ti_dev), 4052 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4053 &sc->ti_tx_coal_ticks); 4054 sc->ti_tx_max_coal_bds = 32; 4055 resource_int_value(device_get_name(sc->ti_dev), 4056 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4057 &sc->ti_tx_max_coal_bds); 4058 sc->ti_tx_buf_ratio = 21; 4059 resource_int_value(device_get_name(sc->ti_dev), 4060 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4061 &sc->ti_tx_buf_ratio); 4062 4063 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4064 resource_int_value(device_get_name(sc->ti_dev), 4065 device_get_unit(sc->ti_dev), "stat_ticks", 4066 &sc->ti_stat_ticks); 4067 }
Cache object: 7224f472e1436cf2ea5e3e745c6cc8dd
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