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sys/dev/ti/if_tireg.h
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: releng/8.3/sys/dev/ti/if_tireg.h 229442 2012-01-03 23:45:44Z yongari $ 33 */ 34 35 /* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. 41 * The first group of registers are actually copies of the PCI 42 * configuration space registers. 43 */ 44 45 #define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46 #define TI_PCI_CMDSTAT 0x004 47 #define TI_PCI_CLASSCODE 0x008 48 #define TI_PCI_BIST 0x00C 49 #define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50 #define TI_PCI_SUBSYS 0x02C 51 #define TI_PCI_ROMBASE 0x030 52 #define TI_PCI_INT 0x03C 53 54 #ifndef PCIM_CMD_MWIEN 55 #define PCIM_CMD_MWIEN 0x0010 56 #endif 57 58 /* 59 * Alteon AceNIC PCI vendor/device ID. 60 */ 61 #define ALT_VENDORID 0x12AE 62 #define ALT_DEVICEID_ACENIC 0x0001 63 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 64 65 /* 66 * 3Com 3c985 PCI vendor/device ID. 67 */ 68 #define TC_VENDORID 0x10B7 69 #define TC_DEVICEID_3C985 0x0001 70 71 /* 72 * Netgear GA620 PCI vendor/device ID. 73 */ 74 #define NG_VENDORID 0x1385 75 #define NG_DEVICEID_GA620 0x620A 76 #define NG_DEVICEID_GA620T 0x630A 77 78 /* 79 * SGI device/vendor ID. 80 */ 81 #define SGI_VENDORID 0x10A9 82 #define SGI_DEVICEID_TIGON 0x0009 83 84 /* 85 * DEC vendor ID, Farallon device ID. Apparently, Farallon used 86 * the DEC vendor ID in their cards by mistake. 87 */ 88 #define DEC_VENDORID 0x1011 89 #define DEC_DEVICEID_FARALLON_PN9000SX 0x001a 90 91 /* 92 * Tigon configuration and control registers. 93 */ 94 #define TI_MISC_HOST_CTL 0x040 95 #define TI_MISC_LOCAL_CTL 0x044 96 #define TI_SEM_AB 0x048 /* Tigon 2 only */ 97 #define TI_MISC_CONF 0x050 /* Tigon 2 only */ 98 #define TI_TIMER_BITS 0x054 99 #define TI_TIMERREF 0x058 100 #define TI_PCI_STATE 0x05C 101 #define TI_MAIN_EVENT_A 0x060 102 #define TI_MAILBOX_EVENT_A 0x064 103 #define TI_WINBASE 0x068 104 #define TI_WINDATA 0x06C 105 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 106 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 107 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 108 #define TI_SERIAL 0x07C 109 110 /* 111 * Misc host control bits. 112 */ 113 #define TI_MHC_INTSTATE 0x00000001 114 #define TI_MHC_CLEARINT 0x00000002 115 #define TI_MHC_RESET 0x00000008 116 #define TI_MHC_BYTE_SWAP_ENB 0x00000010 117 #define TI_MHC_WORD_SWAP_ENB 0x00000020 118 #define TI_MHC_MASK_INTS 0x00000040 119 #define TI_MHC_CHIP_REV_MASK 0xF0000000 120 121 #define TI_MHC_BIGENDIAN_INIT \ 122 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 123 124 #define TI_MHC_LITTLEENDIAN_INIT \ 125 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 126 127 /* 128 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 129 * Rev 5 is also the Tigon 2, but is a broken version which was never 130 * used in any actual hardware, so we ignore it. 131 */ 132 #define TI_REV_TIGON_I 0x40000000 133 #define TI_REV_TIGON_II 0x60000000 134 135 /* 136 * Firmware revision that we want. 137 */ 138 #define TI_FIRMWARE_MAJOR 0xc 139 #define TI_FIRMWARE_MINOR 0x4 140 #define TI_FIRMWARE_FIX 0xb 141 142 /* 143 * Miscelaneous Local Control register. 144 */ 145 #define TI_MLC_EE_WRITE_ENB 0x00000010 146 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147 #define TI_MLC_LOCALADDR_21 0x00004000 148 #define TI_MLC_LOCALADDR_22 0x00008000 149 #define TI_MLC_SBUS_WRITEERR 0x00080000 150 #define TI_MLC_EE_CLK 0x00100000 151 #define TI_MLC_EE_TXEN 0x00200000 152 #define TI_MLC_EE_DOUT 0x00400000 153 #define TI_MLC_EE_DIN 0x00800000 154 155 /* Possible memory sizes. */ 156 #define TI_MLC_SRAM_BANK_DISA 0x00000000 157 #define TI_MLC_SRAM_BANK_1024K 0x00000100 158 #define TI_MLC_SRAM_BANK_512K 0x00000200 159 #define TI_MLC_SRAM_BANK_256K 0x00000300 160 161 /* 162 * Offset of MAC address inside EEPROM. 163 */ 164 #define TI_EE_MAC_OFFSET 0x8c 165 166 #define TI_DMA_ASSIST 0x11C 167 #define TI_CPU_STATE 0x140 168 #define TI_CPU_PROGRAM_COUNTER 0x144 169 #define TI_SRAM_ADDR 0x154 170 #define TI_SRAM_DATA 0x158 171 #define TI_GEN_0 0x180 172 #define TI_GEN_X 0x1FC 173 #define TI_MAC_TX_STATE 0x200 174 #define TI_MAC_RX_STATE 0x220 175 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 176 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 177 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 178 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 179 #define TI_GEN_B_0 0x280 /* Tigon 2 only */ 180 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 181 182 /* 183 * Misc config register. 184 */ 185 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 186 187 /* 188 * PCI state register. 189 */ 190 #define TI_PCISTATE_FORCE_RESET 0x00000001 191 #define TI_PCISTATE_PROVIDE_LEN 0x00000002 192 #define TI_PCISTATE_READ_MAXDMA 0x0000001C 193 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 194 #define TI_PCISTATE_MINDMA 0x0000FF00 195 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 196 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 197 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 198 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 199 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 200 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 201 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 202 #define TI_PCISTATE_READ_CMD 0x0F000000 203 #define TI_PCISTATE_WRITE_CMD 0xF0000000 204 205 #define TI_PCI_READMAX_4 0x04 206 #define TI_PCI_READMAX_16 0x08 207 #define TI_PCI_READMAX_32 0x0C 208 #define TI_PCI_READMAX_64 0x10 209 #define TI_PCI_READMAX_128 0x14 210 #define TI_PCI_READMAX_256 0x18 211 #define TI_PCI_READMAX_1024 0x1C 212 213 #define TI_PCI_WRITEMAX_4 0x20 214 #define TI_PCI_WRITEMAX_16 0x40 215 #define TI_PCI_WRITEMAX_32 0x60 216 #define TI_PCI_WRITEMAX_64 0x80 217 #define TI_PCI_WRITEMAX_128 0xA0 218 #define TI_PCI_WRITEMAX_256 0xC0 219 #define TI_PCI_WRITEMAX_1024 0xE0 220 221 #define TI_PCI_READ_CMD 0x06000000 222 #define TI_PCI_WRITE_CMD 0x70000000 223 224 /* 225 * DMA state register. 226 */ 227 #define TI_DMASTATE_ENABLE 0x00000001 228 #define TI_DMASTATE_PAUSE 0x00000002 229 230 /* 231 * CPU state register. 232 */ 233 #define TI_CPUSTATE_RESET 0x00000001 234 #define TI_CPUSTATE_STEP 0x00000002 235 #define TI_CPUSTATE_ROMFAIL 0x00000010 236 #define TI_CPUSTATE_HALT 0x00010000 237 /* 238 * MAC TX state register 239 */ 240 #define TI_TXSTATE_RESET 0x00000001 241 #define TI_TXSTATE_ENB 0x00000002 242 #define TI_TXSTATE_STOP 0x00000004 243 244 /* 245 * MAC RX state register 246 */ 247 #define TI_RXSTATE_RESET 0x00000001 248 #define TI_RXSTATE_ENB 0x00000002 249 #define TI_RXSTATE_STOP 0x00000004 250 251 /* 252 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 253 * split into 64 bit registers. Only the lower 32 bits of each mailbox 254 * are used. 255 */ 256 #define TI_MB_HOSTINTR_HI 0x500 257 #define TI_MB_HOSTINTR_LO 0x504 258 #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 259 #define TI_MB_CMDPROD_IDX_HI 0x508 260 #define TI_MB_CMDPROD_IDX_LO 0x50C 261 #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 262 #define TI_MB_SENDPROD_IDX_HI 0x510 263 #define TI_MB_SENDPROD_IDX_LO 0x514 264 #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 265 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 266 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 267 #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 268 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 269 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 270 #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 271 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 272 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 273 #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 274 #define TI_MB_RSVD 0x530 275 276 /* 277 * Tigon 2 general communication registers. These are 64 and 32 bit 278 * registers which are only valid after the firmware has been 279 * loaded and started. They actually exist in NIC memory but are 280 * mapped into the host memory via the shared memory region. 281 * 282 * The NIC internally maps these registers starting at address 0, 283 * so to determine the NIC address of any of these registers, we 284 * subtract 0x600 (the address of the first register). 285 */ 286 287 #define TI_GCR_BASE 0x600 288 #define TI_GCR_MACADDR 0x600 289 #define TI_GCR_PAR0 0x600 290 #define TI_GCR_PAR1 0x604 291 #define TI_GCR_GENINFO_HI 0x608 292 #define TI_GCR_GENINFO_LO 0x60C 293 #define TI_GCR_MCASTADDR 0x610 /* obsolete */ 294 #define TI_GCR_MAR0 0x610 /* obsolete */ 295 #define TI_GCR_MAR1 0x614 /* obsolete */ 296 #define TI_GCR_OPMODE 0x618 297 #define TI_GCR_DMA_READCFG 0x61C 298 #define TI_GCR_DMA_WRITECFG 0x620 299 #define TI_GCR_TX_BUFFER_RATIO 0x624 300 #define TI_GCR_EVENTCONS_IDX 0x628 301 #define TI_GCR_CMDCONS_IDX 0x62C 302 #define TI_GCR_TUNEPARMS 0x630 303 #define TI_GCR_RX_COAL_TICKS 0x630 304 #define TI_GCR_TX_COAL_TICKS 0x634 305 #define TI_GCR_STAT_TICKS 0x638 306 #define TI_GCR_TX_MAX_COAL_BD 0x63C 307 #define TI_GCR_RX_MAX_COAL_BD 0x640 308 #define TI_GCR_NIC_TRACING 0x644 309 #define TI_GCR_GLINK 0x648 310 #define TI_GCR_LINK 0x64C 311 #define TI_GCR_NICTRACE_PTR 0x650 312 #define TI_GCR_NICTRACE_START 0x654 313 #define TI_GCR_NICTRACE_LEN 0x658 314 #define TI_GCR_IFINDEX 0x65C 315 #define TI_GCR_IFMTU 0x660 316 #define TI_GCR_MASK_INTRS 0x664 317 #define TI_GCR_GLINK_STAT 0x668 318 #define TI_GCR_LINK_STAT 0x66C 319 #define TI_GCR_RXRETURNCONS_IDX 0x680 320 #define TI_GCR_CMDRING 0x700 321 322 #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE) 323 324 /* 325 * Local memory window. The local memory window is a 2K shared 326 * memory region which can be used to access the NIC's internal 327 * SRAM. The window can be mapped to a given 2K region using 328 * the TI_WINDOW_BASE register. 329 */ 330 #define TI_WINDOW 0x800 331 #define TI_WINLEN 0x800 332 333 #define TI_TICKS_PER_SEC 1000000 334 335 /* 336 * Operation mode register. 337 */ 338 #define TI_OPMODE_BYTESWAP_BD 0x00000002 339 #define TI_OPMODE_WORDSWAP_BD 0x00000004 340 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */ 341 #define TI_OPMODE_BYTESWAP_DATA 0x00000010 342 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040 343 #define TI_OPMODE_SBUS 0x00000100 344 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 345 #define TI_OPMODE_INCLUDE_CRC 0x00000400 346 #define TI_OPMODE_RX_BADFRAMES 0x00000800 347 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000 348 #define TI_OPMODE_NO_TX_INTRS 0x00002000 349 #define TI_OPMODE_NO_RX_INTRS 0x00004000 350 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ 351 #define TI_OPMODE_JUMBO_HDRSPLIT 0x00008000 352 353 /* 354 * DMA configuration thresholds. 355 */ 356 #define TI_DMA_STATE_THRESH_16W 0x00000100 357 #define TI_DMA_STATE_THRESH_8W 0x00000080 358 #define TI_DMA_STATE_THRESH_4W 0x00000040 359 #define TI_DMA_STATE_THRESH_2W 0x00000020 360 #define TI_DMA_STATE_THRESH_1W 0x00000010 361 362 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008 363 364 /* 365 * Gigabit link status bits. 366 */ 367 #define TI_GLNK_SENSE_NO_BEG 0x00002000 368 #define TI_GLNK_LOOPBACK 0x00004000 369 #define TI_GLNK_PREF 0x00008000 370 #define TI_GLNK_1000MB 0x00040000 371 #define TI_GLNK_FULL_DUPLEX 0x00080000 372 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 373 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000 374 #define TI_GLNK_AUTONEGENB 0x20000000 375 #define TI_GLNK_ENB 0x40000000 376 377 /* 378 * Link status bits. 379 */ 380 #define TI_LNK_LOOPBACK 0x00004000 381 #define TI_LNK_PREF 0x00008000 382 #define TI_LNK_10MB 0x00010000 383 #define TI_LNK_100MB 0x00020000 384 #define TI_LNK_1000MB 0x00040000 385 #define TI_LNK_FULL_DUPLEX 0x00080000 386 #define TI_LNK_HALF_DUPLEX 0x00100000 387 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 388 #define TI_LNK_RX_FLOWCTL_Y 0x00800000 389 #define TI_LNK_AUTONEGENB 0x20000000 390 #define TI_LNK_ENB 0x40000000 391 392 /* 393 * Ring size constants. 394 */ 395 #define TI_EVENT_RING_CNT 256 396 #define TI_CMD_RING_CNT 64 397 #define TI_STD_RX_RING_CNT 512 398 #define TI_JUMBO_RX_RING_CNT 256 399 #define TI_MINI_RX_RING_CNT 1024 400 #define TI_RETURN_RING_CNT 2048 401 402 #define TI_MAXTXSEGS 32 403 #define TI_RING_ALIGN 32 404 #define TI_JUMBO_RING_ALIGN 64 405 406 /* 407 * Possible TX ring sizes. 408 */ 409 #define TI_TX_RING_CNT_128 128 410 #define TI_TX_RING_BASE_128 0x3800 411 412 #define TI_TX_RING_CNT_256 256 413 #define TI_TX_RING_BASE_256 0x3000 414 415 #define TI_TX_RING_CNT_512 512 416 #define TI_TX_RING_BASE_512 0x2000 417 418 #define TI_TX_RING_CNT TI_TX_RING_CNT_512 419 #define TI_TX_RING_BASE TI_TX_RING_BASE_512 420 421 /* 422 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 423 * is limited to 2MB total, and in general I think most adapters have 424 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 425 * be safe we use the largest possible value (zeroing memory that 426 * isn't there doesn't hurt anything). 427 */ 428 #define TI_MEM_MAX 0x7FFFFF 429 430 /* 431 * Maximum register address on the Tigon. 432 */ 433 #define TI_REG_MAX 0x3fff 434 435 /* 436 * These values were taken from Alteon's tg.h. 437 */ 438 #define TI_BEG_SRAM 0x0 /* host thinks it's here */ 439 #define TI_BEG_SCRATCH 0xc00000 /* beg of scratch pad area */ 440 #define TI_END_SRAM_II 0x800000 /* end of SRAM, for 2 MB stuffed */ 441 #define TI_END_SCRATCH_II 0xc04000 /* end of scratch pad CPU A (16KB) */ 442 #define TI_END_SCRATCH_B 0xc02000 /* end of scratch pad CPU B (8KB) */ 443 #define TI_BEG_SCRATCH_B_DEBUG 0xd00000 /* beg of scratch pad for ioctl */ 444 #define TI_END_SCRATCH_B_DEBUG 0xd02000 /* end of scratch pad for ioctl */ 445 #define TI_SCRATCH_DEBUG_OFF 0x100000 /* offset for ioctl usage */ 446 #define TI_END_SRAM_I 0x200000 /* end of SRAM, for 2 MB stuffed */ 447 #define TI_END_SCRATCH_I 0xc00800 /* end of scratch pad area (2KB) */ 448 #define TI_BEG_PROM 0x40000000 /* beg of PROM, special access */ 449 #define TI_BEG_FLASH 0x80000000 /* beg of EEPROM, special access */ 450 #define TI_END_FLASH 0x80100000 /* end of EEPROM for 1 MB stuff */ 451 #define TI_BEG_SER_EEPROM 0xa0000000 /* beg of Serial EEPROM (fake out) */ 452 #define TI_END_SER_EEPROM 0xa0002000 /* end of Serial EEPROM (fake out) */ 453 #define TI_BEG_REGS 0xc0000000 /* beg of register area */ 454 #define TI_END_REGS 0xc0000400 /* end of register area */ 455 #define TI_END_WRITE_REGS 0xc0000180 /* can't write GPRs currently */ 456 #define TI_BEG_REGS2 0xc0000200 /* beg of second writeable reg area */ 457 /* the EEPROM is byte addressable in a pretty odd way */ 458 #define EEPROM_BYTE_LOC 0xff000000 459 460 /* 461 * From Alteon's tg.h. 462 */ 463 #define TI_PROCESSOR_A 0 464 #define TI_PROCESSOR_B 1 465 #define TI_CPU_A TG_PROCESSOR_A 466 #define TI_CPU_B TG_PROCESSOR_B 467 468 /* 469 * Following macro can be used to access to any of the CPU registers 470 * It will adjust the address appropriately. 471 * Parameters: 472 * reg - The register to access, e.g TI_CPU_CONTROL 473 * cpu - cpu, i.e PROCESSOR_A or PROCESSOR_B (or TI_CPU_A or TI_CPU_B) 474 */ 475 #define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100) 476 477 /* 478 * Even on the alpha, pci addresses are 32-bit quantities 479 */ 480 481 typedef struct { 482 uint32_t ti_addr_hi; 483 uint32_t ti_addr_lo; 484 } ti_hostaddr; 485 486 #define TI_HOSTADDR(x) x.ti_addr_lo 487 488 static __inline void 489 ti_hostaddr64(ti_hostaddr *x, bus_addr_t addr) 490 { 491 uint64_t baddr; 492 493 baddr = (uint64_t)addr; 494 x->ti_addr_lo = baddr & 0xffffffff; 495 x->ti_addr_hi = baddr >> 32; 496 } 497 498 /* 499 * Ring control block structure. The rules for the max_len field 500 * are as follows: 501 * 502 * For the send ring, max_len indicates the number of entries in the 503 * ring (128, 256 or 512). 504 * 505 * For the standard receive ring, max_len indicates the threshold 506 * used to decide when a frame should be put in the jumbo receive ring 507 * instead of the standard one. 508 * 509 * For the mini ring, max_len indicates the size of the buffers in the 510 * ring. This is the value used to decide when a frame is small enough 511 * to be placed in the mini ring. 512 * 513 * For the return receive ring, max_len indicates the number of entries 514 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 515 * 2048 for backwards compatibility). The value 1024 can only be used 516 * if the mini ring is disabled. 517 */ 518 struct ti_rcb { 519 ti_hostaddr ti_hostaddr; 520 #if BYTE_ORDER == BIG_ENDIAN 521 uint16_t ti_max_len; 522 uint16_t ti_flags; 523 #else 524 uint16_t ti_flags; 525 uint16_t ti_max_len; 526 #endif 527 uint32_t ti_unused; 528 }; 529 530 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 531 #define TI_RCB_FLAG_IP_CKSUM 0x00000002 532 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 533 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 534 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 535 #define TI_RCB_FLAG_HOST_RING 0x00000040 536 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 537 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 538 #define TI_RCB_FLAG_RING_DISABLED 0x00000200 539 540 struct ti_producer { 541 uint32_t ti_idx; 542 uint32_t ti_unused; 543 }; 544 545 /* 546 * Tigon general information block. This resides in host memory 547 * and contains the status counters, ring control blocks and 548 * producer pointers. 549 */ 550 551 struct ti_gib { 552 struct ti_stats ti_stats; 553 struct ti_rcb ti_ev_rcb; 554 struct ti_rcb ti_cmd_rcb; 555 struct ti_rcb ti_tx_rcb; 556 struct ti_rcb ti_std_rx_rcb; 557 struct ti_rcb ti_jumbo_rx_rcb; 558 struct ti_rcb ti_mini_rx_rcb; 559 struct ti_rcb ti_return_rcb; 560 ti_hostaddr ti_ev_prodidx_ptr; 561 ti_hostaddr ti_return_prodidx_ptr; 562 ti_hostaddr ti_tx_considx_ptr; 563 ti_hostaddr ti_refresh_stats_ptr; 564 }; 565 566 /* 567 * Buffer descriptor structures. There are basically three types 568 * of structures: normal receive descriptors, extended receive 569 * descriptors and transmit descriptors. The extended receive 570 * descriptors are optionally used only for the jumbo receive ring. 571 */ 572 573 struct ti_rx_desc { 574 ti_hostaddr ti_addr; 575 #if BYTE_ORDER == BIG_ENDIAN 576 uint16_t ti_idx; 577 uint16_t ti_len; 578 #else 579 uint16_t ti_len; 580 uint16_t ti_idx; 581 #endif 582 #if BYTE_ORDER == BIG_ENDIAN 583 uint16_t ti_type; 584 uint16_t ti_flags; 585 #else 586 uint16_t ti_flags; 587 uint16_t ti_type; 588 #endif 589 #if BYTE_ORDER == BIG_ENDIAN 590 uint16_t ti_ip_cksum; 591 uint16_t ti_tcp_udp_cksum; 592 #else 593 uint16_t ti_tcp_udp_cksum; 594 uint16_t ti_ip_cksum; 595 #endif 596 #if BYTE_ORDER == BIG_ENDIAN 597 uint16_t ti_error_flags; 598 uint16_t ti_vlan_tag; 599 #else 600 uint16_t ti_vlan_tag; 601 uint16_t ti_error_flags; 602 #endif 603 uint32_t ti_rsvd; 604 uint32_t ti_opaque; 605 }; 606 607 #define TI_STD_RX_RING_SZ (sizeof(struct ti_rx_desc) * TI_STD_RX_RING_CNT) 608 #define TI_MINI_RX_RING_SZ (sizeof(struct ti_rx_desc) * TI_MINI_RX_RING_CNT) 609 #define TI_RX_RETURN_RING_SZ (sizeof(struct ti_rx_desc) * TI_RETURN_RING_CNT) 610 611 struct ti_rx_desc_ext { 612 ti_hostaddr ti_addr1; 613 ti_hostaddr ti_addr2; 614 ti_hostaddr ti_addr3; 615 #if BYTE_ORDER == BIG_ENDIAN 616 uint16_t ti_len1; 617 uint16_t ti_len2; 618 #else 619 uint16_t ti_len2; 620 uint16_t ti_len1; 621 #endif 622 #if BYTE_ORDER == BIG_ENDIAN 623 uint16_t ti_len3; 624 uint16_t ti_rsvd0; 625 #else 626 uint16_t ti_rsvd0; 627 uint16_t ti_len3; 628 #endif 629 ti_hostaddr ti_addr0; 630 #if BYTE_ORDER == BIG_ENDIAN 631 uint16_t ti_idx; 632 uint16_t ti_len0; 633 #else 634 uint16_t ti_len0; 635 uint16_t ti_idx; 636 #endif 637 #if BYTE_ORDER == BIG_ENDIAN 638 uint16_t ti_type; 639 uint16_t ti_flags; 640 #else 641 uint16_t ti_flags; 642 uint16_t ti_type; 643 #endif 644 #if BYTE_ORDER == BIG_ENDIAN 645 uint16_t ti_ip_cksum; 646 uint16_t ti_tcp_udp_cksum; 647 #else 648 uint16_t ti_tcp_udp_cksum; 649 uint16_t ti_ip_cksum; 650 #endif 651 #if BYTE_ORDER == BIG_ENDIAN 652 uint16_t ti_error_flags; 653 uint16_t ti_vlan_tag; 654 #else 655 uint16_t ti_vlan_tag; 656 uint16_t ti_error_flags; 657 #endif 658 uint32_t ti_rsvd1; 659 uint32_t ti_opaque; 660 }; 661 662 #ifdef TI_SF_BUF_JUMBO 663 #define TI_JUMBO_RX_RING_SZ \ 664 (sizeof(struct ti_rx_desc_ext) * TI_JUMBO_RX_RING_CNT) 665 #else 666 #define TI_JUMBO_RX_RING_SZ \ 667 (sizeof(struct ti_rx_desc) * TI_JUMBO_RX_RING_CNT) 668 #endif 669 670 /* 671 * Transmit descriptors are, mercifully, very small. 672 */ 673 struct ti_tx_desc { 674 ti_hostaddr ti_addr; 675 #if BYTE_ORDER == BIG_ENDIAN 676 uint16_t ti_len; 677 uint16_t ti_flags; 678 #else 679 uint16_t ti_flags; 680 uint16_t ti_len; 681 #endif 682 #if BYTE_ORDER == BIG_ENDIAN 683 uint16_t ti_rsvd; 684 uint16_t ti_vlan_tag; 685 #else 686 uint16_t ti_vlan_tag; 687 uint16_t ti_rsvd; 688 #endif 689 }; 690 691 #define TI_TX_RING_SZ (sizeof(struct ti_tx_desc) * TI_TX_RING_CNT) 692 693 /* 694 * NOTE! On the Alpha, we have an alignment constraint. 695 * The first thing in the packet is a 14-byte Ethernet header. 696 * This means that the packet is misaligned. To compensate, 697 * we actually offset the data 2 bytes into the cluster. This 698 * aligns the packet after the Ethernet header at a 32-bit 699 * boundary. 700 */ 701 702 #define TI_FRAMELEN 1518 703 #define TI_JUMBO_FRAMELEN 9018 704 #define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 705 #define TI_PAGE_SIZE PAGE_SIZE 706 #define TI_MIN_FRAMELEN 60 707 708 /* 709 * Buffer descriptor error flags. 710 */ 711 #define TI_BDERR_CRC 0x0001 712 #define TI_BDERR_COLLDETECT 0x0002 713 #define TI_BDERR_LINKLOST 0x0004 714 #define TI_BDERR_DECODE 0x0008 715 #define TI_BDERR_ODD_NIBBLES 0x0010 716 #define TI_BDERR_MAC_ABRT 0x0020 717 #define TI_BDERR_RUNT 0x0040 718 #define TI_BDERR_TRUNC 0x0080 719 #define TI_BDERR_GIANT 0x0100 720 721 /* 722 * Buffer descriptor flags. 723 */ 724 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 725 #define TI_BDFLAG_IP_CKSUM 0x0002 726 #define TI_BDFLAG_END 0x0004 727 #define TI_BDFLAG_MORE 0x0008 728 #define TI_BDFLAG_JUMBO_RING 0x0010 729 #define TI_BDFLAG_UCAST_PKT 0x0020 730 #define TI_BDFLAG_MCAST_PKT 0x0040 731 #define TI_BDFLAG_BCAST_PKT 0x0060 732 #define TI_BDFLAG_IP_FRAG 0x0080 733 #define TI_BDFLAG_IP_FRAG_END 0x0100 734 #define TI_BDFLAG_VLAN_TAG 0x0200 735 #define TI_BDFLAG_ERROR 0x0400 736 #define TI_BDFLAG_COAL_NOW 0x0800 737 #define TI_BDFLAG_MINI_RING 0x1000 738 739 /* 740 * Descriptor type flags. I think these only have meaning for 741 * the Tigon 1. I had to extract them from the sample driver source 742 * since they aren't in the manual. 743 */ 744 #define TI_BDTYPE_TYPE_NULL 0x0000 745 #define TI_BDTYPE_SEND_BD 0x0001 746 #define TI_BDTYPE_RECV_BD 0x0002 747 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003 748 #define TI_BDTYPE_RECV_BD_LAST 0x0004 749 #define TI_BDTYPE_SEND_DATA 0x0005 750 #define TI_BDTYPE_SEND_DATA_LAST 0x0006 751 #define TI_BDTYPE_RECV_DATA 0x0007 752 #define TI_BDTYPE_RECV_DATA_LAST 0x000b 753 #define TI_BDTYPE_EVENT_RUPT 0x000c 754 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d 755 #define TI_BDTYPE_ODD_START 0x000e 756 #define TI_BDTYPE_UPDATE_STATS 0x000f 757 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 758 #define TI_BDTYPE_EVENT_PROD 0x0011 759 #define TI_BDTYPE_TX_CONS 0x0012 760 #define TI_BDTYPE_RX_PROD 0x0013 761 #define TI_BDTYPE_REFRESH_STATS 0x0014 762 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 763 #define TI_BDTYPE_SEND_DATA_COAL 0x0016 764 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 765 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 766 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 767 768 /* 769 * Tigon command structure. 770 */ 771 struct ti_cmd_desc { 772 uint32_t ti_cmdx; 773 }; 774 775 #define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff) 776 #define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff) 777 #define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff) 778 779 #define TI_CMD_HOST_STATE 0x01 780 #define TI_CMD_CODE_STACK_UP 0x01 781 #define TI_CMD_CODE_STACK_DOWN 0x02 782 783 /* 784 * This command enables software address filtering. It's a workaround 785 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 786 */ 787 #define TI_CMD_FDR_FILTERING 0x02 788 #define TI_CMD_CODE_FILT_ENB 0x01 789 #define TI_CMD_CODE_FILT_DIS 0x02 790 791 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 792 #define TI_CMD_UPDATE_GENCOM 0x04 793 #define TI_CMD_RESET_JUMBO_RING 0x05 794 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06 795 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 796 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 797 798 #define TI_CMD_SET_PROMISC_MODE 0x0A 799 #define TI_CMD_CODE_PROMISC_ENB 0x01 800 #define TI_CMD_CODE_PROMISC_DIS 0x02 801 802 #define TI_CMD_LINK_NEGOTIATION 0x0B 803 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 804 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 805 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02 806 807 #define TI_CMD_SET_MAC_ADDR 0x0C 808 #define TI_CMD_CLR_PROFILE 0x0D 809 810 #define TI_CMD_SET_ALLMULTI 0x0E 811 #define TI_CMD_CODE_ALLMULTI_ENB 0x01 812 #define TI_CMD_CODE_ALLMULTI_DIS 0x02 813 814 #define TI_CMD_CLR_STATS 0x0F 815 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 816 #define TI_CMD_RFRSH_STATS 0x11 817 818 #define TI_CMD_EXT_ADD_MCAST 0x12 819 #define TI_CMD_EXT_DEL_MCAST 0x13 820 821 /* 822 * Utility macros to make issuing commands a little simpler. Assumes 823 * that 'sc' and 'cmd' are in local scope. 824 */ 825 #define TI_DO_CMD(x, y, z) do { \ 826 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \ 827 ti_cmd(sc, &cmd); \ 828 } while(0) 829 830 #define TI_DO_CMD_EXT(x, y, z, v, w) do { \ 831 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \ 832 ti_cmd_ext(sc, &cmd, (v), (w)); \ 833 } while(0) 834 835 /* 836 * Other utility macros. 837 */ 838 #define TI_INC(x, y) (x) = ((x) + 1) % y 839 840 #define TI_UPDATE_JUMBOPROD(x, y) do { \ 841 if ((x)->ti_hwrev == TI_HWREV_TIGON) \ 842 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, (y)); \ 843 else \ 844 CSR_WRITE_4((x), TI_MB_JUMBORXPROD_IDX, (y)); \ 845 } while(0) 846 847 #define TI_UPDATE_MINIPROD(x, y) \ 848 CSR_WRITE_4((x), TI_MB_MINIRXPROD_IDX, (y)) 849 850 #define TI_UPDATE_STDPROD(x, y) do { \ 851 if ((x)->ti_hwrev == TI_HWREV_TIGON) \ 852 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, (y)); \ 853 else \ 854 CSR_WRITE_4((x), TI_MB_STDRXPROD_IDX, (y)); \ 855 } while(0) 856 857 /* 858 * Tigon event structure. 859 */ 860 struct ti_event_desc { 861 uint32_t ti_eventx; 862 uint32_t ti_rsvd; 863 }; 864 #define TI_EVENT_RING_SZ (sizeof(struct ti_event_desc) * TI_EVENT_RING_CNT) 865 866 #define TI_EVENT_EVENT(e) (((((e)->ti_eventx)) >> 24) & 0xff) 867 #define TI_EVENT_CODE(e) (((((e)->ti_eventx)) >> 12) & 0xfff) 868 #define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff) 869 870 /* 871 * Tigon events. 872 */ 873 #define TI_EV_FIRMWARE_UP 0x01 874 #define TI_EV_STATS_UPDATED 0x04 875 876 #define TI_EV_LINKSTAT_CHANGED 0x06 877 #define TI_EV_CODE_GIG_LINK_UP 0x01 878 #define TI_EV_CODE_LINK_DOWN 0x02 879 #define TI_EV_CODE_LINK_UP 0x03 880 881 #define TI_EV_ERROR 0x07 882 #define TI_EV_CODE_ERR_INVAL_CMD 0x01 883 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02 884 #define TI_EV_CODE_ERR_BADCFG 0x03 885 886 #define TI_EV_MCAST_UPDATED 0x08 887 #define TI_EV_CODE_MCAST_ADD 0x01 888 #define TI_EV_CODE_MCAST_DEL 0x02 889 890 #define TI_EV_RESET_JUMBO_RING 0x09 891 /* 892 * Register access macros. The Tigon always uses memory mapped register 893 * accesses and all registers must be accessed with 32 bit operations. 894 */ 895 896 #define CSR_WRITE_4(sc, reg, val) \ 897 bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, (reg), (val)) 898 899 #define CSR_READ_4(sc, reg) \ 900 bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, (reg)) 901 902 #define TI_SETBIT(sc, reg, x) \ 903 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) | (x))) 904 #define TI_CLRBIT(sc, reg, x) \ 905 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & ~(x))) 906 907 struct ti_txdesc { 908 struct mbuf *tx_m; 909 bus_dmamap_t tx_dmamap; 910 STAILQ_ENTRY(ti_txdesc) tx_q; 911 }; 912 913 STAILQ_HEAD(ti_txdq, ti_txdesc); 914 915 struct ti_status { 916 /* 917 * Make sure producer structures are aligned on 32-byte cache 918 * line boundaries. We can create separate DMA area for each 919 * producer/consumer area but it wouldn't get much benefit 920 * since driver use a global driver lock. 921 */ 922 struct ti_producer ti_ev_prodidx_r; 923 uint32_t ti_pad0[6]; 924 struct ti_producer ti_return_prodidx_r; 925 uint32_t ti_pad1[6]; 926 struct ti_producer ti_tx_considx_r; 927 uint32_t ti_pad2[6]; 928 }; 929 930 /* 931 * Ring structures. Most of these reside in host memory and we tell 932 * the NIC where they are via the ring control blocks. The exceptions 933 * are the tx and command rings, which live in NIC memory and which 934 * we access via the shared memory window. 935 */ 936 struct ti_ring_data { 937 struct ti_gib *ti_info; 938 bus_addr_t ti_info_paddr; 939 struct ti_status *ti_status; 940 bus_addr_t ti_status_paddr; 941 struct ti_rx_desc *ti_rx_std_ring; 942 bus_addr_t ti_rx_std_ring_paddr; 943 #ifdef TI_SF_BUF_JUMBO 944 struct ti_rx_desc_ext *ti_rx_jumbo_ring; 945 #else 946 struct ti_rx_desc *ti_rx_jumbo_ring; 947 #endif 948 bus_addr_t ti_rx_jumbo_ring_paddr; 949 struct ti_rx_desc *ti_rx_mini_ring; 950 bus_addr_t ti_rx_mini_ring_paddr; 951 struct ti_rx_desc *ti_rx_return_ring; 952 bus_addr_t ti_rx_return_ring_paddr; 953 struct ti_event_desc *ti_event_ring; 954 bus_addr_t ti_event_ring_paddr; 955 struct ti_tx_desc *ti_tx_ring; 956 bus_addr_t ti_tx_ring_paddr; 957 }; 958 959 /* 960 * Mbuf pointers. We need these to keep track of the virtual addresses 961 * of our mbuf chains since we can only convert from physical to virtual, 962 * not the other way around. 963 */ 964 struct ti_chain_data { 965 bus_dma_tag_t ti_parent_tag; 966 bus_dma_tag_t ti_gib_tag; 967 bus_dmamap_t ti_gib_map; 968 bus_dma_tag_t ti_event_ring_tag; 969 bus_dmamap_t ti_event_ring_map; 970 bus_dma_tag_t ti_status_tag; 971 bus_dmamap_t ti_status_map; 972 bus_dma_tag_t ti_tx_ring_tag; 973 bus_dmamap_t ti_tx_ring_map; 974 bus_dma_tag_t ti_tx_tag; 975 struct ti_txdesc ti_txdesc[TI_TX_RING_CNT]; 976 struct ti_txdq ti_txfreeq; 977 struct ti_txdq ti_txbusyq; 978 bus_dma_tag_t ti_rx_return_ring_tag; 979 bus_dmamap_t ti_rx_return_ring_map; 980 bus_dma_tag_t ti_rx_std_ring_tag; 981 bus_dmamap_t ti_rx_std_ring_map; 982 bus_dma_tag_t ti_rx_std_tag; 983 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 984 bus_dmamap_t ti_rx_std_maps[TI_STD_RX_RING_CNT]; 985 bus_dmamap_t ti_rx_std_sparemap; 986 bus_dma_tag_t ti_rx_jumbo_ring_tag; 987 bus_dmamap_t ti_rx_jumbo_ring_map; 988 bus_dma_tag_t ti_rx_jumbo_tag; 989 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 990 bus_dmamap_t ti_rx_jumbo_maps[TI_JUMBO_RX_RING_CNT]; 991 bus_dmamap_t ti_rx_jumbo_sparemap; 992 bus_dma_tag_t ti_rx_mini_ring_tag; 993 bus_dmamap_t ti_rx_mini_ring_map; 994 bus_dma_tag_t ti_rx_mini_tag; 995 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 996 bus_dmamap_t ti_rx_mini_maps[TI_MINI_RX_RING_CNT]; 997 bus_dmamap_t ti_rx_mini_sparemap; 998 }; 999 1000 struct ti_type { 1001 uint16_t ti_vid; 1002 uint16_t ti_did; 1003 const char *ti_name; 1004 }; 1005 1006 #define TI_HWREV_TIGON 0x01 1007 #define TI_HWREV_TIGON_II 0x02 1008 #define TI_TIMEOUT 1000 1009 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1010 1011 struct ti_mc_entry { 1012 struct ether_addr mc_addr; 1013 SLIST_ENTRY(ti_mc_entry) mc_entries; 1014 }; 1015 1016 typedef enum { 1017 TI_FLAG_NONE = 0x00, 1018 TI_FLAG_DEBUGING = 0x01, 1019 TI_FLAG_WAIT_FOR_LINK = 0x02 1020 } ti_flag_vals; 1021 1022 struct ti_softc { 1023 device_t ti_dev; 1024 struct ifnet *ti_ifp; 1025 bus_space_handle_t ti_bhandle; 1026 bus_space_tag_t ti_btag; 1027 void *ti_intrhand; 1028 struct resource *ti_irq; 1029 struct resource *ti_res; 1030 struct ifmedia ifmedia; /* media info */ 1031 uint8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1032 uint8_t ti_copper; /* 1000baseTX card */ 1033 uint8_t ti_linkstat; /* Link state */ 1034 int ti_hdrsplit; /* enable header splitting */ 1035 int ti_dac; 1036 struct ti_ring_data ti_rdata; /* rings */ 1037 struct ti_chain_data ti_cdata; /* mbufs */ 1038 #define ti_ev_prodidx ti_rdata.ti_status->ti_ev_prodidx_r 1039 #define ti_return_prodidx ti_rdata.ti_status->ti_return_prodidx_r 1040 #define ti_tx_considx ti_rdata.ti_status->ti_tx_considx_r 1041 int ti_tx_saved_prodidx; 1042 int ti_tx_saved_considx; 1043 int ti_rx_saved_considx; 1044 int ti_ev_saved_considx; 1045 int ti_cmd_saved_prodidx; 1046 int ti_std; /* current std ring head */ 1047 int ti_mini; /* current mini ring head */ 1048 int ti_jumbo; /* current jumo ring head */ 1049 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1050 uint32_t ti_stat_ticks; 1051 uint32_t ti_rx_coal_ticks; 1052 uint32_t ti_tx_coal_ticks; 1053 uint32_t ti_rx_max_coal_bds; 1054 uint32_t ti_tx_max_coal_bds; 1055 uint32_t ti_tx_buf_ratio; 1056 int ti_if_flags; 1057 int ti_txcnt; 1058 struct mtx ti_mtx; 1059 struct callout ti_watchdog; 1060 int ti_timer; 1061 ti_flag_vals ti_flags; 1062 uint8_t *ti_membuf; 1063 uint8_t *ti_membuf2; 1064 struct cdev *dev; 1065 }; 1066 1067 #define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1068 #define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 1069 #define TI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ti_mtx, MA_OWNED) 1070 1071 /* 1072 * Microchip Technology 24Cxx EEPROM control bytes 1073 */ 1074 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1075 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1076 1077 /* 1078 * Note that EEPROM_START leaves transmission enabled. 1079 */ 1080 #define EEPROM_START do { \ 1081 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1082 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1083 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1084 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1085 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \ 1086 } while(0) 1087 1088 /* 1089 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1090 * that no further data can be written to the EEPROM I/O pin. 1091 */ 1092 #define EEPROM_STOP do { \ 1093 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1094 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1095 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1096 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1097 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1098 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1099 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \ 1100 } while(0)
Cache object: ae56c30dbddb40111bf986aca8c62eb8
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