Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/trm/trm.c
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1 /* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 *(C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 12 */ 13 14 #include <sys/cdefs.h> 15 __FBSDID("$FreeBSD: releng/5.3/sys/dev/trm/trm.c 129879 2004-05-30 20:08:47Z phk $"); 16 17 /* 18 * HISTORY: 19 * 20 * REV# DATE NAME DESCRIPTION 21 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 22 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 23 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 24 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 25 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 26 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 27 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 28 */ 29 30 /* 31 * 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 */ 56 57 /* 58 * Imported into FreeBSD source repository, and updated to compile under 59 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 60 */ 61 62 /* 63 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 64 * <doginou@ci0.org>, 2002-03-04 65 */ 66 67 #include <sys/param.h> 68 69 #include <sys/systm.h> 70 #include <sys/malloc.h> 71 #include <sys/queue.h> 72 #if __FreeBSD_version >= 500000 73 #include <sys/bio.h> 74 #endif 75 #include <sys/buf.h> 76 #include <sys/bus.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcireg.h> 85 #include <machine/resource.h> 86 #include <machine/bus_pio.h> 87 #include <machine/bus.h> 88 #include <machine/clock.h> 89 #include <sys/rman.h> 90 91 #include <cam/cam.h> 92 #include <cam/cam_ccb.h> 93 #include <cam/cam_sim.h> 94 #include <cam/cam_xpt_sim.h> 95 #include <cam/cam_debug.h> 96 97 #include <cam/scsi/scsi_all.h> 98 #include <cam/scsi/scsi_message.h> 99 100 #include <dev/trm/trm.h> 101 102 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 103 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 104 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 105 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 106 reg, value) 107 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 108 reg, value) 109 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 110 reg, value) 111 112 #define PCI_Vendor_ID_TEKRAM 0x1DE1 113 #define PCI_Device_ID_TRM_S1040 0x0391 114 #define PCI_DEVICEID_TRMS1040 0x03911DE1 115 #define PCI_DEVICEID_TRMS2080 0x03921DE1 116 117 #ifdef trm_DEBUG1 118 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 119 #else 120 #define TRM_DPRINTF(fmt, arg...) {} 121 #endif /* TRM_DEBUG */ 122 123 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 124 static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 125 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 126 static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 127 static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 128 static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 129 static void NVRAM_trm_wait_30us(PACB pACB); 130 131 static void trm_Interrupt(void *vpACB); 132 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 133 u_int16_t * pscsi_status); 134 static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 135 u_int16_t * pscsi_status); 136 static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 137 u_int16_t * pscsi_status); 138 static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 139 u_int16_t * pscsi_status); 140 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 141 u_int16_t * pscsi_status); 142 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 143 u_int16_t * pscsi_status); 144 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 145 u_int16_t * pscsi_status); 146 static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 147 u_int16_t * pscsi_status); 148 static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 149 u_int16_t * pscsi_status); 150 static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 151 u_int16_t * pscsi_status); 152 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 153 u_int16_t * pscsi_status); 154 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 155 u_int16_t * pscsi_status); 156 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 157 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 158 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 159 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 160 static void trm_Disconnect(PACB pACB); 161 static void trm_Reselect(PACB pACB); 162 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 163 static void trm_DoingSRB_Done(PACB pACB); 164 static void trm_ScsiRstDetect(PACB pACB); 165 static void trm_ResetSCSIBus(PACB pACB); 166 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 167 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 168 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 169 static void trm_SendSRB(PACB pACB, PSRB pSRB); 170 static int trm_probe(device_t tag); 171 static int trm_attach(device_t tag); 172 static void trm_reset(PACB pACB); 173 174 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 175 176 static int trm_initAdapter(PACB pACB, u_int16_t unit); 177 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 178 u_int32_t i, u_int32_t j); 179 static int trm_initSRB(PACB pACB); 180 static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 181 /* CAM SIM entry points */ 182 #define ccb_trmsrb_ptr spriv_ptr0 183 #define ccb_trmacb_ptr spriv_ptr1 184 static void trm_action(struct cam_sim *psim, union ccb *pccb); 185 static void trm_poll(struct cam_sim *psim); 186 187 188 static void * trm_SCSI_phase0[] = { 189 trm_DataOutPhase0, /* phase:0 */ 190 trm_DataInPhase0, /* phase:1 */ 191 trm_CommandPhase0, /* phase:2 */ 192 trm_StatusPhase0, /* phase:3 */ 193 trm_Nop0, /* phase:4 */ 194 trm_Nop1, /* phase:5 */ 195 trm_MsgOutPhase0, /* phase:6 */ 196 trm_MsgInPhase0, /* phase:7 */ 197 }; 198 199 /* 200 * 201 * stateV = (void *) trm_SCSI_phase1[phase] 202 * 203 */ 204 static void * trm_SCSI_phase1[] = { 205 trm_DataOutPhase1, /* phase:0 */ 206 trm_DataInPhase1, /* phase:1 */ 207 trm_CommandPhase1, /* phase:2 */ 208 trm_StatusPhase1, /* phase:3 */ 209 trm_Nop0, /* phase:4 */ 210 trm_Nop1, /* phase:5 */ 211 trm_MsgOutPhase1, /* phase:6 */ 212 trm_MsgInPhase1, /* phase:7 */ 213 }; 214 215 216 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 217 /* 218 *Fast20: 000 50ns, 20.0 Mbytes/s 219 * 001 75ns, 13.3 Mbytes/s 220 * 010 100ns, 10.0 Mbytes/s 221 * 011 125ns, 8.0 Mbytes/s 222 * 100 150ns, 6.6 Mbytes/s 223 * 101 175ns, 5.7 Mbytes/s 224 * 110 200ns, 5.0 Mbytes/s 225 * 111 250ns, 4.0 Mbytes/s 226 * 227 *Fast40: 000 25ns, 40.0 Mbytes/s 228 * 001 50ns, 20.0 Mbytes/s 229 * 010 75ns, 13.3 Mbytes/s 230 * 011 100ns, 10.0 Mbytes/s 231 * 100 125ns, 8.0 Mbytes/s 232 * 101 150ns, 6.6 Mbytes/s 233 * 110 175ns, 5.7 Mbytes/s 234 * 111 200ns, 5.0 Mbytes/s 235 */ 236 /* real period: */ 237 u_int8_t dc395x_clock_period[] = { 238 12,/* 48 ns 20 MB/sec */ 239 18,/* 72 ns 13.3 MB/sec */ 240 25,/* 100 ns 10.0 MB/sec */ 241 31,/* 124 ns 8.0 MB/sec */ 242 37,/* 148 ns 6.6 MB/sec */ 243 43,/* 172 ns 5.7 MB/sec */ 244 50,/* 200 ns 5.0 MB/sec */ 245 62 /* 248 ns 4.0 MB/sec */ 246 }; 247 248 u_int8_t dc395u2x_clock_period[]={ 249 10,/* 25 ns 40.0 MB/sec */ 250 12,/* 48 ns 20.0 MB/sec */ 251 18,/* 72 ns 13.3 MB/sec */ 252 25,/* 100 ns 10.0 MB/sec */ 253 31,/* 124 ns 8.0 MB/sec */ 254 37,/* 148 ns 6.6 MB/sec */ 255 43,/* 172 ns 5.7 MB/sec */ 256 50,/* 200 ns 5.0 MB/sec */ 257 }; 258 259 #define dc395x_tinfo_period dc395x_clock_period 260 #define dc395u2x_tinfo_period dc395u2x_clock_period 261 262 static PSRB 263 trm_GetSRB(PACB pACB) 264 { 265 int intflag; 266 PSRB pSRB; 267 268 intflag = splcam(); 269 pSRB = pACB->pFreeSRB; 270 if (pSRB) { 271 pACB->pFreeSRB = pSRB->pNextSRB; 272 pSRB->pNextSRB = NULL; 273 } 274 splx(intflag); 275 return (pSRB); 276 } 277 278 static void 279 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 280 { 281 PSRB psrb1; 282 int intflag; 283 284 intflag = splcam(); 285 if ((psrb1 = pDCB->pWaitingSRB)) { 286 pSRB->pNextSRB = psrb1; 287 pDCB->pWaitingSRB = pSRB; 288 } else { 289 pSRB->pNextSRB = NULL; 290 pDCB->pWaitingSRB = pSRB; 291 pDCB->pWaitingLastSRB = pSRB; 292 } 293 splx(intflag); 294 } 295 296 static void 297 trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 298 { 299 PSRB psrb1; 300 int intflag; 301 302 intflag = splcam(); 303 pDCB->GoingSRBCnt--; 304 psrb1 = pDCB->pGoingSRB; 305 if (pSRB == psrb1) 306 /* 307 * if this SRB is GoingSRB 308 * remove this SRB from GoingSRB Q 309 */ 310 pDCB->pGoingSRB = psrb1->pNextSRB; 311 else { 312 /* 313 * if this SRB is not current GoingSRB 314 * remove this SRB from GoingSRB Q 315 */ 316 while (pSRB != psrb1->pNextSRB) 317 psrb1 = psrb1->pNextSRB; 318 psrb1->pNextSRB = pSRB->pNextSRB; 319 if (pSRB == pDCB->pGoingLastSRB) 320 pDCB->pGoingLastSRB = psrb1; 321 } 322 if ((psrb1 = pDCB->pWaitingSRB)) { 323 /* 324 * if WaitingSRB Q is not NULL 325 * Q back this SRB into WaitingSRB 326 */ 327 328 pSRB->pNextSRB = psrb1; 329 pDCB->pWaitingSRB = pSRB; 330 } else { 331 pSRB->pNextSRB = NULL; 332 pDCB->pWaitingSRB = pSRB; 333 pDCB->pWaitingLastSRB = pSRB; 334 } 335 splx(intflag); 336 } 337 338 static void 339 trm_DoWaitingSRB(PACB pACB) 340 { 341 int intflag; 342 PDCB ptr, ptr1; 343 PSRB pSRB; 344 345 intflag = splcam(); 346 if (!(pACB->pActiveDCB) && 347 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 348 ptr = pACB->pDCBRunRobin; 349 if (!ptr) { 350 ptr = pACB->pLinkDCB; 351 pACB->pDCBRunRobin = ptr; 352 } 353 ptr1 = ptr; 354 for (;ptr1 ;) { 355 pACB->pDCBRunRobin = ptr1->pNextDCB; 356 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 357 || !(pSRB = ptr1->pWaitingSRB)) { 358 if (pACB->pDCBRunRobin == ptr) 359 break; 360 ptr1 = ptr1->pNextDCB; 361 } else { 362 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 363 /* 364 * If trm_StartSCSI return 0 : 365 * current interrupt status is interrupt enable 366 * It's said that SCSI processor is unoccupied 367 */ 368 ptr1->GoingSRBCnt++; 369 if (ptr1->pWaitingLastSRB == pSRB) { 370 ptr1->pWaitingSRB = NULL; 371 ptr1->pWaitingLastSRB = NULL; 372 } else 373 ptr1->pWaitingSRB = pSRB->pNextSRB; 374 pSRB->pNextSRB = NULL; 375 if (ptr1->pGoingSRB) 376 ptr1->pGoingLastSRB->pNextSRB = pSRB; 377 else 378 ptr1->pGoingSRB = pSRB; 379 ptr1->pGoingLastSRB = pSRB; 380 } 381 break; 382 } 383 } 384 } 385 splx(intflag); 386 return; 387 } 388 389 static void 390 trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 391 { 392 393 if (pDCB->pWaitingSRB) { 394 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 395 pDCB->pWaitingLastSRB = pSRB; 396 pSRB->pNextSRB = NULL; 397 } else { 398 pDCB->pWaitingSRB = pSRB; 399 pDCB->pWaitingLastSRB = pSRB; 400 } 401 } 402 403 static u_int32_t 404 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 405 { 406 int offset; 407 408 offset = pSRB->TagNumber; 409 return (pACB->sense_busaddr + 410 (offset * sizeof(struct scsi_sense_data))); 411 } 412 413 static struct scsi_sense_data * 414 trm_get_sense_buf(PACB pACB, PSRB pSRB) 415 { 416 int offset; 417 418 offset = pSRB->TagNumber; 419 return (&pACB->sense_buffers[offset]); 420 } 421 static void 422 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 423 { 424 int flags; 425 PACB pACB; 426 PSRB pSRB; 427 union ccb *ccb; 428 u_long totalxferlen=0; 429 430 flags = splcam(); 431 pSRB = (PSRB)arg; 432 ccb = pSRB->pccb; 433 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 434 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 435 if (nseg != 0) { 436 PSEG psg; 437 bus_dma_segment_t *end_seg; 438 int op; 439 440 /* Copy the segments into our SG list */ 441 end_seg = dm_segs + nseg; 442 psg = pSRB->pSRBSGL; 443 while (dm_segs < end_seg) { 444 psg->address = dm_segs->ds_addr; 445 psg->length = (u_long)dm_segs->ds_len; 446 totalxferlen += dm_segs->ds_len; 447 psg++; 448 dm_segs++; 449 } 450 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 451 op = BUS_DMASYNC_PREREAD; 452 } else { 453 op = BUS_DMASYNC_PREWRITE; 454 } 455 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 456 } 457 pSRB->RetryCnt = 0; 458 pSRB->SRBTotalXferLength = totalxferlen; 459 pSRB->SRBSGCount = nseg; 460 pSRB->SRBSGIndex = 0; 461 pSRB->AdaptStatus = 0; 462 pSRB->TargetStatus = 0; 463 pSRB->MsgCnt = 0; 464 pSRB->SRBStatus = 0; 465 pSRB->SRBFlag = 0; 466 pSRB->SRBState = 0; 467 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 468 469 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 470 if (nseg != 0) 471 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 472 pSRB->pNextSRB = pACB->pFreeSRB; 473 pACB->pFreeSRB = pSRB; 474 xpt_done(ccb); 475 splx(flags); 476 return; 477 } 478 ccb->ccb_h.status |= CAM_SIM_QUEUED; 479 #if 0 480 /* XXX Need a timeout handler */ 481 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 482 #endif 483 trm_SendSRB(pACB, pSRB); 484 splx(flags); 485 return; 486 } 487 488 static void 489 trm_SendSRB(PACB pACB, PSRB pSRB) 490 { 491 PDCB pDCB; 492 493 pDCB = pSRB->pSRBDCB; 494 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 495 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 496 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 497 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 498 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 499 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 500 trm_SRBwaiting(pDCB, pSRB); 501 goto SND_EXIT; 502 } 503 504 if (pDCB->pWaitingSRB) { 505 trm_SRBwaiting(pDCB, pSRB); 506 pSRB = pDCB->pWaitingSRB; 507 pDCB->pWaitingSRB = pSRB->pNextSRB; 508 pSRB->pNextSRB = NULL; 509 } 510 511 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 512 /* 513 * If trm_StartSCSI return 0 : 514 * current interrupt status is interrupt enable 515 * It's said that SCSI processor is unoccupied 516 */ 517 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 518 if (pDCB->pGoingSRB) { 519 pDCB->pGoingLastSRB->pNextSRB = pSRB; 520 pDCB->pGoingLastSRB = pSRB; 521 } else { 522 pDCB->pGoingSRB = pSRB; 523 pDCB->pGoingLastSRB = pSRB; 524 } 525 } else { 526 /* 527 * If trm_StartSCSI return 1 : 528 * current interrupt status is interrupt disreenable 529 * It's said that SCSI processor has more one SRB need to do 530 */ 531 trm_RewaitSRB0(pDCB, pSRB); 532 } 533 SND_EXIT: 534 return; 535 } 536 537 538 static void 539 trm_action(struct cam_sim *psim, union ccb *pccb) 540 { 541 PACB pACB; 542 int actionflags; 543 u_int target_id,target_lun; 544 545 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 546 547 actionflags = splcam(); 548 pACB = (PACB) cam_sim_softc(psim); 549 target_id = pccb->ccb_h.target_id; 550 target_lun = pccb->ccb_h.target_lun; 551 552 switch (pccb->ccb_h.func_code) { 553 case XPT_NOOP: 554 TRM_DPRINTF(" XPT_NOOP \n"); 555 pccb->ccb_h.status = CAM_REQ_INVALID; 556 xpt_done(pccb); 557 break; 558 /* 559 * Execute the requested I/O operation 560 */ 561 case XPT_SCSI_IO: { 562 PDCB pDCB = NULL; 563 PSRB pSRB; 564 struct ccb_scsiio *pcsio; 565 566 pcsio = &pccb->csio; 567 TRM_DPRINTF(" XPT_SCSI_IO \n"); 568 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 569 ,target_id, target_lun); 570 TRM_DPRINTF( 571 "pACB->scan_devices[target_id][target_lun]= %d \n" 572 ,pACB->scan_devices[target_id][target_lun]); 573 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 574 CAM_REQ_INPROG) { 575 xpt_done(pccb); 576 splx(actionflags); 577 return; 578 } 579 pDCB = &pACB->DCBarray[target_id][target_lun]; 580 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 581 pACB->scan_devices[target_id][target_lun] = 1; 582 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 583 target_id, target_lun); 584 } 585 /* 586 * Assign an SRB and connect it with this ccb. 587 */ 588 pSRB = trm_GetSRB(pACB); 589 if (!pSRB) { 590 /* Freeze SIMQ */ 591 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 592 xpt_done(pccb); 593 splx(actionflags); 594 return; 595 } 596 pSRB->pSRBDCB = pDCB; 597 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 598 pccb->ccb_h.ccb_trmacb_ptr = pACB; 599 pSRB->pccb = pccb; 600 pSRB->ScsiCmdLen = pcsio->cdb_len; 601 /* 602 * move layer of CAM command block to layer of SCSI 603 * Request Block for SCSI processor command doing 604 */ 605 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 606 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 607 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 608 ,pcsio->cdb_len); 609 } else { 610 pccb->ccb_h.status = CAM_REQ_INVALID; 611 pSRB->pNextSRB = pACB->pFreeSRB; 612 pACB->pFreeSRB= pSRB; 613 xpt_done(pccb); 614 splx(actionflags); 615 return; 616 } 617 } else 618 bcopy(pcsio->cdb_io.cdb_bytes, 619 pSRB->CmdBlock, pcsio->cdb_len); 620 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 621 != CAM_DIR_NONE) { 622 if ((pccb->ccb_h.flags & 623 CAM_SCATTER_VALID) == 0) { 624 if ((pccb->ccb_h.flags 625 & CAM_DATA_PHYS) == 0) { 626 int vmflags; 627 int error; 628 629 vmflags = splsoftvm(); 630 error = bus_dmamap_load( 631 pACB->buffer_dmat, 632 pSRB->dmamap, 633 pcsio->data_ptr, 634 pcsio->dxfer_len, 635 trm_ExecuteSRB, 636 pSRB, 637 0); 638 if (error == EINPROGRESS) { 639 xpt_freeze_simq( 640 pACB->psim, 641 1); 642 pccb->ccb_h.status |= 643 CAM_RELEASE_SIMQ; 644 } 645 splx(vmflags); 646 } else { 647 struct bus_dma_segment seg; 648 649 /* Pointer to physical buffer */ 650 seg.ds_addr = 651 (bus_addr_t)pcsio->data_ptr; 652 seg.ds_len = pcsio->dxfer_len; 653 trm_ExecuteSRB(pSRB, &seg, 1, 654 0); 655 } 656 } else { 657 /* CAM_SCATTER_VALID */ 658 struct bus_dma_segment *segs; 659 660 if ((pccb->ccb_h.flags & 661 CAM_SG_LIST_PHYS) == 0 || 662 (pccb->ccb_h.flags 663 & CAM_DATA_PHYS) != 0) { 664 pSRB->pNextSRB = pACB->pFreeSRB; 665 pACB->pFreeSRB = pSRB; 666 pccb->ccb_h.status = 667 CAM_PROVIDE_FAIL; 668 xpt_done(pccb); 669 splx(actionflags); 670 return; 671 } 672 673 /* cam SG list is physical, 674 * cam data is virtual 675 */ 676 segs = (struct bus_dma_segment *) 677 pcsio->data_ptr; 678 trm_ExecuteSRB(pSRB, segs, 679 pcsio->sglist_cnt, 1); 680 } /* CAM_SCATTER_VALID */ 681 } else 682 trm_ExecuteSRB(pSRB, NULL, 0, 0); 683 } 684 break; 685 case XPT_GDEV_TYPE: 686 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 687 pccb->ccb_h.status = CAM_REQ_INVALID; 688 xpt_done(pccb); 689 break; 690 case XPT_GDEVLIST: 691 TRM_DPRINTF(" XPT_GDEVLIST \n"); 692 pccb->ccb_h.status = CAM_REQ_INVALID; 693 xpt_done(pccb); 694 break; 695 /* 696 * Path routing inquiry 697 * Path Inquiry CCB 698 */ 699 case XPT_PATH_INQ: { 700 struct ccb_pathinq *cpi = &pccb->cpi; 701 702 TRM_DPRINTF(" XPT_PATH_INQ \n"); 703 cpi->version_num = 1; 704 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 705 cpi->target_sprt = 0; 706 cpi->hba_misc = 0; 707 cpi->hba_eng_cnt = 0; 708 cpi->max_target = 15 ; 709 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 710 cpi->initiator_id = pACB->AdaptSCSIID; 711 cpi->bus_id = cam_sim_bus(psim); 712 cpi->base_transfer_speed = 3300; 713 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 714 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 715 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 716 cpi->unit_number = cam_sim_unit(psim); 717 cpi->ccb_h.status = CAM_REQ_CMP; 718 xpt_done(pccb); 719 } 720 break; 721 /* 722 * Release a frozen SIM queue 723 * Release SIM Queue 724 */ 725 case XPT_REL_SIMQ: 726 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 727 pccb->ccb_h.status = CAM_REQ_INVALID; 728 xpt_done(pccb); 729 break; 730 /* 731 * Set Asynchronous Callback Parameters 732 * Set Asynchronous Callback CCB 733 */ 734 case XPT_SASYNC_CB: 735 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 736 pccb->ccb_h.status = CAM_REQ_INVALID; 737 xpt_done(pccb); 738 break; 739 /* 740 * Set device type information 741 * Set Device Type CCB 742 */ 743 case XPT_SDEV_TYPE: 744 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 745 pccb->ccb_h.status = CAM_REQ_INVALID; 746 xpt_done(pccb); 747 break; 748 /* 749 * (Re)Scan the SCSI Bus 750 * Rescan the given bus, or bus/target/lun 751 */ 752 case XPT_SCAN_BUS: 753 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 754 pccb->ccb_h.status = CAM_REQ_INVALID; 755 xpt_done(pccb); 756 break; 757 /* 758 * Get EDT entries matching the given pattern 759 */ 760 case XPT_DEV_MATCH: 761 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 762 pccb->ccb_h.status = CAM_REQ_INVALID; 763 xpt_done(pccb); 764 break; 765 /* 766 * Turn on debugging for a bus, target or lun 767 */ 768 case XPT_DEBUG: 769 TRM_DPRINTF(" XPT_DEBUG \n"); 770 pccb->ccb_h.status = CAM_REQ_INVALID; 771 xpt_done(pccb); 772 break; 773 /* 774 * XPT_ABORT = 0x10, Abort the specified CCB 775 * Abort XPT request CCB 776 */ 777 case XPT_ABORT: 778 TRM_DPRINTF(" XPT_ABORT \n"); 779 pccb->ccb_h.status = CAM_REQ_INVALID; 780 xpt_done(pccb); 781 break; 782 /* 783 * Reset the specified SCSI bus 784 * Reset SCSI Bus CCB 785 */ 786 case XPT_RESET_BUS: { 787 int i; 788 789 TRM_DPRINTF(" XPT_RESET_BUS \n"); 790 trm_reset(pACB); 791 pACB->ACBFlag=0; 792 for (i=0; i<500; i++) 793 DELAY(1000); 794 pccb->ccb_h.status = CAM_REQ_CMP; 795 xpt_done(pccb); 796 } 797 break; 798 /* 799 * Bus Device Reset the specified SCSI device 800 * Reset SCSI Device CCB 801 */ 802 case XPT_RESET_DEV: 803 /* 804 * Don't (yet?) support vendor 805 * specific commands. 806 */ 807 TRM_DPRINTF(" XPT_RESET_DEV \n"); 808 pccb->ccb_h.status = CAM_REQ_INVALID; 809 xpt_done(pccb); 810 break; 811 /* 812 * Terminate the I/O process 813 * Terminate I/O Process Request CCB 814 */ 815 case XPT_TERM_IO: 816 TRM_DPRINTF(" XPT_TERM_IO \n"); 817 pccb->ccb_h.status = CAM_REQ_INVALID; 818 xpt_done(pccb); 819 break; 820 /* 821 * Scan Logical Unit 822 */ 823 case XPT_SCAN_LUN: 824 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 825 pccb->ccb_h.status = CAM_REQ_INVALID; 826 xpt_done(pccb); 827 break; 828 829 /* 830 * Get/Set transfer rate/width/disconnection/tag queueing 831 * settings 832 * (GET) default/user transfer settings for the target 833 */ 834 case XPT_GET_TRAN_SETTINGS: { 835 struct ccb_trans_settings *cts; 836 int intflag; 837 struct trm_transinfo *tinfo; 838 PDCB pDCB; 839 840 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 841 cts = &pccb->cts; 842 pDCB = &pACB->DCBarray[target_id][target_lun]; 843 intflag = splcam(); 844 /* 845 * disable interrupt 846 */ 847 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 848 /* current transfer settings */ 849 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 850 cts->flags = CCB_TRANS_DISC_ENB; 851 else 852 cts->flags = 0;/* no tag & disconnect */ 853 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 854 cts->flags |= CCB_TRANS_TAG_ENB; 855 tinfo = &pDCB->tinfo.current; 856 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 857 cts->flags); 858 } else { 859 /* default(user) transfer settings */ 860 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 861 cts->flags = CCB_TRANS_DISC_ENB; 862 else 863 cts->flags = 0; 864 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 865 cts->flags |= CCB_TRANS_TAG_ENB; 866 tinfo = &pDCB->tinfo.user; 867 TRM_DPRINTF("USER: cts->flags= %2x \n", 868 cts->flags); 869 } 870 cts->sync_period = tinfo->period; 871 cts->sync_offset = tinfo->offset; 872 cts->bus_width = tinfo->width; 873 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 874 pDCB->SyncPeriod); 875 TRM_DPRINTF("period: %d \n", tinfo->period); 876 TRM_DPRINTF("offset: %d \n", tinfo->offset); 877 TRM_DPRINTF("width: %d \n", tinfo->width); 878 879 splx(intflag); 880 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 881 CCB_TRANS_SYNC_OFFSET_VALID | 882 CCB_TRANS_BUS_WIDTH_VALID | 883 CCB_TRANS_DISC_VALID | 884 CCB_TRANS_TQ_VALID; 885 pccb->ccb_h.status = CAM_REQ_CMP; 886 xpt_done(pccb); 887 } 888 break; 889 /* 890 * Get/Set transfer rate/width/disconnection/tag queueing 891 * settings 892 * (Set) transfer rate/width negotiation settings 893 */ 894 case XPT_SET_TRAN_SETTINGS: { 895 struct ccb_trans_settings *cts; 896 u_int update_type; 897 int intflag; 898 PDCB pDCB; 899 900 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 901 cts = &pccb->cts; 902 update_type = 0; 903 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 904 update_type |= TRM_TRANS_GOAL; 905 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 906 update_type |= TRM_TRANS_USER; 907 intflag = splcam(); 908 pDCB = &pACB->DCBarray[target_id][target_lun]; 909 910 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 911 /*ccb disc enables */ 912 if (update_type & TRM_TRANS_GOAL) { 913 if ((cts->flags & CCB_TRANS_DISC_ENB) 914 != 0) 915 pDCB->tinfo.disc_tag 916 |= TRM_CUR_DISCENB; 917 else 918 pDCB->tinfo.disc_tag &= 919 ~TRM_CUR_DISCENB; 920 } 921 if (update_type & TRM_TRANS_USER) { 922 if ((cts->flags & CCB_TRANS_DISC_ENB) 923 != 0) 924 pDCB->tinfo.disc_tag 925 |= TRM_USR_DISCENB; 926 else 927 pDCB->tinfo.disc_tag &= 928 ~TRM_USR_DISCENB; 929 } 930 } 931 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 932 /* if ccb tag q active */ 933 if (update_type & TRM_TRANS_GOAL) { 934 if ((cts->flags & CCB_TRANS_TAG_ENB) 935 != 0) 936 pDCB->tinfo.disc_tag |= 937 TRM_CUR_TAGENB; 938 else 939 pDCB->tinfo.disc_tag &= 940 ~TRM_CUR_TAGENB; 941 } 942 if (update_type & TRM_TRANS_USER) { 943 if ((cts->flags & CCB_TRANS_TAG_ENB) 944 != 0) 945 pDCB->tinfo.disc_tag |= 946 TRM_USR_TAGENB; 947 else 948 pDCB->tinfo.disc_tag &= 949 ~TRM_USR_TAGENB; 950 } 951 } 952 /* Minimum sync period factor */ 953 954 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 955 /* if ccb sync active */ 956 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 957 if ((cts->sync_period != 0) && 958 (cts->sync_period < 125)) 959 cts->sync_period = 125; 960 /* 1/(125*4) minsync 2 MByte/sec */ 961 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 962 != 0) { 963 if (cts->sync_offset == 0) 964 cts->sync_period = 0; 965 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 966 if (cts->sync_offset > 15) 967 cts->sync_offset = 15; 968 } 969 } 970 if ((update_type & TRM_TRANS_USER) != 0) { 971 pDCB->tinfo.user.period = cts->sync_period; 972 pDCB->tinfo.user.offset = cts->sync_offset; 973 pDCB->tinfo.user.width = cts->bus_width; 974 } 975 if ((update_type & TRM_TRANS_GOAL) != 0) { 976 pDCB->tinfo.goal.period = cts->sync_period; 977 pDCB->tinfo.goal.offset = cts->sync_offset; 978 pDCB->tinfo.goal.width = cts->bus_width; 979 } 980 splx(intflag); 981 pccb->ccb_h.status = CAM_REQ_CMP; 982 xpt_done(pccb); 983 break; 984 } 985 /* 986 * Calculate the geometry parameters for a device give 987 * the sector size and volume size. 988 */ 989 case XPT_CALC_GEOMETRY: 990 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 991 cam_calc_geometry(&pccb->ccg, /*extended*/1); 992 xpt_done(pccb); 993 break; 994 case XPT_ENG_INQ: 995 TRM_DPRINTF(" XPT_ENG_INQ \n"); 996 pccb->ccb_h.status = CAM_REQ_INVALID; 997 xpt_done(pccb); 998 break; 999 /* 1000 * HBA execute engine request 1001 * This structure must match SCSIIO size 1002 */ 1003 case XPT_ENG_EXEC: 1004 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1005 pccb->ccb_h.status = CAM_REQ_INVALID; 1006 xpt_done(pccb); 1007 break; 1008 /* 1009 * XPT_EN_LUN = 0x30, Enable LUN as a target 1010 * Target mode structures. 1011 */ 1012 case XPT_EN_LUN: 1013 /* 1014 * Don't (yet?) support vendor 1015 * specific commands. 1016 */ 1017 TRM_DPRINTF(" XPT_EN_LUN \n"); 1018 pccb->ccb_h.status = CAM_REQ_INVALID; 1019 xpt_done(pccb); 1020 break; 1021 /* 1022 * Execute target I/O request 1023 */ 1024 case XPT_TARGET_IO: 1025 /* 1026 * Don't (yet?) support vendor 1027 * specific commands. 1028 */ 1029 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1030 pccb->ccb_h.status = CAM_REQ_INVALID; 1031 xpt_done(pccb); 1032 break; 1033 /* 1034 * Accept Host Target Mode CDB 1035 */ 1036 case XPT_ACCEPT_TARGET_IO: 1037 /* 1038 * Don't (yet?) support vendor 1039 * specific commands. 1040 */ 1041 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1042 pccb->ccb_h.status = CAM_REQ_INVALID; 1043 xpt_done(pccb); 1044 break; 1045 /* 1046 * Continue Host Target I/O Connection 1047 */ 1048 case XPT_CONT_TARGET_IO: 1049 /* 1050 * Don't (yet?) support vendor 1051 * specific commands. 1052 */ 1053 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1054 pccb->ccb_h.status = CAM_REQ_INVALID; 1055 xpt_done(pccb); 1056 break; 1057 /* 1058 * Notify Host Target driver of event 1059 */ 1060 case XPT_IMMED_NOTIFY: 1061 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1062 pccb->ccb_h.status = CAM_REQ_INVALID; 1063 xpt_done(pccb); 1064 break; 1065 /* 1066 * Acknowledgement of event 1067 */ 1068 case XPT_NOTIFY_ACK: 1069 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1070 pccb->ccb_h.status = CAM_REQ_INVALID; 1071 xpt_done(pccb); 1072 break; 1073 /* 1074 * XPT_VUNIQUE = 0x80 1075 */ 1076 case XPT_VUNIQUE: 1077 pccb->ccb_h.status = CAM_REQ_INVALID; 1078 xpt_done(pccb); 1079 break; 1080 default: 1081 pccb->ccb_h.status = CAM_REQ_INVALID; 1082 xpt_done(pccb); 1083 break; 1084 } 1085 splx(actionflags); 1086 } 1087 1088 static void 1089 trm_poll(struct cam_sim *psim) 1090 { 1091 trm_Interrupt(cam_sim_softc(psim)); 1092 } 1093 1094 static void 1095 trm_ResetDevParam(PACB pACB) 1096 { 1097 PDCB pDCB, pdcb; 1098 PNVRAMTYPE pEEpromBuf; 1099 u_int8_t PeriodIndex; 1100 1101 pDCB = pACB->pLinkDCB; 1102 if (pDCB == NULL) 1103 return; 1104 pdcb = pDCB; 1105 do { 1106 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1107 pDCB->SyncPeriod = 0; 1108 pDCB->SyncOffset = 0; 1109 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1110 pDCB->DevMode = 1111 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1112 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1113 PeriodIndex = 1114 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1115 if (pACB->AdaptType == 1) /* is U2? */ 1116 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1117 else 1118 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1119 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1120 (pACB->Config & HCC_WIDE_CARD)) 1121 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1122 pDCB = pDCB->pNextDCB; 1123 } 1124 while (pdcb != pDCB); 1125 } 1126 1127 static void 1128 trm_RecoverSRB(PACB pACB) 1129 { 1130 PDCB pDCB, pdcb; 1131 PSRB psrb, psrb2; 1132 u_int16_t cnt, i; 1133 1134 pDCB = pACB->pLinkDCB; 1135 if (pDCB == NULL) 1136 return; 1137 pdcb = pDCB; 1138 do { 1139 cnt = pdcb->GoingSRBCnt; 1140 psrb = pdcb->pGoingSRB; 1141 for (i = 0; i < cnt; i++) { 1142 psrb2 = psrb; 1143 psrb = psrb->pNextSRB; 1144 if (pdcb->pWaitingSRB) { 1145 psrb2->pNextSRB = pdcb->pWaitingSRB; 1146 pdcb->pWaitingSRB = psrb2; 1147 } else { 1148 pdcb->pWaitingSRB = psrb2; 1149 pdcb->pWaitingLastSRB = psrb2; 1150 psrb2->pNextSRB = NULL; 1151 } 1152 } 1153 pdcb->GoingSRBCnt = 0; 1154 pdcb->pGoingSRB = NULL; 1155 pdcb = pdcb->pNextDCB; 1156 } 1157 while (pdcb != pDCB); 1158 } 1159 1160 static void 1161 trm_reset(PACB pACB) 1162 { 1163 int intflag; 1164 u_int16_t i; 1165 1166 TRM_DPRINTF("trm: RESET"); 1167 intflag = splcam(); 1168 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1169 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1170 1171 trm_ResetSCSIBus(pACB); 1172 for (i = 0; i < 500; i++) 1173 DELAY(1000); 1174 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1175 /* Enable DMA interrupt */ 1176 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1177 /* Clear DMA FIFO */ 1178 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1179 /* Clear SCSI FIFO */ 1180 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1181 trm_ResetDevParam(pACB); 1182 trm_DoingSRB_Done(pACB); 1183 pACB->pActiveDCB = NULL; 1184 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1185 trm_DoWaitingSRB(pACB); 1186 /* Tell the XPT layer that a bus reset occured */ 1187 if (pACB->ppath != NULL) 1188 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1189 splx(intflag); 1190 return; 1191 } 1192 1193 static u_int16_t 1194 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1195 { 1196 u_int16_t return_code; 1197 u_int8_t scsicommand, i,command,identify_message; 1198 u_int8_t * ptr; 1199 union ccb *pccb; 1200 struct ccb_scsiio *pcsio; 1201 1202 pccb = pSRB->pccb; 1203 pcsio = &pccb->csio; 1204 1205 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1206 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1207 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1208 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1209 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1210 /* Flush FIFO */ 1211 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1212 1213 identify_message = pDCB->IdentifyMsg; 1214 1215 if ((pSRB->CmdBlock[0] == INQUIRY) || 1216 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1217 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1218 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1219 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1220 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1221 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1222 if (!(pDCB->IdentifyMsg & 7) || 1223 (pSRB->CmdBlock[0] != INQUIRY)) { 1224 scsicommand = SCMD_SEL_ATNSTOP; 1225 pSRB->SRBState = SRB_MSGOUT; 1226 goto polling; 1227 } 1228 } 1229 /* 1230 * Send identify message 1231 */ 1232 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1233 scsicommand = SCMD_SEL_ATN; 1234 pSRB->SRBState = SRB_START_; 1235 } else { 1236 /* not inquiry,request sense,auto request sense */ 1237 /* 1238 * Send identify message 1239 */ 1240 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1241 scsicommand = SCMD_SEL_ATN; 1242 pSRB->SRBState = SRB_START_; 1243 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1244 /* Send Tag message */ 1245 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1246 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1247 scsicommand = SCMD_SEL_ATN3; 1248 } 1249 } 1250 polling: 1251 /* 1252 * Send CDB ..command block ......... 1253 */ 1254 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1255 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1256 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1257 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1258 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1259 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1260 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1261 } else { 1262 ptr = (u_int8_t *) pSRB->CmdBlock; 1263 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1264 command = *ptr++; 1265 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1266 } 1267 } 1268 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1269 /* 1270 * If trm_StartSCSI return 1 : 1271 * current interrupt status is interrupt disreenable 1272 * It's said that SCSI processor has more one SRB need to do, 1273 * SCSI processor has been occupied by one SRB. 1274 */ 1275 pSRB->SRBState = SRB_READY; 1276 return_code = 1; 1277 } else { 1278 /* 1279 * If trm_StartSCSI return 0 : 1280 * current interrupt status is interrupt enable 1281 * It's said that SCSI processor is unoccupied 1282 */ 1283 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1284 pACB->pActiveDCB = pDCB; 1285 pDCB->pActiveSRB = pSRB; 1286 return_code = 0; 1287 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1288 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1289 /* 1290 * SCSI cammand 1291 */ 1292 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1293 } 1294 return (return_code); 1295 } 1296 1297 static void 1298 trm_Interrupt(vpACB) 1299 void *vpACB; 1300 { 1301 PACB pACB; 1302 PDCB pDCB; 1303 PSRB pSRB; 1304 u_int16_t phase; 1305 void (*stateV)(PACB, PSRB, u_int16_t *); 1306 u_int16_t scsi_status=0; 1307 u_int8_t scsi_intstatus; 1308 1309 pACB = vpACB; 1310 1311 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1312 if (!(scsi_status & SCSIINTERRUPT)) { 1313 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1314 return; 1315 } 1316 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1317 1318 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1319 1320 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1321 1322 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1323 trm_Disconnect(pACB); 1324 return; 1325 } 1326 1327 if (scsi_intstatus & INT_RESELECTED) { 1328 trm_Reselect(pACB); 1329 return; 1330 } 1331 if (scsi_intstatus & INT_SCSIRESET) { 1332 trm_ScsiRstDetect(pACB); 1333 return; 1334 } 1335 1336 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1337 pDCB = pACB->pActiveDCB; 1338 KASSERT(pDCB != NULL, ("no active DCB")); 1339 pSRB = pDCB->pActiveSRB; 1340 if (pDCB->DCBFlag & ABORT_DEV_) 1341 trm_EnableMsgOutAbort1(pACB, pSRB); 1342 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1343 stateV = (void *) trm_SCSI_phase0[phase]; 1344 stateV(pACB, pSRB, &scsi_status); 1345 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1346 /* phase:0,1,2,3,4,5,6,7 */ 1347 phase = (u_int16_t) scsi_status & PHASEMASK; 1348 stateV = (void *) trm_SCSI_phase1[phase]; 1349 stateV(pACB, pSRB, &scsi_status); 1350 } 1351 } 1352 1353 static void 1354 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1355 { 1356 1357 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1358 *pscsi_status = PH_BUS_FREE; 1359 /*.. initial phase*/ 1360 } 1361 1362 static void 1363 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1364 { 1365 u_int8_t bval; 1366 u_int16_t i, cnt; 1367 u_int8_t * ptr; 1368 PDCB pDCB; 1369 1370 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1371 pDCB = pACB->pActiveDCB; 1372 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1373 cnt = pSRB->MsgCnt; 1374 if (cnt) { 1375 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1376 for (i = 0; i < cnt; i++) { 1377 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1378 ptr++; 1379 } 1380 pSRB->MsgCnt = 0; 1381 if ((pDCB->DCBFlag & ABORT_DEV_) && 1382 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1383 pSRB->SRBState = SRB_ABORT_SENT; 1384 } 1385 } else { 1386 bval = MSG_ABORT; 1387 if ((pSRB->CmdBlock[0] == INQUIRY) || 1388 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1389 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1390 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1391 goto mop1; 1392 } 1393 } 1394 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1395 } 1396 } else { 1397 mop1: /* message out phase */ 1398 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1399 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1400 /* 1401 * WIDE DATA TRANSFER REQUEST code (03h) 1402 */ 1403 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1404 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1405 TRMREG_SCSI_FIFO); 1406 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1407 /* (01h) */ 1408 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1409 /* Message length (02h) */ 1410 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1411 /* wide data xfer (03h) */ 1412 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1413 /* width:0(8bit),1(16bit),2(32bit) */ 1414 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1415 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1416 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1417 /* 1418 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1419 */ 1420 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1421 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1422 TRMREG_SCSI_FIFO); 1423 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1424 /* (01h) */ 1425 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1426 /* Message length (03h) */ 1427 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1428 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1429 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1430 /* Transfer peeriod factor */ 1431 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1432 TRMREG_SCSI_FIFO); 1433 /* REQ/ACK offset */ 1434 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1435 } 1436 } 1437 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1438 /* it's important for atn stop */ 1439 /* 1440 * SCSI cammand 1441 */ 1442 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1443 } 1444 1445 static void 1446 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1447 { 1448 1449 } 1450 1451 static void 1452 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1453 { 1454 PDCB pDCB; 1455 u_int8_t * ptr; 1456 u_int16_t i, cnt; 1457 union ccb *pccb; 1458 struct ccb_scsiio *pcsio; 1459 1460 pccb = pSRB->pccb; 1461 pcsio = &pccb->csio; 1462 1463 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1464 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1465 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1466 ptr = (u_int8_t *) pSRB->CmdBlock; 1467 for (i = 0; i < cnt; i++) { 1468 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1469 ptr++; 1470 } 1471 } else { 1472 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1473 pDCB = pACB->pActiveDCB; 1474 /* target id */ 1475 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1476 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1477 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1478 /* sizeof(struct scsi_sense_data) */ 1479 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1480 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1481 } 1482 pSRB->SRBState = SRB_COMMAND; 1483 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1484 /* it's important for atn stop*/ 1485 /* 1486 * SCSI cammand 1487 */ 1488 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1489 } 1490 1491 static void 1492 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1493 { 1494 PDCB pDCB; 1495 u_int8_t TempDMAstatus,SGIndexTemp; 1496 u_int16_t scsi_status; 1497 PSEG pseg; 1498 u_long TempSRBXferredLength,dLeftCounter=0; 1499 1500 pDCB = pSRB->pSRBDCB; 1501 scsi_status = *pscsi_status; 1502 1503 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1504 if (scsi_status & PARITYERROR) 1505 pSRB->SRBStatus |= PARITY_ERROR; 1506 if (!(scsi_status & SCSIXFERDONE)) { 1507 /* 1508 * when data transfer from DMA FIFO to SCSI FIFO 1509 * if there was some data left in SCSI FIFO 1510 */ 1511 dLeftCounter = (u_long) 1512 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1513 if (pDCB->SyncPeriod & WIDE_SYNC) { 1514 /* 1515 * if WIDE scsi SCSI FIFOCNT unit is word 1516 * so need to * 2 1517 */ 1518 dLeftCounter <<= 1; 1519 } 1520 } 1521 /* 1522 * caculate all the residue data that not yet tranfered 1523 * SCSI transfer counter + left in SCSI FIFO data 1524 * 1525 * .....TRM_SCSI_COUNTER (24bits) 1526 * The counter always decrement by one for every SCSI byte 1527 *transfer. 1528 * .....TRM_SCSI_FIFOCNT (5bits) 1529 * The counter is SCSI FIFO offset counter 1530 */ 1531 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1532 if (dLeftCounter == 1) { 1533 dLeftCounter = 0; 1534 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1535 } 1536 if ((dLeftCounter == 0) || 1537 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1538 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1539 while (!(TempDMAstatus & DMAXFERCOMP)) { 1540 TempDMAstatus = 1541 trm_reg_read8(TRMREG_DMA_STATUS); 1542 } 1543 pSRB->SRBTotalXferLength = 0; 1544 } else { 1545 /* Update SG list */ 1546 /* 1547 * if transfer not yet complete 1548 * there were some data residue in SCSI FIFO or 1549 * SCSI transfer counter not empty 1550 */ 1551 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1552 /* 1553 * data that had transferred length 1554 */ 1555 TempSRBXferredLength = 1556 pSRB->SRBTotalXferLength - dLeftCounter; 1557 /* 1558 * next time to be transferred length 1559 */ 1560 pSRB->SRBTotalXferLength = dLeftCounter; 1561 /* 1562 * parsing from last time disconnect SRBSGIndex 1563 */ 1564 pseg = 1565 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1566 for (SGIndexTemp = pSRB->SRBSGIndex; 1567 SGIndexTemp < pSRB->SRBSGCount; 1568 SGIndexTemp++) { 1569 /* 1570 * find last time which SG transfer be 1571 * disconnect 1572 */ 1573 if (TempSRBXferredLength >= 1574 pseg->length) 1575 TempSRBXferredLength -= 1576 pseg->length; 1577 else { 1578 /* 1579 * update last time disconnected SG 1580 * list 1581 */ 1582 pseg->length -= 1583 TempSRBXferredLength; 1584 /* residue data length */ 1585 pseg->address += 1586 TempSRBXferredLength; 1587 /* residue data pointer */ 1588 pSRB->SRBSGIndex = SGIndexTemp; 1589 break; 1590 } 1591 pseg++; 1592 } 1593 } 1594 } 1595 } 1596 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1597 } 1598 1599 1600 static void 1601 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1602 { 1603 u_int16_t ioDir; 1604 /* 1605 * do prepare befor transfer when data out phase 1606 */ 1607 1608 ioDir = XFERDATAOUT; 1609 trm_DataIO_transfer(pACB, pSRB, ioDir); 1610 } 1611 1612 static void 1613 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1614 { 1615 u_int8_t TempDMAstatus, SGIndexTemp; 1616 u_int16_t scsi_status; 1617 PSEG pseg; 1618 u_long TempSRBXferredLength,dLeftCounter = 0; 1619 1620 scsi_status = *pscsi_status; 1621 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1622 if (scsi_status & PARITYERROR) 1623 pSRB->SRBStatus |= PARITY_ERROR; 1624 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1625 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1626 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1627 while (!(TempDMAstatus & DMAXFERCOMP)) 1628 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1629 pSRB->SRBTotalXferLength = 0; 1630 } else { 1631 /* 1632 * parsing the case: 1633 * when a transfer not yet complete 1634 * but be disconnected by uper layer 1635 * if transfer not yet complete 1636 * there were some data residue in SCSI FIFO or 1637 * SCSI transfer counter not empty 1638 */ 1639 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1640 /* 1641 * data that had transferred length 1642 */ 1643 TempSRBXferredLength = 1644 pSRB->SRBTotalXferLength - dLeftCounter; 1645 /* 1646 * next time to be transferred length 1647 */ 1648 pSRB->SRBTotalXferLength = dLeftCounter; 1649 /* 1650 * parsing from last time disconnect SRBSGIndex 1651 */ 1652 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1653 for (SGIndexTemp = pSRB->SRBSGIndex; 1654 SGIndexTemp < pSRB->SRBSGCount; 1655 SGIndexTemp++) { 1656 /* 1657 * find last time which SG transfer be disconnect 1658 */ 1659 if (TempSRBXferredLength >= pseg->length) 1660 TempSRBXferredLength -= pseg->length; 1661 else { 1662 /* 1663 * update last time disconnected SG list 1664 */ 1665 pseg->length -= TempSRBXferredLength; 1666 /* residue data length */ 1667 pseg->address += TempSRBXferredLength; 1668 /* residue data pointer */ 1669 pSRB->SRBSGIndex = SGIndexTemp; 1670 break; 1671 } 1672 pseg++; 1673 } 1674 } 1675 } 1676 } 1677 } 1678 1679 static void 1680 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1681 { 1682 u_int16_t ioDir; 1683 /* 1684 * do prepare befor transfer when data in phase 1685 */ 1686 1687 ioDir = XFERDATAIN; 1688 trm_DataIO_transfer(pACB, pSRB, ioDir); 1689 } 1690 1691 static void 1692 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1693 { 1694 u_int8_t bval; 1695 PDCB pDCB; 1696 1697 pDCB = pSRB->pSRBDCB; 1698 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1699 if (pSRB->SRBTotalXferLength != 0) { 1700 /* 1701 * load what physical address of Scatter/Gather list 1702 table want to be transfer 1703 */ 1704 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1705 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1706 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1707 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1708 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1709 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1710 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1711 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1712 1713 pSRB->SRBState = SRB_DATA_XFER; 1714 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1715 trm_reg_write32( 1716 (pSRB->SRBSGPhyAddr + 1717 ((u_long)pSRB->SRBSGIndex << 3)), 1718 TRMREG_DMA_XLOWADDR); 1719 /* 1720 * load how many bytes in the Scatter/Gather 1721 * list table 1722 */ 1723 trm_reg_write32( 1724 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1725 TRMREG_DMA_XCNT); 1726 /* 1727 * load total transfer length (24bits) max value 1728 * 16Mbyte 1729 */ 1730 trm_reg_write32(pSRB->SRBTotalXferLength, 1731 TRMREG_SCSI_COUNTER); 1732 /* Start DMA transfer */ 1733 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1734 /* Start SCSI transfer */ 1735 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1736 /* it's important for atn stop */ 1737 /* 1738 * SCSI cammand 1739 */ 1740 bval = (ioDir == XFERDATAOUT) ? 1741 SCMD_DMA_OUT : SCMD_DMA_IN; 1742 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1743 } else { 1744 /* xfer pad */ 1745 if (pSRB->SRBSGCount) { 1746 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1747 pSRB->SRBStatus |= OVER_RUN; 1748 } 1749 if (pDCB->SyncPeriod & WIDE_SYNC) 1750 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1751 else 1752 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1753 if (ioDir == XFERDATAOUT) 1754 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1755 else 1756 trm_reg_read16(TRMREG_SCSI_FIFO); 1757 pSRB->SRBState |= SRB_XFERPAD; 1758 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1759 /* it's important for atn stop */ 1760 /* 1761 * SCSI cammand 1762 */ 1763 bval = (ioDir == XFERDATAOUT) ? 1764 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1765 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1766 } 1767 } 1768 } 1769 1770 static void 1771 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1772 { 1773 1774 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1775 pSRB->SRBState = SRB_COMPLETED; 1776 *pscsi_status = PH_BUS_FREE; 1777 /*.. initial phase*/ 1778 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1779 /* it's important for atn stop */ 1780 /* 1781 * SCSI cammand 1782 */ 1783 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1784 } 1785 1786 1787 1788 static void 1789 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1790 { 1791 1792 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1793 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1794 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1795 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1796 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1797 } else { 1798 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1799 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1800 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1801 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1802 } 1803 pSRB->SRBState = SRB_STATUS; 1804 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1805 /* it's important for atn stop */ 1806 /* 1807 * SCSI cammand 1808 */ 1809 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1810 } 1811 1812 /* 1813 *scsiiom 1814 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1815 * stateV = (void *) trm_SCSI_phase0[phase] 1816 * if phase =7 1817 * extended message codes: 1818 * 1819 * code description 1820 * 1821 * 02h Reserved 1822 * 00h MODIFY DATA POINTER 1823 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1824 * 03h WIDE DATA TRANSFER REQUEST 1825 * 04h - 7Fh Reserved 1826 * 80h - FFh Vendor specific 1827 * 1828 */ 1829 1830 static void 1831 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1832 { 1833 u_int8_t message_in_code,bIndex,message_in_tag_id; 1834 PDCB pDCB; 1835 PSRB pSRBTemp; 1836 1837 pDCB = pACB->pActiveDCB; 1838 1839 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1840 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1841 if (message_in_code == MSG_DISCONNECT) { 1842 pSRB->SRBState = SRB_DISCONNECT; 1843 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1844 /* it's important for atn stop */ 1845 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1846 /* 1847 * SCSI command 1848 */ 1849 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1850 return; 1851 } else if (message_in_code == MSG_SAVE_PTR) { 1852 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1853 /* it's important for atn stop */ 1854 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1855 /* 1856 * SCSI command 1857 */ 1858 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1859 return; 1860 } else if ((message_in_code == MSG_EXTENDED) || 1861 ((message_in_code >= MSG_SIMPLE_QTAG) && 1862 (message_in_code <= MSG_ORDER_QTAG))) { 1863 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1864 pSRB->MsgInBuf[0] = message_in_code; 1865 /* extended message (01h) */ 1866 pSRB->MsgCnt = 1; 1867 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1868 /* extended message length (n) */ 1869 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1870 /* it's important for atn stop */ 1871 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1872 /* 1873 * SCSI command 1874 */ 1875 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1876 return; 1877 } else if (message_in_code == MSG_REJECT_) { 1878 /* Reject message */ 1879 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1880 /* do wide nego reject */ 1881 pDCB = pSRB->pSRBDCB; 1882 pDCB->SyncMode |= WIDE_NEGO_DONE; 1883 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1884 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1885 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1886 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1887 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1888 /* Set ATN, in case ATN was clear */ 1889 pSRB->SRBState |= SRB_MSGOUT; 1890 trm_reg_write16( 1891 DO_SETATN, 1892 TRMREG_SCSI_CONTROL); 1893 } else { 1894 /* Clear ATN */ 1895 trm_reg_write16( 1896 DO_CLRATN, 1897 TRMREG_SCSI_CONTROL); 1898 } 1899 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1900 /* do sync nego reject */ 1901 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1902 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1903 pDCB = pSRB->pSRBDCB; 1904 pDCB->SyncMode &= 1905 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1906 pDCB->SyncPeriod = 0; 1907 pDCB->SyncOffset = 0; 1908 /* 1909 * 1910 * program SCSI control register 1911 * 1912 */ 1913 trm_reg_write8(pDCB->SyncPeriod, 1914 TRMREG_SCSI_SYNC); 1915 trm_reg_write8(pDCB->SyncOffset, 1916 TRMREG_SCSI_OFFSET); 1917 trm_SetXferRate(pACB,pSRB,pDCB); 1918 } 1919 } 1920 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1921 /* it's important for atn stop */ 1922 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1923 /* 1924 * SCSI command 1925 */ 1926 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1927 return; 1928 } else if (message_in_code == MSG_IGNOREWIDE) { 1929 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1930 trm_reg_read8(TRMREG_SCSI_FIFO); 1931 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1932 /* it's important for atn stop */ 1933 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1934 /* 1935 * SCSI command 1936 */ 1937 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1938 return; 1939 } else { 1940 /* Restore data pointer message */ 1941 /* Save data pointer message */ 1942 /* Completion message */ 1943 /* NOP message */ 1944 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1945 /* it's important for atn stop */ 1946 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1947 /* 1948 * SCSI command 1949 */ 1950 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1951 return; 1952 } 1953 } else { 1954 /* 1955 * Parsing incomming extented messages 1956 */ 1957 *pSRB->pMsgPtr = message_in_code; 1958 pSRB->MsgCnt++; 1959 pSRB->pMsgPtr++; 1960 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1961 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1962 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1963 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1964 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1965 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1966 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1967 /* 1968 * is QUEUE tag message : 1969 * 1970 * byte 0: 1971 * HEAD QUEUE TAG (20h) 1972 * ORDERED QUEUE TAG (21h) 1973 * SIMPLE QUEUE TAG (22h) 1974 * byte 1: 1975 * Queue tag (00h - FFh) 1976 */ 1977 if (pSRB->MsgCnt == 2) { 1978 pSRB->SRBState = 0; 1979 message_in_tag_id = pSRB->MsgInBuf[1]; 1980 pSRB = pDCB->pGoingSRB; 1981 pSRBTemp = pDCB->pGoingLastSRB; 1982 if (pSRB) { 1983 for (;;) { 1984 if (pSRB->TagNumber != 1985 message_in_tag_id) { 1986 if (pSRB == pSRBTemp) { 1987 goto mingx0; 1988 } 1989 pSRB = pSRB->pNextSRB; 1990 } else 1991 break; 1992 } 1993 if (pDCB->DCBFlag & ABORT_DEV_) { 1994 pSRB->SRBState = SRB_ABORT_SENT; 1995 trm_EnableMsgOutAbort1( 1996 pACB, pSRB); 1997 } 1998 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1999 TRM_DPRINTF("SRB not yet disconnect........ \n "); 2000 goto mingx0; 2001 } 2002 pDCB->pActiveSRB = pSRB; 2003 pSRB->SRBState = SRB_DATA_XFER; 2004 } else { 2005 mingx0: 2006 pSRB = &pACB->TmpSRB; 2007 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2008 pDCB->pActiveSRB = pSRB; 2009 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2010 trm_EnableMsgOutAbort2( 2011 pACB, 2012 pSRB); 2013 } 2014 } 2015 *pscsi_status = PH_BUS_FREE; 2016 /* .. initial phase */ 2017 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2018 /* it's important for atn stop */ 2019 /* 2020 * SCSI command 2021 */ 2022 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2023 return; 2024 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2025 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2026 /* 2027 * is Wide data xfer Extended message : 2028 * ====================================== 2029 * WIDE DATA TRANSFER REQUEST 2030 * ====================================== 2031 * byte 0 : Extended message (01h) 2032 * byte 1 : Extended message length (02h) 2033 * byte 2 : WIDE DATA TRANSFER code (03h) 2034 * byte 3 : Transfer width exponent 2035 */ 2036 pDCB = pSRB->pSRBDCB; 2037 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2038 if ((pSRB->MsgInBuf[1] != 2)) { 2039 /* Length is wrong, reject it */ 2040 pDCB->SyncMode &= 2041 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2042 pSRB->MsgCnt = 1; 2043 pSRB->MsgInBuf[0] = MSG_REJECT_; 2044 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2045 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2046 /* it's important for atn stop */ 2047 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2048 /* 2049 * SCSI command 2050 */ 2051 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2052 return; 2053 } 2054 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2055 /* Do wide negoniation */ 2056 if (pSRB->MsgInBuf[3] > 2) { 2057 /* > 32 bit */ 2058 /* reject_msg: */ 2059 pDCB->SyncMode &= 2060 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2061 pSRB->MsgCnt = 1; 2062 pSRB->MsgInBuf[0] = MSG_REJECT_; 2063 trm_reg_write16(DO_SETATN, 2064 TRMREG_SCSI_CONTROL); 2065 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2066 /* it's important for atn stop */ 2067 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2068 /* 2069 * SCSI command 2070 */ 2071 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2072 return; 2073 } 2074 if (pSRB->MsgInBuf[3] == 2) { 2075 pSRB->MsgInBuf[3] = 1; 2076 /* do 16 bits */ 2077 } else { 2078 if (!(pDCB->SyncMode 2079 & WIDE_NEGO_DONE)) { 2080 pSRB->SRBState &= 2081 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2082 pDCB->SyncMode |= 2083 WIDE_NEGO_DONE; 2084 pDCB->SyncMode &= 2085 ~(SYNC_NEGO_DONE | 2086 EN_ATN_STOP | 2087 WIDE_NEGO_ENABLE); 2088 if (pSRB->MsgInBuf[3] != 0) { 2089 /* is Wide data xfer */ 2090 pDCB->SyncPeriod |= 2091 WIDE_SYNC; 2092 pDCB->tinfo.current.width 2093 = MSG_EXT_WDTR_BUS_16_BIT; 2094 pDCB->tinfo.goal.width 2095 = MSG_EXT_WDTR_BUS_16_BIT; 2096 } 2097 } 2098 } 2099 } else 2100 pSRB->MsgInBuf[3] = 0; 2101 pSRB->SRBState |= SRB_MSGOUT; 2102 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2103 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2104 /* it's important for atn stop */ 2105 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2106 /* 2107 * SCSI command 2108 */ 2109 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2110 return; 2111 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2112 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2113 /* 2114 * is 8bit transfer Extended message : 2115 * ================================= 2116 * SYNCHRONOUS DATA TRANSFER REQUEST 2117 * ================================= 2118 * byte 0 : Extended message (01h) 2119 * byte 1 : Extended message length (03) 2120 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2121 * byte 3 : Transfer period factor 2122 * byte 4 : REQ/ACK offset 2123 */ 2124 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2125 if ((pSRB->MsgInBuf[1] != 3) || 2126 (pSRB->MsgInBuf[2] != 1)) { 2127 /* reject_msg: */ 2128 pSRB->MsgCnt = 1; 2129 pSRB->MsgInBuf[0] = MSG_REJECT_; 2130 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2131 *pscsi_status = PH_BUS_FREE; 2132 /* .. initial phase */ 2133 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2134 /* it's important for atn stop */ 2135 /* 2136 * SCSI cammand 2137 */ 2138 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2139 return; 2140 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2141 /* set async */ 2142 pDCB = pSRB->pSRBDCB; 2143 /* disable sync & sync nego */ 2144 pDCB->SyncMode &= 2145 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2146 pDCB->SyncPeriod = 0; 2147 pDCB->SyncOffset = 0; 2148 pDCB->tinfo.goal.period = 0; 2149 pDCB->tinfo.goal.offset = 0; 2150 pDCB->tinfo.current.period = 0; 2151 pDCB->tinfo.current.offset = 0; 2152 pDCB->tinfo.current.width = 2153 MSG_EXT_WDTR_BUS_8_BIT; 2154 /* 2155 * 2156 * program SCSI control register 2157 * 2158 */ 2159 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2160 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2161 trm_SetXferRate(pACB,pSRB,pDCB); 2162 *pscsi_status = PH_BUS_FREE; 2163 /* .. initial phase */ 2164 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2165 /* it's important for atn stop */ 2166 /* 2167 * SCSI cammand 2168 */ 2169 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2170 return; 2171 } else { 2172 /* set sync */ 2173 pDCB = pSRB->pSRBDCB; 2174 pDCB->SyncMode |= 2175 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2176 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2177 /* Transfer period factor */ 2178 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2179 /* REQ/ACK offset */ 2180 if (pACB->AdaptType == 1) { 2181 for(bIndex = 0; bIndex < 7; bIndex++) { 2182 if (pSRB->MsgInBuf[3] <= 2183 dc395u2x_clock_period[bIndex]) { 2184 pDCB->tinfo.goal.period = 2185 dc395u2x_tinfo_period[bIndex]; 2186 pDCB->tinfo.current.period = 2187 dc395u2x_tinfo_period[bIndex]; 2188 pDCB->tinfo.goal.offset = 2189 pDCB->SyncOffset; 2190 pDCB->tinfo.current.offset = 2191 pDCB->SyncOffset; 2192 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2193 break; 2194 } 2195 } 2196 } else { 2197 for(bIndex = 0; bIndex < 7; bIndex++) { 2198 if (pSRB->MsgInBuf[3] <= 2199 dc395x_clock_period[bIndex]) { 2200 pDCB->tinfo.goal.period = 2201 dc395x_tinfo_period[bIndex]; 2202 pDCB->tinfo.current.period = 2203 dc395x_tinfo_period[bIndex]; 2204 pDCB->tinfo.goal.offset = 2205 pDCB->SyncOffset; 2206 pDCB->tinfo.current.offset = 2207 pDCB->SyncOffset; 2208 pDCB->SyncPeriod |= 2209 (bIndex|ALT_SYNC); 2210 break; 2211 } 2212 } 2213 } 2214 /* 2215 * 2216 * program SCSI control register 2217 * 2218 */ 2219 trm_reg_write8(pDCB->SyncPeriod, 2220 TRMREG_SCSI_SYNC); 2221 trm_reg_write8(pDCB->SyncOffset, 2222 TRMREG_SCSI_OFFSET); 2223 trm_SetXferRate(pACB,pSRB,pDCB); 2224 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2225 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2226 /* 2227 ** SCSI command 2228 */ 2229 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2230 return; 2231 } 2232 } 2233 *pscsi_status = PH_BUS_FREE; 2234 /* .. initial phase */ 2235 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2236 /* it's important for atn stop */ 2237 /* 2238 * SCSI cammand 2239 */ 2240 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2241 } 2242 } 2243 2244 static void 2245 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2246 { 2247 2248 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2249 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2250 if (!(pSRB->SRBState & SRB_MSGIN)) { 2251 pSRB->SRBState &= SRB_DISCONNECT; 2252 pSRB->SRBState |= SRB_MSGIN; 2253 } 2254 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2255 /* it's important for atn stop*/ 2256 /* 2257 * SCSI cammand 2258 */ 2259 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2260 } 2261 2262 static void 2263 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2264 { 2265 2266 } 2267 2268 static void 2269 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2270 { 2271 2272 } 2273 2274 static void 2275 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2276 { 2277 union ccb *pccb; 2278 struct ccb_trans_settings neg; 2279 u_int16_t cnt, i; 2280 u_int8_t bval; 2281 PDCB pDCBTemp; 2282 2283 /* 2284 * set all lun device's period , offset 2285 */ 2286 TRM_DPRINTF("trm_SetXferRate\n"); 2287 pccb = pSRB->pccb; 2288 neg.sync_period = pDCB->tinfo.goal.period; 2289 neg.sync_offset = pDCB->tinfo.goal.offset; 2290 neg.valid = CCB_TRANS_SYNC_RATE_VALID | CCB_TRANS_SYNC_OFFSET_VALID; 2291 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2292 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2293 if (!(pDCB->IdentifyMsg & 0x07)) { 2294 pDCBTemp = pACB->pLinkDCB; 2295 cnt = pACB->DeviceCnt; 2296 bval = pDCB->TargetID; 2297 for (i = 0; i < cnt; i++) { 2298 if (pDCBTemp->TargetID == bval) { 2299 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2300 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2301 pDCBTemp->SyncMode = pDCB->SyncMode; 2302 } 2303 pDCBTemp = pDCBTemp->pNextDCB; 2304 } 2305 } 2306 return; 2307 } 2308 2309 /* 2310 * scsiiom 2311 * trm_Interrupt 2312 * 2313 * 2314 * ---SCSI bus phase 2315 * 2316 * PH_DATA_OUT 0x00 Data out phase 2317 * PH_DATA_IN 0x01 Data in phase 2318 * PH_COMMAND 0x02 Command phase 2319 * PH_STATUS 0x03 Status phase 2320 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2321 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2322 * PH_MSG_OUT 0x06 Message out phase 2323 * PH_MSG_IN 0x07 Message in phase 2324 * 2325 */ 2326 static void 2327 trm_Disconnect(PACB pACB) 2328 { 2329 PDCB pDCB; 2330 PSRB pSRB, psrb; 2331 u_int16_t i,j, cnt; 2332 u_int target_id,target_lun; 2333 2334 TRM_DPRINTF("trm_Disconnect...............\n "); 2335 2336 pDCB = pACB->pActiveDCB; 2337 if (!pDCB) { 2338 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2339 j = 400; 2340 while (--j) 2341 DELAY(1); 2342 /* 1 msec */ 2343 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2344 TRMREG_SCSI_CONTROL); 2345 return; 2346 } 2347 pSRB = pDCB->pActiveSRB; 2348 /* bug pSRB=0 */ 2349 target_id = pSRB->pccb->ccb_h.target_id; 2350 target_lun = pSRB->pccb->ccb_h.target_lun; 2351 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2352 pACB->pActiveDCB = 0; 2353 pSRB->ScsiPhase = PH_BUS_FREE; 2354 /* SCSI bus free Phase */ 2355 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2356 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2357 pSRB->SRBState = 0; 2358 trm_DoWaitingSRB(pACB); 2359 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2360 pDCB->DCBFlag = 0; 2361 cnt = pDCB->GoingSRBCnt; 2362 pDCB->GoingSRBCnt = 0; 2363 pSRB = pDCB->pGoingSRB; 2364 for (i = 0; i < cnt; i++) { 2365 psrb = pSRB->pNextSRB; 2366 pSRB->pNextSRB = pACB->pFreeSRB; 2367 pACB->pFreeSRB = pSRB; 2368 pSRB = psrb; 2369 } 2370 pDCB->pGoingSRB = 0; 2371 trm_DoWaitingSRB(pACB); 2372 } else { 2373 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2374 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2375 /* Selection time out */ 2376 if (!(pACB->scan_devices[target_id][target_lun]) && 2377 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2378 pSRB->CmdBlock[0] != INQUIRY) { 2379 pSRB->SRBState = SRB_READY; 2380 trm_RewaitSRB(pDCB, pSRB); 2381 } else { 2382 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2383 goto disc1; 2384 } 2385 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2386 /* 2387 * SRB_DISCONNECT 2388 */ 2389 trm_DoWaitingSRB(pACB); 2390 } else if (pSRB->SRBState & SRB_COMPLETED) { 2391 disc1: 2392 /* 2393 * SRB_COMPLETED 2394 */ 2395 pDCB->pActiveSRB = 0; 2396 pSRB->SRBState = SRB_FREE; 2397 trm_SRBdone(pACB, pDCB, pSRB); 2398 } 2399 } 2400 return; 2401 } 2402 2403 static void 2404 trm_Reselect(PACB pACB) 2405 { 2406 PDCB pDCB; 2407 PSRB pSRB; 2408 u_int16_t RselTarLunId; 2409 2410 TRM_DPRINTF("trm_Reselect................. \n"); 2411 pDCB = pACB->pActiveDCB; 2412 if (pDCB) { 2413 /* Arbitration lost but Reselection win */ 2414 pSRB = pDCB->pActiveSRB; 2415 pSRB->SRBState = SRB_READY; 2416 trm_RewaitSRB(pDCB, pSRB); 2417 } 2418 /* Read Reselected Target Id and LUN */ 2419 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2420 pDCB = pACB->pLinkDCB; 2421 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2422 /* get pDCB of the reselect id */ 2423 pDCB = pDCB->pNextDCB; 2424 } 2425 2426 pACB->pActiveDCB = pDCB; 2427 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2428 pSRB = &pACB->TmpSRB; 2429 pDCB->pActiveSRB = pSRB; 2430 } else { 2431 pSRB = pDCB->pActiveSRB; 2432 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2433 /* 2434 * abort command 2435 */ 2436 pSRB = &pACB->TmpSRB; 2437 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2438 pDCB->pActiveSRB = pSRB; 2439 trm_EnableMsgOutAbort1(pACB, pSRB); 2440 } else { 2441 if (pDCB->DCBFlag & ABORT_DEV_) { 2442 pSRB->SRBState = SRB_ABORT_SENT; 2443 trm_EnableMsgOutAbort1(pACB, pSRB); 2444 } else 2445 pSRB->SRBState = SRB_DATA_XFER; 2446 } 2447 } 2448 pSRB->ScsiPhase = PH_BUS_FREE; 2449 /* SCSI bus free Phase */ 2450 /* 2451 * Program HA ID, target ID, period and offset 2452 */ 2453 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2454 /* target ID */ 2455 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2456 /* host ID */ 2457 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2458 /* period */ 2459 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2460 /* offset */ 2461 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2462 /* it's important for atn stop*/ 2463 /* 2464 * SCSI cammand 2465 */ 2466 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2467 /* to rls the /ACK signal */ 2468 } 2469 2470 static void 2471 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2472 { 2473 PSRB psrb; 2474 u_int8_t bval, bval1,status; 2475 union ccb *pccb; 2476 struct ccb_scsiio *pcsio; 2477 PSCSI_INQDATA ptr; 2478 int intflag; 2479 u_int target_id,target_lun; 2480 PDCB pTempDCB; 2481 2482 pccb = pSRB->pccb; 2483 if (pccb == NULL) 2484 return; 2485 pcsio = &pccb->csio; 2486 target_id = pSRB->pccb->ccb_h.target_id; 2487 target_lun = pSRB->pccb->ccb_h.target_lun; 2488 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2489 bus_dmasync_op_t op; 2490 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2491 op = BUS_DMASYNC_POSTREAD; 2492 else 2493 op = BUS_DMASYNC_POSTWRITE; 2494 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2495 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2496 } 2497 /* 2498 * 2499 * target status 2500 * 2501 */ 2502 status = pSRB->TargetStatus; 2503 pcsio->scsi_status=SCSI_STAT_GOOD; 2504 pccb->ccb_h.status = CAM_REQ_CMP; 2505 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2506 /* 2507 * status of auto request sense 2508 */ 2509 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2510 pSRB->AdaptStatus = 0; 2511 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2512 2513 if (status == SCSI_STATUS_CHECK_COND) { 2514 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2515 goto ckc_e; 2516 } 2517 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2518 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2519 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2520 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2521 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2522 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2523 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2524 pcsio->sense_len); 2525 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2526 | CAM_AUTOSNS_VALID; 2527 goto ckc_e; 2528 } 2529 /* 2530 * target status 2531 */ 2532 if (status) { 2533 if (status == SCSI_STATUS_CHECK_COND) { 2534 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2535 TRM_DPRINTF("trm_RequestSense..................\n"); 2536 trm_RequestSense(pACB, pDCB, pSRB); 2537 return; 2538 } 2539 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2540 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2541 goto ckc_e; 2542 } else if (status == SCSI_STAT_QUEUEFULL) { 2543 bval = (u_int8_t) pDCB->GoingSRBCnt; 2544 bval--; 2545 pDCB->MaxActiveCommandCnt = bval; 2546 trm_RewaitSRB(pDCB, pSRB); 2547 pSRB->AdaptStatus = 0; 2548 pSRB->TargetStatus = 0; 2549 return; 2550 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2551 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2552 pSRB->TargetStatus = 0; 2553 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2554 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2555 } else if (status == SCSI_STAT_BUSY) { 2556 TRM_DPRINTF("trm: target busy at %s %d\n", 2557 __FILE__, __LINE__); 2558 pcsio->scsi_status = SCSI_STAT_BUSY; 2559 pccb->ccb_h.status = CAM_SCSI_BUSY; 2560 return; 2561 /* The device busy, try again later? */ 2562 } else if (status == SCSI_STAT_RESCONFLICT) { 2563 TRM_DPRINTF("trm: target reserved at %s %d\n", 2564 __FILE__, __LINE__); 2565 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2566 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2567 return; 2568 } else { 2569 pSRB->AdaptStatus = 0; 2570 if (pSRB->RetryCnt) { 2571 pSRB->RetryCnt--; 2572 pSRB->TargetStatus = 0; 2573 pSRB->SRBSGIndex = 0; 2574 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2575 /* 2576 * If trm_StartSCSI return 1 : 2577 * current interrupt status is interrupt 2578 * disreenable 2579 * It's said that SCSI processor has more 2580 * one SRB need to do 2581 */ 2582 trm_RewaitSRB(pDCB, pSRB); 2583 } 2584 return; 2585 } else { 2586 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2587 __FILE__, __LINE__); 2588 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2589 } 2590 } 2591 } else { 2592 /* 2593 * process initiator status.......................... 2594 * Adapter (initiator) status 2595 */ 2596 status = pSRB->AdaptStatus; 2597 if (status & H_OVER_UNDER_RUN) { 2598 pSRB->TargetStatus = 0; 2599 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2600 /* Illegal length (over/under run) */ 2601 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2602 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2603 __FILE__, __LINE__); 2604 pDCB->tinfo.goal.period = 0; 2605 pDCB->tinfo.goal.offset = 0; 2606 /* Driver failed to perform operation */ 2607 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2608 } else { 2609 /* no error */ 2610 pSRB->AdaptStatus = 0; 2611 pSRB->TargetStatus = 0; 2612 pccb->ccb_h.status = CAM_REQ_CMP; 2613 /* there is no error, (sense is invalid) */ 2614 } 2615 } 2616 ckc_e: 2617 if (pACB->scan_devices[target_id][target_lun]) { 2618 /* 2619 * if SCSI command in "scan devices" duty 2620 */ 2621 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2622 pACB->scan_devices[target_id][target_lun] = 0; 2623 /* SCSI command phase :test unit ready */ 2624 else if (pSRB->CmdBlock[0] == INQUIRY) { 2625 /* 2626 * SCSI command phase :inquiry scsi device data 2627 * (type,capacity,manufacture.... 2628 */ 2629 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2630 goto NO_DEV; 2631 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2632 /* page fault */ 2633 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2634 ptr->DevType); 2635 bval1 = ptr->DevType & SCSI_DEVTYPE; 2636 if (bval1 == SCSI_NODEV) { 2637 NO_DEV: 2638 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2639 target_id, 2640 target_lun); 2641 intflag = splcam(); 2642 pACB->scan_devices[target_id][target_lun] = 0; 2643 /* no device set scan device flag =0*/ 2644 /* pDCB Q link */ 2645 /* move the head of DCB to tempDCB*/ 2646 pTempDCB=pACB->pLinkDCB; 2647 /* search current DCB for pass link */ 2648 while (pTempDCB->pNextDCB != pDCB) { 2649 pTempDCB = pTempDCB->pNextDCB; 2650 } 2651 /* 2652 * when the current DCB found than connect 2653 * current DCB tail 2654 */ 2655 /* to the DCB tail that before current DCB */ 2656 pTempDCB->pNextDCB = pDCB->pNextDCB; 2657 /* 2658 * if there was only one DCB ,connect his tail 2659 * to his head 2660 */ 2661 if (pACB->pLinkDCB == pDCB) 2662 pACB->pLinkDCB = pTempDCB->pNextDCB; 2663 if (pACB->pDCBRunRobin == pDCB) 2664 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2665 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2666 pACB->DeviceCnt--; 2667 if (pACB->DeviceCnt == 0) { 2668 pACB->pLinkDCB = NULL; 2669 pACB->pDCBRunRobin = NULL; 2670 } 2671 splx(intflag); 2672 } else { 2673 #ifdef trm_DEBUG1 2674 int j; 2675 for (j = 0; j < 28; j++) { 2676 TRM_DPRINTF("ptr=%2x ", 2677 ((u_int8_t *)ptr)[j]); 2678 } 2679 #endif 2680 pDCB->DevType = bval1; 2681 if (bval1 == SCSI_DASD || 2682 bval1 == SCSI_OPTICAL) { 2683 if ((((ptr->Vers & 0x07) >= 2) || 2684 ((ptr->RDF & 0x0F) == 2)) && 2685 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2686 (pDCB->DevMode & TAG_QUEUING_) && 2687 (pDCB->DevMode & EN_DISCONNECT_)) { 2688 if (pDCB->DevMode & 2689 TAG_QUEUING_) { 2690 pDCB-> 2691 MaxActiveCommandCnt = 2692 pACB->TagMaxNum; 2693 pDCB->SyncMode |= 2694 EN_TAG_QUEUING; 2695 pDCB->tinfo.disc_tag |= 2696 TRM_CUR_TAGENB; 2697 } else { 2698 pDCB->SyncMode |= 2699 EN_ATN_STOP; 2700 pDCB->tinfo.disc_tag &= 2701 ~TRM_CUR_TAGENB; 2702 } 2703 } 2704 } 2705 } 2706 /* pSRB->CmdBlock[0] == INQUIRY */ 2707 } 2708 /* pACB->scan_devices[target_id][target_lun] */ 2709 } 2710 intflag = splcam(); 2711 /* ReleaseSRB(pDCB, pSRB); */ 2712 if (pSRB == pDCB->pGoingSRB) 2713 pDCB->pGoingSRB = pSRB->pNextSRB; 2714 else { 2715 psrb = pDCB->pGoingSRB; 2716 while (psrb->pNextSRB != pSRB) { 2717 psrb = psrb->pNextSRB; 2718 } 2719 psrb->pNextSRB = pSRB->pNextSRB; 2720 if (pSRB == pDCB->pGoingLastSRB) { 2721 pDCB->pGoingLastSRB = psrb; 2722 } 2723 } 2724 pSRB->pNextSRB = pACB->pFreeSRB; 2725 pACB->pFreeSRB = pSRB; 2726 pDCB->GoingSRBCnt--; 2727 trm_DoWaitingSRB(pACB); 2728 2729 splx(intflag); 2730 /* Notify cmd done */ 2731 xpt_done (pccb); 2732 } 2733 2734 static void 2735 trm_DoingSRB_Done(PACB pACB) 2736 { 2737 PDCB pDCB, pdcb; 2738 PSRB psrb, psrb2; 2739 u_int16_t cnt, i; 2740 union ccb *pccb; 2741 2742 pDCB = pACB->pLinkDCB; 2743 if (pDCB == NULL) 2744 return; 2745 pdcb = pDCB; 2746 do { 2747 cnt = pdcb->GoingSRBCnt; 2748 psrb = pdcb->pGoingSRB; 2749 for (i = 0; i < cnt; i++) { 2750 psrb2 = psrb->pNextSRB; 2751 pccb = psrb->pccb; 2752 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2753 /* ReleaseSRB(pDCB, pSRB); */ 2754 psrb->pNextSRB = pACB->pFreeSRB; 2755 pACB->pFreeSRB = psrb; 2756 xpt_done(pccb); 2757 psrb = psrb2; 2758 } 2759 pdcb->GoingSRBCnt = 0;; 2760 pdcb->pGoingSRB = NULL; 2761 pdcb = pdcb->pNextDCB; 2762 } 2763 while (pdcb != pDCB); 2764 } 2765 2766 static void 2767 trm_ResetSCSIBus(PACB pACB) 2768 { 2769 int intflag; 2770 2771 intflag = splcam(); 2772 pACB->ACBFlag |= RESET_DEV; 2773 2774 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2775 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2776 splx(intflag); 2777 return; 2778 } 2779 2780 static void 2781 trm_ScsiRstDetect(PACB pACB) 2782 { 2783 int intflag; 2784 u_long wlval; 2785 2786 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2787 wlval = 1000; 2788 while (--wlval) 2789 DELAY(1000); 2790 intflag = splcam(); 2791 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2792 2793 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2794 2795 if (pACB->ACBFlag & RESET_DEV) 2796 pACB->ACBFlag |= RESET_DONE; 2797 else { 2798 pACB->ACBFlag |= RESET_DETECT; 2799 trm_ResetDevParam(pACB); 2800 /* trm_DoingSRB_Done(pACB); ???? */ 2801 trm_RecoverSRB(pACB); 2802 pACB->pActiveDCB = NULL; 2803 pACB->ACBFlag = 0; 2804 trm_DoWaitingSRB(pACB); 2805 } 2806 splx(intflag); 2807 return; 2808 } 2809 2810 static void 2811 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2812 { 2813 union ccb *pccb; 2814 struct ccb_scsiio *pcsio; 2815 2816 pccb = pSRB->pccb; 2817 pcsio = &pccb->csio; 2818 2819 pSRB->SRBFlag |= AUTO_REQSENSE; 2820 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2821 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2822 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2823 pSRB->SRBSGCount); 2824 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2825 2826 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2827 pSRB->AdaptStatus = 0; 2828 pSRB->TargetStatus = 0; 2829 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2830 2831 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2832 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2833 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2834 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2835 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2836 pSRB->SRBSGCount = 1; 2837 pSRB->SRBSGIndex = 0; 2838 2839 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2840 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2841 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2842 pSRB->ScsiCmdLen = 6; 2843 2844 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2845 /* 2846 * If trm_StartSCSI return 1 : 2847 * current interrupt status is interrupt disreenable 2848 * It's said that SCSI processor has more one SRB need to do 2849 */ 2850 trm_RewaitSRB(pDCB, pSRB); 2851 } 2852 2853 static void 2854 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2855 { 2856 2857 pSRB->MsgCnt = 1; 2858 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2859 } 2860 2861 static void 2862 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2863 { 2864 2865 pSRB->MsgOutBuf[0] = MSG_ABORT; 2866 trm_EnableMsgOutAbort2(pACB, pSRB); 2867 } 2868 2869 static void 2870 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2871 { 2872 PNVRAMTYPE pEEpromBuf; 2873 u_int8_t bval,PeriodIndex; 2874 u_int target_id,target_lun; 2875 PDCB pTempDCB; 2876 int intflag; 2877 2878 target_id = i; 2879 target_lun = j; 2880 2881 /* 2882 * Using the lun 0 device to init other DCB first, if the device 2883 * has been initialized. 2884 * I don't want init sync arguments one by one, it is the same. 2885 */ 2886 if (target_lun != 0 && 2887 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2888 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2889 sizeof(TRM_DCB)); 2890 intflag = splcam(); 2891 if (pACB->pLinkDCB == 0) { 2892 pACB->pLinkDCB = pDCB; 2893 /* 2894 * RunRobin impersonate the role 2895 * that let each device had good proportion 2896 * about SCSI command proceeding 2897 */ 2898 pACB->pDCBRunRobin = pDCB; 2899 pDCB->pNextDCB = pDCB; 2900 } else { 2901 pTempDCB=pACB->pLinkDCB; 2902 /* search the last nod of DCB link */ 2903 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2904 pTempDCB = pTempDCB->pNextDCB; 2905 /* connect current DCB with last DCB tail */ 2906 pTempDCB->pNextDCB = pDCB; 2907 /* connect current DCB tail to this DCB Q head */ 2908 pDCB->pNextDCB=pACB->pLinkDCB; 2909 } 2910 splx(intflag); 2911 2912 pACB->DeviceCnt++; 2913 pDCB->TargetID = target_id; 2914 pDCB->TargetLUN = target_lun; 2915 pDCB->pWaitingSRB = NULL; 2916 pDCB->pGoingSRB = NULL; 2917 pDCB->GoingSRBCnt = 0; 2918 pDCB->pActiveSRB = NULL; 2919 pDCB->MaxActiveCommandCnt = 1; 2920 pDCB->DCBFlag = 0; 2921 pDCB->DCBstatus |= DS_IN_QUEUE; 2922 /* $$$$$$$ */ 2923 pEEpromBuf = &trm_eepromBuf[unit]; 2924 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2925 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2926 /* $$$$$$$ */ 2927 /* 2928 * disconnect enable ? 2929 */ 2930 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2931 bval = 0xC0; 2932 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2933 } else { 2934 bval = 0x80; 2935 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2936 } 2937 bval |= target_lun; 2938 pDCB->IdentifyMsg = bval; 2939 if (target_lun != 0 && 2940 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2941 return; 2942 /* $$$$$$$ */ 2943 /* 2944 * tag Qing enable ? 2945 */ 2946 if (pDCB->DevMode & TAG_QUEUING_) { 2947 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2948 } else 2949 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2950 /* $$$$$$$ */ 2951 /* 2952 * wide nego ,sync nego enable ? 2953 */ 2954 pDCB->SyncPeriod = 0; 2955 pDCB->SyncOffset = 0; 2956 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2957 if (pACB->AdaptType==1) {/* is U2? */ 2958 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2959 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2960 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2961 } else { 2962 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2963 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2964 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2965 } 2966 pDCB->SyncMode = 0; 2967 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2968 (pACB->Config & HCC_WIDE_CARD)) 2969 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2970 /* enable wide nego */ 2971 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2972 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2973 /* enable sync nego */ 2974 /* $$$$$$$ */ 2975 /* 2976 * Fill in tinfo structure. 2977 */ 2978 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2979 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2980 2981 pDCB->tinfo.current.period = 0; 2982 pDCB->tinfo.current.offset = 0; 2983 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2984 } 2985 2986 static void 2987 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2988 { 2989 PSRB pSRB; 2990 2991 pSRB=(PSRB) arg; 2992 pSRB->SRBSGPhyAddr=segs->ds_addr; 2993 return; 2994 } 2995 2996 static void 2997 trm_destroySRB(PACB pACB) 2998 { 2999 PSRB pSRB; 3000 3001 pSRB = pACB->pFreeSRB; 3002 while (pSRB) { 3003 if (pSRB->sg_dmamap) { 3004 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 3005 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 3006 pSRB->sg_dmamap); 3007 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap); 3008 } 3009 if (pSRB->dmamap) 3010 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 3011 pSRB = pSRB->pNextSRB; 3012 } 3013 } 3014 3015 static int 3016 trm_initSRB(PACB pACB) 3017 { 3018 u_int16_t i; 3019 PSRB pSRB; 3020 int error; 3021 3022 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 3023 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3024 3025 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 3026 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3027 return ENXIO; 3028 } 3029 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3030 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3031 trm_srbmapSG, pSRB, /*flags*/0); 3032 if (i != TRM_MAX_SRB_CNT - 1) { 3033 /* 3034 * link all SRB 3035 */ 3036 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3037 } else { 3038 /* 3039 * load NULL to NextSRB of the last SRB 3040 */ 3041 pSRB->pNextSRB = NULL; 3042 } 3043 pSRB->TagNumber = i; 3044 3045 /* 3046 * Create the dmamap. This is no longer optional! 3047 */ 3048 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 3049 &pSRB->dmamap)) != 0) 3050 return (error); 3051 3052 } 3053 return (0); 3054 } 3055 3056 3057 3058 3059 static void 3060 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3061 { 3062 PNVRAMTYPE pEEpromBuf; 3063 3064 pEEpromBuf = &trm_eepromBuf[unit]; 3065 pACB->max_id = 15; 3066 3067 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3068 pACB->max_lun = 7; 3069 else 3070 pACB->max_lun = 0; 3071 3072 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3073 pACB->max_id, pACB->max_lun); 3074 pACB->pLinkDCB = NULL; 3075 pACB->pDCBRunRobin = NULL; 3076 pACB->pActiveDCB = NULL; 3077 pACB->AdapterUnit = (u_int8_t)unit; 3078 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3079 pACB->AdaptSCSILUN = 0; 3080 pACB->DeviceCnt = 0; 3081 pACB->AdaptType = adaptType; 3082 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3083 pACB->ACBFlag = 0; 3084 return; 3085 } 3086 3087 static void 3088 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3089 { 3090 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3091 u_int8_t bAddr; 3092 3093 /* Enable SEEPROM */ 3094 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3095 TRMREG_GEN_CONTROL); 3096 /* 3097 * Write enable 3098 */ 3099 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3100 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3101 NVRAM_trm_wait_30us(pACB); 3102 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3103 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3104 } 3105 /* 3106 * Write disable 3107 */ 3108 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3109 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3110 NVRAM_trm_wait_30us(pACB); 3111 /* Disable SEEPROM */ 3112 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3113 TRMREG_GEN_CONTROL); 3114 return; 3115 } 3116 3117 static void 3118 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3119 { 3120 int i; 3121 u_int8_t bSendData; 3122 /* 3123 * Send write command & address 3124 */ 3125 3126 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3127 /* 3128 * Write data 3129 */ 3130 for (i = 0; i < 8; i++, bData <<= 1) { 3131 bSendData = NVR_SELECT; 3132 if (bData & 0x80) 3133 /* Start from bit 7 */ 3134 bSendData |= NVR_BITOUT; 3135 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3136 NVRAM_trm_wait_30us(pACB); 3137 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3138 NVRAM_trm_wait_30us(pACB); 3139 } 3140 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3141 NVRAM_trm_wait_30us(pACB); 3142 /* 3143 * Disable chip select 3144 */ 3145 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3146 NVRAM_trm_wait_30us(pACB); 3147 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3148 NVRAM_trm_wait_30us(pACB); 3149 /* 3150 * Wait for write ready 3151 */ 3152 while (1) { 3153 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3154 NVRAM_trm_wait_30us(pACB); 3155 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3156 NVRAM_trm_wait_30us(pACB); 3157 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3158 break; 3159 } 3160 } 3161 /* 3162 * Disable chip select 3163 */ 3164 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3165 return; 3166 } 3167 3168 static void 3169 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3170 { 3171 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3172 u_int8_t bAddr; 3173 3174 /* 3175 * Enable SEEPROM 3176 */ 3177 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3178 TRMREG_GEN_CONTROL); 3179 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3180 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3181 /* 3182 * Disable SEEPROM 3183 */ 3184 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3185 TRMREG_GEN_CONTROL); 3186 return; 3187 } 3188 3189 static u_int8_t 3190 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3191 { 3192 int i; 3193 u_int8_t bReadData, bData = 0; 3194 /* 3195 * Send read command & address 3196 */ 3197 3198 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3199 3200 for (i = 0; i < 8; i++) { 3201 /* 3202 * Read data 3203 */ 3204 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3205 NVRAM_trm_wait_30us(pACB); 3206 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3207 /* 3208 * Get data bit while falling edge 3209 */ 3210 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3211 bData <<= 1; 3212 if (bReadData & NVR_BITIN) { 3213 bData |= 1; 3214 } 3215 NVRAM_trm_wait_30us(pACB); 3216 } 3217 /* 3218 * Disable chip select 3219 */ 3220 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3221 return (bData); 3222 } 3223 3224 static void 3225 NVRAM_trm_wait_30us(PACB pACB) 3226 { 3227 3228 /* ScsiPortStallExecution(30); wait 30 us */ 3229 trm_reg_write8(5, TRMREG_GEN_TIMER); 3230 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3231 return; 3232 } 3233 3234 static void 3235 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3236 { 3237 int i; 3238 u_int8_t bSendData; 3239 3240 for (i = 0; i < 3; i++, bCmd <<= 1) { 3241 /* 3242 * Program SB+OP code 3243 */ 3244 bSendData = NVR_SELECT; 3245 if (bCmd & 0x04) 3246 bSendData |= NVR_BITOUT; 3247 /* start from bit 2 */ 3248 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3249 NVRAM_trm_wait_30us(pACB); 3250 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3251 NVRAM_trm_wait_30us(pACB); 3252 } 3253 for (i = 0; i < 7; i++, bAddr <<= 1) { 3254 /* 3255 * Program address 3256 */ 3257 bSendData = NVR_SELECT; 3258 if (bAddr & 0x40) 3259 /* Start from bit 6 */ 3260 bSendData |= NVR_BITOUT; 3261 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3262 NVRAM_trm_wait_30us(pACB); 3263 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3264 NVRAM_trm_wait_30us(pACB); 3265 } 3266 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3267 NVRAM_trm_wait_30us(pACB); 3268 } 3269 3270 static void 3271 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3272 { 3273 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3274 u_int16_t wAddr, wCheckSum; 3275 u_long dAddr, *dpEeprom; 3276 3277 NVRAM_trm_read_all(pEEpromBuf,pACB); 3278 wCheckSum = 0; 3279 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3280 wAddr < 64; wAddr++, wpEeprom++) { 3281 wCheckSum += *wpEeprom; 3282 } 3283 if (wCheckSum != 0x1234) { 3284 /* 3285 * Checksum error, load default 3286 */ 3287 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3288 pEEpromBuf->NvramSubVendorID[1] = 3289 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3290 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3291 pEEpromBuf->NvramSubSysID[1] = 3292 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3293 pEEpromBuf->NvramSubClass = 0x00; 3294 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3295 pEEpromBuf->NvramVendorID[1] = 3296 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3297 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3298 pEEpromBuf->NvramDeviceID[1] = 3299 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3300 pEEpromBuf->NvramReserved = 0x00; 3301 3302 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3303 dAddr < 16; dAddr++, dpEeprom++) { 3304 *dpEeprom = 0x00000077; 3305 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3306 } 3307 3308 *dpEeprom++ = 0x04000F07; 3309 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3310 *dpEeprom++ = 0x00000015; 3311 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3312 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3313 *dpEeprom = 0x00; 3314 pEEpromBuf->NvramCheckSum = 0x00; 3315 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3316 wAddr < 63; wAddr++, wpEeprom++) 3317 wCheckSum += *wpEeprom; 3318 *wpEeprom = 0x1234 - wCheckSum; 3319 NVRAM_trm_write_all(pEEpromBuf,pACB); 3320 } 3321 return; 3322 } 3323 static int 3324 trm_initAdapter(PACB pACB, u_int16_t unit) 3325 { 3326 PNVRAMTYPE pEEpromBuf; 3327 u_int16_t wval; 3328 u_int8_t bval; 3329 3330 pEEpromBuf = &trm_eepromBuf[unit]; 3331 3332 /* 250ms selection timeout */ 3333 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3334 /* Mask all the interrupt */ 3335 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3336 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3337 /* Reset SCSI module */ 3338 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3339 /* program configuration 0 */ 3340 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3341 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3342 pACB->Config |= HCC_WIDE_CARD; 3343 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3344 pACB->Config |= HCC_SCSI_RESET; 3345 if (pACB->Config & HCC_PARITY) 3346 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3347 else 3348 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3349 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3350 /* program configuration 1 */ 3351 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3352 /* program Host ID */ 3353 bval = pEEpromBuf->NvramScsiId; 3354 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3355 /* set ansynchronous transfer */ 3356 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3357 /* Trun LED control off*/ 3358 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3359 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3360 /* DMA config */ 3361 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3362 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3363 /* Clear pending interrupt status */ 3364 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3365 /* Enable SCSI interrupt */ 3366 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3367 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3368 return (0); 3369 } 3370 3371 static void 3372 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3373 { 3374 PACB pACB; 3375 3376 pACB = (PACB)arg; 3377 pACB->srb_physbase = segs->ds_addr; 3378 } 3379 3380 static void 3381 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3382 { 3383 bus_addr_t *baddr; 3384 3385 baddr = (bus_addr_t *)arg; 3386 *baddr = segs->ds_addr; 3387 } 3388 3389 static PACB 3390 trm_init(u_int16_t unit, device_t dev) 3391 { 3392 PACB pACB; 3393 int rid = PCIR_BAR(0), i = 0, j = 0; 3394 u_int16_t adaptType = 0; 3395 3396 pACB = (PACB) device_get_softc(dev); 3397 if (!pACB) { 3398 printf("trm%d: cannot allocate ACB !\n", unit); 3399 return (NULL); 3400 } 3401 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3402 &rid, RF_ACTIVE); 3403 if (pACB->iores == NULL) { 3404 printf("trm_init: bus_alloc_resource failed!\n"); 3405 return (NULL); 3406 } 3407 switch (pci_get_devid(dev)) { 3408 case PCI_DEVICEID_TRMS1040: 3409 adaptType = 0; 3410 break; 3411 case PCI_DEVICEID_TRMS2080: 3412 adaptType = 1; 3413 break; 3414 default: 3415 printf("trm_init %d: unknown adapter type!\n", unit); 3416 goto bad; 3417 } 3418 pACB->dev = dev; 3419 pACB->tag = rman_get_bustag(pACB->iores); 3420 pACB->bsh = rman_get_bushandle(pACB->iores); 3421 if (bus_dma_tag_create( 3422 /*parent_dmat*/ pACB->parent_dmat, 3423 /*alignment*/ 1, 3424 /*boundary*/ 0, 3425 /*lowaddr*/ BUS_SPACE_MAXADDR, 3426 /*highaddr*/ BUS_SPACE_MAXADDR, 3427 /*filter*/ NULL, 3428 /*filterarg*/ NULL, 3429 /*maxsize*/ MAXBSIZE, 3430 /*nsegments*/ TRM_NSEG, 3431 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3432 /*flags*/ BUS_DMA_ALLOCNOW, 3433 /*lockfunc*/ busdma_lock_mutex, 3434 /*lockarg*/ &Giant, 3435 /* dmat */ &pACB->buffer_dmat) != 0) 3436 goto bad; 3437 /* DMA tag for our ccb structures */ 3438 if (bus_dma_tag_create( 3439 /*parent_dmat*/pACB->parent_dmat, 3440 /*alignment*/ 1, 3441 /*boundary*/ 0, 3442 /*lowaddr*/ BUS_SPACE_MAXADDR, 3443 /*highaddr*/ BUS_SPACE_MAXADDR, 3444 /*filter*/ NULL, 3445 /*filterarg*/ NULL, 3446 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3447 /*nsegments*/ 1, 3448 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3449 /*flags*/ 0, 3450 /*lockfunc*/ busdma_lock_mutex, 3451 /*lockarg*/ &Giant, 3452 /*dmat*/ &pACB->srb_dmat) != 0) { 3453 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3454 goto bad; 3455 } 3456 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3457 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3458 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3459 goto bad; 3460 } 3461 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3462 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3463 /* flags */0); 3464 /* Create, allocate, and map DMA buffers for autosense data */ 3465 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3466 /*boundary*/0, 3467 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3468 /*highaddr*/BUS_SPACE_MAXADDR, 3469 /*filter*/NULL, /*filterarg*/NULL, 3470 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3471 /*nsegments*/1, 3472 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3473 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3474 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3475 if (bootverbose) 3476 device_printf(dev, "cannot create sense buffer dmat\n"); 3477 goto bad; 3478 } 3479 3480 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3481 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3482 goto bad; 3483 3484 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3485 pACB->sense_buffers, 3486 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3487 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3488 3489 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3490 trm_initACB(pACB, adaptType, unit); 3491 for (i = 0; i < (pACB->max_id + 1); i++) { 3492 if (pACB->AdaptSCSIID == i) 3493 continue; 3494 for(j = 0; j < (pACB->max_lun + 1); j++) { 3495 pACB->scan_devices[i][j] = 1; 3496 /* we assume we need to scan all devices */ 3497 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3498 } 3499 } 3500 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3501 if (bus_dma_tag_create( 3502 /*parent_dmat*/NULL, 3503 /*alignment*/ 1, 3504 /*boundary*/ 0, 3505 /*lowaddr*/ BUS_SPACE_MAXADDR, 3506 /*highaddr*/ BUS_SPACE_MAXADDR, 3507 /*filter*/ NULL, 3508 /*filterarg*/ NULL, 3509 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3510 /*nsegments*/ 1, 3511 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3512 /*flags*/ 0, 3513 /*lockfunc*/ busdma_lock_mutex, 3514 /*lockarg*/ &Giant, 3515 /*dmat*/ &pACB->sg_dmat) != 0) 3516 goto bad; 3517 3518 if (trm_initSRB(pACB)) { 3519 printf("trm_initSRB: error\n"); 3520 goto bad; 3521 } 3522 if (trm_initAdapter(pACB, unit)) { 3523 printf("trm_initAdapter: initial ERROR\n"); 3524 goto bad; 3525 } 3526 return (pACB); 3527 bad: 3528 if (pACB->iores) 3529 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3530 pACB->iores); 3531 if (pACB->sense_dmamap) { 3532 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3533 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3534 pACB->sense_dmamap); 3535 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3536 } 3537 if (pACB->sense_dmat) 3538 bus_dma_tag_destroy(pACB->sense_dmat); 3539 if (pACB->sg_dmat) { 3540 trm_destroySRB(pACB); 3541 bus_dma_tag_destroy(pACB->sg_dmat); 3542 } 3543 if (pACB->srb_dmamap) { 3544 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3545 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3546 pACB->srb_dmamap); 3547 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3548 } 3549 if (pACB->srb_dmat) 3550 bus_dma_tag_destroy(pACB->srb_dmat); 3551 if (pACB->buffer_dmat) 3552 bus_dma_tag_destroy(pACB->buffer_dmat); 3553 return (NULL); 3554 } 3555 3556 static int 3557 trm_attach(device_t dev) 3558 { 3559 struct cam_devq *device_Q; 3560 u_long device_id; 3561 PACB pACB = 0; 3562 int rid = 0; 3563 int unit = device_get_unit(dev); 3564 3565 device_id = pci_get_devid(dev); 3566 /* 3567 * These cards do not allow memory mapped accesses 3568 */ 3569 if ((pACB = trm_init((u_int16_t) unit, 3570 dev)) == NULL) { 3571 printf("trm%d: trm_init error!\n",unit); 3572 return (ENXIO); 3573 } 3574 /* After setting up the adapter, map our interrupt */ 3575 /* 3576 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3577 * start queue to reset to the idle loop. 3578 * Create device queue of SIM(s) 3579 * (MAX_START_JOB - 1) : max_sim_transactions 3580 */ 3581 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3582 RF_SHAREABLE | RF_ACTIVE); 3583 if (pACB->irq == NULL || 3584 bus_setup_intr(dev, pACB->irq, 3585 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3586 printf("trm%d: register Interrupt handler error!\n", unit); 3587 goto bad; 3588 } 3589 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3590 if (device_Q == NULL){ 3591 printf("trm%d: device_Q == NULL !\n",unit); 3592 goto bad; 3593 } 3594 /* 3595 * Now tell the generic SCSI layer 3596 * about our bus. 3597 * If this is the xpt layer creating a sim, then it's OK 3598 * to wait for an allocation. 3599 * XXX Should we pass in a flag to indicate that wait is OK? 3600 * 3601 * SIM allocation 3602 * 3603 * SCSI Interface Modules 3604 * The sim driver creates a sim for each controller. The sim device 3605 * queue is separately created in order to allow resource sharing betwee 3606 * sims. For instance, a driver may create one sim for each channel of 3607 * a multi-channel controller and use the same queue for each channel. 3608 * In this way, the queue resources are shared across all the channels 3609 * of the multi-channel controller. 3610 * trm_action : sim_action_func 3611 * trm_poll : sim_poll_func 3612 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3613 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3614 * pACB->unit : unit 3615 * 1 : max_dev_transactions 3616 * MAX_TAGS : max_tagged_dev_transactions 3617 * 3618 * *******Construct our first channel SIM entry 3619 */ 3620 pACB->psim = cam_sim_alloc(trm_action, 3621 trm_poll, 3622 "trm", 3623 pACB, 3624 unit, 3625 1, 3626 TRM_MAX_TAGS_CMD_QUEUE, 3627 device_Q); 3628 if (pACB->psim == NULL) { 3629 printf("trm%d: SIM allocate fault !\n",unit); 3630 cam_simq_free(device_Q); /* SIM allocate fault*/ 3631 goto bad; 3632 } 3633 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3634 printf("trm%d: xpt_bus_register fault !\n",unit); 3635 goto bad; 3636 } 3637 if (xpt_create_path(&pACB->ppath, 3638 NULL, 3639 cam_sim_path(pACB->psim), 3640 CAM_TARGET_WILDCARD, 3641 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3642 printf("trm%d: xpt_create_path fault !\n",unit); 3643 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3644 goto bad; 3645 } 3646 return (0); 3647 bad: 3648 if (pACB->iores) 3649 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3650 pACB->iores); 3651 if (pACB->sg_dmat) { 3652 trm_destroySRB(pACB); 3653 bus_dma_tag_destroy(pACB->sg_dmat); 3654 } 3655 3656 if (pACB->srb_dmamap) { 3657 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3658 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3659 pACB->srb_dmamap); 3660 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3661 } 3662 if (pACB->srb_dmat) 3663 bus_dma_tag_destroy(pACB->srb_dmat); 3664 if (pACB->sense_dmamap) { 3665 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3666 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3667 pACB->sense_dmamap); 3668 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3669 } 3670 if (pACB->sense_dmat) 3671 bus_dma_tag_destroy(pACB->sense_dmat); 3672 if (pACB->buffer_dmat) 3673 bus_dma_tag_destroy(pACB->buffer_dmat); 3674 if (pACB->ih) 3675 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3676 if (pACB->irq) 3677 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3678 if (pACB->psim) 3679 cam_sim_free(pACB->psim, TRUE); 3680 3681 return (ENXIO); 3682 3683 } 3684 3685 /* 3686 * pci_device 3687 * trm_probe (device_t tag, pcidi_t type) 3688 * 3689 */ 3690 static int 3691 trm_probe(device_t dev) 3692 { 3693 switch (pci_get_devid(dev)) { 3694 case PCI_DEVICEID_TRMS1040: 3695 device_set_desc(dev, 3696 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3697 return (0); 3698 case PCI_DEVICEID_TRMS2080: 3699 device_set_desc(dev, 3700 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3701 return 0; 3702 default: 3703 return (ENXIO); 3704 } 3705 } 3706 3707 static int 3708 trm_detach(device_t dev) 3709 { 3710 PACB pACB = device_get_softc(dev); 3711 3712 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3713 trm_destroySRB(pACB); 3714 bus_dma_tag_destroy(pACB->sg_dmat); 3715 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3716 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3717 pACB->srb_dmamap); 3718 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3719 bus_dma_tag_destroy(pACB->srb_dmat); 3720 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3721 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3722 pACB->sense_dmamap); 3723 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3724 bus_dma_tag_destroy(pACB->sense_dmat); 3725 bus_dma_tag_destroy(pACB->buffer_dmat); 3726 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3727 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3728 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3729 xpt_free_path(pACB->ppath); 3730 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3731 cam_sim_free(pACB->psim, TRUE); 3732 return (0); 3733 } 3734 static device_method_t trm_methods[] = { 3735 /* Device interface */ 3736 DEVMETHOD(device_probe, trm_probe), 3737 DEVMETHOD(device_attach, trm_attach), 3738 DEVMETHOD(device_detach, trm_detach), 3739 { 0, 0 } 3740 }; 3741 3742 static driver_t trm_driver = { 3743 "trm", trm_methods, sizeof(struct _ACB) 3744 }; 3745 3746 static devclass_t trm_devclass; 3747 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3748 MODULE_DEPEND(trm, cam, 1, 1, 1);
Cache object: f714d95ee95d9ccc43571c29ad67dfe5
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