Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/trm/trm.c
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1 /* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 */ 12 13 #include <sys/cdefs.h> 14 __FBSDID("$FreeBSD: releng/8.4/sys/dev/trm/trm.c 233025 2012-03-16 09:22:59Z scottl $"); 15 16 /* 17 * HISTORY: 18 * 19 * REV# DATE NAME DESCRIPTION 20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 27 */ 28 29 /*- 30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. The name of the author may not be used to endorse or promote products 41 * derived from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 */ 55 56 /* 57 * Imported into FreeBSD source repository, and updated to compile under 58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 59 */ 60 61 /* 62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 63 * <doginou@ci0.org>, 2002-03-04 64 */ 65 66 #include <sys/param.h> 67 68 #include <sys/systm.h> 69 #include <sys/malloc.h> 70 #include <sys/queue.h> 71 #if __FreeBSD_version >= 500000 72 #include <sys/bio.h> 73 #endif 74 #include <sys/buf.h> 75 #include <sys/bus.h> 76 #include <sys/kernel.h> 77 #include <sys/module.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/pci/pcivar.h> 83 #include <dev/pci/pcireg.h> 84 #include <machine/resource.h> 85 #include <machine/bus.h> 86 #include <sys/rman.h> 87 88 #include <cam/cam.h> 89 #include <cam/cam_ccb.h> 90 #include <cam/cam_sim.h> 91 #include <cam/cam_xpt_sim.h> 92 #include <cam/cam_debug.h> 93 94 #include <cam/scsi/scsi_all.h> 95 #include <cam/scsi/scsi_message.h> 96 97 #include <dev/trm/trm.h> 98 99 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 100 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 101 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 102 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 103 reg, value) 104 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 105 reg, value) 106 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 107 reg, value) 108 109 #define PCI_Vendor_ID_TEKRAM 0x1DE1 110 #define PCI_Device_ID_TRM_S1040 0x0391 111 #define PCI_DEVICEID_TRMS1040 0x03911DE1 112 #define PCI_DEVICEID_TRMS2080 0x03921DE1 113 114 #ifdef trm_DEBUG1 115 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 116 #else 117 #define TRM_DPRINTF(fmt, arg...) {} 118 #endif /* TRM_DEBUG */ 119 120 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 121 static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 122 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 123 static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124 static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 125 static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 126 static void NVRAM_trm_wait_30us(PACB pACB); 127 128 static void trm_Interrupt(void *vpACB); 129 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 130 u_int16_t * pscsi_status); 131 static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133 static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135 static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143 static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145 static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147 static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 154 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 155 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 156 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 157 static void trm_Disconnect(PACB pACB); 158 static void trm_Reselect(PACB pACB); 159 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 160 static void trm_DoingSRB_Done(PACB pACB); 161 static void trm_ScsiRstDetect(PACB pACB); 162 static void trm_ResetSCSIBus(PACB pACB); 163 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 164 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 165 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 166 static void trm_SendSRB(PACB pACB, PSRB pSRB); 167 static int trm_probe(device_t tag); 168 static int trm_attach(device_t tag); 169 static void trm_reset(PACB pACB); 170 171 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 172 173 static int trm_initAdapter(PACB pACB, u_int16_t unit); 174 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 175 u_int32_t i, u_int32_t j); 176 static int trm_initSRB(PACB pACB); 177 static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 178 /* CAM SIM entry points */ 179 #define ccb_trmsrb_ptr spriv_ptr0 180 #define ccb_trmacb_ptr spriv_ptr1 181 static void trm_action(struct cam_sim *psim, union ccb *pccb); 182 static void trm_poll(struct cam_sim *psim); 183 184 185 static void * trm_SCSI_phase0[] = { 186 trm_DataOutPhase0, /* phase:0 */ 187 trm_DataInPhase0, /* phase:1 */ 188 trm_CommandPhase0, /* phase:2 */ 189 trm_StatusPhase0, /* phase:3 */ 190 trm_Nop0, /* phase:4 */ 191 trm_Nop1, /* phase:5 */ 192 trm_MsgOutPhase0, /* phase:6 */ 193 trm_MsgInPhase0, /* phase:7 */ 194 }; 195 196 /* 197 * 198 * stateV = (void *) trm_SCSI_phase1[phase] 199 * 200 */ 201 static void * trm_SCSI_phase1[] = { 202 trm_DataOutPhase1, /* phase:0 */ 203 trm_DataInPhase1, /* phase:1 */ 204 trm_CommandPhase1, /* phase:2 */ 205 trm_StatusPhase1, /* phase:3 */ 206 trm_Nop0, /* phase:4 */ 207 trm_Nop1, /* phase:5 */ 208 trm_MsgOutPhase1, /* phase:6 */ 209 trm_MsgInPhase1, /* phase:7 */ 210 }; 211 212 213 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 214 /* 215 *Fast20: 000 50ns, 20.0 Mbytes/s 216 * 001 75ns, 13.3 Mbytes/s 217 * 010 100ns, 10.0 Mbytes/s 218 * 011 125ns, 8.0 Mbytes/s 219 * 100 150ns, 6.6 Mbytes/s 220 * 101 175ns, 5.7 Mbytes/s 221 * 110 200ns, 5.0 Mbytes/s 222 * 111 250ns, 4.0 Mbytes/s 223 * 224 *Fast40: 000 25ns, 40.0 Mbytes/s 225 * 001 50ns, 20.0 Mbytes/s 226 * 010 75ns, 13.3 Mbytes/s 227 * 011 100ns, 10.0 Mbytes/s 228 * 100 125ns, 8.0 Mbytes/s 229 * 101 150ns, 6.6 Mbytes/s 230 * 110 175ns, 5.7 Mbytes/s 231 * 111 200ns, 5.0 Mbytes/s 232 */ 233 /* real period: */ 234 u_int8_t dc395x_clock_period[] = { 235 12,/* 48 ns 20 MB/sec */ 236 18,/* 72 ns 13.3 MB/sec */ 237 25,/* 100 ns 10.0 MB/sec */ 238 31,/* 124 ns 8.0 MB/sec */ 239 37,/* 148 ns 6.6 MB/sec */ 240 43,/* 172 ns 5.7 MB/sec */ 241 50,/* 200 ns 5.0 MB/sec */ 242 62 /* 248 ns 4.0 MB/sec */ 243 }; 244 245 u_int8_t dc395u2x_clock_period[]={ 246 10,/* 25 ns 40.0 MB/sec */ 247 12,/* 48 ns 20.0 MB/sec */ 248 18,/* 72 ns 13.3 MB/sec */ 249 25,/* 100 ns 10.0 MB/sec */ 250 31,/* 124 ns 8.0 MB/sec */ 251 37,/* 148 ns 6.6 MB/sec */ 252 43,/* 172 ns 5.7 MB/sec */ 253 50,/* 200 ns 5.0 MB/sec */ 254 }; 255 256 #define dc395x_tinfo_period dc395x_clock_period 257 #define dc395u2x_tinfo_period dc395u2x_clock_period 258 259 static PSRB 260 trm_GetSRB(PACB pACB) 261 { 262 int intflag; 263 PSRB pSRB; 264 265 intflag = splcam(); 266 pSRB = pACB->pFreeSRB; 267 if (pSRB) { 268 pACB->pFreeSRB = pSRB->pNextSRB; 269 pSRB->pNextSRB = NULL; 270 } 271 splx(intflag); 272 return (pSRB); 273 } 274 275 static void 276 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 277 { 278 PSRB psrb1; 279 int intflag; 280 281 intflag = splcam(); 282 if ((psrb1 = pDCB->pWaitingSRB)) { 283 pSRB->pNextSRB = psrb1; 284 pDCB->pWaitingSRB = pSRB; 285 } else { 286 pSRB->pNextSRB = NULL; 287 pDCB->pWaitingSRB = pSRB; 288 pDCB->pWaitingLastSRB = pSRB; 289 } 290 splx(intflag); 291 } 292 293 static void 294 trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 295 { 296 PSRB psrb1; 297 int intflag; 298 299 intflag = splcam(); 300 pDCB->GoingSRBCnt--; 301 psrb1 = pDCB->pGoingSRB; 302 if (pSRB == psrb1) 303 /* 304 * if this SRB is GoingSRB 305 * remove this SRB from GoingSRB Q 306 */ 307 pDCB->pGoingSRB = psrb1->pNextSRB; 308 else { 309 /* 310 * if this SRB is not current GoingSRB 311 * remove this SRB from GoingSRB Q 312 */ 313 while (pSRB != psrb1->pNextSRB) 314 psrb1 = psrb1->pNextSRB; 315 psrb1->pNextSRB = pSRB->pNextSRB; 316 if (pSRB == pDCB->pGoingLastSRB) 317 pDCB->pGoingLastSRB = psrb1; 318 } 319 if ((psrb1 = pDCB->pWaitingSRB)) { 320 /* 321 * if WaitingSRB Q is not NULL 322 * Q back this SRB into WaitingSRB 323 */ 324 325 pSRB->pNextSRB = psrb1; 326 pDCB->pWaitingSRB = pSRB; 327 } else { 328 pSRB->pNextSRB = NULL; 329 pDCB->pWaitingSRB = pSRB; 330 pDCB->pWaitingLastSRB = pSRB; 331 } 332 splx(intflag); 333 } 334 335 static void 336 trm_DoWaitingSRB(PACB pACB) 337 { 338 int intflag; 339 PDCB ptr, ptr1; 340 PSRB pSRB; 341 342 intflag = splcam(); 343 if (!(pACB->pActiveDCB) && 344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 345 ptr = pACB->pDCBRunRobin; 346 if (!ptr) { 347 ptr = pACB->pLinkDCB; 348 pACB->pDCBRunRobin = ptr; 349 } 350 ptr1 = ptr; 351 for (;ptr1 ;) { 352 pACB->pDCBRunRobin = ptr1->pNextDCB; 353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 354 || !(pSRB = ptr1->pWaitingSRB)) { 355 if (pACB->pDCBRunRobin == ptr) 356 break; 357 ptr1 = ptr1->pNextDCB; 358 } else { 359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 360 /* 361 * If trm_StartSCSI return 0 : 362 * current interrupt status is interrupt enable 363 * It's said that SCSI processor is unoccupied 364 */ 365 ptr1->GoingSRBCnt++; 366 if (ptr1->pWaitingLastSRB == pSRB) { 367 ptr1->pWaitingSRB = NULL; 368 ptr1->pWaitingLastSRB = NULL; 369 } else 370 ptr1->pWaitingSRB = pSRB->pNextSRB; 371 pSRB->pNextSRB = NULL; 372 if (ptr1->pGoingSRB) 373 ptr1->pGoingLastSRB->pNextSRB = pSRB; 374 else 375 ptr1->pGoingSRB = pSRB; 376 ptr1->pGoingLastSRB = pSRB; 377 } 378 break; 379 } 380 } 381 } 382 splx(intflag); 383 return; 384 } 385 386 static void 387 trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 388 { 389 390 if (pDCB->pWaitingSRB) { 391 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 392 pDCB->pWaitingLastSRB = pSRB; 393 pSRB->pNextSRB = NULL; 394 } else { 395 pDCB->pWaitingSRB = pSRB; 396 pDCB->pWaitingLastSRB = pSRB; 397 } 398 } 399 400 static u_int32_t 401 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 402 { 403 int offset; 404 405 offset = pSRB->TagNumber; 406 return (pACB->sense_busaddr + 407 (offset * sizeof(struct scsi_sense_data))); 408 } 409 410 static struct scsi_sense_data * 411 trm_get_sense_buf(PACB pACB, PSRB pSRB) 412 { 413 int offset; 414 415 offset = pSRB->TagNumber; 416 return (&pACB->sense_buffers[offset]); 417 } 418 static void 419 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 420 { 421 int flags; 422 PACB pACB; 423 PSRB pSRB; 424 union ccb *ccb; 425 u_long totalxferlen=0; 426 427 flags = splcam(); 428 pSRB = (PSRB)arg; 429 ccb = pSRB->pccb; 430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 431 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 432 if (nseg != 0) { 433 PSEG psg; 434 bus_dma_segment_t *end_seg; 435 int op; 436 437 /* Copy the segments into our SG list */ 438 end_seg = dm_segs + nseg; 439 psg = pSRB->pSRBSGL; 440 while (dm_segs < end_seg) { 441 psg->address = dm_segs->ds_addr; 442 psg->length = (u_long)dm_segs->ds_len; 443 totalxferlen += dm_segs->ds_len; 444 psg++; 445 dm_segs++; 446 } 447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 448 op = BUS_DMASYNC_PREREAD; 449 } else { 450 op = BUS_DMASYNC_PREWRITE; 451 } 452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 453 } 454 pSRB->RetryCnt = 0; 455 pSRB->SRBTotalXferLength = totalxferlen; 456 pSRB->SRBSGCount = nseg; 457 pSRB->SRBSGIndex = 0; 458 pSRB->AdaptStatus = 0; 459 pSRB->TargetStatus = 0; 460 pSRB->MsgCnt = 0; 461 pSRB->SRBStatus = 0; 462 pSRB->SRBFlag = 0; 463 pSRB->SRBState = 0; 464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 465 466 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 467 if (nseg != 0) 468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 469 pSRB->pNextSRB = pACB->pFreeSRB; 470 pACB->pFreeSRB = pSRB; 471 xpt_done(ccb); 472 splx(flags); 473 return; 474 } 475 ccb->ccb_h.status |= CAM_SIM_QUEUED; 476 #if 0 477 /* XXX Need a timeout handler */ 478 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 479 #endif 480 trm_SendSRB(pACB, pSRB); 481 splx(flags); 482 return; 483 } 484 485 static void 486 trm_SendSRB(PACB pACB, PSRB pSRB) 487 { 488 PDCB pDCB; 489 490 pDCB = pSRB->pSRBDCB; 491 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 492 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 493 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 494 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 495 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 496 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 497 trm_SRBwaiting(pDCB, pSRB); 498 goto SND_EXIT; 499 } 500 501 if (pDCB->pWaitingSRB) { 502 trm_SRBwaiting(pDCB, pSRB); 503 pSRB = pDCB->pWaitingSRB; 504 pDCB->pWaitingSRB = pSRB->pNextSRB; 505 pSRB->pNextSRB = NULL; 506 } 507 508 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 509 /* 510 * If trm_StartSCSI return 0 : 511 * current interrupt status is interrupt enable 512 * It's said that SCSI processor is unoccupied 513 */ 514 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 515 if (pDCB->pGoingSRB) { 516 pDCB->pGoingLastSRB->pNextSRB = pSRB; 517 pDCB->pGoingLastSRB = pSRB; 518 } else { 519 pDCB->pGoingSRB = pSRB; 520 pDCB->pGoingLastSRB = pSRB; 521 } 522 } else { 523 /* 524 * If trm_StartSCSI return 1 : 525 * current interrupt status is interrupt disreenable 526 * It's said that SCSI processor has more one SRB need to do 527 */ 528 trm_RewaitSRB0(pDCB, pSRB); 529 } 530 SND_EXIT: 531 return; 532 } 533 534 535 static void 536 trm_action(struct cam_sim *psim, union ccb *pccb) 537 { 538 PACB pACB; 539 int actionflags; 540 u_int target_id,target_lun; 541 542 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 543 544 actionflags = splcam(); 545 pACB = (PACB) cam_sim_softc(psim); 546 target_id = pccb->ccb_h.target_id; 547 target_lun = pccb->ccb_h.target_lun; 548 549 switch (pccb->ccb_h.func_code) { 550 case XPT_NOOP: 551 TRM_DPRINTF(" XPT_NOOP \n"); 552 pccb->ccb_h.status = CAM_REQ_INVALID; 553 xpt_done(pccb); 554 break; 555 /* 556 * Execute the requested I/O operation 557 */ 558 case XPT_SCSI_IO: { 559 PDCB pDCB = NULL; 560 PSRB pSRB; 561 struct ccb_scsiio *pcsio; 562 563 pcsio = &pccb->csio; 564 TRM_DPRINTF(" XPT_SCSI_IO \n"); 565 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 566 ,target_id, target_lun); 567 TRM_DPRINTF( 568 "pACB->scan_devices[target_id][target_lun]= %d \n" 569 ,pACB->scan_devices[target_id][target_lun]); 570 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 571 CAM_REQ_INPROG) { 572 xpt_done(pccb); 573 splx(actionflags); 574 return; 575 } 576 pDCB = &pACB->DCBarray[target_id][target_lun]; 577 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 578 pACB->scan_devices[target_id][target_lun] = 1; 579 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 580 target_id, target_lun); 581 } 582 /* 583 * Assign an SRB and connect it with this ccb. 584 */ 585 pSRB = trm_GetSRB(pACB); 586 if (!pSRB) { 587 /* Freeze SIMQ */ 588 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 589 xpt_done(pccb); 590 splx(actionflags); 591 return; 592 } 593 pSRB->pSRBDCB = pDCB; 594 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 595 pccb->ccb_h.ccb_trmacb_ptr = pACB; 596 pSRB->pccb = pccb; 597 pSRB->ScsiCmdLen = pcsio->cdb_len; 598 /* 599 * move layer of CAM command block to layer of SCSI 600 * Request Block for SCSI processor command doing 601 */ 602 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 603 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 604 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 605 ,pcsio->cdb_len); 606 } else { 607 pccb->ccb_h.status = CAM_REQ_INVALID; 608 pSRB->pNextSRB = pACB->pFreeSRB; 609 pACB->pFreeSRB= pSRB; 610 xpt_done(pccb); 611 splx(actionflags); 612 return; 613 } 614 } else 615 bcopy(pcsio->cdb_io.cdb_bytes, 616 pSRB->CmdBlock, pcsio->cdb_len); 617 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 618 != CAM_DIR_NONE) { 619 if ((pccb->ccb_h.flags & 620 CAM_SCATTER_VALID) == 0) { 621 if ((pccb->ccb_h.flags 622 & CAM_DATA_PHYS) == 0) { 623 int vmflags; 624 int error; 625 626 vmflags = splsoftvm(); 627 error = bus_dmamap_load( 628 pACB->buffer_dmat, 629 pSRB->dmamap, 630 pcsio->data_ptr, 631 pcsio->dxfer_len, 632 trm_ExecuteSRB, 633 pSRB, 634 0); 635 if (error == EINPROGRESS) { 636 xpt_freeze_simq( 637 pACB->psim, 638 1); 639 pccb->ccb_h.status |= 640 CAM_RELEASE_SIMQ; 641 } 642 splx(vmflags); 643 } else { 644 struct bus_dma_segment seg; 645 646 /* Pointer to physical buffer */ 647 seg.ds_addr = 648 (bus_addr_t)pcsio->data_ptr; 649 seg.ds_len = pcsio->dxfer_len; 650 trm_ExecuteSRB(pSRB, &seg, 1, 651 0); 652 } 653 } else { 654 /* CAM_SCATTER_VALID */ 655 struct bus_dma_segment *segs; 656 657 if ((pccb->ccb_h.flags & 658 CAM_SG_LIST_PHYS) == 0 || 659 (pccb->ccb_h.flags 660 & CAM_DATA_PHYS) != 0) { 661 pSRB->pNextSRB = pACB->pFreeSRB; 662 pACB->pFreeSRB = pSRB; 663 pccb->ccb_h.status = 664 CAM_PROVIDE_FAIL; 665 xpt_done(pccb); 666 splx(actionflags); 667 return; 668 } 669 670 /* cam SG list is physical, 671 * cam data is virtual 672 */ 673 segs = (struct bus_dma_segment *) 674 pcsio->data_ptr; 675 trm_ExecuteSRB(pSRB, segs, 676 pcsio->sglist_cnt, 1); 677 } /* CAM_SCATTER_VALID */ 678 } else 679 trm_ExecuteSRB(pSRB, NULL, 0, 0); 680 } 681 break; 682 case XPT_GDEV_TYPE: 683 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 684 pccb->ccb_h.status = CAM_REQ_INVALID; 685 xpt_done(pccb); 686 break; 687 case XPT_GDEVLIST: 688 TRM_DPRINTF(" XPT_GDEVLIST \n"); 689 pccb->ccb_h.status = CAM_REQ_INVALID; 690 xpt_done(pccb); 691 break; 692 /* 693 * Path routing inquiry 694 * Path Inquiry CCB 695 */ 696 case XPT_PATH_INQ: { 697 struct ccb_pathinq *cpi = &pccb->cpi; 698 699 TRM_DPRINTF(" XPT_PATH_INQ \n"); 700 cpi->version_num = 1; 701 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 702 cpi->target_sprt = 0; 703 cpi->hba_misc = 0; 704 cpi->hba_eng_cnt = 0; 705 cpi->max_target = 15 ; 706 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 707 cpi->initiator_id = pACB->AdaptSCSIID; 708 cpi->bus_id = cam_sim_bus(psim); 709 cpi->base_transfer_speed = 3300; 710 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 711 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 712 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 713 cpi->unit_number = cam_sim_unit(psim); 714 cpi->transport = XPORT_SPI; 715 cpi->transport_version = 2; 716 cpi->protocol = PROTO_SCSI; 717 cpi->protocol_version = SCSI_REV_2; 718 cpi->ccb_h.status = CAM_REQ_CMP; 719 xpt_done(pccb); 720 } 721 break; 722 /* 723 * Release a frozen SIM queue 724 * Release SIM Queue 725 */ 726 case XPT_REL_SIMQ: 727 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 728 pccb->ccb_h.status = CAM_REQ_INVALID; 729 xpt_done(pccb); 730 break; 731 /* 732 * Set Asynchronous Callback Parameters 733 * Set Asynchronous Callback CCB 734 */ 735 case XPT_SASYNC_CB: 736 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 737 pccb->ccb_h.status = CAM_REQ_INVALID; 738 xpt_done(pccb); 739 break; 740 /* 741 * Set device type information 742 * Set Device Type CCB 743 */ 744 case XPT_SDEV_TYPE: 745 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 746 pccb->ccb_h.status = CAM_REQ_INVALID; 747 xpt_done(pccb); 748 break; 749 /* 750 * Get EDT entries matching the given pattern 751 */ 752 case XPT_DEV_MATCH: 753 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 754 pccb->ccb_h.status = CAM_REQ_INVALID; 755 xpt_done(pccb); 756 break; 757 /* 758 * Turn on debugging for a bus, target or lun 759 */ 760 case XPT_DEBUG: 761 TRM_DPRINTF(" XPT_DEBUG \n"); 762 pccb->ccb_h.status = CAM_REQ_INVALID; 763 xpt_done(pccb); 764 break; 765 /* 766 * XPT_ABORT = 0x10, Abort the specified CCB 767 * Abort XPT request CCB 768 */ 769 case XPT_ABORT: 770 TRM_DPRINTF(" XPT_ABORT \n"); 771 pccb->ccb_h.status = CAM_REQ_INVALID; 772 xpt_done(pccb); 773 break; 774 /* 775 * Reset the specified SCSI bus 776 * Reset SCSI Bus CCB 777 */ 778 case XPT_RESET_BUS: { 779 int i; 780 781 TRM_DPRINTF(" XPT_RESET_BUS \n"); 782 trm_reset(pACB); 783 pACB->ACBFlag=0; 784 for (i=0; i<500; i++) 785 DELAY(1000); 786 pccb->ccb_h.status = CAM_REQ_CMP; 787 xpt_done(pccb); 788 } 789 break; 790 /* 791 * Bus Device Reset the specified SCSI device 792 * Reset SCSI Device CCB 793 */ 794 case XPT_RESET_DEV: 795 /* 796 * Don't (yet?) support vendor 797 * specific commands. 798 */ 799 TRM_DPRINTF(" XPT_RESET_DEV \n"); 800 pccb->ccb_h.status = CAM_REQ_INVALID; 801 xpt_done(pccb); 802 break; 803 /* 804 * Terminate the I/O process 805 * Terminate I/O Process Request CCB 806 */ 807 case XPT_TERM_IO: 808 TRM_DPRINTF(" XPT_TERM_IO \n"); 809 pccb->ccb_h.status = CAM_REQ_INVALID; 810 xpt_done(pccb); 811 break; 812 /* 813 * Get/Set transfer rate/width/disconnection/tag queueing 814 * settings 815 * (GET) default/user transfer settings for the target 816 */ 817 case XPT_GET_TRAN_SETTINGS: { 818 struct ccb_trans_settings *cts = &pccb->cts; 819 int intflag; 820 struct trm_transinfo *tinfo; 821 PDCB pDCB; 822 struct ccb_trans_settings_scsi *scsi = 823 &cts->proto_specific.scsi; 824 struct ccb_trans_settings_spi *spi = 825 &cts->xport_specific.spi; 826 827 cts->protocol = PROTO_SCSI; 828 cts->protocol_version = SCSI_REV_2; 829 cts->transport = XPORT_SPI; 830 cts->transport_version = 2; 831 832 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 833 pDCB = &pACB->DCBarray[target_id][target_lun]; 834 intflag = splcam(); 835 /* 836 * disable interrupt 837 */ 838 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 839 /* current transfer settings */ 840 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 841 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 842 else 843 spi->flags = 0;/* no tag & disconnect */ 844 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 845 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 846 tinfo = &pDCB->tinfo.current; 847 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 848 cts->flags); 849 } else { 850 /* default(user) transfer settings */ 851 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 852 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 853 else 854 spi->flags = 0; 855 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 856 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 857 tinfo = &pDCB->tinfo.user; 858 TRM_DPRINTF("USER: cts->flags= %2x \n", 859 cts->flags); 860 } 861 spi->sync_period = tinfo->period; 862 spi->sync_offset = tinfo->offset; 863 spi->bus_width = tinfo->width; 864 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 865 pDCB->SyncPeriod); 866 TRM_DPRINTF("period: %d \n", tinfo->period); 867 TRM_DPRINTF("offset: %d \n", tinfo->offset); 868 TRM_DPRINTF("width: %d \n", tinfo->width); 869 870 splx(intflag); 871 spi->valid = CTS_SPI_VALID_SYNC_RATE | 872 CTS_SPI_VALID_SYNC_OFFSET | 873 CTS_SPI_VALID_BUS_WIDTH | 874 CTS_SPI_VALID_DISC; 875 scsi->valid = CTS_SCSI_VALID_TQ; 876 pccb->ccb_h.status = CAM_REQ_CMP; 877 xpt_done(pccb); 878 } 879 break; 880 /* 881 * Get/Set transfer rate/width/disconnection/tag queueing 882 * settings 883 * (Set) transfer rate/width negotiation settings 884 */ 885 case XPT_SET_TRAN_SETTINGS: { 886 struct ccb_trans_settings *cts = &pccb->cts; 887 u_int update_type; 888 int intflag; 889 PDCB pDCB; 890 struct ccb_trans_settings_scsi *scsi = 891 &cts->proto_specific.scsi; 892 struct ccb_trans_settings_spi *spi = 893 &cts->xport_specific.spi; 894 895 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 896 update_type = 0; 897 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 898 update_type |= TRM_TRANS_GOAL; 899 if (cts->type == CTS_TYPE_USER_SETTINGS) 900 update_type |= TRM_TRANS_USER; 901 intflag = splcam(); 902 pDCB = &pACB->DCBarray[target_id][target_lun]; 903 904 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 905 /*ccb disc enables */ 906 if (update_type & TRM_TRANS_GOAL) { 907 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 908 != 0) 909 pDCB->tinfo.disc_tag 910 |= TRM_CUR_DISCENB; 911 else 912 pDCB->tinfo.disc_tag &= 913 ~TRM_CUR_DISCENB; 914 } 915 if (update_type & TRM_TRANS_USER) { 916 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 917 != 0) 918 pDCB->tinfo.disc_tag 919 |= TRM_USR_DISCENB; 920 else 921 pDCB->tinfo.disc_tag &= 922 ~TRM_USR_DISCENB; 923 } 924 } 925 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 926 /* if ccb tag q active */ 927 if (update_type & TRM_TRANS_GOAL) { 928 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 929 != 0) 930 pDCB->tinfo.disc_tag |= 931 TRM_CUR_TAGENB; 932 else 933 pDCB->tinfo.disc_tag &= 934 ~TRM_CUR_TAGENB; 935 } 936 if (update_type & TRM_TRANS_USER) { 937 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 938 != 0) 939 pDCB->tinfo.disc_tag |= 940 TRM_USR_TAGENB; 941 else 942 pDCB->tinfo.disc_tag &= 943 ~TRM_USR_TAGENB; 944 } 945 } 946 /* Minimum sync period factor */ 947 948 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 949 /* if ccb sync active */ 950 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 951 if ((spi->sync_period != 0) && 952 (spi->sync_period < 125)) 953 spi->sync_period = 125; 954 /* 1/(125*4) minsync 2 MByte/sec */ 955 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) 956 != 0) { 957 if (spi->sync_offset == 0) 958 spi->sync_period = 0; 959 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 960 if (spi->sync_offset > 15) 961 spi->sync_offset = 15; 962 } 963 } 964 if ((update_type & TRM_TRANS_USER) != 0) { 965 pDCB->tinfo.user.period = spi->sync_period; 966 pDCB->tinfo.user.offset = spi->sync_offset; 967 pDCB->tinfo.user.width = spi->bus_width; 968 } 969 if ((update_type & TRM_TRANS_GOAL) != 0) { 970 pDCB->tinfo.goal.period = spi->sync_period; 971 pDCB->tinfo.goal.offset = spi->sync_offset; 972 pDCB->tinfo.goal.width = spi->bus_width; 973 } 974 splx(intflag); 975 pccb->ccb_h.status = CAM_REQ_CMP; 976 xpt_done(pccb); 977 break; 978 } 979 /* 980 * Calculate the geometry parameters for a device give 981 * the sector size and volume size. 982 */ 983 case XPT_CALC_GEOMETRY: 984 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 985 cam_calc_geometry(&pccb->ccg, /*extended*/1); 986 xpt_done(pccb); 987 break; 988 case XPT_ENG_INQ: 989 TRM_DPRINTF(" XPT_ENG_INQ \n"); 990 pccb->ccb_h.status = CAM_REQ_INVALID; 991 xpt_done(pccb); 992 break; 993 /* 994 * HBA execute engine request 995 * This structure must match SCSIIO size 996 */ 997 case XPT_ENG_EXEC: 998 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 999 pccb->ccb_h.status = CAM_REQ_INVALID; 1000 xpt_done(pccb); 1001 break; 1002 /* 1003 * XPT_EN_LUN = 0x30, Enable LUN as a target 1004 * Target mode structures. 1005 */ 1006 case XPT_EN_LUN: 1007 /* 1008 * Don't (yet?) support vendor 1009 * specific commands. 1010 */ 1011 TRM_DPRINTF(" XPT_EN_LUN \n"); 1012 pccb->ccb_h.status = CAM_REQ_INVALID; 1013 xpt_done(pccb); 1014 break; 1015 /* 1016 * Execute target I/O request 1017 */ 1018 case XPT_TARGET_IO: 1019 /* 1020 * Don't (yet?) support vendor 1021 * specific commands. 1022 */ 1023 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1024 pccb->ccb_h.status = CAM_REQ_INVALID; 1025 xpt_done(pccb); 1026 break; 1027 /* 1028 * Accept Host Target Mode CDB 1029 */ 1030 case XPT_ACCEPT_TARGET_IO: 1031 /* 1032 * Don't (yet?) support vendor 1033 * specific commands. 1034 */ 1035 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1036 pccb->ccb_h.status = CAM_REQ_INVALID; 1037 xpt_done(pccb); 1038 break; 1039 /* 1040 * Continue Host Target I/O Connection 1041 */ 1042 case XPT_CONT_TARGET_IO: 1043 /* 1044 * Don't (yet?) support vendor 1045 * specific commands. 1046 */ 1047 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1048 pccb->ccb_h.status = CAM_REQ_INVALID; 1049 xpt_done(pccb); 1050 break; 1051 /* 1052 * Notify Host Target driver of event 1053 */ 1054 case XPT_IMMED_NOTIFY: 1055 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1056 pccb->ccb_h.status = CAM_REQ_INVALID; 1057 xpt_done(pccb); 1058 break; 1059 /* 1060 * Acknowledgement of event 1061 */ 1062 case XPT_NOTIFY_ACK: 1063 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1064 pccb->ccb_h.status = CAM_REQ_INVALID; 1065 xpt_done(pccb); 1066 break; 1067 /* 1068 * XPT_VUNIQUE = 0x80 1069 */ 1070 case XPT_VUNIQUE: 1071 pccb->ccb_h.status = CAM_REQ_INVALID; 1072 xpt_done(pccb); 1073 break; 1074 default: 1075 pccb->ccb_h.status = CAM_REQ_INVALID; 1076 xpt_done(pccb); 1077 break; 1078 } 1079 splx(actionflags); 1080 } 1081 1082 static void 1083 trm_poll(struct cam_sim *psim) 1084 { 1085 trm_Interrupt(cam_sim_softc(psim)); 1086 } 1087 1088 static void 1089 trm_ResetDevParam(PACB pACB) 1090 { 1091 PDCB pDCB, pdcb; 1092 PNVRAMTYPE pEEpromBuf; 1093 u_int8_t PeriodIndex; 1094 1095 pDCB = pACB->pLinkDCB; 1096 if (pDCB == NULL) 1097 return; 1098 pdcb = pDCB; 1099 do { 1100 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1101 pDCB->SyncPeriod = 0; 1102 pDCB->SyncOffset = 0; 1103 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1104 pDCB->DevMode = 1105 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1106 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1107 PeriodIndex = 1108 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1109 if (pACB->AdaptType == 1) /* is U2? */ 1110 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1111 else 1112 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1113 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1114 (pACB->Config & HCC_WIDE_CARD)) 1115 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1116 pDCB = pDCB->pNextDCB; 1117 } 1118 while (pdcb != pDCB); 1119 } 1120 1121 static void 1122 trm_RecoverSRB(PACB pACB) 1123 { 1124 PDCB pDCB, pdcb; 1125 PSRB psrb, psrb2; 1126 u_int16_t cnt, i; 1127 1128 pDCB = pACB->pLinkDCB; 1129 if (pDCB == NULL) 1130 return; 1131 pdcb = pDCB; 1132 do { 1133 cnt = pdcb->GoingSRBCnt; 1134 psrb = pdcb->pGoingSRB; 1135 for (i = 0; i < cnt; i++) { 1136 psrb2 = psrb; 1137 psrb = psrb->pNextSRB; 1138 if (pdcb->pWaitingSRB) { 1139 psrb2->pNextSRB = pdcb->pWaitingSRB; 1140 pdcb->pWaitingSRB = psrb2; 1141 } else { 1142 pdcb->pWaitingSRB = psrb2; 1143 pdcb->pWaitingLastSRB = psrb2; 1144 psrb2->pNextSRB = NULL; 1145 } 1146 } 1147 pdcb->GoingSRBCnt = 0; 1148 pdcb->pGoingSRB = NULL; 1149 pdcb = pdcb->pNextDCB; 1150 } 1151 while (pdcb != pDCB); 1152 } 1153 1154 static void 1155 trm_reset(PACB pACB) 1156 { 1157 int intflag; 1158 u_int16_t i; 1159 1160 TRM_DPRINTF("trm: RESET"); 1161 intflag = splcam(); 1162 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1163 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1164 1165 trm_ResetSCSIBus(pACB); 1166 for (i = 0; i < 500; i++) 1167 DELAY(1000); 1168 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1169 /* Enable DMA interrupt */ 1170 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1171 /* Clear DMA FIFO */ 1172 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1173 /* Clear SCSI FIFO */ 1174 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1175 trm_ResetDevParam(pACB); 1176 trm_DoingSRB_Done(pACB); 1177 pACB->pActiveDCB = NULL; 1178 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1179 trm_DoWaitingSRB(pACB); 1180 /* Tell the XPT layer that a bus reset occured */ 1181 if (pACB->ppath != NULL) 1182 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1183 splx(intflag); 1184 return; 1185 } 1186 1187 static u_int16_t 1188 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1189 { 1190 u_int16_t return_code; 1191 u_int8_t scsicommand, i,command,identify_message; 1192 u_int8_t * ptr; 1193 union ccb *pccb; 1194 struct ccb_scsiio *pcsio; 1195 1196 pccb = pSRB->pccb; 1197 pcsio = &pccb->csio; 1198 1199 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1200 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1201 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1202 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1203 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1204 /* Flush FIFO */ 1205 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1206 1207 identify_message = pDCB->IdentifyMsg; 1208 1209 if ((pSRB->CmdBlock[0] == INQUIRY) || 1210 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1211 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1212 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1213 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1214 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1215 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1216 if (!(pDCB->IdentifyMsg & 7) || 1217 (pSRB->CmdBlock[0] != INQUIRY)) { 1218 scsicommand = SCMD_SEL_ATNSTOP; 1219 pSRB->SRBState = SRB_MSGOUT; 1220 goto polling; 1221 } 1222 } 1223 /* 1224 * Send identify message 1225 */ 1226 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1227 scsicommand = SCMD_SEL_ATN; 1228 pSRB->SRBState = SRB_START_; 1229 } else { 1230 /* not inquiry,request sense,auto request sense */ 1231 /* 1232 * Send identify message 1233 */ 1234 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1235 scsicommand = SCMD_SEL_ATN; 1236 pSRB->SRBState = SRB_START_; 1237 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1238 /* Send Tag message */ 1239 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1240 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1241 scsicommand = SCMD_SEL_ATN3; 1242 } 1243 } 1244 polling: 1245 /* 1246 * Send CDB ..command block ......... 1247 */ 1248 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1249 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1250 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1251 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1252 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1253 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1254 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1255 } else { 1256 ptr = (u_int8_t *) pSRB->CmdBlock; 1257 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1258 command = *ptr++; 1259 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1260 } 1261 } 1262 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1263 /* 1264 * If trm_StartSCSI return 1 : 1265 * current interrupt status is interrupt disreenable 1266 * It's said that SCSI processor has more one SRB need to do, 1267 * SCSI processor has been occupied by one SRB. 1268 */ 1269 pSRB->SRBState = SRB_READY; 1270 return_code = 1; 1271 } else { 1272 /* 1273 * If trm_StartSCSI return 0 : 1274 * current interrupt status is interrupt enable 1275 * It's said that SCSI processor is unoccupied 1276 */ 1277 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1278 pACB->pActiveDCB = pDCB; 1279 pDCB->pActiveSRB = pSRB; 1280 return_code = 0; 1281 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1282 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1283 /* 1284 * SCSI cammand 1285 */ 1286 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1287 } 1288 return (return_code); 1289 } 1290 1291 static void 1292 trm_Interrupt(vpACB) 1293 void *vpACB; 1294 { 1295 PACB pACB; 1296 PDCB pDCB; 1297 PSRB pSRB; 1298 u_int16_t phase; 1299 void (*stateV)(PACB, PSRB, u_int16_t *); 1300 u_int16_t scsi_status=0; 1301 u_int8_t scsi_intstatus; 1302 1303 pACB = vpACB; 1304 1305 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1306 if (!(scsi_status & SCSIINTERRUPT)) { 1307 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1308 return; 1309 } 1310 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1311 1312 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1313 1314 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1315 1316 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1317 trm_Disconnect(pACB); 1318 return; 1319 } 1320 1321 if (scsi_intstatus & INT_RESELECTED) { 1322 trm_Reselect(pACB); 1323 return; 1324 } 1325 if (scsi_intstatus & INT_SCSIRESET) { 1326 trm_ScsiRstDetect(pACB); 1327 return; 1328 } 1329 1330 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1331 pDCB = pACB->pActiveDCB; 1332 KASSERT(pDCB != NULL, ("no active DCB")); 1333 pSRB = pDCB->pActiveSRB; 1334 if (pDCB->DCBFlag & ABORT_DEV_) 1335 trm_EnableMsgOutAbort1(pACB, pSRB); 1336 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1337 stateV = (void *) trm_SCSI_phase0[phase]; 1338 stateV(pACB, pSRB, &scsi_status); 1339 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1340 /* phase:0,1,2,3,4,5,6,7 */ 1341 phase = (u_int16_t) scsi_status & PHASEMASK; 1342 stateV = (void *) trm_SCSI_phase1[phase]; 1343 stateV(pACB, pSRB, &scsi_status); 1344 } 1345 } 1346 1347 static void 1348 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1349 { 1350 1351 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1352 *pscsi_status = PH_BUS_FREE; 1353 /*.. initial phase*/ 1354 } 1355 1356 static void 1357 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1358 { 1359 u_int8_t bval; 1360 u_int16_t i, cnt; 1361 u_int8_t * ptr; 1362 PDCB pDCB; 1363 1364 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1365 pDCB = pACB->pActiveDCB; 1366 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1367 cnt = pSRB->MsgCnt; 1368 if (cnt) { 1369 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1370 for (i = 0; i < cnt; i++) { 1371 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1372 ptr++; 1373 } 1374 pSRB->MsgCnt = 0; 1375 if ((pDCB->DCBFlag & ABORT_DEV_) && 1376 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1377 pSRB->SRBState = SRB_ABORT_SENT; 1378 } 1379 } else { 1380 bval = MSG_ABORT; 1381 if ((pSRB->CmdBlock[0] == INQUIRY) || 1382 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1383 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1384 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1385 goto mop1; 1386 } 1387 } 1388 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1389 } 1390 } else { 1391 mop1: /* message out phase */ 1392 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1393 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1394 /* 1395 * WIDE DATA TRANSFER REQUEST code (03h) 1396 */ 1397 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1398 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1399 TRMREG_SCSI_FIFO); 1400 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1401 /* (01h) */ 1402 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1403 /* Message length (02h) */ 1404 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1405 /* wide data xfer (03h) */ 1406 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1407 /* width:0(8bit),1(16bit),2(32bit) */ 1408 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1409 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1410 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1411 /* 1412 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1413 */ 1414 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1415 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1416 TRMREG_SCSI_FIFO); 1417 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1418 /* (01h) */ 1419 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1420 /* Message length (03h) */ 1421 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1422 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1423 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1424 /* Transfer peeriod factor */ 1425 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1426 TRMREG_SCSI_FIFO); 1427 /* REQ/ACK offset */ 1428 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1429 } 1430 } 1431 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1432 /* it's important for atn stop */ 1433 /* 1434 * SCSI cammand 1435 */ 1436 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1437 } 1438 1439 static void 1440 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1441 { 1442 1443 } 1444 1445 static void 1446 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1447 { 1448 PDCB pDCB; 1449 u_int8_t * ptr; 1450 u_int16_t i, cnt; 1451 union ccb *pccb; 1452 struct ccb_scsiio *pcsio; 1453 1454 pccb = pSRB->pccb; 1455 pcsio = &pccb->csio; 1456 1457 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1458 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1459 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1460 ptr = (u_int8_t *) pSRB->CmdBlock; 1461 for (i = 0; i < cnt; i++) { 1462 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1463 ptr++; 1464 } 1465 } else { 1466 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1467 pDCB = pACB->pActiveDCB; 1468 /* target id */ 1469 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1470 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1471 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1472 /* sizeof(struct scsi_sense_data) */ 1473 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1474 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1475 } 1476 pSRB->SRBState = SRB_COMMAND; 1477 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1478 /* it's important for atn stop*/ 1479 /* 1480 * SCSI cammand 1481 */ 1482 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1483 } 1484 1485 static void 1486 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1487 { 1488 PDCB pDCB; 1489 u_int8_t TempDMAstatus,SGIndexTemp; 1490 u_int16_t scsi_status; 1491 PSEG pseg; 1492 u_long TempSRBXferredLength,dLeftCounter=0; 1493 1494 pDCB = pSRB->pSRBDCB; 1495 scsi_status = *pscsi_status; 1496 1497 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1498 if (scsi_status & PARITYERROR) 1499 pSRB->SRBStatus |= PARITY_ERROR; 1500 if (!(scsi_status & SCSIXFERDONE)) { 1501 /* 1502 * when data transfer from DMA FIFO to SCSI FIFO 1503 * if there was some data left in SCSI FIFO 1504 */ 1505 dLeftCounter = (u_long) 1506 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1507 if (pDCB->SyncPeriod & WIDE_SYNC) { 1508 /* 1509 * if WIDE scsi SCSI FIFOCNT unit is word 1510 * so need to * 2 1511 */ 1512 dLeftCounter <<= 1; 1513 } 1514 } 1515 /* 1516 * caculate all the residue data that not yet tranfered 1517 * SCSI transfer counter + left in SCSI FIFO data 1518 * 1519 * .....TRM_SCSI_COUNTER (24bits) 1520 * The counter always decrement by one for every SCSI byte 1521 *transfer. 1522 * .....TRM_SCSI_FIFOCNT (5bits) 1523 * The counter is SCSI FIFO offset counter 1524 */ 1525 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1526 if (dLeftCounter == 1) { 1527 dLeftCounter = 0; 1528 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1529 } 1530 if ((dLeftCounter == 0) || 1531 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1532 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1533 while (!(TempDMAstatus & DMAXFERCOMP)) { 1534 TempDMAstatus = 1535 trm_reg_read8(TRMREG_DMA_STATUS); 1536 } 1537 pSRB->SRBTotalXferLength = 0; 1538 } else { 1539 /* Update SG list */ 1540 /* 1541 * if transfer not yet complete 1542 * there were some data residue in SCSI FIFO or 1543 * SCSI transfer counter not empty 1544 */ 1545 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1546 /* 1547 * data that had transferred length 1548 */ 1549 TempSRBXferredLength = 1550 pSRB->SRBTotalXferLength - dLeftCounter; 1551 /* 1552 * next time to be transferred length 1553 */ 1554 pSRB->SRBTotalXferLength = dLeftCounter; 1555 /* 1556 * parsing from last time disconnect SRBSGIndex 1557 */ 1558 pseg = 1559 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1560 for (SGIndexTemp = pSRB->SRBSGIndex; 1561 SGIndexTemp < pSRB->SRBSGCount; 1562 SGIndexTemp++) { 1563 /* 1564 * find last time which SG transfer be 1565 * disconnect 1566 */ 1567 if (TempSRBXferredLength >= 1568 pseg->length) 1569 TempSRBXferredLength -= 1570 pseg->length; 1571 else { 1572 /* 1573 * update last time disconnected SG 1574 * list 1575 */ 1576 pseg->length -= 1577 TempSRBXferredLength; 1578 /* residue data length */ 1579 pseg->address += 1580 TempSRBXferredLength; 1581 /* residue data pointer */ 1582 pSRB->SRBSGIndex = SGIndexTemp; 1583 break; 1584 } 1585 pseg++; 1586 } 1587 } 1588 } 1589 } 1590 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1591 } 1592 1593 1594 static void 1595 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1596 { 1597 u_int16_t ioDir; 1598 /* 1599 * do prepare befor transfer when data out phase 1600 */ 1601 1602 ioDir = XFERDATAOUT; 1603 trm_DataIO_transfer(pACB, pSRB, ioDir); 1604 } 1605 1606 static void 1607 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1608 { 1609 u_int8_t TempDMAstatus, SGIndexTemp; 1610 u_int16_t scsi_status; 1611 PSEG pseg; 1612 u_long TempSRBXferredLength,dLeftCounter = 0; 1613 1614 scsi_status = *pscsi_status; 1615 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1616 if (scsi_status & PARITYERROR) 1617 pSRB->SRBStatus |= PARITY_ERROR; 1618 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1619 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1620 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1621 while (!(TempDMAstatus & DMAXFERCOMP)) 1622 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1623 pSRB->SRBTotalXferLength = 0; 1624 } else { 1625 /* 1626 * parsing the case: 1627 * when a transfer not yet complete 1628 * but be disconnected by uper layer 1629 * if transfer not yet complete 1630 * there were some data residue in SCSI FIFO or 1631 * SCSI transfer counter not empty 1632 */ 1633 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1634 /* 1635 * data that had transferred length 1636 */ 1637 TempSRBXferredLength = 1638 pSRB->SRBTotalXferLength - dLeftCounter; 1639 /* 1640 * next time to be transferred length 1641 */ 1642 pSRB->SRBTotalXferLength = dLeftCounter; 1643 /* 1644 * parsing from last time disconnect SRBSGIndex 1645 */ 1646 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1647 for (SGIndexTemp = pSRB->SRBSGIndex; 1648 SGIndexTemp < pSRB->SRBSGCount; 1649 SGIndexTemp++) { 1650 /* 1651 * find last time which SG transfer be disconnect 1652 */ 1653 if (TempSRBXferredLength >= pseg->length) 1654 TempSRBXferredLength -= pseg->length; 1655 else { 1656 /* 1657 * update last time disconnected SG list 1658 */ 1659 pseg->length -= TempSRBXferredLength; 1660 /* residue data length */ 1661 pseg->address += TempSRBXferredLength; 1662 /* residue data pointer */ 1663 pSRB->SRBSGIndex = SGIndexTemp; 1664 break; 1665 } 1666 pseg++; 1667 } 1668 } 1669 } 1670 } 1671 } 1672 1673 static void 1674 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1675 { 1676 u_int16_t ioDir; 1677 /* 1678 * do prepare befor transfer when data in phase 1679 */ 1680 1681 ioDir = XFERDATAIN; 1682 trm_DataIO_transfer(pACB, pSRB, ioDir); 1683 } 1684 1685 static void 1686 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1687 { 1688 u_int8_t bval; 1689 PDCB pDCB; 1690 1691 pDCB = pSRB->pSRBDCB; 1692 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1693 if (pSRB->SRBTotalXferLength != 0) { 1694 /* 1695 * load what physical address of Scatter/Gather list 1696 table want to be transfer 1697 */ 1698 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1699 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1700 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1701 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1702 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1703 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1704 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1705 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1706 1707 pSRB->SRBState = SRB_DATA_XFER; 1708 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1709 trm_reg_write32( 1710 (pSRB->SRBSGPhyAddr + 1711 ((u_long)pSRB->SRBSGIndex << 3)), 1712 TRMREG_DMA_XLOWADDR); 1713 /* 1714 * load how many bytes in the Scatter/Gather 1715 * list table 1716 */ 1717 trm_reg_write32( 1718 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1719 TRMREG_DMA_XCNT); 1720 /* 1721 * load total transfer length (24bits) max value 1722 * 16Mbyte 1723 */ 1724 trm_reg_write32(pSRB->SRBTotalXferLength, 1725 TRMREG_SCSI_COUNTER); 1726 /* Start DMA transfer */ 1727 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1728 /* Start SCSI transfer */ 1729 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1730 /* it's important for atn stop */ 1731 /* 1732 * SCSI cammand 1733 */ 1734 bval = (ioDir == XFERDATAOUT) ? 1735 SCMD_DMA_OUT : SCMD_DMA_IN; 1736 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1737 } else { 1738 /* xfer pad */ 1739 if (pSRB->SRBSGCount) { 1740 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1741 pSRB->SRBStatus |= OVER_RUN; 1742 } 1743 if (pDCB->SyncPeriod & WIDE_SYNC) 1744 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1745 else 1746 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1747 if (ioDir == XFERDATAOUT) 1748 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1749 else 1750 trm_reg_read16(TRMREG_SCSI_FIFO); 1751 pSRB->SRBState |= SRB_XFERPAD; 1752 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1753 /* it's important for atn stop */ 1754 /* 1755 * SCSI cammand 1756 */ 1757 bval = (ioDir == XFERDATAOUT) ? 1758 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1759 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1760 } 1761 } 1762 } 1763 1764 static void 1765 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1766 { 1767 1768 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1769 pSRB->SRBState = SRB_COMPLETED; 1770 *pscsi_status = PH_BUS_FREE; 1771 /*.. initial phase*/ 1772 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1773 /* it's important for atn stop */ 1774 /* 1775 * SCSI cammand 1776 */ 1777 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1778 } 1779 1780 1781 1782 static void 1783 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1784 { 1785 1786 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1787 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1788 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1789 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1790 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1791 } else { 1792 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1793 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1794 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1795 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1796 } 1797 pSRB->SRBState = SRB_STATUS; 1798 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1799 /* it's important for atn stop */ 1800 /* 1801 * SCSI cammand 1802 */ 1803 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1804 } 1805 1806 /* 1807 *scsiiom 1808 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1809 * stateV = (void *) trm_SCSI_phase0[phase] 1810 * if phase =7 1811 * extended message codes: 1812 * 1813 * code description 1814 * 1815 * 02h Reserved 1816 * 00h MODIFY DATA POINTER 1817 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1818 * 03h WIDE DATA TRANSFER REQUEST 1819 * 04h - 7Fh Reserved 1820 * 80h - FFh Vendor specific 1821 * 1822 */ 1823 1824 static void 1825 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1826 { 1827 u_int8_t message_in_code,bIndex,message_in_tag_id; 1828 PDCB pDCB; 1829 PSRB pSRBTemp; 1830 1831 pDCB = pACB->pActiveDCB; 1832 1833 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1834 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1835 if (message_in_code == MSG_DISCONNECT) { 1836 pSRB->SRBState = SRB_DISCONNECT; 1837 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1838 /* it's important for atn stop */ 1839 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1840 /* 1841 * SCSI command 1842 */ 1843 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1844 return; 1845 } else if (message_in_code == MSG_SAVE_PTR) { 1846 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1847 /* it's important for atn stop */ 1848 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1849 /* 1850 * SCSI command 1851 */ 1852 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1853 return; 1854 } else if ((message_in_code == MSG_EXTENDED) || 1855 ((message_in_code >= MSG_SIMPLE_QTAG) && 1856 (message_in_code <= MSG_ORDER_QTAG))) { 1857 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1858 pSRB->MsgInBuf[0] = message_in_code; 1859 /* extended message (01h) */ 1860 pSRB->MsgCnt = 1; 1861 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1862 /* extended message length (n) */ 1863 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1864 /* it's important for atn stop */ 1865 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1866 /* 1867 * SCSI command 1868 */ 1869 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1870 return; 1871 } else if (message_in_code == MSG_REJECT_) { 1872 /* Reject message */ 1873 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1874 /* do wide nego reject */ 1875 pDCB = pSRB->pSRBDCB; 1876 pDCB->SyncMode |= WIDE_NEGO_DONE; 1877 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1878 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1879 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1880 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1881 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1882 /* Set ATN, in case ATN was clear */ 1883 pSRB->SRBState |= SRB_MSGOUT; 1884 trm_reg_write16( 1885 DO_SETATN, 1886 TRMREG_SCSI_CONTROL); 1887 } else { 1888 /* Clear ATN */ 1889 trm_reg_write16( 1890 DO_CLRATN, 1891 TRMREG_SCSI_CONTROL); 1892 } 1893 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1894 /* do sync nego reject */ 1895 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1896 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1897 pDCB = pSRB->pSRBDCB; 1898 pDCB->SyncMode &= 1899 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1900 pDCB->SyncPeriod = 0; 1901 pDCB->SyncOffset = 0; 1902 /* 1903 * 1904 * program SCSI control register 1905 * 1906 */ 1907 trm_reg_write8(pDCB->SyncPeriod, 1908 TRMREG_SCSI_SYNC); 1909 trm_reg_write8(pDCB->SyncOffset, 1910 TRMREG_SCSI_OFFSET); 1911 trm_SetXferRate(pACB,pSRB,pDCB); 1912 } 1913 } 1914 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1915 /* it's important for atn stop */ 1916 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1917 /* 1918 * SCSI command 1919 */ 1920 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1921 return; 1922 } else if (message_in_code == MSG_IGNOREWIDE) { 1923 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1924 trm_reg_read8(TRMREG_SCSI_FIFO); 1925 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1926 /* it's important for atn stop */ 1927 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1928 /* 1929 * SCSI command 1930 */ 1931 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1932 return; 1933 } else { 1934 /* Restore data pointer message */ 1935 /* Save data pointer message */ 1936 /* Completion message */ 1937 /* NOP message */ 1938 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1939 /* it's important for atn stop */ 1940 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1941 /* 1942 * SCSI command 1943 */ 1944 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1945 return; 1946 } 1947 } else { 1948 /* 1949 * Parsing incomming extented messages 1950 */ 1951 *pSRB->pMsgPtr = message_in_code; 1952 pSRB->MsgCnt++; 1953 pSRB->pMsgPtr++; 1954 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1955 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1956 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1957 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1958 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1959 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1960 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1961 /* 1962 * is QUEUE tag message : 1963 * 1964 * byte 0: 1965 * HEAD QUEUE TAG (20h) 1966 * ORDERED QUEUE TAG (21h) 1967 * SIMPLE QUEUE TAG (22h) 1968 * byte 1: 1969 * Queue tag (00h - FFh) 1970 */ 1971 if (pSRB->MsgCnt == 2) { 1972 pSRB->SRBState = 0; 1973 message_in_tag_id = pSRB->MsgInBuf[1]; 1974 pSRB = pDCB->pGoingSRB; 1975 pSRBTemp = pDCB->pGoingLastSRB; 1976 if (pSRB) { 1977 for (;;) { 1978 if (pSRB->TagNumber != 1979 message_in_tag_id) { 1980 if (pSRB == pSRBTemp) { 1981 goto mingx0; 1982 } 1983 pSRB = pSRB->pNextSRB; 1984 } else 1985 break; 1986 } 1987 if (pDCB->DCBFlag & ABORT_DEV_) { 1988 pSRB->SRBState = SRB_ABORT_SENT; 1989 trm_EnableMsgOutAbort1( 1990 pACB, pSRB); 1991 } 1992 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1993 TRM_DPRINTF("SRB not yet disconnect........ \n "); 1994 goto mingx0; 1995 } 1996 pDCB->pActiveSRB = pSRB; 1997 pSRB->SRBState = SRB_DATA_XFER; 1998 } else { 1999 mingx0: 2000 pSRB = &pACB->TmpSRB; 2001 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2002 pDCB->pActiveSRB = pSRB; 2003 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2004 trm_EnableMsgOutAbort2( 2005 pACB, 2006 pSRB); 2007 } 2008 } 2009 *pscsi_status = PH_BUS_FREE; 2010 /* .. initial phase */ 2011 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2012 /* it's important for atn stop */ 2013 /* 2014 * SCSI command 2015 */ 2016 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2017 return; 2018 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2019 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2020 /* 2021 * is Wide data xfer Extended message : 2022 * ====================================== 2023 * WIDE DATA TRANSFER REQUEST 2024 * ====================================== 2025 * byte 0 : Extended message (01h) 2026 * byte 1 : Extended message length (02h) 2027 * byte 2 : WIDE DATA TRANSFER code (03h) 2028 * byte 3 : Transfer width exponent 2029 */ 2030 pDCB = pSRB->pSRBDCB; 2031 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2032 if ((pSRB->MsgInBuf[1] != 2)) { 2033 /* Length is wrong, reject it */ 2034 pDCB->SyncMode &= 2035 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2036 pSRB->MsgCnt = 1; 2037 pSRB->MsgInBuf[0] = MSG_REJECT_; 2038 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2039 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2040 /* it's important for atn stop */ 2041 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2042 /* 2043 * SCSI command 2044 */ 2045 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2046 return; 2047 } 2048 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2049 /* Do wide negoniation */ 2050 if (pSRB->MsgInBuf[3] > 2) { 2051 /* > 32 bit */ 2052 /* reject_msg: */ 2053 pDCB->SyncMode &= 2054 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2055 pSRB->MsgCnt = 1; 2056 pSRB->MsgInBuf[0] = MSG_REJECT_; 2057 trm_reg_write16(DO_SETATN, 2058 TRMREG_SCSI_CONTROL); 2059 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2060 /* it's important for atn stop */ 2061 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2062 /* 2063 * SCSI command 2064 */ 2065 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2066 return; 2067 } 2068 if (pSRB->MsgInBuf[3] == 2) { 2069 pSRB->MsgInBuf[3] = 1; 2070 /* do 16 bits */ 2071 } else { 2072 if (!(pDCB->SyncMode 2073 & WIDE_NEGO_DONE)) { 2074 pSRB->SRBState &= 2075 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2076 pDCB->SyncMode |= 2077 WIDE_NEGO_DONE; 2078 pDCB->SyncMode &= 2079 ~(SYNC_NEGO_DONE | 2080 EN_ATN_STOP | 2081 WIDE_NEGO_ENABLE); 2082 if (pSRB->MsgInBuf[3] != 0) { 2083 /* is Wide data xfer */ 2084 pDCB->SyncPeriod |= 2085 WIDE_SYNC; 2086 pDCB->tinfo.current.width 2087 = MSG_EXT_WDTR_BUS_16_BIT; 2088 pDCB->tinfo.goal.width 2089 = MSG_EXT_WDTR_BUS_16_BIT; 2090 } 2091 } 2092 } 2093 } else 2094 pSRB->MsgInBuf[3] = 0; 2095 pSRB->SRBState |= SRB_MSGOUT; 2096 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2097 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2098 /* it's important for atn stop */ 2099 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2100 /* 2101 * SCSI command 2102 */ 2103 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2104 return; 2105 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2106 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2107 /* 2108 * is 8bit transfer Extended message : 2109 * ================================= 2110 * SYNCHRONOUS DATA TRANSFER REQUEST 2111 * ================================= 2112 * byte 0 : Extended message (01h) 2113 * byte 1 : Extended message length (03) 2114 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2115 * byte 3 : Transfer period factor 2116 * byte 4 : REQ/ACK offset 2117 */ 2118 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2119 if ((pSRB->MsgInBuf[1] != 3) || 2120 (pSRB->MsgInBuf[2] != 1)) { 2121 /* reject_msg: */ 2122 pSRB->MsgCnt = 1; 2123 pSRB->MsgInBuf[0] = MSG_REJECT_; 2124 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2125 *pscsi_status = PH_BUS_FREE; 2126 /* .. initial phase */ 2127 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2128 /* it's important for atn stop */ 2129 /* 2130 * SCSI cammand 2131 */ 2132 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2133 return; 2134 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2135 /* set async */ 2136 pDCB = pSRB->pSRBDCB; 2137 /* disable sync & sync nego */ 2138 pDCB->SyncMode &= 2139 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2140 pDCB->SyncPeriod = 0; 2141 pDCB->SyncOffset = 0; 2142 pDCB->tinfo.goal.period = 0; 2143 pDCB->tinfo.goal.offset = 0; 2144 pDCB->tinfo.current.period = 0; 2145 pDCB->tinfo.current.offset = 0; 2146 pDCB->tinfo.current.width = 2147 MSG_EXT_WDTR_BUS_8_BIT; 2148 /* 2149 * 2150 * program SCSI control register 2151 * 2152 */ 2153 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2154 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2155 trm_SetXferRate(pACB,pSRB,pDCB); 2156 *pscsi_status = PH_BUS_FREE; 2157 /* .. initial phase */ 2158 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2159 /* it's important for atn stop */ 2160 /* 2161 * SCSI cammand 2162 */ 2163 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2164 return; 2165 } else { 2166 /* set sync */ 2167 pDCB = pSRB->pSRBDCB; 2168 pDCB->SyncMode |= 2169 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2170 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2171 /* Transfer period factor */ 2172 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2173 /* REQ/ACK offset */ 2174 if (pACB->AdaptType == 1) { 2175 for(bIndex = 0; bIndex < 7; bIndex++) { 2176 if (pSRB->MsgInBuf[3] <= 2177 dc395u2x_clock_period[bIndex]) { 2178 pDCB->tinfo.goal.period = 2179 dc395u2x_tinfo_period[bIndex]; 2180 pDCB->tinfo.current.period = 2181 dc395u2x_tinfo_period[bIndex]; 2182 pDCB->tinfo.goal.offset = 2183 pDCB->SyncOffset; 2184 pDCB->tinfo.current.offset = 2185 pDCB->SyncOffset; 2186 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2187 break; 2188 } 2189 } 2190 } else { 2191 for(bIndex = 0; bIndex < 7; bIndex++) { 2192 if (pSRB->MsgInBuf[3] <= 2193 dc395x_clock_period[bIndex]) { 2194 pDCB->tinfo.goal.period = 2195 dc395x_tinfo_period[bIndex]; 2196 pDCB->tinfo.current.period = 2197 dc395x_tinfo_period[bIndex]; 2198 pDCB->tinfo.goal.offset = 2199 pDCB->SyncOffset; 2200 pDCB->tinfo.current.offset = 2201 pDCB->SyncOffset; 2202 pDCB->SyncPeriod |= 2203 (bIndex|ALT_SYNC); 2204 break; 2205 } 2206 } 2207 } 2208 /* 2209 * 2210 * program SCSI control register 2211 * 2212 */ 2213 trm_reg_write8(pDCB->SyncPeriod, 2214 TRMREG_SCSI_SYNC); 2215 trm_reg_write8(pDCB->SyncOffset, 2216 TRMREG_SCSI_OFFSET); 2217 trm_SetXferRate(pACB,pSRB,pDCB); 2218 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2219 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2220 /* 2221 ** SCSI command 2222 */ 2223 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2224 return; 2225 } 2226 } 2227 *pscsi_status = PH_BUS_FREE; 2228 /* .. initial phase */ 2229 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2230 /* it's important for atn stop */ 2231 /* 2232 * SCSI cammand 2233 */ 2234 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2235 } 2236 } 2237 2238 static void 2239 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2240 { 2241 2242 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2243 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2244 if (!(pSRB->SRBState & SRB_MSGIN)) { 2245 pSRB->SRBState &= SRB_DISCONNECT; 2246 pSRB->SRBState |= SRB_MSGIN; 2247 } 2248 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2249 /* it's important for atn stop*/ 2250 /* 2251 * SCSI cammand 2252 */ 2253 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2254 } 2255 2256 static void 2257 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2258 { 2259 2260 } 2261 2262 static void 2263 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2264 { 2265 2266 } 2267 2268 static void 2269 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2270 { 2271 union ccb *pccb; 2272 struct ccb_trans_settings neg; 2273 u_int16_t cnt, i; 2274 u_int8_t bval; 2275 PDCB pDCBTemp; 2276 2277 /* 2278 * set all lun device's period , offset 2279 */ 2280 TRM_DPRINTF("trm_SetXferRate\n"); 2281 pccb = pSRB->pccb; 2282 memset(&neg, 0, sizeof (neg)); 2283 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period; 2284 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset; 2285 neg.xport_specific.spi.valid = 2286 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET; 2287 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2288 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2289 if (!(pDCB->IdentifyMsg & 0x07)) { 2290 pDCBTemp = pACB->pLinkDCB; 2291 cnt = pACB->DeviceCnt; 2292 bval = pDCB->TargetID; 2293 for (i = 0; i < cnt; i++) { 2294 if (pDCBTemp->TargetID == bval) { 2295 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2296 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2297 pDCBTemp->SyncMode = pDCB->SyncMode; 2298 } 2299 pDCBTemp = pDCBTemp->pNextDCB; 2300 } 2301 } 2302 return; 2303 } 2304 2305 /* 2306 * scsiiom 2307 * trm_Interrupt 2308 * 2309 * 2310 * ---SCSI bus phase 2311 * 2312 * PH_DATA_OUT 0x00 Data out phase 2313 * PH_DATA_IN 0x01 Data in phase 2314 * PH_COMMAND 0x02 Command phase 2315 * PH_STATUS 0x03 Status phase 2316 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2317 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2318 * PH_MSG_OUT 0x06 Message out phase 2319 * PH_MSG_IN 0x07 Message in phase 2320 * 2321 */ 2322 static void 2323 trm_Disconnect(PACB pACB) 2324 { 2325 PDCB pDCB; 2326 PSRB pSRB, psrb; 2327 u_int16_t i,j, cnt; 2328 u_int target_id,target_lun; 2329 2330 TRM_DPRINTF("trm_Disconnect...............\n "); 2331 2332 pDCB = pACB->pActiveDCB; 2333 if (!pDCB) { 2334 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2335 j = 400; 2336 while (--j) 2337 DELAY(1); 2338 /* 1 msec */ 2339 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2340 TRMREG_SCSI_CONTROL); 2341 return; 2342 } 2343 pSRB = pDCB->pActiveSRB; 2344 /* bug pSRB=0 */ 2345 target_id = pSRB->pccb->ccb_h.target_id; 2346 target_lun = pSRB->pccb->ccb_h.target_lun; 2347 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2348 pACB->pActiveDCB = 0; 2349 pSRB->ScsiPhase = PH_BUS_FREE; 2350 /* SCSI bus free Phase */ 2351 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2352 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2353 pSRB->SRBState = 0; 2354 trm_DoWaitingSRB(pACB); 2355 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2356 pDCB->DCBFlag = 0; 2357 cnt = pDCB->GoingSRBCnt; 2358 pDCB->GoingSRBCnt = 0; 2359 pSRB = pDCB->pGoingSRB; 2360 for (i = 0; i < cnt; i++) { 2361 psrb = pSRB->pNextSRB; 2362 pSRB->pNextSRB = pACB->pFreeSRB; 2363 pACB->pFreeSRB = pSRB; 2364 pSRB = psrb; 2365 } 2366 pDCB->pGoingSRB = 0; 2367 trm_DoWaitingSRB(pACB); 2368 } else { 2369 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2370 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2371 /* Selection time out */ 2372 if (!(pACB->scan_devices[target_id][target_lun]) && 2373 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2374 pSRB->CmdBlock[0] != INQUIRY) { 2375 pSRB->SRBState = SRB_READY; 2376 trm_RewaitSRB(pDCB, pSRB); 2377 } else { 2378 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2379 goto disc1; 2380 } 2381 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2382 /* 2383 * SRB_DISCONNECT 2384 */ 2385 trm_DoWaitingSRB(pACB); 2386 } else if (pSRB->SRBState & SRB_COMPLETED) { 2387 disc1: 2388 /* 2389 * SRB_COMPLETED 2390 */ 2391 pDCB->pActiveSRB = 0; 2392 pSRB->SRBState = SRB_FREE; 2393 trm_SRBdone(pACB, pDCB, pSRB); 2394 } 2395 } 2396 return; 2397 } 2398 2399 static void 2400 trm_Reselect(PACB pACB) 2401 { 2402 PDCB pDCB; 2403 PSRB pSRB; 2404 u_int16_t RselTarLunId; 2405 2406 TRM_DPRINTF("trm_Reselect................. \n"); 2407 pDCB = pACB->pActiveDCB; 2408 if (pDCB) { 2409 /* Arbitration lost but Reselection win */ 2410 pSRB = pDCB->pActiveSRB; 2411 pSRB->SRBState = SRB_READY; 2412 trm_RewaitSRB(pDCB, pSRB); 2413 } 2414 /* Read Reselected Target Id and LUN */ 2415 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2416 pDCB = pACB->pLinkDCB; 2417 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2418 /* get pDCB of the reselect id */ 2419 pDCB = pDCB->pNextDCB; 2420 } 2421 2422 pACB->pActiveDCB = pDCB; 2423 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2424 pSRB = &pACB->TmpSRB; 2425 pDCB->pActiveSRB = pSRB; 2426 } else { 2427 pSRB = pDCB->pActiveSRB; 2428 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2429 /* 2430 * abort command 2431 */ 2432 pSRB = &pACB->TmpSRB; 2433 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2434 pDCB->pActiveSRB = pSRB; 2435 trm_EnableMsgOutAbort1(pACB, pSRB); 2436 } else { 2437 if (pDCB->DCBFlag & ABORT_DEV_) { 2438 pSRB->SRBState = SRB_ABORT_SENT; 2439 trm_EnableMsgOutAbort1(pACB, pSRB); 2440 } else 2441 pSRB->SRBState = SRB_DATA_XFER; 2442 } 2443 } 2444 pSRB->ScsiPhase = PH_BUS_FREE; 2445 /* SCSI bus free Phase */ 2446 /* 2447 * Program HA ID, target ID, period and offset 2448 */ 2449 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2450 /* target ID */ 2451 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2452 /* host ID */ 2453 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2454 /* period */ 2455 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2456 /* offset */ 2457 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2458 /* it's important for atn stop*/ 2459 /* 2460 * SCSI cammand 2461 */ 2462 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2463 /* to rls the /ACK signal */ 2464 } 2465 2466 static void 2467 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2468 { 2469 PSRB psrb; 2470 u_int8_t bval, bval1,status; 2471 union ccb *pccb; 2472 struct ccb_scsiio *pcsio; 2473 PSCSI_INQDATA ptr; 2474 int intflag; 2475 u_int target_id,target_lun; 2476 PDCB pTempDCB; 2477 2478 pccb = pSRB->pccb; 2479 if (pccb == NULL) 2480 return; 2481 pcsio = &pccb->csio; 2482 target_id = pSRB->pccb->ccb_h.target_id; 2483 target_lun = pSRB->pccb->ccb_h.target_lun; 2484 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2485 bus_dmasync_op_t op; 2486 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2487 op = BUS_DMASYNC_POSTREAD; 2488 else 2489 op = BUS_DMASYNC_POSTWRITE; 2490 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2491 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2492 } 2493 /* 2494 * 2495 * target status 2496 * 2497 */ 2498 status = pSRB->TargetStatus; 2499 pcsio->scsi_status=SCSI_STAT_GOOD; 2500 pccb->ccb_h.status = CAM_REQ_CMP; 2501 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2502 /* 2503 * status of auto request sense 2504 */ 2505 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2506 pSRB->AdaptStatus = 0; 2507 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2508 2509 if (status == SCSI_STATUS_CHECK_COND) { 2510 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2511 goto ckc_e; 2512 } 2513 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2514 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2515 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2516 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2517 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2518 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2519 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2520 pcsio->sense_len); 2521 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2522 | CAM_AUTOSNS_VALID; 2523 goto ckc_e; 2524 } 2525 /* 2526 * target status 2527 */ 2528 if (status) { 2529 if (status == SCSI_STATUS_CHECK_COND) { 2530 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2531 TRM_DPRINTF("trm_RequestSense..................\n"); 2532 trm_RequestSense(pACB, pDCB, pSRB); 2533 return; 2534 } 2535 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2536 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2537 goto ckc_e; 2538 } else if (status == SCSI_STAT_QUEUEFULL) { 2539 bval = (u_int8_t) pDCB->GoingSRBCnt; 2540 bval--; 2541 pDCB->MaxActiveCommandCnt = bval; 2542 trm_RewaitSRB(pDCB, pSRB); 2543 pSRB->AdaptStatus = 0; 2544 pSRB->TargetStatus = 0; 2545 return; 2546 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2547 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2548 pSRB->TargetStatus = 0; 2549 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2550 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2551 } else if (status == SCSI_STAT_BUSY) { 2552 TRM_DPRINTF("trm: target busy at %s %d\n", 2553 __FILE__, __LINE__); 2554 pcsio->scsi_status = SCSI_STAT_BUSY; 2555 pccb->ccb_h.status = CAM_SCSI_BUSY; 2556 return; 2557 /* The device busy, try again later? */ 2558 } else if (status == SCSI_STAT_RESCONFLICT) { 2559 TRM_DPRINTF("trm: target reserved at %s %d\n", 2560 __FILE__, __LINE__); 2561 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2562 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2563 return; 2564 } else { 2565 pSRB->AdaptStatus = 0; 2566 if (pSRB->RetryCnt) { 2567 pSRB->RetryCnt--; 2568 pSRB->TargetStatus = 0; 2569 pSRB->SRBSGIndex = 0; 2570 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2571 /* 2572 * If trm_StartSCSI return 1 : 2573 * current interrupt status is interrupt 2574 * disreenable 2575 * It's said that SCSI processor has more 2576 * one SRB need to do 2577 */ 2578 trm_RewaitSRB(pDCB, pSRB); 2579 } 2580 return; 2581 } else { 2582 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2583 __FILE__, __LINE__); 2584 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2585 } 2586 } 2587 } else { 2588 /* 2589 * process initiator status.......................... 2590 * Adapter (initiator) status 2591 */ 2592 status = pSRB->AdaptStatus; 2593 if (status & H_OVER_UNDER_RUN) { 2594 pSRB->TargetStatus = 0; 2595 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2596 /* Illegal length (over/under run) */ 2597 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2598 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2599 __FILE__, __LINE__); 2600 pDCB->tinfo.goal.period = 0; 2601 pDCB->tinfo.goal.offset = 0; 2602 /* Driver failed to perform operation */ 2603 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2604 } else { 2605 /* no error */ 2606 pSRB->AdaptStatus = 0; 2607 pSRB->TargetStatus = 0; 2608 pccb->ccb_h.status = CAM_REQ_CMP; 2609 /* there is no error, (sense is invalid) */ 2610 } 2611 } 2612 ckc_e: 2613 if (pACB->scan_devices[target_id][target_lun]) { 2614 /* 2615 * if SCSI command in "scan devices" duty 2616 */ 2617 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2618 pACB->scan_devices[target_id][target_lun] = 0; 2619 /* SCSI command phase :test unit ready */ 2620 else if (pSRB->CmdBlock[0] == INQUIRY) { 2621 /* 2622 * SCSI command phase :inquiry scsi device data 2623 * (type,capacity,manufacture.... 2624 */ 2625 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2626 goto NO_DEV; 2627 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2628 /* page fault */ 2629 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2630 ptr->DevType); 2631 bval1 = ptr->DevType & SCSI_DEVTYPE; 2632 if (bval1 == SCSI_NODEV) { 2633 NO_DEV: 2634 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2635 target_id, 2636 target_lun); 2637 intflag = splcam(); 2638 pACB->scan_devices[target_id][target_lun] = 0; 2639 /* no device set scan device flag =0*/ 2640 /* pDCB Q link */ 2641 /* move the head of DCB to tempDCB*/ 2642 pTempDCB=pACB->pLinkDCB; 2643 /* search current DCB for pass link */ 2644 while (pTempDCB->pNextDCB != pDCB) { 2645 pTempDCB = pTempDCB->pNextDCB; 2646 } 2647 /* 2648 * when the current DCB found than connect 2649 * current DCB tail 2650 */ 2651 /* to the DCB tail that before current DCB */ 2652 pTempDCB->pNextDCB = pDCB->pNextDCB; 2653 /* 2654 * if there was only one DCB ,connect his tail 2655 * to his head 2656 */ 2657 if (pACB->pLinkDCB == pDCB) 2658 pACB->pLinkDCB = pTempDCB->pNextDCB; 2659 if (pACB->pDCBRunRobin == pDCB) 2660 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2661 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2662 pACB->DeviceCnt--; 2663 if (pACB->DeviceCnt == 0) { 2664 pACB->pLinkDCB = NULL; 2665 pACB->pDCBRunRobin = NULL; 2666 } 2667 splx(intflag); 2668 } else { 2669 #ifdef trm_DEBUG1 2670 int j; 2671 for (j = 0; j < 28; j++) { 2672 TRM_DPRINTF("ptr=%2x ", 2673 ((u_int8_t *)ptr)[j]); 2674 } 2675 #endif 2676 pDCB->DevType = bval1; 2677 if (bval1 == SCSI_DASD || 2678 bval1 == SCSI_OPTICAL) { 2679 if ((((ptr->Vers & 0x07) >= 2) || 2680 ((ptr->RDF & 0x0F) == 2)) && 2681 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2682 (pDCB->DevMode & TAG_QUEUING_) && 2683 (pDCB->DevMode & EN_DISCONNECT_)) { 2684 if (pDCB->DevMode & 2685 TAG_QUEUING_) { 2686 pDCB-> 2687 MaxActiveCommandCnt = 2688 pACB->TagMaxNum; 2689 pDCB->SyncMode |= 2690 EN_TAG_QUEUING; 2691 pDCB->tinfo.disc_tag |= 2692 TRM_CUR_TAGENB; 2693 } else { 2694 pDCB->SyncMode |= 2695 EN_ATN_STOP; 2696 pDCB->tinfo.disc_tag &= 2697 ~TRM_CUR_TAGENB; 2698 } 2699 } 2700 } 2701 } 2702 /* pSRB->CmdBlock[0] == INQUIRY */ 2703 } 2704 /* pACB->scan_devices[target_id][target_lun] */ 2705 } 2706 intflag = splcam(); 2707 /* ReleaseSRB(pDCB, pSRB); */ 2708 if (pSRB == pDCB->pGoingSRB) 2709 pDCB->pGoingSRB = pSRB->pNextSRB; 2710 else { 2711 psrb = pDCB->pGoingSRB; 2712 while (psrb->pNextSRB != pSRB) { 2713 psrb = psrb->pNextSRB; 2714 } 2715 psrb->pNextSRB = pSRB->pNextSRB; 2716 if (pSRB == pDCB->pGoingLastSRB) { 2717 pDCB->pGoingLastSRB = psrb; 2718 } 2719 } 2720 pSRB->pNextSRB = pACB->pFreeSRB; 2721 pACB->pFreeSRB = pSRB; 2722 pDCB->GoingSRBCnt--; 2723 trm_DoWaitingSRB(pACB); 2724 2725 splx(intflag); 2726 /* Notify cmd done */ 2727 xpt_done (pccb); 2728 } 2729 2730 static void 2731 trm_DoingSRB_Done(PACB pACB) 2732 { 2733 PDCB pDCB, pdcb; 2734 PSRB psrb, psrb2; 2735 u_int16_t cnt, i; 2736 union ccb *pccb; 2737 2738 pDCB = pACB->pLinkDCB; 2739 if (pDCB == NULL) 2740 return; 2741 pdcb = pDCB; 2742 do { 2743 cnt = pdcb->GoingSRBCnt; 2744 psrb = pdcb->pGoingSRB; 2745 for (i = 0; i < cnt; i++) { 2746 psrb2 = psrb->pNextSRB; 2747 pccb = psrb->pccb; 2748 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2749 /* ReleaseSRB(pDCB, pSRB); */ 2750 psrb->pNextSRB = pACB->pFreeSRB; 2751 pACB->pFreeSRB = psrb; 2752 xpt_done(pccb); 2753 psrb = psrb2; 2754 } 2755 pdcb->GoingSRBCnt = 0; 2756 pdcb->pGoingSRB = NULL; 2757 pdcb = pdcb->pNextDCB; 2758 } 2759 while (pdcb != pDCB); 2760 } 2761 2762 static void 2763 trm_ResetSCSIBus(PACB pACB) 2764 { 2765 int intflag; 2766 2767 intflag = splcam(); 2768 pACB->ACBFlag |= RESET_DEV; 2769 2770 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2771 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2772 splx(intflag); 2773 return; 2774 } 2775 2776 static void 2777 trm_ScsiRstDetect(PACB pACB) 2778 { 2779 int intflag; 2780 u_long wlval; 2781 2782 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2783 wlval = 1000; 2784 while (--wlval) 2785 DELAY(1000); 2786 intflag = splcam(); 2787 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2788 2789 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2790 2791 if (pACB->ACBFlag & RESET_DEV) 2792 pACB->ACBFlag |= RESET_DONE; 2793 else { 2794 pACB->ACBFlag |= RESET_DETECT; 2795 trm_ResetDevParam(pACB); 2796 /* trm_DoingSRB_Done(pACB); ???? */ 2797 trm_RecoverSRB(pACB); 2798 pACB->pActiveDCB = NULL; 2799 pACB->ACBFlag = 0; 2800 trm_DoWaitingSRB(pACB); 2801 } 2802 splx(intflag); 2803 return; 2804 } 2805 2806 static void 2807 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2808 { 2809 union ccb *pccb; 2810 struct ccb_scsiio *pcsio; 2811 2812 pccb = pSRB->pccb; 2813 pcsio = &pccb->csio; 2814 2815 pSRB->SRBFlag |= AUTO_REQSENSE; 2816 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2817 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2818 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2819 pSRB->SRBSGCount); 2820 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2821 2822 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2823 pSRB->AdaptStatus = 0; 2824 pSRB->TargetStatus = 0; 2825 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2826 2827 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2828 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2829 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2830 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2831 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2832 pSRB->SRBSGCount = 1; 2833 pSRB->SRBSGIndex = 0; 2834 2835 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2836 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2837 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2838 pSRB->ScsiCmdLen = 6; 2839 2840 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2841 /* 2842 * If trm_StartSCSI return 1 : 2843 * current interrupt status is interrupt disreenable 2844 * It's said that SCSI processor has more one SRB need to do 2845 */ 2846 trm_RewaitSRB(pDCB, pSRB); 2847 } 2848 2849 static void 2850 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2851 { 2852 2853 pSRB->MsgCnt = 1; 2854 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2855 } 2856 2857 static void 2858 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2859 { 2860 2861 pSRB->MsgOutBuf[0] = MSG_ABORT; 2862 trm_EnableMsgOutAbort2(pACB, pSRB); 2863 } 2864 2865 static void 2866 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2867 { 2868 PNVRAMTYPE pEEpromBuf; 2869 u_int8_t bval,PeriodIndex; 2870 u_int target_id,target_lun; 2871 PDCB pTempDCB; 2872 int intflag; 2873 2874 target_id = i; 2875 target_lun = j; 2876 2877 /* 2878 * Using the lun 0 device to init other DCB first, if the device 2879 * has been initialized. 2880 * I don't want init sync arguments one by one, it is the same. 2881 */ 2882 if (target_lun != 0 && 2883 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2884 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2885 sizeof(TRM_DCB)); 2886 intflag = splcam(); 2887 if (pACB->pLinkDCB == 0) { 2888 pACB->pLinkDCB = pDCB; 2889 /* 2890 * RunRobin impersonate the role 2891 * that let each device had good proportion 2892 * about SCSI command proceeding 2893 */ 2894 pACB->pDCBRunRobin = pDCB; 2895 pDCB->pNextDCB = pDCB; 2896 } else { 2897 pTempDCB=pACB->pLinkDCB; 2898 /* search the last nod of DCB link */ 2899 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2900 pTempDCB = pTempDCB->pNextDCB; 2901 /* connect current DCB with last DCB tail */ 2902 pTempDCB->pNextDCB = pDCB; 2903 /* connect current DCB tail to this DCB Q head */ 2904 pDCB->pNextDCB=pACB->pLinkDCB; 2905 } 2906 splx(intflag); 2907 2908 pACB->DeviceCnt++; 2909 pDCB->TargetID = target_id; 2910 pDCB->TargetLUN = target_lun; 2911 pDCB->pWaitingSRB = NULL; 2912 pDCB->pGoingSRB = NULL; 2913 pDCB->GoingSRBCnt = 0; 2914 pDCB->pActiveSRB = NULL; 2915 pDCB->MaxActiveCommandCnt = 1; 2916 pDCB->DCBFlag = 0; 2917 pDCB->DCBstatus |= DS_IN_QUEUE; 2918 /* $$$$$$$ */ 2919 pEEpromBuf = &trm_eepromBuf[unit]; 2920 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2921 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2922 /* $$$$$$$ */ 2923 /* 2924 * disconnect enable ? 2925 */ 2926 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2927 bval = 0xC0; 2928 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2929 } else { 2930 bval = 0x80; 2931 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2932 } 2933 bval |= target_lun; 2934 pDCB->IdentifyMsg = bval; 2935 if (target_lun != 0 && 2936 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2937 return; 2938 /* $$$$$$$ */ 2939 /* 2940 * tag Qing enable ? 2941 */ 2942 if (pDCB->DevMode & TAG_QUEUING_) { 2943 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2944 } else 2945 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2946 /* $$$$$$$ */ 2947 /* 2948 * wide nego ,sync nego enable ? 2949 */ 2950 pDCB->SyncPeriod = 0; 2951 pDCB->SyncOffset = 0; 2952 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2953 if (pACB->AdaptType==1) {/* is U2? */ 2954 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2955 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2956 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2957 } else { 2958 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2959 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2960 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2961 } 2962 pDCB->SyncMode = 0; 2963 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2964 (pACB->Config & HCC_WIDE_CARD)) 2965 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2966 /* enable wide nego */ 2967 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2968 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2969 /* enable sync nego */ 2970 /* $$$$$$$ */ 2971 /* 2972 * Fill in tinfo structure. 2973 */ 2974 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2975 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2976 2977 pDCB->tinfo.current.period = 0; 2978 pDCB->tinfo.current.offset = 0; 2979 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2980 } 2981 2982 static void 2983 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2984 { 2985 PSRB pSRB; 2986 2987 pSRB=(PSRB) arg; 2988 pSRB->SRBSGPhyAddr=segs->ds_addr; 2989 return; 2990 } 2991 2992 static void 2993 trm_destroySRB(PACB pACB) 2994 { 2995 PSRB pSRB; 2996 2997 pSRB = pACB->pFreeSRB; 2998 while (pSRB) { 2999 if (pSRB->sg_dmamap) { 3000 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 3001 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 3002 pSRB->sg_dmamap); 3003 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap); 3004 } 3005 if (pSRB->dmamap) 3006 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 3007 pSRB = pSRB->pNextSRB; 3008 } 3009 } 3010 3011 static int 3012 trm_initSRB(PACB pACB) 3013 { 3014 u_int16_t i; 3015 PSRB pSRB; 3016 int error; 3017 3018 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 3019 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3020 3021 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 3022 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3023 return ENXIO; 3024 } 3025 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3026 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3027 trm_srbmapSG, pSRB, /*flags*/0); 3028 if (i != TRM_MAX_SRB_CNT - 1) { 3029 /* 3030 * link all SRB 3031 */ 3032 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3033 } else { 3034 /* 3035 * load NULL to NextSRB of the last SRB 3036 */ 3037 pSRB->pNextSRB = NULL; 3038 } 3039 pSRB->TagNumber = i; 3040 3041 /* 3042 * Create the dmamap. This is no longer optional! 3043 */ 3044 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 3045 &pSRB->dmamap)) != 0) 3046 return (error); 3047 3048 } 3049 return (0); 3050 } 3051 3052 3053 3054 3055 static void 3056 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3057 { 3058 PNVRAMTYPE pEEpromBuf; 3059 3060 pEEpromBuf = &trm_eepromBuf[unit]; 3061 pACB->max_id = 15; 3062 3063 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3064 pACB->max_lun = 7; 3065 else 3066 pACB->max_lun = 0; 3067 3068 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3069 pACB->max_id, pACB->max_lun); 3070 pACB->pLinkDCB = NULL; 3071 pACB->pDCBRunRobin = NULL; 3072 pACB->pActiveDCB = NULL; 3073 pACB->AdapterUnit = (u_int8_t)unit; 3074 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3075 pACB->AdaptSCSILUN = 0; 3076 pACB->DeviceCnt = 0; 3077 pACB->AdaptType = adaptType; 3078 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3079 pACB->ACBFlag = 0; 3080 return; 3081 } 3082 3083 static void 3084 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3085 { 3086 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3087 u_int8_t bAddr; 3088 3089 /* Enable SEEPROM */ 3090 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3091 TRMREG_GEN_CONTROL); 3092 /* 3093 * Write enable 3094 */ 3095 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3096 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3097 NVRAM_trm_wait_30us(pACB); 3098 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3099 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3100 } 3101 /* 3102 * Write disable 3103 */ 3104 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3105 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3106 NVRAM_trm_wait_30us(pACB); 3107 /* Disable SEEPROM */ 3108 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3109 TRMREG_GEN_CONTROL); 3110 return; 3111 } 3112 3113 static void 3114 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3115 { 3116 int i; 3117 u_int8_t bSendData; 3118 /* 3119 * Send write command & address 3120 */ 3121 3122 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3123 /* 3124 * Write data 3125 */ 3126 for (i = 0; i < 8; i++, bData <<= 1) { 3127 bSendData = NVR_SELECT; 3128 if (bData & 0x80) 3129 /* Start from bit 7 */ 3130 bSendData |= NVR_BITOUT; 3131 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3132 NVRAM_trm_wait_30us(pACB); 3133 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3134 NVRAM_trm_wait_30us(pACB); 3135 } 3136 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3137 NVRAM_trm_wait_30us(pACB); 3138 /* 3139 * Disable chip select 3140 */ 3141 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3142 NVRAM_trm_wait_30us(pACB); 3143 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3144 NVRAM_trm_wait_30us(pACB); 3145 /* 3146 * Wait for write ready 3147 */ 3148 while (1) { 3149 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3150 NVRAM_trm_wait_30us(pACB); 3151 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3152 NVRAM_trm_wait_30us(pACB); 3153 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3154 break; 3155 } 3156 } 3157 /* 3158 * Disable chip select 3159 */ 3160 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3161 return; 3162 } 3163 3164 static void 3165 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3166 { 3167 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3168 u_int8_t bAddr; 3169 3170 /* 3171 * Enable SEEPROM 3172 */ 3173 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3174 TRMREG_GEN_CONTROL); 3175 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3176 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3177 /* 3178 * Disable SEEPROM 3179 */ 3180 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3181 TRMREG_GEN_CONTROL); 3182 return; 3183 } 3184 3185 static u_int8_t 3186 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3187 { 3188 int i; 3189 u_int8_t bReadData, bData = 0; 3190 /* 3191 * Send read command & address 3192 */ 3193 3194 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3195 3196 for (i = 0; i < 8; i++) { 3197 /* 3198 * Read data 3199 */ 3200 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3201 NVRAM_trm_wait_30us(pACB); 3202 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3203 /* 3204 * Get data bit while falling edge 3205 */ 3206 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3207 bData <<= 1; 3208 if (bReadData & NVR_BITIN) { 3209 bData |= 1; 3210 } 3211 NVRAM_trm_wait_30us(pACB); 3212 } 3213 /* 3214 * Disable chip select 3215 */ 3216 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3217 return (bData); 3218 } 3219 3220 static void 3221 NVRAM_trm_wait_30us(PACB pACB) 3222 { 3223 3224 /* ScsiPortStallExecution(30); wait 30 us */ 3225 trm_reg_write8(5, TRMREG_GEN_TIMER); 3226 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3227 return; 3228 } 3229 3230 static void 3231 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3232 { 3233 int i; 3234 u_int8_t bSendData; 3235 3236 for (i = 0; i < 3; i++, bCmd <<= 1) { 3237 /* 3238 * Program SB+OP code 3239 */ 3240 bSendData = NVR_SELECT; 3241 if (bCmd & 0x04) 3242 bSendData |= NVR_BITOUT; 3243 /* start from bit 2 */ 3244 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3245 NVRAM_trm_wait_30us(pACB); 3246 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3247 NVRAM_trm_wait_30us(pACB); 3248 } 3249 for (i = 0; i < 7; i++, bAddr <<= 1) { 3250 /* 3251 * Program address 3252 */ 3253 bSendData = NVR_SELECT; 3254 if (bAddr & 0x40) 3255 /* Start from bit 6 */ 3256 bSendData |= NVR_BITOUT; 3257 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3258 NVRAM_trm_wait_30us(pACB); 3259 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3260 NVRAM_trm_wait_30us(pACB); 3261 } 3262 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3263 NVRAM_trm_wait_30us(pACB); 3264 } 3265 3266 static void 3267 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3268 { 3269 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3270 u_int16_t wAddr, wCheckSum; 3271 u_long dAddr, *dpEeprom; 3272 3273 NVRAM_trm_read_all(pEEpromBuf,pACB); 3274 wCheckSum = 0; 3275 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3276 wAddr < 64; wAddr++, wpEeprom++) { 3277 wCheckSum += *wpEeprom; 3278 } 3279 if (wCheckSum != 0x1234) { 3280 /* 3281 * Checksum error, load default 3282 */ 3283 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3284 pEEpromBuf->NvramSubVendorID[1] = 3285 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3286 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3287 pEEpromBuf->NvramSubSysID[1] = 3288 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3289 pEEpromBuf->NvramSubClass = 0x00; 3290 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3291 pEEpromBuf->NvramVendorID[1] = 3292 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3293 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3294 pEEpromBuf->NvramDeviceID[1] = 3295 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3296 pEEpromBuf->NvramReserved = 0x00; 3297 3298 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3299 dAddr < 16; dAddr++, dpEeprom++) { 3300 *dpEeprom = 0x00000077; 3301 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3302 } 3303 3304 *dpEeprom++ = 0x04000F07; 3305 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3306 *dpEeprom++ = 0x00000015; 3307 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3308 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3309 *dpEeprom = 0x00; 3310 pEEpromBuf->NvramCheckSum = 0x00; 3311 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3312 wAddr < 63; wAddr++, wpEeprom++) 3313 wCheckSum += *wpEeprom; 3314 *wpEeprom = 0x1234 - wCheckSum; 3315 NVRAM_trm_write_all(pEEpromBuf,pACB); 3316 } 3317 return; 3318 } 3319 static int 3320 trm_initAdapter(PACB pACB, u_int16_t unit) 3321 { 3322 PNVRAMTYPE pEEpromBuf; 3323 u_int16_t wval; 3324 u_int8_t bval; 3325 3326 pEEpromBuf = &trm_eepromBuf[unit]; 3327 3328 /* 250ms selection timeout */ 3329 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3330 /* Mask all the interrupt */ 3331 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3332 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3333 /* Reset SCSI module */ 3334 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3335 /* program configuration 0 */ 3336 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3337 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3338 pACB->Config |= HCC_WIDE_CARD; 3339 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3340 pACB->Config |= HCC_SCSI_RESET; 3341 if (pACB->Config & HCC_PARITY) 3342 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3343 else 3344 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3345 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3346 /* program configuration 1 */ 3347 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3348 /* program Host ID */ 3349 bval = pEEpromBuf->NvramScsiId; 3350 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3351 /* set ansynchronous transfer */ 3352 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3353 /* Trun LED control off*/ 3354 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3355 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3356 /* DMA config */ 3357 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3358 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3359 /* Clear pending interrupt status */ 3360 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3361 /* Enable SCSI interrupt */ 3362 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3363 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3364 return (0); 3365 } 3366 3367 static void 3368 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3369 { 3370 PACB pACB; 3371 3372 pACB = (PACB)arg; 3373 pACB->srb_physbase = segs->ds_addr; 3374 } 3375 3376 static void 3377 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3378 { 3379 bus_addr_t *baddr; 3380 3381 baddr = (bus_addr_t *)arg; 3382 *baddr = segs->ds_addr; 3383 } 3384 3385 static PACB 3386 trm_init(u_int16_t unit, device_t dev) 3387 { 3388 PACB pACB; 3389 int rid = PCIR_BAR(0), i = 0, j = 0; 3390 u_int16_t adaptType = 0; 3391 3392 pACB = (PACB) device_get_softc(dev); 3393 if (!pACB) { 3394 printf("trm%d: cannot allocate ACB !\n", unit); 3395 return (NULL); 3396 } 3397 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3398 &rid, RF_ACTIVE); 3399 if (pACB->iores == NULL) { 3400 printf("trm_init: bus_alloc_resource failed!\n"); 3401 return (NULL); 3402 } 3403 switch (pci_get_devid(dev)) { 3404 case PCI_DEVICEID_TRMS1040: 3405 adaptType = 0; 3406 break; 3407 case PCI_DEVICEID_TRMS2080: 3408 adaptType = 1; 3409 break; 3410 default: 3411 printf("trm_init %d: unknown adapter type!\n", unit); 3412 goto bad; 3413 } 3414 pACB->dev = dev; 3415 pACB->tag = rman_get_bustag(pACB->iores); 3416 pACB->bsh = rman_get_bushandle(pACB->iores); 3417 if (bus_dma_tag_create( 3418 /*parent_dmat*/ bus_get_dma_tag(dev), 3419 /*alignment*/ 1, 3420 /*boundary*/ 0, 3421 /*lowaddr*/ BUS_SPACE_MAXADDR, 3422 /*highaddr*/ BUS_SPACE_MAXADDR, 3423 /*filter*/ NULL, 3424 /*filterarg*/ NULL, 3425 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3426 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3427 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3428 /*flags*/ 0, 3429 /*lockfunc*/ NULL, 3430 /*lockarg*/ NULL, 3431 /* dmat */ &pACB->parent_dmat) != 0) 3432 goto bad; 3433 if (bus_dma_tag_create( 3434 /*parent_dmat*/ pACB->parent_dmat, 3435 /*alignment*/ 1, 3436 /*boundary*/ 0, 3437 /*lowaddr*/ BUS_SPACE_MAXADDR, 3438 /*highaddr*/ BUS_SPACE_MAXADDR, 3439 /*filter*/ NULL, 3440 /*filterarg*/ NULL, 3441 /*maxsize*/ MAXBSIZE, 3442 /*nsegments*/ TRM_NSEG, 3443 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3444 /*flags*/ BUS_DMA_ALLOCNOW, 3445 /*lockfunc*/ busdma_lock_mutex, 3446 /*lockarg*/ &Giant, 3447 /* dmat */ &pACB->buffer_dmat) != 0) 3448 goto bad; 3449 /* DMA tag for our ccb structures */ 3450 if (bus_dma_tag_create( 3451 /*parent_dmat*/pACB->parent_dmat, 3452 /*alignment*/ 1, 3453 /*boundary*/ 0, 3454 /*lowaddr*/ BUS_SPACE_MAXADDR, 3455 /*highaddr*/ BUS_SPACE_MAXADDR, 3456 /*filter*/ NULL, 3457 /*filterarg*/ NULL, 3458 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3459 /*nsegments*/ 1, 3460 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3461 /*flags*/ 0, 3462 /*lockfunc*/ busdma_lock_mutex, 3463 /*lockarg*/ &Giant, 3464 /*dmat*/ &pACB->srb_dmat) != 0) { 3465 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3466 goto bad; 3467 } 3468 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3469 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3470 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3471 goto bad; 3472 } 3473 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3474 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3475 /* flags */0); 3476 /* Create, allocate, and map DMA buffers for autosense data */ 3477 if (bus_dma_tag_create( 3478 /*parent_dmat*/pACB->parent_dmat, 3479 /*alignment*/1, 3480 /*boundary*/0, 3481 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3482 /*highaddr*/BUS_SPACE_MAXADDR, 3483 /*filter*/NULL, /*filterarg*/NULL, 3484 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3485 /*nsegments*/1, 3486 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3487 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3488 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3489 if (bootverbose) 3490 device_printf(dev, "cannot create sense buffer dmat\n"); 3491 goto bad; 3492 } 3493 3494 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3495 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3496 goto bad; 3497 3498 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3499 pACB->sense_buffers, 3500 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3501 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3502 3503 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3504 trm_initACB(pACB, adaptType, unit); 3505 for (i = 0; i < (pACB->max_id + 1); i++) { 3506 if (pACB->AdaptSCSIID == i) 3507 continue; 3508 for(j = 0; j < (pACB->max_lun + 1); j++) { 3509 pACB->scan_devices[i][j] = 1; 3510 /* we assume we need to scan all devices */ 3511 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3512 } 3513 } 3514 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3515 if (bus_dma_tag_create( 3516 /*parent_dmat*/pACB->parent_dmat, 3517 /*alignment*/ 1, 3518 /*boundary*/ 0, 3519 /*lowaddr*/ BUS_SPACE_MAXADDR, 3520 /*highaddr*/ BUS_SPACE_MAXADDR, 3521 /*filter*/ NULL, 3522 /*filterarg*/ NULL, 3523 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3524 /*nsegments*/ 1, 3525 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3526 /*flags*/ 0, 3527 /*lockfunc*/ busdma_lock_mutex, 3528 /*lockarg*/ &Giant, 3529 /*dmat*/ &pACB->sg_dmat) != 0) 3530 goto bad; 3531 3532 if (trm_initSRB(pACB)) { 3533 printf("trm_initSRB: error\n"); 3534 goto bad; 3535 } 3536 if (trm_initAdapter(pACB, unit)) { 3537 printf("trm_initAdapter: initial ERROR\n"); 3538 goto bad; 3539 } 3540 return (pACB); 3541 bad: 3542 if (pACB->iores) 3543 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3544 pACB->iores); 3545 if (pACB->sense_dmamap) { 3546 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3547 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3548 pACB->sense_dmamap); 3549 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3550 } 3551 if (pACB->sense_dmat) 3552 bus_dma_tag_destroy(pACB->sense_dmat); 3553 if (pACB->sg_dmat) { 3554 trm_destroySRB(pACB); 3555 bus_dma_tag_destroy(pACB->sg_dmat); 3556 } 3557 if (pACB->srb_dmamap) { 3558 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3559 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3560 pACB->srb_dmamap); 3561 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3562 } 3563 if (pACB->srb_dmat) 3564 bus_dma_tag_destroy(pACB->srb_dmat); 3565 if (pACB->buffer_dmat) 3566 bus_dma_tag_destroy(pACB->buffer_dmat); 3567 if (pACB->parent_dmat) 3568 bus_dma_tag_destroy(pACB->parent_dmat); 3569 return (NULL); 3570 } 3571 3572 static int 3573 trm_attach(device_t dev) 3574 { 3575 struct cam_devq *device_Q; 3576 u_long device_id; 3577 PACB pACB = 0; 3578 int rid = 0; 3579 int unit = device_get_unit(dev); 3580 3581 device_id = pci_get_devid(dev); 3582 /* 3583 * These cards do not allow memory mapped accesses 3584 */ 3585 if ((pACB = trm_init((u_int16_t) unit, 3586 dev)) == NULL) { 3587 printf("trm%d: trm_init error!\n",unit); 3588 return (ENXIO); 3589 } 3590 /* After setting up the adapter, map our interrupt */ 3591 /* 3592 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3593 * start queue to reset to the idle loop. 3594 * Create device queue of SIM(s) 3595 * (MAX_START_JOB - 1) : max_sim_transactions 3596 */ 3597 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3598 RF_SHAREABLE | RF_ACTIVE); 3599 if (pACB->irq == NULL || 3600 bus_setup_intr(dev, pACB->irq, 3601 INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) { 3602 printf("trm%d: register Interrupt handler error!\n", unit); 3603 goto bad; 3604 } 3605 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3606 if (device_Q == NULL){ 3607 printf("trm%d: device_Q == NULL !\n",unit); 3608 goto bad; 3609 } 3610 /* 3611 * Now tell the generic SCSI layer 3612 * about our bus. 3613 * If this is the xpt layer creating a sim, then it's OK 3614 * to wait for an allocation. 3615 * XXX Should we pass in a flag to indicate that wait is OK? 3616 * 3617 * SIM allocation 3618 * 3619 * SCSI Interface Modules 3620 * The sim driver creates a sim for each controller. The sim device 3621 * queue is separately created in order to allow resource sharing betwee 3622 * sims. For instance, a driver may create one sim for each channel of 3623 * a multi-channel controller and use the same queue for each channel. 3624 * In this way, the queue resources are shared across all the channels 3625 * of the multi-channel controller. 3626 * trm_action : sim_action_func 3627 * trm_poll : sim_poll_func 3628 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3629 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3630 * pACB->unit : unit 3631 * 1 : max_dev_transactions 3632 * MAX_TAGS : max_tagged_dev_transactions 3633 * 3634 * *******Construct our first channel SIM entry 3635 */ 3636 pACB->psim = cam_sim_alloc(trm_action, 3637 trm_poll, 3638 "trm", 3639 pACB, 3640 unit, 3641 &Giant, 3642 1, 3643 TRM_MAX_TAGS_CMD_QUEUE, 3644 device_Q); 3645 if (pACB->psim == NULL) { 3646 printf("trm%d: SIM allocate fault !\n",unit); 3647 cam_simq_free(device_Q); /* SIM allocate fault*/ 3648 goto bad; 3649 } 3650 if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS) { 3651 printf("trm%d: xpt_bus_register fault !\n",unit); 3652 goto bad; 3653 } 3654 if (xpt_create_path(&pACB->ppath, 3655 NULL, 3656 cam_sim_path(pACB->psim), 3657 CAM_TARGET_WILDCARD, 3658 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3659 printf("trm%d: xpt_create_path fault !\n",unit); 3660 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3661 goto bad; 3662 } 3663 return (0); 3664 bad: 3665 if (pACB->iores) 3666 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3667 pACB->iores); 3668 if (pACB->sg_dmat) { 3669 trm_destroySRB(pACB); 3670 bus_dma_tag_destroy(pACB->sg_dmat); 3671 } 3672 3673 if (pACB->srb_dmamap) { 3674 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3675 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3676 pACB->srb_dmamap); 3677 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3678 } 3679 if (pACB->srb_dmat) 3680 bus_dma_tag_destroy(pACB->srb_dmat); 3681 if (pACB->sense_dmamap) { 3682 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3683 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3684 pACB->sense_dmamap); 3685 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3686 } 3687 if (pACB->sense_dmat) 3688 bus_dma_tag_destroy(pACB->sense_dmat); 3689 if (pACB->buffer_dmat) 3690 bus_dma_tag_destroy(pACB->buffer_dmat); 3691 if (pACB->ih) 3692 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3693 if (pACB->irq) 3694 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3695 if (pACB->psim) 3696 cam_sim_free(pACB->psim, TRUE); 3697 3698 return (ENXIO); 3699 3700 } 3701 3702 /* 3703 * pci_device 3704 * trm_probe (device_t tag, pcidi_t type) 3705 * 3706 */ 3707 static int 3708 trm_probe(device_t dev) 3709 { 3710 switch (pci_get_devid(dev)) { 3711 case PCI_DEVICEID_TRMS1040: 3712 device_set_desc(dev, 3713 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3714 return (BUS_PROBE_DEFAULT); 3715 case PCI_DEVICEID_TRMS2080: 3716 device_set_desc(dev, 3717 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3718 return (BUS_PROBE_DEFAULT); 3719 default: 3720 return (ENXIO); 3721 } 3722 } 3723 3724 static int 3725 trm_detach(device_t dev) 3726 { 3727 PACB pACB = device_get_softc(dev); 3728 3729 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3730 trm_destroySRB(pACB); 3731 bus_dma_tag_destroy(pACB->sg_dmat); 3732 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3733 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3734 pACB->srb_dmamap); 3735 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3736 bus_dma_tag_destroy(pACB->srb_dmat); 3737 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3738 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3739 pACB->sense_dmamap); 3740 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3741 bus_dma_tag_destroy(pACB->sense_dmat); 3742 bus_dma_tag_destroy(pACB->buffer_dmat); 3743 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3744 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3745 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3746 xpt_free_path(pACB->ppath); 3747 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3748 cam_sim_free(pACB->psim, TRUE); 3749 return (0); 3750 } 3751 static device_method_t trm_methods[] = { 3752 /* Device interface */ 3753 DEVMETHOD(device_probe, trm_probe), 3754 DEVMETHOD(device_attach, trm_attach), 3755 DEVMETHOD(device_detach, trm_detach), 3756 { 0, 0 } 3757 }; 3758 3759 static driver_t trm_driver = { 3760 "trm", trm_methods, sizeof(struct _ACB) 3761 }; 3762 3763 static devclass_t trm_devclass; 3764 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3765 MODULE_DEPEND(trm, pci, 1, 1, 1); 3766 MODULE_DEPEND(trm, cam, 1, 1, 1);
Cache object: cf706e004db154e37e39ff8ca9d8bf03
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