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sys/dev/trm/trm.h
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1 /*- 2 * File Name : trm.h 3 * 4 * Tekram DC395U/UW/F ,DC315/U 5 * PCI SCSI Bus Master Host Adapter Device Driver 6 * (SCSI chip set used Tekram ASIC TRM-S1040) 7 * 8 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: releng/11.2/sys/dev/trm/trm.h 331722 2018-03-29 02:50:57Z eadler $ 33 */ 34 35 #ifndef trm_H 36 #define trm_H 37 38 /* SCSI CAM */ 39 40 #define TRM_TRANS_CUR 0x01 /* Modify current neogtiation status */ 41 #define TRM_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 42 #define TRM_TRANS_GOAL 0x04 /* Modify negotiation goal */ 43 #define TRM_TRANS_USER 0x08 /* Modify user negotiation settings */ 44 45 struct trm_transinfo { 46 u_int8_t width; 47 u_int8_t period; 48 u_int8_t offset; 49 }; 50 51 struct trm_target_info { 52 u_int8_t disc_tag; /* bits define..... */ 53 #define TRM_CUR_DISCENB 0x01 /* current setting disconnect enable */ 54 #define TRM_CUR_TAGENB 0x02 /* current setting tag command Q enable */ 55 #define TRM_USR_DISCENB 0x04 /* user adapter device setting disconnect enable */ 56 #define TRM_USR_TAGENB 0x08 /* user adapter device setting tag command Q enable*/ 57 struct trm_transinfo current; /* info of current */ 58 struct trm_transinfo goal; /* info of after negotiating */ 59 struct trm_transinfo user; /* info of user adapter device setting */ 60 }; 61 /* 62 * SCSI CAM ** 63 */ 64 65 /* 66 * bus_dma_segment_t 67 * 68 * Describes a single contiguous DMA transaction. Values 69 * are suitable for programming into DMA registers. 70 * 71 *typedef struct bus_dma_segment 72 *{ 73 * bus_addr_t ds_addr; // DMA address 74 * bus_size_t ds_len; // length of transfer 75 *} bus_dma_segment_t; 76 */ 77 78 /*;----------------------Segment Entry------------------------------------*/ 79 typedef struct _SGentry { 80 u_int32_t address; 81 u_int32_t length; 82 } SGentry, *PSEG; 83 /* 84 *----------------------------------------------------------------------- 85 * feature of chip set MAX value 86 *----------------------------------------------------------------------- 87 */ 88 89 #define TRM_MAX_ADAPTER_NUM 4 90 #define TRM_MAX_DEVICES 16 91 #define TRM_MAX_SG_LISTENTRY 32 92 #define TRM_MAX_TARGETS 16 93 #define TRM_MAX_TAGS_CMD_QUEUE 256 /* MAX_CMD_QUEUE 20*/ 94 #define TRM_MAX_CMD_PER_LUN 32 95 #define TRM_MAX_SRB_CNT 256 96 #define TRM_MAX_START_JOB 256 97 #define TRM_MAXPHYS (128 * 1024) 98 #define TRM_NSEG (btoc(TRM_MAXPHYS) + 1) 99 #define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */ 100 #define PAGELEN 4096 101 102 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40MHz) */ 103 104 /* 105 * CAM ccb 106 * Union of all CCB types for kernel space allocation. This union should 107 * never be used for manipulating CCBs - its only use is for the allocation 108 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 109 * and the argument to xpt_ccb_free. 110 * 111 *union ccb { 112 * struct ccb_hdr ccb_h; // For convenience 113 * struct ccb_scsiio csio; 114 * struct ccb_getdev cgd; 115 * struct ccb_getdevlist cgdl; 116 * struct ccb_pathinq cpi; 117 * struct ccb_relsim crs; 118 * struct ccb_setasync csa; 119 * struct ccb_setdev csd; 120 * struct ccb_dev_match cdm; 121 * struct ccb_trans_settings cts; 122 * struct ccb_calc_geometry ccg; 123 * struct ccb_abort cab; 124 * struct ccb_resetbus crb; 125 * struct ccb_resetdev crd; 126 * struct ccb_termio tio; 127 * struct ccb_accept_tio atio; 128 * struct ccb_scsiio ctio; 129 * struct ccb_en_lun cel; 130 * struct ccb_immed_notify cin; 131 * struct ccb_notify_ack cna; 132 * struct ccb_eng_inq cei; 133 * struct ccb_eng_exec cee; 134 * struct ccb_rescan crcn; 135 * struct ccb_debug cdbg; 136 * }; 137 */ 138 139 /* 140 *----------------------------------------------------------------------- 141 * SCSI Request Block 142 *----------------------------------------------------------------------- 143 */ 144 struct _SRB { 145 u_int8_t CmdBlock[12]; 146 u_long Segment0[2]; 147 u_long Segment1[2]; 148 struct _SRB *pNextSRB; 149 struct _DCB *pSRBDCB; 150 SGentry SgSenseTemp; 151 152 PSEG pSRBSGL; /* scatter gather list */ 153 154 u_int32_t SRBSGPhyAddr; /* a segment starting address */ 155 u_int32_t SRBTotalXferLength; 156 157 /* 158 * CAM ccb 159 */ 160 union ccb *pccb; 161 bus_dmamap_t sg_dmamap; 162 bus_dmamap_t dmamap; 163 u_int16_t SRBState; 164 u_int8_t * pMsgPtr; 165 166 u_int8_t SRBSGCount; 167 u_int8_t SRBSGIndex; 168 u_int8_t MsgInBuf[6]; 169 u_int8_t MsgOutBuf[6]; 170 171 u_int8_t AdaptStatus; 172 u_int8_t TargetStatus; 173 u_int8_t MsgCnt; 174 u_int8_t TagNumber; 175 176 u_int8_t SRBStatus; 177 u_int8_t RetryCnt; 178 u_int8_t SRBFlag; 179 u_int8_t ScsiCmdLen; 180 u_int8_t ScsiPhase; 181 u_int8_t Reserved[3]; /*;for dword alignment */ 182 }; 183 typedef struct _SRB TRM_SRB, *PSRB; 184 185 /* 186 *----------------------------------------------------------------------- 187 * Device Control Block 188 *----------------------------------------------------------------------- 189 */ 190 struct _DCB 191 { 192 PSRB pWaitingSRB; 193 PSRB pWaitingLastSRB; 194 195 PSRB pGoingSRB; 196 PSRB pGoingLastSRB; 197 198 PSRB pActiveSRB; 199 200 u_int16_t GoingSRBCnt; 201 u_int16_t MaxActiveCommandCnt; 202 203 u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */ 204 u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 205 u_int8_t DCBFlag; 206 u_int8_t DevType; 207 208 u_int8_t SyncMode; /* mode ? (1 sync):(0 async) */ 209 u_int8_t MaxNegoPeriod; /* for nego. */ 210 u_int8_t SyncPeriod; /* for reg. */ 211 u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */ 212 213 u_int8_t DevMode; 214 u_int8_t AdpMode; 215 216 u_int8_t IdentifyMsg; 217 u_int8_t DCBstatus; /* DCB status */ 218 /*u_int8_t Reserved[3]; for dword alignment */ 219 struct trm_target_info tinfo; /* 10 bytes */ 220 struct _DCB *pNextDCB; 221 }; 222 typedef struct _DCB TRM_DCB, *PDCB; 223 224 /* 225 *----------------------------------------------------------------------- 226 * Adapter Control Block 227 *----------------------------------------------------------------------- 228 */ 229 struct _ACB 230 { 231 device_t dev; 232 233 bus_space_tag_t tag; 234 bus_space_handle_t bsh; 235 bus_dma_tag_t parent_dmat; 236 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 237 bus_dma_tag_t srb_dmat; 238 bus_dma_tag_t sense_dmat; /* dmat for sense buffer */ 239 bus_dma_tag_t sg_dmat; 240 bus_dmamap_t sense_dmamap; 241 bus_dmamap_t srb_dmamap; 242 bus_addr_t sense_busaddr; 243 struct scsi_sense_data *sense_buffers; 244 struct resource *iores, *irq; 245 void *ih; 246 /* 247 * CAM SIM/XPT 248 */ 249 struct cam_sim *psim; 250 struct cam_path *ppath; 251 252 TRM_SRB TmpSRB; 253 TRM_DCB DCBarray[16][8]; 254 255 u_int32_t srb_physbase; 256 257 PSRB pFreeSRB; 258 PDCB pActiveDCB; 259 260 PDCB pLinkDCB; 261 PDCB pDCBRunRobin; 262 263 u_int16_t max_id; 264 u_int16_t max_lun; 265 266 u_int8_t msgin123[4]; 267 268 u_int8_t scan_devices[16][8]; 269 270 u_int8_t AdaptSCSIID; /*; Adapter SCSI Target ID */ 271 u_int8_t AdaptSCSILUN; /*; Adapter SCSI LUN */ 272 u_int8_t DeviceCnt; 273 u_int8_t ACBFlag; 274 275 u_int8_t TagMaxNum; 276 u_int8_t Config; 277 u_int8_t AdaptType; 278 u_int8_t AdapterUnit; /* nth Adapter this driver */ 279 }; 280 typedef struct _ACB TRM_ACB, *PACB; 281 /* 282 * ----SRB State machine definition 283 */ 284 #define SRB_FREE 0x0000 285 #define SRB_WAIT 0x0001 286 #define SRB_READY 0x0002 287 #define SRB_MSGOUT 0x0004 /*arbitration+msg_out 1st byte*/ 288 #define SRB_MSGIN 0x0008 289 #define SRB_EXTEND_MSGIN 0x0010 290 #define SRB_COMMAND 0x0020 291 #define SRB_START_ 0x0040 /*arbitration+msg_out+command_out*/ 292 #define SRB_DISCONNECT 0x0080 293 #define SRB_DATA_XFER 0x0100 294 #define SRB_XFERPAD 0x0200 295 #define SRB_STATUS 0x0400 296 #define SRB_COMPLETED 0x0800 297 #define SRB_ABORT_SENT 0x1000 298 #define SRB_DO_SYNC_NEGO 0x2000 299 #define SRB_DO_WIDE_NEGO 0x4000 300 #define SRB_UNEXPECT_RESEL 0x8000 301 /* 302 * 303 * ACB Config 304 * 305 */ 306 #define HCC_WIDE_CARD 0x20 307 #define HCC_SCSI_RESET 0x10 308 #define HCC_PARITY 0x08 309 #define HCC_AUTOTERM 0x04 310 #define HCC_LOW8TERM 0x02 311 #define HCC_UP8TERM 0x01 312 /* 313 * ---ACB Flag 314 */ 315 #define RESET_DEV 0x00000001 316 #define RESET_DETECT 0x00000002 317 #define RESET_DONE 0x00000004 318 319 /* 320 * ---DCB Flag 321 */ 322 #define ABORT_DEV_ 0x00000001 323 324 /* 325 * ---DCB status 326 */ 327 #define DS_IN_QUEUE 0x00000001 328 329 /* 330 * ---SRB status 331 */ 332 #define SRB_OK 0x00000001 333 #define ABORTION 0x00000002 334 #define OVER_RUN 0x00000004 335 #define UNDER_RUN 0x00000008 336 #define PARITY_ERROR 0x00000010 337 #define SRB_ERROR 0x00000020 338 339 /* 340 * ---SRB Flag 341 */ 342 #define DATAOUT 0x00000080 343 #define DATAIN 0x00000040 344 #define RESIDUAL_VALID 0x00000020 345 #define ENABLE_TIMER 0x00000010 346 #define RESET_DEV0 0x00000004 347 #define ABORT_DEV 0x00000002 348 #define AUTO_REQSENSE 0x00000001 349 350 /* 351 * ---Adapter status 352 */ 353 #define H_STATUS_GOOD 0x00 354 #define H_SEL_TIMEOUT 0x11 355 #define H_OVER_UNDER_RUN 0x12 356 #define H_UNEXP_BUS_FREE 0x13 357 #define H_TARGET_PHASE_F 0x14 358 #define H_INVALID_CCB_OP 0x16 359 #define H_LINK_CCB_BAD 0x17 360 #define H_BAD_TARGET_DIR 0x18 361 #define H_DUPLICATE_CCB 0x19 362 #define H_BAD_CCB_OR_SG 0x1A 363 #define H_ABORT 0x0FF 364 365 /* 366 * ---SCSI Status byte codes 367 */ 368 #define SCSI_STAT_GOOD 0x00 /*; Good status */ 369 #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */ 370 #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */ 371 #define SCSI_STAT_BUSY 0x08 /*; Target busy status */ 372 #define SCSI_STAT_INTER 0x10 /*; Intermediate status */ 373 #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */ 374 #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */ 375 #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */ 376 #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */ 377 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 378 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 379 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 380 381 /* 382 * ---Sync_Mode 383 */ 384 #define SYNC_WIDE_TAG_ATNT_DISABLE 0x00000000 385 #define SYNC_NEGO_ENABLE 0x00000001 386 #define SYNC_NEGO_DONE 0x00000002 387 #define WIDE_NEGO_ENABLE 0x00000004 388 #define WIDE_NEGO_DONE 0x00000008 389 #define EN_TAG_QUEUING 0x00000010 390 #define EN_ATN_STOP 0x00000020 391 392 #define SYNC_NEGO_OFFSET 15 393 /* 394 * ---SCSI bus phase 395 */ 396 #define SCSI_DATA_OUT_ 0 397 #define SCSI_DATA_IN_ 1 398 #define SCSI_COMMAND 2 399 #define SCSI_STATUS_ 3 400 #define SCSI_NOP0 4 401 #define SCSI_NOP1 5 402 #define SCSI_MSG_OUT 6 403 #define SCSI_MSG_IN 7 404 405 /* 406 * ----SCSI MSG u_int8_t 407 */ 408 #define MSG_COMPLETE 0x00 409 #define MSG_EXTENDED 0x01 410 #define MSG_SAVE_PTR 0x02 411 #define MSG_RESTORE_PTR 0x03 412 #define MSG_DISCONNECT 0x04 413 #define MSG_INITIATOR_ERROR 0x05 414 #define MSG_ABORT 0x06 415 #define MSG_REJECT_ 0x07 416 #define MSG_NOP 0x08 417 #define MSG_PARITY_ERROR 0x09 418 #define MSG_LINK_CMD_COMPL 0x0A 419 #define MSG_LINK_CMD_COMPL_FLG 0x0B 420 #define MSG_BUS_RESET 0x0C 421 /* #define MSG_ABORT_TAG 0x0D */ 422 #define MSG_SIMPLE_QTAG 0x20 423 #define MSG_HEAD_QTAG 0x21 424 #define MSG_ORDER_QTAG 0x22 425 #define MSG_IGNOREWIDE 0x23 426 /* #define MSG_IDENTIFY 0x80 */ 427 #define MSG_HOST_ID 0xC0 428 /* bus wide length */ 429 #define MSG_EXT_WDTR_BUS_8_BIT 0x00 430 #define MSG_EXT_WDTR_BUS_16_BIT 0x01 431 #define MSG_EXT_WDTR_BUS_32_BIT 0x02 432 /* 433 * ----SCSI STATUS u_int8_t 434 */ 435 #define STATUS_GOOD 0x00 436 #define CHECK_CONDITION_ 0x02 437 #define STATUS_BUSY 0x08 438 #define STATUS_INTERMEDIATE 0x10 439 #define RESERVE_CONFLICT 0x18 440 441 /* 442 * ---- cmd->result 443 */ 444 #define STATUS_MASK_ 0xFF 445 #define MSG_MASK 0xFF00 446 #define RETURN_MASK 0xFF0000 447 448 /* 449 * Inquiry Data format 450 */ 451 452 typedef struct _SCSIInqData { /* INQ */ 453 454 u_int8_t DevType; /* Periph Qualifier & Periph Dev Type */ 455 u_int8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 456 u_int8_t Vers; /* ISO, ECMA, & ANSI versions */ 457 u_int8_t RDF; /* AEN, TRMIOP, & response data format*/ 458 u_int8_t AddLen; /* length of additional data */ 459 u_int8_t Res1; /* reserved */ 460 u_int8_t Res2; /* reserved */ 461 u_int8_t Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ 462 u_int8_t VendorID[8]; /* Vendor Identification */ 463 u_int8_t ProductID[16]; /* Product Identification */ 464 u_int8_t ProductRev[4]; /* Product Revision */ 465 } SCSI_INQDATA, *PSCSI_INQDATA; 466 467 468 /* 469 * Inquiry byte 0 masks 470 */ 471 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ 472 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ 473 /* 474 * Inquiry byte 1 mask 475 */ 476 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ 477 /* 478 * Peripheral Device Type definitions 479 */ 480 #define SCSI_DASD 0x00 /* Direct-access Device */ 481 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 482 #define SCSI_PRINTER 0x02 /* Printer device */ 483 #define SCSI_PROCESSOR 0x03 /* Processor device */ 484 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 485 #define SCSI_CDROM 0x05 /* CD-ROM device */ 486 #define SCSI_SCANNER 0x06 /* Scanner device */ 487 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 488 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 489 #define SCSI_COMM 0x09 /* Communications device */ 490 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 491 /* 492 * Inquiry flag definitions (Inq data byte 7) 493 */ 494 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ 495 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ 496 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ 497 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ 498 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ 499 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ 500 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ 501 /* 502 *========================================================== 503 * EEPROM byte offset 504 *========================================================== 505 */ 506 typedef struct _EEprom { 507 u_int8_t EE_MODE1; 508 u_int8_t EE_SPEED; 509 u_int8_t xx1; 510 u_int8_t xx2; 511 } EEprom, *PEEprom; 512 513 #define EE_ADAPT_SCSI_ID 64 514 #define EE_MODE2 65 515 #define EE_DELAY 66 516 #define EE_TAG_CMD_NUM 67 517 518 /* 519 * EE_MODE1 bits definition 520 */ 521 #define PARITY_CHK_ 0x00000001 522 #define SYNC_NEGO_ 0x00000002 523 #define EN_DISCONNECT_ 0x00000004 524 #define SEND_START_ 0x00000008 525 #define TAG_QUEUING_ 0x00000010 526 527 /* 528 * EE_MODE2 bits definition 529 */ 530 #define MORE2_DRV 0x00000001 531 #define GREATER_1G 0x00000002 532 #define RST_SCSI_BUS 0x00000004 533 #define ACTIVE_NEGATION 0x00000008 534 #define NO_SEEK 0x00000010 535 #define LUN_CHECK 0x00000020 536 537 #define ENABLE_CE 0x01 538 #define DISABLE_CE 0x00 539 #define EEPROM_READ 0x80 540 541 /* 542 * The PCI configuration register offset for TRM_S1040 543 * Registers bit Definition 544 */ 545 #define TRMREG_ID 0x00 /* Vendor and Device ID */ 546 #define TRMREG_COMMAND 0x04 /* PCI command register */ 547 #define TRMREG_IOBASE 0x10 /* I/O Space base address */ 548 #define TRMREG_ROMBASE 0x30 /* Expansion ROM Base Address */ 549 #define TRMREG_INTLINE 0x3C /* Interrupt line */ 550 551 /* 552 * 553 * The SCSI register offset for TRM_S1040 554 * 555 */ 556 #define TRMREG_SCSI_STATUS 0x80 /* SCSI Status (R) */ 557 /* ######### */ 558 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 559 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */ 560 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero*/ 561 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 562 #define COMMANDABORT 0x0040 /* SCSI command abort */ 563 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 564 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 565 #define PARITYERROR 0x0008 /* SCSI parity error */ 566 567 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 568 #define PH_DATA_OUT 0x00 /* Data out phase */ 569 #define PH_DATA_IN 0x01 /* Data in phase */ 570 #define PH_COMMAND 0x02 /* Command phase */ 571 #define PH_STATUS 0x03 /* Status phase */ 572 #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */ 573 #define PH_MSG_OUT 0x06 /* Message out phase */ 574 #define PH_MSG_IN 0x07 /* Message in phase */ 575 576 #define TRMREG_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 577 /* ######### */ 578 #define DO_CLRATN 0x0400 /* Clear ATN */ 579 #define DO_SETATN 0x0200 /* Set ATN */ 580 #define DO_CMDABORT 0x0100 /* Abort SCSI command */ 581 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 582 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 583 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 584 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 585 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 586 #define TRMREG_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 587 #define TRMREG_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 588 #define TRMREG_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 589 /* ######### */ 590 #define INT_SCAM 0x80 /* SCAM selection interrupt */ 591 #define INT_SELECT 0x40 /* Selection interrupt */ 592 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 593 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 594 #define INT_RESELECTED 0x08 /* Reselected interrupt */ 595 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt*/ 596 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 597 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 598 #define TRMREG_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 599 /* 600 * Bit Name Definition 601 * 07-05 0 RSVD Reversed. Always 0. 602 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 603 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 604 */ 605 #define TRMREG_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W)*/ 606 /* ######### */ 607 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ 608 #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ 609 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ 610 /* 611 * SYNCM 7 6 5 4 3 2 1 0 612 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 613 * Default 0 0 0 0 0 0 0 0 614 * 615 * 616 * Bit Name Definition 617 * 07-06 0 RSVD Reversed. Always read 0 618 * 05 0 LVDS Reversed. Always read 0 619 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 620 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 621 * 622 * @@ When this bit is set, 623 * the synchronous period bits 2:0 624 * in the Synchronous Mode register 625 * are used to transfer data 626 * at the Fast-20 rate. 627 * @@ When this bit is reset, 628 * the synchronous period bits 2:0 629 * in the Synchronous Mode Register 630 * are used to transfer data 631 * at the Fast-40 rate. 632 * 633 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 634 * These 3 bits specify 635 * the Synchronous SCSI Transfer Rate 636 * for Fast-20 and Fast-10. 637 * These bits are also reset 638 * by a SCSI Bus reset. 639 * 640 * For Fast-10 bit ALTPD = 0 and LVDS = 0 641 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 642 * 643 * 000 100ns, 10.0 Mbytes/s 644 * 001 150ns, 6.6 Mbytes/s 645 * 010 200ns, 5.0 Mbytes/s 646 * 011 250ns, 4.0 Mbytes/s 647 * 100 300ns, 3.3 Mbytes/s 648 * 101 350ns, 2.8 Mbytes/s 649 * 110 400ns, 2.5 Mbytes/s 650 * 111 450ns, 2.2 Mbytes/s 651 * 652 * For Fast-20 bit ALTPD = 1 and LVDS = 0 653 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 654 * 655 * 000 50ns, 20.0 Mbytes/s 656 * 001 75ns, 13.3 Mbytes/s 657 * 010 100ns, 10.0 Mbytes/s 658 * 011 125ns, 8.0 Mbytes/s 659 * 100 150ns, 6.6 Mbytes/s 660 * 101 175ns, 5.7 Mbytes/s 661 * 110 200ns, 5.0 Mbytes/s 662 * 111 250ns, 4.0 Mbytes/s 663 * 664 * For Fast-40 bit ALTPD = 0 and LVDS = 1 665 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 666 * 667 * 000 25ns, 40.0 Mbytes/s 668 * 001 50ns, 20.0 Mbytes/s 669 * 010 75ns, 13.3 Mbytes/s 670 * 011 100ns, 10.0 Mbytes/s 671 * 100 125ns, 8.0 Mbytes/s 672 * 101 150ns, 6.6 Mbytes/s 673 * 110 175ns, 5.7 Mbytes/s 674 * 111 200ns, 5.0 Mbytes/s 675 */ 676 677 /* 678 *************************************** 679 */ 680 #define TRMREG_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 681 /* 682 *************************************** 683 */ 684 #define TRMREG_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 685 /* 686 *************************************** 687 */ 688 #define TRMREG_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 689 /* 690 *************************************** 691 */ 692 #define TRMREG_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W)*/ 693 /* 694 *************************************** 695 */ 696 #define TRMREG_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 697 /* ######### */ 698 #define EN_SCAM 0x80 /* Enable SCAM selection interrupt*/ 699 #define EN_SELECT 0x40 /* Enable selection interrupt */ 700 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt*/ 701 #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt*/ 702 #define EN_RESELECTED 0x08 /* Enable reselected interrupt */ 703 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/ 704 #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ 705 #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt*/ 706 /* 707 *************************************** 708 */ 709 #define TRMREG_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 710 /* ######### */ 711 #define PHASELATCH 0x40 /* Enable phase latch */ 712 #define INITIATOR 0x20 /* Enable initiator mode */ 713 #define PARITYCHECK 0x10 /* Enable parity check */ 714 #define BLOCKRST 0x01 /* Disable SCSI reset1 */ 715 /* 716 *************************************** 717 */ 718 #define TRMREG_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 719 /* ######### */ 720 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 721 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 722 #define ACTIVE_NEG 0x02 /* Enable active negation */ 723 #define ACTIVE_HISLEW 0x01 /* Enable high slew rate (3/6 ns) */ 724 /* 725 *************************************** 726 */ 727 #define TRMREG_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ 728 /* 729 *************************************** 730 */ 731 #define TRMREG_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 732 /* ######### */ 733 #define SCMD_COMP 0x12 /* Command complete */ 734 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 735 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 736 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 737 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 738 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 739 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 740 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 741 #define SCMD_MSGACCEPT 0xD8 /* Message accept */ 742 /* 743 * Code Command Description 744 * 745 * 02 Enable reselection with FIFO 746 * 40 Select without ATN with FIFO 747 * 60 Select with ATN with FIFO 748 * 64 Select with ATN3 with FIFO 749 * A0 Select with ATN and stop with FIFO 750 * C0 Transfer information out with FIFO 751 * C1 Transfer information out with DMA 752 * C2 Transfer information in with FIFO 753 * C3 Transfer information in with DMA 754 * 12 Initiator command complete with FIFO 755 * 50 Initiator transfer information out sequence without ATN with FIFO 756 * 70 Initiator transfer information out sequence with ATN with FIFO 757 * 74 Initiator transfer information out sequence with ATN3 with FIFO 758 * 52 Initiator transfer information in sequence without ATN with FIFO 759 * 72 Initiator transfer information in sequence with ATN with FIFO 760 * 76 Initiator transfer information in sequence with ATN3 with FIFO 761 * 90 Initiator transfer information out command complete with FIFO 762 * 92 Initiator transfer information in command complete with FIFO 763 * D2 Enable selection 764 * 08 Reselection 765 * 48 Disconnect command with FIFO 766 * 88 Terminate command with FIFO 767 * C8 Target command complete with FIFO 768 * 18 SCAM Arbitration/ Selection 769 * 5A Enable reselection 770 * 98 Select without ATN with FIFO 771 * B8 Select with ATN with FIFO 772 * D8 Message Accepted 773 * 58 NOP 774 */ 775 /* 776 *************************************** 777 */ 778 #define TRMREG_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 779 /* 780 *************************************** 781 */ 782 #define TRMREG_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 783 /* 784 *************************************** 785 */ 786 #define TRMREG_SCSI_TCR00 0x9C /* SCSI Target Control 0 (R/W) */ 787 /* ######### */ 788 #define TCR0_DO_WIDE_NEGO 0x80 /* Do wide NEGO */ 789 #define TCR0_DO_SYNC_NEGO 0x40 /* Do sync NEGO */ 790 #define TCR0_DISCONNECT_EN 0x20 /* Disconnection enable */ 791 #define TCR0_OFFSET_MASK 0x1F /* Offset number */ 792 /* 793 *************************************** 794 */ 795 #define TRMREG_SCSI_TCR01 0x9D /* SCSI Target Control 0 (R/W) */ 796 /* ######### */ 797 #define TCR0_ENABLE_LVDS 0xF8 /* LVD */ 798 #define TCR0_ENABLE_WIDE 0xF9 /* SE */ 799 /* 800 **************************************** 801 */ 802 803 /* 804 *************************************** 805 */ 806 #define TRMREG_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 807 /* ######### */ 808 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 809 #define NON_TAG_BUSY 0x0080 /* Non tag command active */ 810 #define ACTTAG_MASK 0x007F /* Active tags */ 811 /* 812 * 813 * The DMA register offset for TRM_S1040 814 * 815 */ 816 #define TRMREG_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 817 /* ######### */ 818 #define XFERDATAIN 0x0103 /* Transfer data in */ 819 #define XFERDATAOUT 0x0102 /* Transfer data out */ 820 /* 821 *************************************** 822 */ 823 #define TRMREG_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 824 /* 825 *************************************** 826 */ 827 #define TRMREG_DMA_CONTROL 0xA1 /* DMA Control (W) */ 828 /* ######### */ 829 #define STOPDMAXFER 0x08 /* Stop DMA transfer */ 830 #define ABORTXFER 0x04 /* Abort DMA transfer */ 831 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 832 #define STARTDMAXFER 0x01 /* Start DMA transfer */ 833 /* 834 *************************************** 835 */ 836 #define TRMREG_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 837 /* ######### */ 838 #define XFERPENDING 0x80 /* Transfer pending */ 839 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 840 #define SCSICOMP 0x01 /* SCSI complete interrupt */ 841 /* 842 *************************************** 843 */ 844 #define TRMREG_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W)*/ 845 /* ######### */ 846 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 847 /* 848 *************************************** 849 */ 850 #define TRMREG_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 851 /* ######### */ 852 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 853 /* 854 *************************************** 855 */ 856 #define TRMREG_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W)*/ 857 /* 858 *************************************** 859 */ 860 #define TRMREG_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 861 /* 862 *************************************** 863 */ 864 #define TRMREG_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ 865 /* 866 *************************************** 867 */ 868 #define TRMREG_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ 869 870 /* 871 * 872 * The general register offset for TRM_S1040 873 * 874 */ 875 #define TRMREG_GEN_CONTROL 0xD4 /* Global Control */ 876 /* ######### */ 877 #define EN_EEPROM 0x10 /* Enable EEPROM programming */ 878 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 879 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 880 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 881 /* 882 *************************************** 883 */ 884 #define TRMREG_GEN_STATUS 0xD5 /* Global Status */ 885 /* ######### */ 886 #define GTIMEOUT 0x80 /* Global timer reach 0 */ 887 #define CON5068 0x10 /* External 50/68 pin connected */ 888 #define CON68 0x08 /* Internal 68 pin connected */ 889 #define CON50 0x04 /* Internal 50 pin connected */ 890 #define WIDESCSI 0x02 /* Wide SCSI card */ 891 /* 892 *************************************** 893 */ 894 #define TRMREG_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ 895 /* ######### */ 896 #define NVR_BITOUT 0x08 /* Serial data out */ 897 #define NVR_BITIN 0x04 /* Serial data in */ 898 #define NVR_CLOCK 0x02 /* Serial clock */ 899 #define NVR_SELECT 0x01 /* Serial select */ 900 /* 901 *************************************** 902 */ 903 #define TRMREG_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ 904 /* 905 *************************************** 906 */ 907 #define TRMREG_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ 908 /* 909 *************************************** 910 */ 911 #define TRMREG_GEN_TIMER 0xDB /* Global timer */ 912 913 /* 914 * The SEEPROM structure for TRM_S1040 915 */ 916 typedef struct NVRAM_TARGET_STRUCT 917 { 918 u_int8_t NvmTarCfg0; /* Target configuration byte 0 */ 919 u_int8_t NvmTarPeriod; /* Target period */ 920 u_int8_t NvmTarCfg2; /* Target configuration byte 2 */ 921 u_int8_t NvmTarCfg3; /* Target configuration byte 3 */ 922 } NVRAMTARGETTYPE; 923 /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */ 924 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 925 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 926 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP*/ 927 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 928 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 929 #define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC ) 930 Parity check enable */ 931 932 /* 933 * 934 * 935 * 936 */ 937 typedef struct NVRAM_STRUC { 938 u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */ 939 u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID*/ 940 u_int8_t NvramSubClass; /*4 Sub Class */ 941 u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */ 942 u_int8_t NvramDeviceID[2]; /*7,8 Device ID */ 943 u_int8_t NvramReserved; /*9 Reserved */ 944 NVRAMTARGETTYPE NvramTarget[TRM_MAX_TARGETS];/* *10,11,12,13 945 *14,15,16,17 * .... 946 * .... 947 *70,71,72,73 948 */ 949 u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */ 950 u_int8_t NvramChannelCfg; /*75 Channel configuration */ 951 u_int8_t NvramDelayTime; /*76 Power on delay time */ 952 u_int8_t NvramMaxTag; /*77 Maximum tags */ 953 u_int8_t NvramReserved0; /*78 */ 954 u_int8_t NvramBootTarget; /*79 */ 955 u_int8_t NvramBootLun; /*80 */ 956 u_int8_t NvramReserved1; /*81 */ 957 u_int16_t Reserved[22]; /*82,..125 */ 958 u_int16_t NvramCheckSum; /*126,127*/ 959 } NVRAMTYPE,*PNVRAMTYPE; 960 /* Nvram Initiater bits definition */ 961 #define MORE2_DRV 0x00000001 962 #define GREATER_1G 0x00000002 963 #define RST_SCSI_BUS 0x00000004 964 #define ACTIVE_NEGATION 0x00000008 965 #define NO_SEEK 0x00000010 966 #define LUN_CHECK 0x00000020 967 968 /* Nvram Adapter NvramChannelCfg bits definition */ 969 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/ 970 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 971 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 972 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives*/ 973 /* 974 *#define NAC_DO_PARITY_CHK 0x08 // Parity check enable 975 */ 976 977 #endif /* trm_H */
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