Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/tsec/if_tsec.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski 5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_device_polling.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 50 #include <net/bpf.h> 51 #include <net/ethernet.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in_systm.h> 61 #include <netinet/in.h> 62 #include <netinet/ip.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/tsec/if_tsec.h> 70 #include <dev/tsec/if_tsecreg.h> 71 72 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 73 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 74 const char *dname); 75 static void tsec_dma_ctl(struct tsec_softc *sc, int state); 76 static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, 77 struct mbuf *m0, uint16_t fcb_flags, int *start_tx); 78 static void tsec_free_dma(struct tsec_softc *sc); 79 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 80 static int tsec_ifmedia_upd(struct ifnet *ifp); 81 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 82 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 83 struct mbuf **mbufp, uint32_t *paddr); 84 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 85 int nseg, int error); 86 static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 87 static void tsec_init(void *xsc); 88 static void tsec_init_locked(struct tsec_softc *sc); 89 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 90 static void tsec_reset_mac(struct tsec_softc *sc); 91 static void tsec_setfilter(struct tsec_softc *sc); 92 static void tsec_set_mac_address(struct tsec_softc *sc); 93 static void tsec_start(struct ifnet *ifp); 94 static void tsec_start_locked(struct ifnet *ifp); 95 static void tsec_stop(struct tsec_softc *sc); 96 static void tsec_tick(void *arg); 97 static void tsec_watchdog(struct tsec_softc *sc); 98 static void tsec_add_sysctls(struct tsec_softc *sc); 99 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 100 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 101 static void tsec_set_rxic(struct tsec_softc *sc); 102 static void tsec_set_txic(struct tsec_softc *sc); 103 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 104 static void tsec_transmit_intr_locked(struct tsec_softc *sc); 105 static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 106 static void tsec_offload_setup(struct tsec_softc *sc); 107 static void tsec_offload_process_frame(struct tsec_softc *sc, 108 struct mbuf *m); 109 static void tsec_setup_multicast(struct tsec_softc *sc); 110 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 111 112 DRIVER_MODULE(miibus, tsec, miibus_driver, 0, 0); 113 MODULE_DEPEND(tsec, ether, 1, 1, 1); 114 MODULE_DEPEND(tsec, miibus, 1, 1, 1); 115 116 struct mtx tsec_phy_mtx; 117 118 int 119 tsec_attach(struct tsec_softc *sc) 120 { 121 uint8_t hwaddr[ETHER_ADDR_LEN]; 122 struct ifnet *ifp; 123 int error = 0; 124 int i; 125 126 /* Initialize global (because potentially shared) MII lock */ 127 if (!mtx_initialized(&tsec_phy_mtx)) 128 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF); 129 130 /* Reset all TSEC counters */ 131 TSEC_TX_RX_COUNTERS_INIT(sc); 132 133 /* Stop DMA engine if enabled by firmware */ 134 tsec_dma_ctl(sc, 0); 135 136 /* Reset MAC */ 137 tsec_reset_mac(sc); 138 139 /* Disable interrupts for now */ 140 tsec_intrs_ctl(sc, 0); 141 142 /* Configure defaults for interrupts coalescing */ 143 sc->rx_ic_time = 768; 144 sc->rx_ic_count = 16; 145 sc->tx_ic_time = 768; 146 sc->tx_ic_count = 16; 147 tsec_set_rxic(sc); 148 tsec_set_txic(sc); 149 tsec_add_sysctls(sc); 150 151 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 152 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 153 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 154 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 155 156 if (error) { 157 tsec_detach(sc); 158 return (ENXIO); 159 } 160 161 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 162 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 163 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 164 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 165 if (error) { 166 tsec_detach(sc); 167 return (ENXIO); 168 } 169 170 /* Allocate a busdma tag for TX mbufs. */ 171 error = bus_dma_tag_create(NULL, /* parent */ 172 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 173 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 174 BUS_SPACE_MAXADDR, /* highaddr */ 175 NULL, NULL, /* filtfunc, filtfuncarg */ 176 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 177 TSEC_TX_MAX_DMA_SEGS, /* nsegments */ 178 MCLBYTES, 0, /* maxsegsz, flags */ 179 NULL, NULL, /* lockfunc, lockfuncarg */ 180 &sc->tsec_tx_mtag); /* dmat */ 181 if (error) { 182 device_printf(sc->dev, "failed to allocate busdma tag " 183 "(tx mbufs)\n"); 184 tsec_detach(sc); 185 return (ENXIO); 186 } 187 188 /* Allocate a busdma tag for RX mbufs. */ 189 error = bus_dma_tag_create(NULL, /* parent */ 190 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 191 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 192 BUS_SPACE_MAXADDR, /* highaddr */ 193 NULL, NULL, /* filtfunc, filtfuncarg */ 194 MCLBYTES, /* maxsize */ 195 1, /* nsegments */ 196 MCLBYTES, 0, /* maxsegsz, flags */ 197 NULL, NULL, /* lockfunc, lockfuncarg */ 198 &sc->tsec_rx_mtag); /* dmat */ 199 if (error) { 200 device_printf(sc->dev, "failed to allocate busdma tag " 201 "(rx mbufs)\n"); 202 tsec_detach(sc); 203 return (ENXIO); 204 } 205 206 /* Create TX busdma maps */ 207 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, 209 &sc->tx_bufmap[i].map); 210 if (error) { 211 device_printf(sc->dev, "failed to init TX ring\n"); 212 tsec_detach(sc); 213 return (ENXIO); 214 } 215 sc->tx_bufmap[i].map_initialized = 1; 216 } 217 218 /* Create RX busdma maps and zero mbuf handlers */ 219 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 220 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 221 &sc->rx_data[i].map); 222 if (error) { 223 device_printf(sc->dev, "failed to init RX ring\n"); 224 tsec_detach(sc); 225 return (ENXIO); 226 } 227 sc->rx_data[i].mbuf = NULL; 228 } 229 230 /* Create mbufs for RX buffers */ 231 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 232 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 233 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 234 if (error) { 235 device_printf(sc->dev, "can't load rx DMA map %d, " 236 "error = %d\n", i, error); 237 tsec_detach(sc); 238 return (error); 239 } 240 } 241 242 /* Create network interface for upper layers */ 243 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 244 if (ifp == NULL) { 245 device_printf(sc->dev, "if_alloc() failed\n"); 246 tsec_detach(sc); 247 return (ENOMEM); 248 } 249 250 ifp->if_softc = sc; 251 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 252 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 253 ifp->if_init = tsec_init; 254 ifp->if_start = tsec_start; 255 ifp->if_ioctl = tsec_ioctl; 256 257 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 258 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 259 IFQ_SET_READY(&ifp->if_snd); 260 261 ifp->if_capabilities = IFCAP_VLAN_MTU; 262 if (sc->is_etsec) 263 ifp->if_capabilities |= IFCAP_HWCSUM; 264 265 ifp->if_capenable = ifp->if_capabilities; 266 267 #ifdef DEVICE_POLLING 268 /* Advertise that polling is supported */ 269 ifp->if_capabilities |= IFCAP_POLLING; 270 #endif 271 272 /* Attach PHY(s) */ 273 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 274 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 275 0); 276 if (error) { 277 device_printf(sc->dev, "attaching PHYs failed\n"); 278 if_free(ifp); 279 sc->tsec_ifp = NULL; 280 tsec_detach(sc); 281 return (error); 282 } 283 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 284 285 /* Set MAC address */ 286 tsec_get_hwaddr(sc, hwaddr); 287 ether_ifattach(ifp, hwaddr); 288 289 return (0); 290 } 291 292 int 293 tsec_detach(struct tsec_softc *sc) 294 { 295 296 if (sc->tsec_ifp != NULL) { 297 #ifdef DEVICE_POLLING 298 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 299 ether_poll_deregister(sc->tsec_ifp); 300 #endif 301 302 /* Stop TSEC controller and free TX queue */ 303 if (sc->sc_rres) 304 tsec_shutdown(sc->dev); 305 306 /* Detach network interface */ 307 ether_ifdetach(sc->tsec_ifp); 308 if_free(sc->tsec_ifp); 309 sc->tsec_ifp = NULL; 310 } 311 312 /* Free DMA resources */ 313 tsec_free_dma(sc); 314 315 return (0); 316 } 317 318 int 319 tsec_shutdown(device_t dev) 320 { 321 struct tsec_softc *sc; 322 323 sc = device_get_softc(dev); 324 325 TSEC_GLOBAL_LOCK(sc); 326 tsec_stop(sc); 327 TSEC_GLOBAL_UNLOCK(sc); 328 return (0); 329 } 330 331 int 332 tsec_suspend(device_t dev) 333 { 334 335 /* TODO not implemented! */ 336 return (0); 337 } 338 339 int 340 tsec_resume(device_t dev) 341 { 342 343 /* TODO not implemented! */ 344 return (0); 345 } 346 347 static void 348 tsec_init(void *xsc) 349 { 350 struct tsec_softc *sc = xsc; 351 352 TSEC_GLOBAL_LOCK(sc); 353 tsec_init_locked(sc); 354 TSEC_GLOBAL_UNLOCK(sc); 355 } 356 357 static int 358 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags) 359 { 360 int timeout; 361 362 /* 363 * The status indicators are not set immediately after a command. 364 * Discard the first value. 365 */ 366 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND); 367 368 timeout = TSEC_READ_RETRY; 369 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout) 370 DELAY(TSEC_READ_DELAY); 371 372 return (timeout == 0); 373 } 374 375 static void 376 tsec_init_locked(struct tsec_softc *sc) 377 { 378 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 379 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 380 struct ifnet *ifp = sc->tsec_ifp; 381 uint32_t val, i; 382 int timeout; 383 384 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 385 return; 386 387 TSEC_GLOBAL_LOCK_ASSERT(sc); 388 tsec_stop(sc); 389 390 /* 391 * These steps are according to the MPC8555E PowerQUICCIII RM: 392 * 14.7 Initialization/Application Information 393 */ 394 395 /* Step 1: soft reset MAC */ 396 tsec_reset_mac(sc); 397 398 /* Step 2: Initialize MACCFG2 */ 399 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 400 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 401 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 402 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 403 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 404 ); 405 406 /* Step 3: Initialize ECNTRL 407 * While the documentation states that R100M is ignored if RPM is 408 * not set, it does seem to be needed to get the orange boxes to 409 * work (which have a Marvell 88E1111 PHY). Go figure. 410 */ 411 412 /* 413 * XXX kludge - use circumstancial evidence to program ECNTRL 414 * correctly. Ideally we need some board information to guide 415 * us here. 416 */ 417 i = TSEC_READ(sc, TSEC_REG_ID2); 418 val = (i & 0xffff) 419 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 420 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 421 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 422 423 /* Step 4: Initialize MAC station address */ 424 tsec_set_mac_address(sc); 425 426 /* 427 * Step 5: Assign a Physical address to the TBI so as to not conflict 428 * with the external PHY physical address 429 */ 430 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 431 432 TSEC_PHY_LOCK(sc); 433 434 /* Step 6: Reset the management interface */ 435 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 436 437 /* Step 7: Setup the MII Mgmt clock speed */ 438 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 439 440 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 441 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY); 442 443 TSEC_PHY_UNLOCK(sc); 444 if (timeout) { 445 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 446 return; 447 } 448 449 /* Step 9: Setup the MII Mgmt */ 450 mii_mediachg(sc->tsec_mii); 451 452 /* Step 10: Clear IEVENT register */ 453 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 454 455 /* Step 11: Enable interrupts */ 456 #ifdef DEVICE_POLLING 457 /* 458 * ...only if polling is not turned on. Disable interrupts explicitly 459 * if polling is enabled. 460 */ 461 if (ifp->if_capenable & IFCAP_POLLING ) 462 tsec_intrs_ctl(sc, 0); 463 else 464 #endif /* DEVICE_POLLING */ 465 tsec_intrs_ctl(sc, 1); 466 467 /* Step 12: Initialize IADDRn */ 468 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 469 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 470 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 471 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 472 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 473 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 474 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 475 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 476 477 /* Step 13: Initialize GADDRn */ 478 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 479 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 480 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 481 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 482 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 483 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 484 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 485 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 486 487 /* Step 14: Initialize RCTRL */ 488 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 489 490 /* Step 15: Initialize DMACTRL */ 491 tsec_dma_ctl(sc, 1); 492 493 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 494 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 495 496 /* 497 * Step 17: Initialize transmit/receive descriptor rings. 498 * Initialize TBASE and RBASE. 499 */ 500 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 501 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 502 503 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 504 tx_desc[i].bufptr = 0; 505 tx_desc[i].length = 0; 506 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 507 TSEC_TXBD_W : 0); 508 } 509 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 511 512 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 513 rx_desc[i].bufptr = sc->rx_data[i].paddr; 514 rx_desc[i].length = 0; 515 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 516 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 517 } 518 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 519 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 520 521 /* Step 18: Initialize the maximum receive buffer length */ 522 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 523 524 /* Step 19: Configure ethernet frame sizes */ 525 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 526 tsec_set_mtu(sc, ifp->if_mtu); 527 528 /* Step 20: Enable Rx and RxBD sdata snooping */ 529 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 530 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 531 532 /* Step 21: Reset collision counters in hardware */ 533 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 534 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 535 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 536 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 537 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 538 539 /* Step 22: Mask all CAM interrupts */ 540 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 541 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 542 543 /* Step 23: Enable Rx and Tx */ 544 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 545 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 546 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 547 548 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 549 TSEC_TX_RX_COUNTERS_INIT(sc); 550 551 /* Step 25: Setup TCP/IP Off-Load engine */ 552 if (sc->is_etsec) 553 tsec_offload_setup(sc); 554 555 /* Step 26: Setup multicast filters */ 556 tsec_setup_multicast(sc); 557 558 /* Step 27: Activate network interface */ 559 ifp->if_drv_flags |= IFF_DRV_RUNNING; 560 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 561 sc->tsec_if_flags = ifp->if_flags; 562 sc->tsec_watchdog = 0; 563 564 /* Schedule watchdog timeout */ 565 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 566 } 567 568 static void 569 tsec_set_mac_address(struct tsec_softc *sc) 570 { 571 uint32_t macbuf[2] = { 0, 0 }; 572 char *macbufp, *curmac; 573 int i; 574 575 TSEC_GLOBAL_LOCK_ASSERT(sc); 576 577 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 578 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN, 579 sizeof(macbuf))); 580 581 macbufp = (char *)macbuf; 582 curmac = (char *)IF_LLADDR(sc->tsec_ifp); 583 584 /* Correct order of MAC address bytes */ 585 for (i = 1; i <= ETHER_ADDR_LEN; i++) 586 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 587 588 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 589 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 590 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 591 } 592 593 /* 594 * DMA control function, if argument state is: 595 * 0 - DMA engine will be disabled 596 * 1 - DMA engine will be enabled 597 */ 598 static void 599 tsec_dma_ctl(struct tsec_softc *sc, int state) 600 { 601 device_t dev; 602 uint32_t dma_flags, timeout; 603 604 dev = sc->dev; 605 606 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 607 608 switch (state) { 609 case 0: 610 /* Temporarily clear stop graceful stop bits. */ 611 tsec_dma_ctl(sc, 1000); 612 613 /* Set it again */ 614 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 615 break; 616 case 1000: 617 case 1: 618 /* Set write with response (WWR), wait (WOP) and snoop bits */ 619 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 620 DMACTRL_WWR | DMACTRL_WOP); 621 622 /* Clear graceful stop bits */ 623 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 624 break; 625 default: 626 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 627 state); 628 } 629 630 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 631 632 switch (state) { 633 case 0: 634 /* Wait for DMA stop */ 635 timeout = TSEC_READ_RETRY; 636 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 637 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 638 DELAY(TSEC_READ_DELAY); 639 640 if (timeout == 0) 641 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 642 break; 643 case 1: 644 /* Restart transmission function */ 645 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 646 } 647 } 648 649 /* 650 * Interrupts control function, if argument state is: 651 * 0 - all TSEC interrupts will be masked 652 * 1 - all TSEC interrupts will be unmasked 653 */ 654 static void 655 tsec_intrs_ctl(struct tsec_softc *sc, int state) 656 { 657 device_t dev; 658 659 dev = sc->dev; 660 661 switch (state) { 662 case 0: 663 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 664 break; 665 case 1: 666 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 667 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 668 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 669 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 670 break; 671 default: 672 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 673 state); 674 } 675 } 676 677 static void 678 tsec_reset_mac(struct tsec_softc *sc) 679 { 680 uint32_t maccfg1_flags; 681 682 /* Set soft reset bit */ 683 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 684 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 685 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 686 687 /* Clear soft reset bit */ 688 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 689 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 690 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 691 } 692 693 static void 694 tsec_watchdog(struct tsec_softc *sc) 695 { 696 struct ifnet *ifp; 697 698 TSEC_GLOBAL_LOCK_ASSERT(sc); 699 700 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 701 return; 702 703 ifp = sc->tsec_ifp; 704 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 705 if_printf(ifp, "watchdog timeout\n"); 706 707 tsec_stop(sc); 708 tsec_init_locked(sc); 709 } 710 711 static void 712 tsec_start(struct ifnet *ifp) 713 { 714 struct tsec_softc *sc = ifp->if_softc; 715 716 TSEC_TRANSMIT_LOCK(sc); 717 tsec_start_locked(ifp); 718 TSEC_TRANSMIT_UNLOCK(sc); 719 } 720 721 static void 722 tsec_start_locked(struct ifnet *ifp) 723 { 724 struct tsec_softc *sc; 725 struct mbuf *m0; 726 struct tsec_tx_fcb *tx_fcb; 727 int csum_flags; 728 int start_tx; 729 uint16_t fcb_flags; 730 731 sc = ifp->if_softc; 732 start_tx = 0; 733 734 TSEC_TRANSMIT_LOCK_ASSERT(sc); 735 736 if (sc->tsec_link == 0) 737 return; 738 739 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 740 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 741 742 for (;;) { 743 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) { 744 /* No free descriptors */ 745 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 746 break; 747 } 748 749 /* Get packet from the queue */ 750 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 751 if (m0 == NULL) 752 break; 753 754 /* Insert TCP/IP Off-load frame control block */ 755 fcb_flags = 0; 756 csum_flags = m0->m_pkthdr.csum_flags; 757 if (csum_flags) { 758 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT); 759 if (m0 == NULL) 760 break; 761 762 if (csum_flags & CSUM_IP) 763 fcb_flags |= TSEC_TX_FCB_IP4 | 764 TSEC_TX_FCB_CSUM_IP; 765 766 if (csum_flags & CSUM_TCP) 767 fcb_flags |= TSEC_TX_FCB_TCP | 768 TSEC_TX_FCB_CSUM_TCP_UDP; 769 770 if (csum_flags & CSUM_UDP) 771 fcb_flags |= TSEC_TX_FCB_UDP | 772 TSEC_TX_FCB_CSUM_TCP_UDP; 773 774 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 775 tx_fcb->flags = fcb_flags; 776 tx_fcb->l3_offset = ETHER_HDR_LEN; 777 tx_fcb->l4_offset = sizeof(struct ip); 778 } 779 780 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx); 781 } 782 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 783 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 784 785 if (start_tx) { 786 /* Enable transmitter and watchdog timer */ 787 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 788 sc->tsec_watchdog = 5; 789 } 790 } 791 792 static void 793 tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0, 794 uint16_t fcb_flags, int *start_tx) 795 { 796 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS]; 797 int error, i, nsegs; 798 struct tsec_bufmap *tx_bufmap; 799 uint32_t tx_idx; 800 uint16_t flags; 801 802 TSEC_TRANSMIT_LOCK_ASSERT(sc); 803 804 tx_idx = sc->tx_idx_head; 805 tx_bufmap = &sc->tx_bufmap[tx_idx]; 806 807 /* Create mapping in DMA memory */ 808 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0, 809 segs, &nsegs, BUS_DMA_NOWAIT); 810 if (error == EFBIG) { 811 /* Too many segments! Defrag and try again. */ 812 struct mbuf *m = m_defrag(m0, M_NOWAIT); 813 814 if (m == NULL) { 815 m_freem(m0); 816 return; 817 } 818 m0 = m; 819 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 820 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 821 } 822 if (error != 0) { 823 /* Give up. */ 824 m_freem(m0); 825 return; 826 } 827 828 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map, 829 BUS_DMASYNC_PREWRITE); 830 tx_bufmap->mbuf = m0; 831 832 /* 833 * Fill in the TX descriptors back to front so that READY bit in first 834 * descriptor is set last. 835 */ 836 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1); 837 sc->tx_idx_head = tx_idx; 838 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC; 839 for (i = nsegs - 1; i >= 0; i--) { 840 struct tsec_desc *tx_desc; 841 842 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1); 843 tx_desc = &sc->tsec_tx_vaddr[tx_idx]; 844 tx_desc->length = segs[i].ds_len; 845 tx_desc->bufptr = segs[i].ds_addr; 846 847 if (i == 0) { 848 wmb(); 849 850 if (fcb_flags != 0) 851 flags |= TSEC_TXBD_TOE; 852 } 853 854 /* 855 * Set flags: 856 * - wrap 857 * - checksum 858 * - ready to send 859 * - transmit the CRC sequence after the last data byte 860 * - interrupt after the last buffer 861 */ 862 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ? 863 TSEC_TXBD_W : 0) | flags; 864 865 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I); 866 } 867 868 BPF_MTAP(ifp, m0); 869 *start_tx = 1; 870 } 871 872 static void 873 tsec_setfilter(struct tsec_softc *sc) 874 { 875 struct ifnet *ifp; 876 uint32_t flags; 877 878 ifp = sc->tsec_ifp; 879 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 880 881 /* Promiscuous mode */ 882 if (ifp->if_flags & IFF_PROMISC) 883 flags |= TSEC_RCTRL_PROM; 884 else 885 flags &= ~TSEC_RCTRL_PROM; 886 887 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 888 } 889 890 #ifdef DEVICE_POLLING 891 static poll_handler_t tsec_poll; 892 893 static int 894 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 895 { 896 uint32_t ie; 897 struct tsec_softc *sc = ifp->if_softc; 898 int rx_npkts; 899 900 rx_npkts = 0; 901 902 TSEC_GLOBAL_LOCK(sc); 903 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 904 TSEC_GLOBAL_UNLOCK(sc); 905 return (rx_npkts); 906 } 907 908 if (cmd == POLL_AND_CHECK_STATUS) { 909 tsec_error_intr_locked(sc, count); 910 911 /* Clear all events reported */ 912 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 913 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 914 } 915 916 tsec_transmit_intr_locked(sc); 917 918 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 919 920 rx_npkts = tsec_receive_intr_locked(sc, count); 921 922 TSEC_RECEIVE_UNLOCK(sc); 923 924 return (rx_npkts); 925 } 926 #endif /* DEVICE_POLLING */ 927 928 static int 929 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 930 { 931 struct tsec_softc *sc = ifp->if_softc; 932 struct ifreq *ifr = (struct ifreq *)data; 933 int mask, error = 0; 934 935 switch (command) { 936 case SIOCSIFMTU: 937 TSEC_GLOBAL_LOCK(sc); 938 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 939 ifp->if_mtu = ifr->ifr_mtu; 940 else 941 error = EINVAL; 942 TSEC_GLOBAL_UNLOCK(sc); 943 break; 944 case SIOCSIFFLAGS: 945 TSEC_GLOBAL_LOCK(sc); 946 if (ifp->if_flags & IFF_UP) { 947 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 948 if ((sc->tsec_if_flags ^ ifp->if_flags) & 949 IFF_PROMISC) 950 tsec_setfilter(sc); 951 952 if ((sc->tsec_if_flags ^ ifp->if_flags) & 953 IFF_ALLMULTI) 954 tsec_setup_multicast(sc); 955 } else 956 tsec_init_locked(sc); 957 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 958 tsec_stop(sc); 959 960 sc->tsec_if_flags = ifp->if_flags; 961 TSEC_GLOBAL_UNLOCK(sc); 962 break; 963 case SIOCADDMULTI: 964 case SIOCDELMULTI: 965 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 966 TSEC_GLOBAL_LOCK(sc); 967 tsec_setup_multicast(sc); 968 TSEC_GLOBAL_UNLOCK(sc); 969 } 970 case SIOCGIFMEDIA: 971 case SIOCSIFMEDIA: 972 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 973 command); 974 break; 975 case SIOCSIFCAP: 976 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 977 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 978 TSEC_GLOBAL_LOCK(sc); 979 ifp->if_capenable &= ~IFCAP_HWCSUM; 980 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 981 tsec_offload_setup(sc); 982 TSEC_GLOBAL_UNLOCK(sc); 983 } 984 #ifdef DEVICE_POLLING 985 if (mask & IFCAP_POLLING) { 986 if (ifr->ifr_reqcap & IFCAP_POLLING) { 987 error = ether_poll_register(tsec_poll, ifp); 988 if (error) 989 return (error); 990 991 TSEC_GLOBAL_LOCK(sc); 992 /* Disable interrupts */ 993 tsec_intrs_ctl(sc, 0); 994 ifp->if_capenable |= IFCAP_POLLING; 995 TSEC_GLOBAL_UNLOCK(sc); 996 } else { 997 error = ether_poll_deregister(ifp); 998 TSEC_GLOBAL_LOCK(sc); 999 /* Enable interrupts */ 1000 tsec_intrs_ctl(sc, 1); 1001 ifp->if_capenable &= ~IFCAP_POLLING; 1002 TSEC_GLOBAL_UNLOCK(sc); 1003 } 1004 } 1005 #endif 1006 break; 1007 1008 default: 1009 error = ether_ioctl(ifp, command, data); 1010 } 1011 1012 /* Flush buffers if not empty */ 1013 if (ifp->if_flags & IFF_UP) 1014 tsec_start(ifp); 1015 return (error); 1016 } 1017 1018 static int 1019 tsec_ifmedia_upd(struct ifnet *ifp) 1020 { 1021 struct tsec_softc *sc = ifp->if_softc; 1022 struct mii_data *mii; 1023 1024 TSEC_TRANSMIT_LOCK(sc); 1025 1026 mii = sc->tsec_mii; 1027 mii_mediachg(mii); 1028 1029 TSEC_TRANSMIT_UNLOCK(sc); 1030 return (0); 1031 } 1032 1033 static void 1034 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1035 { 1036 struct tsec_softc *sc = ifp->if_softc; 1037 struct mii_data *mii; 1038 1039 TSEC_TRANSMIT_LOCK(sc); 1040 1041 mii = sc->tsec_mii; 1042 mii_pollstat(mii); 1043 1044 ifmr->ifm_active = mii->mii_media_active; 1045 ifmr->ifm_status = mii->mii_media_status; 1046 1047 TSEC_TRANSMIT_UNLOCK(sc); 1048 } 1049 1050 static int 1051 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1052 uint32_t *paddr) 1053 { 1054 struct mbuf *new_mbuf; 1055 bus_dma_segment_t seg[1]; 1056 int error, nsegs; 1057 1058 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1059 1060 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1061 if (new_mbuf == NULL) 1062 return (ENOBUFS); 1063 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1064 1065 if (*mbufp) { 1066 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1067 bus_dmamap_unload(tag, map); 1068 } 1069 1070 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1071 BUS_DMA_NOWAIT); 1072 KASSERT(nsegs == 1, ("Too many segments returned!")); 1073 if (nsegs != 1 || error) 1074 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1075 1076 #if 0 1077 if (error) { 1078 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1079 error); 1080 m_freem(new_mbuf); 1081 return (ENOBUFS); 1082 } 1083 #endif 1084 1085 #if 0 1086 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1087 ("Wrong alignment of RX buffer!")); 1088 #endif 1089 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1090 1091 (*mbufp) = new_mbuf; 1092 (*paddr) = seg->ds_addr; 1093 return (0); 1094 } 1095 1096 static void 1097 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1098 { 1099 u_int32_t *paddr; 1100 1101 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1102 paddr = arg; 1103 *paddr = segs->ds_addr; 1104 } 1105 1106 static int 1107 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1108 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1109 { 1110 int error; 1111 1112 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1113 error = bus_dma_tag_create(NULL, /* parent */ 1114 PAGE_SIZE, 0, /* alignment, boundary */ 1115 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1116 BUS_SPACE_MAXADDR, /* highaddr */ 1117 NULL, NULL, /* filtfunc, filtfuncarg */ 1118 dsize, 1, /* maxsize, nsegments */ 1119 dsize, 0, /* maxsegsz, flags */ 1120 NULL, NULL, /* lockfunc, lockfuncarg */ 1121 dtag); /* dmat */ 1122 1123 if (error) { 1124 device_printf(dev, "failed to allocate busdma %s tag\n", 1125 dname); 1126 (*vaddr) = NULL; 1127 return (ENXIO); 1128 } 1129 1130 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1131 dmap); 1132 if (error) { 1133 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1134 dname); 1135 bus_dma_tag_destroy(*dtag); 1136 (*vaddr) = NULL; 1137 return (ENXIO); 1138 } 1139 1140 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1141 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1142 if (error) { 1143 device_printf(dev, "cannot get address of the %s " 1144 "descriptors\n", dname); 1145 bus_dmamem_free(*dtag, *vaddr, *dmap); 1146 bus_dma_tag_destroy(*dtag); 1147 (*vaddr) = NULL; 1148 return (ENXIO); 1149 } 1150 1151 return (0); 1152 } 1153 1154 static void 1155 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1156 { 1157 1158 if (vaddr == NULL) 1159 return; 1160 1161 /* Unmap descriptors from DMA memory */ 1162 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1163 BUS_DMASYNC_POSTWRITE); 1164 bus_dmamap_unload(dtag, dmap); 1165 1166 /* Free descriptors memory */ 1167 bus_dmamem_free(dtag, vaddr, dmap); 1168 1169 /* Destroy descriptors tag */ 1170 bus_dma_tag_destroy(dtag); 1171 } 1172 1173 static void 1174 tsec_free_dma(struct tsec_softc *sc) 1175 { 1176 int i; 1177 1178 /* Free TX maps */ 1179 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1180 if (sc->tx_bufmap[i].map_initialized) 1181 bus_dmamap_destroy(sc->tsec_tx_mtag, 1182 sc->tx_bufmap[i].map); 1183 /* Destroy tag for TX mbufs */ 1184 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1185 1186 /* Free RX mbufs and maps */ 1187 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1188 if (sc->rx_data[i].mbuf) { 1189 /* Unload buffer from DMA */ 1190 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1191 BUS_DMASYNC_POSTREAD); 1192 bus_dmamap_unload(sc->tsec_rx_mtag, 1193 sc->rx_data[i].map); 1194 1195 /* Free buffer */ 1196 m_freem(sc->rx_data[i].mbuf); 1197 } 1198 /* Destroy map for this buffer */ 1199 if (sc->rx_data[i].map != NULL) 1200 bus_dmamap_destroy(sc->tsec_rx_mtag, 1201 sc->rx_data[i].map); 1202 } 1203 /* Destroy tag for RX mbufs */ 1204 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1205 1206 /* Unload TX/RX descriptors */ 1207 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1208 sc->tsec_tx_vaddr); 1209 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1210 sc->tsec_rx_vaddr); 1211 } 1212 1213 static void 1214 tsec_stop(struct tsec_softc *sc) 1215 { 1216 struct ifnet *ifp; 1217 uint32_t tmpval; 1218 1219 TSEC_GLOBAL_LOCK_ASSERT(sc); 1220 1221 ifp = sc->tsec_ifp; 1222 1223 /* Disable interface and watchdog timer */ 1224 callout_stop(&sc->tsec_callout); 1225 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1226 sc->tsec_watchdog = 0; 1227 1228 /* Disable all interrupts and stop DMA */ 1229 tsec_intrs_ctl(sc, 0); 1230 tsec_dma_ctl(sc, 0); 1231 1232 /* Remove pending data from TX queue */ 1233 while (sc->tx_idx_tail != sc->tx_idx_head) { 1234 bus_dmamap_sync(sc->tsec_tx_mtag, 1235 sc->tx_bufmap[sc->tx_idx_tail].map, 1236 BUS_DMASYNC_POSTWRITE); 1237 bus_dmamap_unload(sc->tsec_tx_mtag, 1238 sc->tx_bufmap[sc->tx_idx_tail].map); 1239 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf); 1240 sc->tx_idx_tail = (sc->tx_idx_tail + 1) 1241 & (TSEC_TX_NUM_DESC - 1); 1242 } 1243 1244 /* Disable RX and TX */ 1245 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1246 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1247 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1248 DELAY(10); 1249 } 1250 1251 static void 1252 tsec_tick(void *arg) 1253 { 1254 struct tsec_softc *sc = arg; 1255 struct ifnet *ifp; 1256 int link; 1257 1258 TSEC_GLOBAL_LOCK(sc); 1259 1260 tsec_watchdog(sc); 1261 1262 ifp = sc->tsec_ifp; 1263 link = sc->tsec_link; 1264 1265 mii_tick(sc->tsec_mii); 1266 1267 if (link == 0 && sc->tsec_link == 1 && 1268 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1269 tsec_start_locked(ifp); 1270 1271 /* Schedule another timeout one second from now. */ 1272 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1273 1274 TSEC_GLOBAL_UNLOCK(sc); 1275 } 1276 1277 /* 1278 * This is the core RX routine. It replenishes mbufs in the descriptor and 1279 * sends data which have been dma'ed into host memory to upper layer. 1280 * 1281 * Loops at most count times if count is > 0, or until done if count < 0. 1282 */ 1283 static int 1284 tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1285 { 1286 struct tsec_desc *rx_desc; 1287 struct ifnet *ifp; 1288 struct rx_data_type *rx_data; 1289 struct mbuf *m; 1290 uint32_t i; 1291 int c, rx_npkts; 1292 uint16_t flags; 1293 1294 TSEC_RECEIVE_LOCK_ASSERT(sc); 1295 1296 ifp = sc->tsec_ifp; 1297 rx_data = sc->rx_data; 1298 rx_npkts = 0; 1299 1300 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1302 1303 for (c = 0; ; c++) { 1304 if (count >= 0 && count-- == 0) 1305 break; 1306 1307 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1308 flags = rx_desc->flags; 1309 1310 /* Check if there is anything to receive */ 1311 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1312 /* 1313 * Avoid generating another interrupt 1314 */ 1315 if (flags & TSEC_RXBD_E) 1316 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1317 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1318 /* 1319 * We didn't consume current descriptor and have to 1320 * return it to the queue 1321 */ 1322 TSEC_BACK_CUR_RX_DESC(sc); 1323 break; 1324 } 1325 1326 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1327 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1328 rx_desc->length = 0; 1329 rx_desc->flags = (rx_desc->flags & 1330 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1331 1332 if (sc->frame != NULL) { 1333 m_free(sc->frame); 1334 sc->frame = NULL; 1335 } 1336 1337 continue; 1338 } 1339 1340 /* Ok... process frame */ 1341 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1342 m = rx_data[i].mbuf; 1343 m->m_len = rx_desc->length; 1344 1345 if (sc->frame != NULL) { 1346 if ((flags & TSEC_RXBD_L) != 0) 1347 m->m_len -= m_length(sc->frame, NULL); 1348 1349 m->m_flags &= ~M_PKTHDR; 1350 m_cat(sc->frame, m); 1351 } else { 1352 sc->frame = m; 1353 } 1354 1355 m = NULL; 1356 1357 if ((flags & TSEC_RXBD_L) != 0) { 1358 m = sc->frame; 1359 sc->frame = NULL; 1360 } 1361 1362 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1363 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1364 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1365 /* 1366 * We ran out of mbufs; didn't consume current 1367 * descriptor and have to return it to the queue. 1368 */ 1369 TSEC_BACK_CUR_RX_DESC(sc); 1370 break; 1371 } 1372 1373 /* Attach new buffer to descriptor and clear flags */ 1374 rx_desc->bufptr = rx_data[i].paddr; 1375 rx_desc->length = 0; 1376 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1377 TSEC_RXBD_E | TSEC_RXBD_I; 1378 1379 if (m != NULL) { 1380 m->m_pkthdr.rcvif = ifp; 1381 1382 m_fixhdr(m); 1383 m_adj(m, -ETHER_CRC_LEN); 1384 1385 if (sc->is_etsec) 1386 tsec_offload_process_frame(sc, m); 1387 1388 TSEC_RECEIVE_UNLOCK(sc); 1389 (*ifp->if_input)(ifp, m); 1390 TSEC_RECEIVE_LOCK(sc); 1391 rx_npkts++; 1392 } 1393 } 1394 1395 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1397 1398 /* 1399 * Make sure TSEC receiver is not halted. 1400 * 1401 * Various conditions can stop the TSEC receiver, but not all are 1402 * signaled and handled by error interrupt, so make sure the receiver 1403 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1404 * halted, and is harmless if already running. 1405 */ 1406 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1407 return (rx_npkts); 1408 } 1409 1410 void 1411 tsec_receive_intr(void *arg) 1412 { 1413 struct tsec_softc *sc = arg; 1414 1415 TSEC_RECEIVE_LOCK(sc); 1416 1417 #ifdef DEVICE_POLLING 1418 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1419 TSEC_RECEIVE_UNLOCK(sc); 1420 return; 1421 } 1422 #endif 1423 1424 /* Confirm the interrupt was received by driver */ 1425 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1426 tsec_receive_intr_locked(sc, -1); 1427 1428 TSEC_RECEIVE_UNLOCK(sc); 1429 } 1430 1431 static void 1432 tsec_transmit_intr_locked(struct tsec_softc *sc) 1433 { 1434 struct ifnet *ifp; 1435 uint32_t tx_idx; 1436 1437 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1438 1439 ifp = sc->tsec_ifp; 1440 1441 /* Update collision statistics */ 1442 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL)); 1443 1444 /* Reset collision counters in hardware */ 1445 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1446 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1447 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1448 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1449 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1450 1451 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1452 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1453 1454 tx_idx = sc->tx_idx_tail; 1455 while (tx_idx != sc->tx_idx_head) { 1456 struct tsec_desc *tx_desc; 1457 struct tsec_bufmap *tx_bufmap; 1458 1459 tx_desc = &sc->tsec_tx_vaddr[tx_idx]; 1460 if (tx_desc->flags & TSEC_TXBD_R) { 1461 break; 1462 } 1463 1464 tx_bufmap = &sc->tx_bufmap[tx_idx]; 1465 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1); 1466 if (tx_bufmap->mbuf == NULL) 1467 continue; 1468 1469 /* 1470 * This is the last buf in this packet, so unmap and free it. 1471 */ 1472 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map, 1473 BUS_DMASYNC_POSTWRITE); 1474 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map); 1475 m_freem(tx_bufmap->mbuf); 1476 tx_bufmap->mbuf = NULL; 1477 1478 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1479 } 1480 sc->tx_idx_tail = tx_idx; 1481 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1482 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1483 1484 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1485 tsec_start_locked(ifp); 1486 1487 if (sc->tx_idx_tail == sc->tx_idx_head) 1488 sc->tsec_watchdog = 0; 1489 } 1490 1491 void 1492 tsec_transmit_intr(void *arg) 1493 { 1494 struct tsec_softc *sc = arg; 1495 1496 TSEC_TRANSMIT_LOCK(sc); 1497 1498 #ifdef DEVICE_POLLING 1499 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1500 TSEC_TRANSMIT_UNLOCK(sc); 1501 return; 1502 } 1503 #endif 1504 /* Confirm the interrupt was received by driver */ 1505 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1506 tsec_transmit_intr_locked(sc); 1507 1508 TSEC_TRANSMIT_UNLOCK(sc); 1509 } 1510 1511 static void 1512 tsec_error_intr_locked(struct tsec_softc *sc, int count) 1513 { 1514 struct ifnet *ifp; 1515 uint32_t eflags; 1516 1517 TSEC_GLOBAL_LOCK_ASSERT(sc); 1518 1519 ifp = sc->tsec_ifp; 1520 1521 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1522 1523 /* Clear events bits in hardware */ 1524 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1525 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1526 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1527 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1528 1529 /* Check transmitter errors */ 1530 if (eflags & TSEC_IEVENT_TXE) { 1531 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1532 1533 if (eflags & TSEC_IEVENT_LC) 1534 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1535 1536 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1537 } 1538 1539 /* Check for discarded frame due to a lack of buffers */ 1540 if (eflags & TSEC_IEVENT_BSY) { 1541 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1542 } 1543 1544 if (ifp->if_flags & IFF_DEBUG) 1545 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1546 eflags); 1547 1548 if (eflags & TSEC_IEVENT_EBERR) { 1549 if_printf(ifp, "System bus error occurred during" 1550 "DMA transaction (flags: 0x%x)\n", eflags); 1551 tsec_init_locked(sc); 1552 } 1553 1554 if (eflags & TSEC_IEVENT_BABT) 1555 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1556 1557 if (eflags & TSEC_IEVENT_BABR) 1558 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1559 } 1560 1561 void 1562 tsec_error_intr(void *arg) 1563 { 1564 struct tsec_softc *sc = arg; 1565 1566 TSEC_GLOBAL_LOCK(sc); 1567 tsec_error_intr_locked(sc, -1); 1568 TSEC_GLOBAL_UNLOCK(sc); 1569 } 1570 1571 int 1572 tsec_miibus_readreg(device_t dev, int phy, int reg) 1573 { 1574 struct tsec_softc *sc; 1575 int timeout; 1576 int rv; 1577 1578 sc = device_get_softc(dev); 1579 1580 TSEC_PHY_LOCK(); 1581 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1582 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1583 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1584 1585 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY); 1586 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT); 1587 TSEC_PHY_UNLOCK(); 1588 1589 if (timeout) 1590 device_printf(dev, "Timeout while reading from PHY!\n"); 1591 1592 return (rv); 1593 } 1594 1595 int 1596 tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1597 { 1598 struct tsec_softc *sc; 1599 int timeout; 1600 1601 sc = device_get_softc(dev); 1602 1603 TSEC_PHY_LOCK(); 1604 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1605 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value); 1606 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY); 1607 TSEC_PHY_UNLOCK(); 1608 1609 if (timeout) 1610 device_printf(dev, "Timeout while writing to PHY!\n"); 1611 1612 return (0); 1613 } 1614 1615 void 1616 tsec_miibus_statchg(device_t dev) 1617 { 1618 struct tsec_softc *sc; 1619 struct mii_data *mii; 1620 uint32_t ecntrl, id, tmp; 1621 int link; 1622 1623 sc = device_get_softc(dev); 1624 mii = sc->tsec_mii; 1625 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1626 1627 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1628 1629 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1630 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1631 else 1632 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1633 1634 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1635 case IFM_1000_T: 1636 case IFM_1000_SX: 1637 tmp |= TSEC_MACCFG2_GMII; 1638 sc->tsec_link = link; 1639 break; 1640 case IFM_100_TX: 1641 case IFM_10_T: 1642 tmp |= TSEC_MACCFG2_MII; 1643 sc->tsec_link = link; 1644 break; 1645 case IFM_NONE: 1646 if (link) 1647 device_printf(dev, "No speed selected but link " 1648 "active!\n"); 1649 sc->tsec_link = 0; 1650 return; 1651 default: 1652 sc->tsec_link = 0; 1653 device_printf(dev, "Unknown speed (%d), link %s!\n", 1654 IFM_SUBTYPE(mii->mii_media_active), 1655 ((link) ? "up" : "down")); 1656 return; 1657 } 1658 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1659 1660 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1661 id = TSEC_READ(sc, TSEC_REG_ID2); 1662 if (id & 0xffff) { 1663 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1664 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1665 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1666 } 1667 } 1668 1669 static void 1670 tsec_add_sysctls(struct tsec_softc *sc) 1671 { 1672 struct sysctl_ctx_list *ctx; 1673 struct sysctl_oid_list *children; 1674 struct sysctl_oid *tree; 1675 1676 ctx = device_get_sysctl_ctx(sc->dev); 1677 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1678 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1679 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing"); 1680 children = SYSCTL_CHILDREN(tree); 1681 1682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1683 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX, 1684 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)"); 1685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1686 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX, 1687 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)"); 1688 1689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1690 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX, 1691 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)"); 1692 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1693 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX, 1694 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)"); 1695 } 1696 1697 /* 1698 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1699 * interrupt is raised either upon: 1700 * 1701 * - threshold-defined period of time elapsed, or 1702 * - threshold-defined number of frames is received/transmitted, 1703 * whichever occurs first. 1704 * 1705 * The following sysctls regulate IC behaviour (for TX/RX separately): 1706 * 1707 * dev.tsec.<unit>.int_coal.rx_time 1708 * dev.tsec.<unit>.int_coal.rx_count 1709 * dev.tsec.<unit>.int_coal.tx_time 1710 * dev.tsec.<unit>.int_coal.tx_count 1711 * 1712 * Values: 1713 * 1714 * - 0 for either time or count disables IC on the given TX/RX path 1715 * 1716 * - count: 1-255 (expresses frame count number; note that value of 1 is 1717 * effectively IC off) 1718 * 1719 * - time: 1-65535 (value corresponds to a real time period and is 1720 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1721 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1722 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1723 * TSEC reference manual. 1724 */ 1725 static int 1726 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1727 { 1728 int error; 1729 uint32_t time; 1730 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1731 1732 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1733 1734 error = sysctl_handle_int(oidp, &time, 0, req); 1735 if (error != 0) 1736 return (error); 1737 1738 if (time > 65535) 1739 return (EINVAL); 1740 1741 TSEC_IC_LOCK(sc); 1742 if (arg2 == TSEC_IC_RX) { 1743 sc->rx_ic_time = time; 1744 tsec_set_rxic(sc); 1745 } else { 1746 sc->tx_ic_time = time; 1747 tsec_set_txic(sc); 1748 } 1749 TSEC_IC_UNLOCK(sc); 1750 1751 return (0); 1752 } 1753 1754 static int 1755 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1756 { 1757 int error; 1758 uint32_t count; 1759 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1760 1761 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1762 1763 error = sysctl_handle_int(oidp, &count, 0, req); 1764 if (error != 0) 1765 return (error); 1766 1767 if (count > 255) 1768 return (EINVAL); 1769 1770 TSEC_IC_LOCK(sc); 1771 if (arg2 == TSEC_IC_RX) { 1772 sc->rx_ic_count = count; 1773 tsec_set_rxic(sc); 1774 } else { 1775 sc->tx_ic_count = count; 1776 tsec_set_txic(sc); 1777 } 1778 TSEC_IC_UNLOCK(sc); 1779 1780 return (0); 1781 } 1782 1783 static void 1784 tsec_set_rxic(struct tsec_softc *sc) 1785 { 1786 uint32_t rxic_val; 1787 1788 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1789 /* Disable RX IC */ 1790 rxic_val = 0; 1791 else { 1792 rxic_val = 0x80000000; 1793 rxic_val |= (sc->rx_ic_count << 21); 1794 rxic_val |= sc->rx_ic_time; 1795 } 1796 1797 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1798 } 1799 1800 static void 1801 tsec_set_txic(struct tsec_softc *sc) 1802 { 1803 uint32_t txic_val; 1804 1805 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1806 /* Disable TX IC */ 1807 txic_val = 0; 1808 else { 1809 txic_val = 0x80000000; 1810 txic_val |= (sc->tx_ic_count << 21); 1811 txic_val |= sc->tx_ic_time; 1812 } 1813 1814 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1815 } 1816 1817 static void 1818 tsec_offload_setup(struct tsec_softc *sc) 1819 { 1820 struct ifnet *ifp = sc->tsec_ifp; 1821 uint32_t reg; 1822 1823 TSEC_GLOBAL_LOCK_ASSERT(sc); 1824 1825 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1826 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1827 1828 if (ifp->if_capenable & IFCAP_TXCSUM) 1829 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1830 else 1831 ifp->if_hwassist = 0; 1832 1833 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1834 1835 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1836 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1837 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1838 1839 if (ifp->if_capenable & IFCAP_RXCSUM) 1840 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1841 TSEC_RCTRL_PRSDEP_PARSE_L234; 1842 1843 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1844 } 1845 1846 static void 1847 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1848 { 1849 struct tsec_rx_fcb rx_fcb; 1850 int csum_flags = 0; 1851 int protocol, flags; 1852 1853 TSEC_RECEIVE_LOCK_ASSERT(sc); 1854 1855 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1856 flags = rx_fcb.flags; 1857 protocol = rx_fcb.protocol; 1858 1859 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1860 csum_flags |= CSUM_IP_CHECKED; 1861 1862 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1863 csum_flags |= CSUM_IP_VALID; 1864 } 1865 1866 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1867 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1868 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1869 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1870 m->m_pkthdr.csum_data = 0xFFFF; 1871 } 1872 1873 m->m_pkthdr.csum_flags = csum_flags; 1874 1875 if (flags & TSEC_RX_FCB_VLAN) { 1876 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1877 m->m_flags |= M_VLANTAG; 1878 } 1879 1880 m_adj(m, sizeof(struct tsec_rx_fcb)); 1881 } 1882 1883 static u_int 1884 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1885 { 1886 uint32_t h, *hashtable = arg; 1887 1888 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF; 1889 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1890 1891 return (1); 1892 } 1893 1894 static void 1895 tsec_setup_multicast(struct tsec_softc *sc) 1896 { 1897 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1898 struct ifnet *ifp = sc->tsec_ifp; 1899 int i; 1900 1901 TSEC_GLOBAL_LOCK_ASSERT(sc); 1902 1903 if (ifp->if_flags & IFF_ALLMULTI) { 1904 for (i = 0; i < 8; i++) 1905 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1906 1907 return; 1908 } 1909 1910 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable); 1911 1912 for (i = 0; i < 8; i++) 1913 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1914 } 1915 1916 static int 1917 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1918 { 1919 1920 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1921 1922 TSEC_GLOBAL_LOCK_ASSERT(sc); 1923 1924 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1925 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1926 return (mtu); 1927 } 1928 1929 return (0); 1930 }
Cache object: c0a1a33c2da22586d8098369b1114a85
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