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FreeBSD/Linux Kernel Cross Reference
sys/dev/tsec/if_tsec.c
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1 /*- 2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: releng/8.4/sys/dev/tsec/if_tsec.c 214909 2010-11-07 11:12:29Z marius $"); 32 33 #ifdef HAVE_KERNEL_OPTION_HEADERS 34 #include "opt_device_polling.h" 35 #endif 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/tsec/if_tsec.h> 67 #include <dev/tsec/if_tsecreg.h> 68 69 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71 const char *dname); 72 static void tsec_dma_ctl(struct tsec_softc *sc, int state); 73 static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74 int fcb_inserted); 75 static void tsec_free_dma(struct tsec_softc *sc); 76 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77 static int tsec_ifmedia_upd(struct ifnet *ifp); 78 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80 struct mbuf **mbufp, uint32_t *paddr); 81 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82 int nseg, int error); 83 static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84 static void tsec_init(void *xsc); 85 static void tsec_init_locked(struct tsec_softc *sc); 86 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87 static void tsec_reset_mac(struct tsec_softc *sc); 88 static void tsec_setfilter(struct tsec_softc *sc); 89 static void tsec_set_mac_address(struct tsec_softc *sc); 90 static void tsec_start(struct ifnet *ifp); 91 static void tsec_start_locked(struct ifnet *ifp); 92 static void tsec_stop(struct tsec_softc *sc); 93 static void tsec_tick(void *arg); 94 static void tsec_watchdog(struct tsec_softc *sc); 95 static void tsec_add_sysctls(struct tsec_softc *sc); 96 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98 static void tsec_set_rxic(struct tsec_softc *sc); 99 static void tsec_set_txic(struct tsec_softc *sc); 100 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101 static void tsec_transmit_intr_locked(struct tsec_softc *sc); 102 static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103 static void tsec_offload_setup(struct tsec_softc *sc); 104 static void tsec_offload_process_frame(struct tsec_softc *sc, 105 struct mbuf *m); 106 static void tsec_setup_multicast(struct tsec_softc *sc); 107 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108 109 struct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */ 110 111 devclass_t tsec_devclass; 112 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 113 MODULE_DEPEND(tsec, ether, 1, 1, 1); 114 MODULE_DEPEND(tsec, miibus, 1, 1, 1); 115 116 int 117 tsec_attach(struct tsec_softc *sc) 118 { 119 uint8_t hwaddr[ETHER_ADDR_LEN]; 120 struct ifnet *ifp; 121 bus_dmamap_t *map_ptr; 122 bus_dmamap_t **map_pptr; 123 int error = 0; 124 int i; 125 126 /* Reset all TSEC counters */ 127 TSEC_TX_RX_COUNTERS_INIT(sc); 128 129 /* Stop DMA engine if enabled by firmware */ 130 tsec_dma_ctl(sc, 0); 131 132 /* Reset MAC */ 133 tsec_reset_mac(sc); 134 135 /* Disable interrupts for now */ 136 tsec_intrs_ctl(sc, 0); 137 138 /* Configure defaults for interrupts coalescing */ 139 sc->rx_ic_time = 768; 140 sc->rx_ic_count = 16; 141 sc->tx_ic_time = 768; 142 sc->tx_ic_count = 16; 143 tsec_set_rxic(sc); 144 tsec_set_txic(sc); 145 tsec_add_sysctls(sc); 146 147 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 148 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 149 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 150 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 151 152 if (error) { 153 tsec_detach(sc); 154 return (ENXIO); 155 } 156 157 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 158 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 159 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 160 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 161 if (error) { 162 tsec_detach(sc); 163 return (ENXIO); 164 } 165 166 /* Allocate a busdma tag for TX mbufs. */ 167 error = bus_dma_tag_create(NULL, /* parent */ 168 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 169 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 170 BUS_SPACE_MAXADDR, /* highaddr */ 171 NULL, NULL, /* filtfunc, filtfuncarg */ 172 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 173 TSEC_TX_NUM_DESC - 1, /* nsegments */ 174 MCLBYTES, 0, /* maxsegsz, flags */ 175 NULL, NULL, /* lockfunc, lockfuncarg */ 176 &sc->tsec_tx_mtag); /* dmat */ 177 if (error) { 178 device_printf(sc->dev, "failed to allocate busdma tag " 179 "(tx mbufs)\n"); 180 tsec_detach(sc); 181 return (ENXIO); 182 } 183 184 /* Allocate a busdma tag for RX mbufs. */ 185 error = bus_dma_tag_create(NULL, /* parent */ 186 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 187 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 188 BUS_SPACE_MAXADDR, /* highaddr */ 189 NULL, NULL, /* filtfunc, filtfuncarg */ 190 MCLBYTES, /* maxsize */ 191 1, /* nsegments */ 192 MCLBYTES, 0, /* maxsegsz, flags */ 193 NULL, NULL, /* lockfunc, lockfuncarg */ 194 &sc->tsec_rx_mtag); /* dmat */ 195 if (error) { 196 device_printf(sc->dev, "failed to allocate busdma tag " 197 "(rx mbufs)\n"); 198 tsec_detach(sc); 199 return (ENXIO); 200 } 201 202 /* Create TX busdma maps */ 203 map_ptr = sc->tx_map_data; 204 map_pptr = sc->tx_map_unused_data; 205 206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 207 map_pptr[i] = &map_ptr[i]; 208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 209 if (error) { 210 device_printf(sc->dev, "failed to init TX ring\n"); 211 tsec_detach(sc); 212 return (ENXIO); 213 } 214 } 215 216 /* Create RX busdma maps and zero mbuf handlers */ 217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 219 &sc->rx_data[i].map); 220 if (error) { 221 device_printf(sc->dev, "failed to init RX ring\n"); 222 tsec_detach(sc); 223 return (ENXIO); 224 } 225 sc->rx_data[i].mbuf = NULL; 226 } 227 228 /* Create mbufs for RX buffers */ 229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 232 if (error) { 233 device_printf(sc->dev, "can't load rx DMA map %d, " 234 "error = %d\n", i, error); 235 tsec_detach(sc); 236 return (error); 237 } 238 } 239 240 /* Create network interface for upper layers */ 241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 242 if (ifp == NULL) { 243 device_printf(sc->dev, "if_alloc() failed\n"); 244 tsec_detach(sc); 245 return (ENOMEM); 246 } 247 248 ifp->if_softc = sc; 249 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 250 ifp->if_mtu = ETHERMTU; 251 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 252 ifp->if_init = tsec_init; 253 ifp->if_start = tsec_start; 254 ifp->if_ioctl = tsec_ioctl; 255 256 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 257 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 258 IFQ_SET_READY(&ifp->if_snd); 259 260 ifp->if_capabilities = IFCAP_VLAN_MTU; 261 if (sc->is_etsec) 262 ifp->if_capabilities |= IFCAP_HWCSUM; 263 264 ifp->if_capenable = ifp->if_capabilities; 265 266 #ifdef DEVICE_POLLING 267 /* Advertise that polling is supported */ 268 ifp->if_capabilities |= IFCAP_POLLING; 269 #endif 270 271 /* Attach PHY(s) */ 272 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 273 tsec_ifmedia_sts, BMSR_DEFCAPMASK, device_get_unit(sc->dev), 274 MII_OFFSET_ANY, 0); 275 if (error) { 276 device_printf(sc->dev, "attaching PHYs failed\n"); 277 if_free(ifp); 278 sc->tsec_ifp = NULL; 279 tsec_detach(sc); 280 return (error); 281 } 282 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 283 284 /* Set MAC address */ 285 tsec_get_hwaddr(sc, hwaddr); 286 ether_ifattach(ifp, hwaddr); 287 288 return (0); 289 } 290 291 int 292 tsec_detach(struct tsec_softc *sc) 293 { 294 295 #ifdef DEVICE_POLLING 296 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 297 ether_poll_deregister(sc->tsec_ifp); 298 #endif 299 300 /* Stop TSEC controller and free TX queue */ 301 if (sc->sc_rres && sc->tsec_ifp) 302 tsec_shutdown(sc->dev); 303 304 /* Detach network interface */ 305 if (sc->tsec_ifp) { 306 ether_ifdetach(sc->tsec_ifp); 307 if_free(sc->tsec_ifp); 308 sc->tsec_ifp = NULL; 309 } 310 311 /* Free DMA resources */ 312 tsec_free_dma(sc); 313 314 return (0); 315 } 316 317 int 318 tsec_shutdown(device_t dev) 319 { 320 struct tsec_softc *sc; 321 322 sc = device_get_softc(dev); 323 324 TSEC_GLOBAL_LOCK(sc); 325 tsec_stop(sc); 326 TSEC_GLOBAL_UNLOCK(sc); 327 return (0); 328 } 329 330 int 331 tsec_suspend(device_t dev) 332 { 333 334 /* TODO not implemented! */ 335 return (0); 336 } 337 338 int 339 tsec_resume(device_t dev) 340 { 341 342 /* TODO not implemented! */ 343 return (0); 344 } 345 346 static void 347 tsec_init(void *xsc) 348 { 349 struct tsec_softc *sc = xsc; 350 351 TSEC_GLOBAL_LOCK(sc); 352 tsec_init_locked(sc); 353 TSEC_GLOBAL_UNLOCK(sc); 354 } 355 356 static void 357 tsec_init_locked(struct tsec_softc *sc) 358 { 359 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 360 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 361 struct ifnet *ifp = sc->tsec_ifp; 362 uint32_t timeout, val, i; 363 364 TSEC_GLOBAL_LOCK_ASSERT(sc); 365 tsec_stop(sc); 366 367 /* 368 * These steps are according to the MPC8555E PowerQUICCIII RM: 369 * 14.7 Initialization/Application Information 370 */ 371 372 /* Step 1: soft reset MAC */ 373 tsec_reset_mac(sc); 374 375 /* Step 2: Initialize MACCFG2 */ 376 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 377 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 378 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 379 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 380 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 381 ); 382 383 /* Step 3: Initialize ECNTRL 384 * While the documentation states that R100M is ignored if RPM is 385 * not set, it does seem to be needed to get the orange boxes to 386 * work (which have a Marvell 88E1111 PHY). Go figure. 387 */ 388 389 /* 390 * XXX kludge - use circumstancial evidence to program ECNTRL 391 * correctly. Ideally we need some board information to guide 392 * us here. 393 */ 394 i = TSEC_READ(sc, TSEC_REG_ID2); 395 val = (i & 0xffff) 396 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 397 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 398 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 399 400 /* Step 4: Initialize MAC station address */ 401 tsec_set_mac_address(sc); 402 403 /* 404 * Step 5: Assign a Physical address to the TBI so as to not conflict 405 * with the external PHY physical address 406 */ 407 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 408 409 /* Step 6: Reset the management interface */ 410 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 411 412 /* Step 7: Setup the MII Mgmt clock speed */ 413 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 414 415 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 416 timeout = TSEC_READ_RETRY; 417 while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) & 418 TSEC_MIIMIND_BUSY)) 419 DELAY(TSEC_READ_DELAY); 420 if (timeout == 0) { 421 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 422 return; 423 } 424 425 /* Step 9: Setup the MII Mgmt */ 426 mii_mediachg(sc->tsec_mii); 427 428 /* Step 10: Clear IEVENT register */ 429 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 430 431 /* Step 11: Enable interrupts */ 432 #ifdef DEVICE_POLLING 433 /* 434 * ...only if polling is not turned on. Disable interrupts explicitly 435 * if polling is enabled. 436 */ 437 if (ifp->if_capenable & IFCAP_POLLING ) 438 tsec_intrs_ctl(sc, 0); 439 else 440 #endif /* DEVICE_POLLING */ 441 tsec_intrs_ctl(sc, 1); 442 443 /* Step 12: Initialize IADDRn */ 444 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 445 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 446 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 447 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 448 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 449 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 450 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 451 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 452 453 /* Step 13: Initialize GADDRn */ 454 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 455 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 456 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 457 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 458 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 459 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 460 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 461 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 462 463 /* Step 14: Initialize RCTRL */ 464 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 465 466 /* Step 15: Initialize DMACTRL */ 467 tsec_dma_ctl(sc, 1); 468 469 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 470 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 471 472 /* 473 * Step 17: Initialize transmit/receive descriptor rings. 474 * Initialize TBASE and RBASE. 475 */ 476 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 477 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 478 479 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 480 tx_desc[i].bufptr = 0; 481 tx_desc[i].length = 0; 482 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 483 TSEC_TXBD_W : 0); 484 } 485 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 486 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 487 488 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 489 rx_desc[i].bufptr = sc->rx_data[i].paddr; 490 rx_desc[i].length = 0; 491 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 492 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 493 } 494 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 496 497 /* Step 18: Initialize the maximum receive buffer length */ 498 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 499 500 /* Step 19: Configure ethernet frame sizes */ 501 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 502 tsec_set_mtu(sc, ifp->if_mtu); 503 504 /* Step 20: Enable Rx and RxBD sdata snooping */ 505 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 506 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 507 508 /* Step 21: Reset collision counters in hardware */ 509 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 510 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 511 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 512 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 513 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 514 515 /* Step 22: Mask all CAM interrupts */ 516 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 517 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 518 519 /* Step 23: Enable Rx and Tx */ 520 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 521 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 522 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 523 524 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 525 TSEC_TX_RX_COUNTERS_INIT(sc); 526 527 /* Step 25: Setup TCP/IP Off-Load engine */ 528 if (sc->is_etsec) 529 tsec_offload_setup(sc); 530 531 /* Step 26: Setup multicast filters */ 532 tsec_setup_multicast(sc); 533 534 /* Step 27: Activate network interface */ 535 ifp->if_drv_flags |= IFF_DRV_RUNNING; 536 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 537 sc->tsec_if_flags = ifp->if_flags; 538 sc->tsec_watchdog = 0; 539 540 /* Schedule watchdog timeout */ 541 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 542 } 543 544 static void 545 tsec_set_mac_address(struct tsec_softc *sc) 546 { 547 uint32_t macbuf[2] = { 0, 0 }; 548 char *macbufp, *curmac; 549 int i; 550 551 TSEC_GLOBAL_LOCK_ASSERT(sc); 552 553 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 554 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 555 sizeof(macbuf))); 556 557 macbufp = (char *)macbuf; 558 curmac = (char *)IF_LLADDR(sc->tsec_ifp); 559 560 /* Correct order of MAC address bytes */ 561 for (i = 1; i <= ETHER_ADDR_LEN; i++) 562 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 563 564 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 565 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 566 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 567 } 568 569 /* 570 * DMA control function, if argument state is: 571 * 0 - DMA engine will be disabled 572 * 1 - DMA engine will be enabled 573 */ 574 static void 575 tsec_dma_ctl(struct tsec_softc *sc, int state) 576 { 577 device_t dev; 578 uint32_t dma_flags, timeout; 579 580 dev = sc->dev; 581 582 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 583 584 switch (state) { 585 case 0: 586 /* Temporarily clear stop graceful stop bits. */ 587 tsec_dma_ctl(sc, 1000); 588 589 /* Set it again */ 590 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 591 break; 592 case 1000: 593 case 1: 594 /* Set write with response (WWR), wait (WOP) and snoop bits */ 595 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 596 DMACTRL_WWR | DMACTRL_WOP); 597 598 /* Clear graceful stop bits */ 599 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 600 break; 601 default: 602 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 603 state); 604 } 605 606 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 607 608 switch (state) { 609 case 0: 610 /* Wait for DMA stop */ 611 timeout = TSEC_READ_RETRY; 612 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 613 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 614 DELAY(TSEC_READ_DELAY); 615 616 if (timeout == 0) 617 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 618 break; 619 case 1: 620 /* Restart transmission function */ 621 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 622 } 623 } 624 625 /* 626 * Interrupts control function, if argument state is: 627 * 0 - all TSEC interrupts will be masked 628 * 1 - all TSEC interrupts will be unmasked 629 */ 630 static void 631 tsec_intrs_ctl(struct tsec_softc *sc, int state) 632 { 633 device_t dev; 634 635 dev = sc->dev; 636 637 switch (state) { 638 case 0: 639 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 640 break; 641 case 1: 642 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 643 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 644 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 645 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 646 break; 647 default: 648 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 649 state); 650 } 651 } 652 653 static void 654 tsec_reset_mac(struct tsec_softc *sc) 655 { 656 uint32_t maccfg1_flags; 657 658 /* Set soft reset bit */ 659 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 660 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 661 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 662 663 /* Clear soft reset bit */ 664 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 665 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 666 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 667 } 668 669 static void 670 tsec_watchdog(struct tsec_softc *sc) 671 { 672 struct ifnet *ifp; 673 674 TSEC_GLOBAL_LOCK_ASSERT(sc); 675 676 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 677 return; 678 679 ifp = sc->tsec_ifp; 680 ifp->if_oerrors++; 681 if_printf(ifp, "watchdog timeout\n"); 682 683 tsec_stop(sc); 684 tsec_init_locked(sc); 685 } 686 687 static void 688 tsec_start(struct ifnet *ifp) 689 { 690 struct tsec_softc *sc = ifp->if_softc; 691 692 TSEC_TRANSMIT_LOCK(sc); 693 tsec_start_locked(ifp); 694 TSEC_TRANSMIT_UNLOCK(sc); 695 } 696 697 static void 698 tsec_start_locked(struct ifnet *ifp) 699 { 700 struct tsec_softc *sc; 701 struct mbuf *m0, *mtmp; 702 struct tsec_tx_fcb *tx_fcb; 703 unsigned int queued = 0; 704 int csum_flags, fcb_inserted = 0; 705 706 sc = ifp->if_softc; 707 708 TSEC_TRANSMIT_LOCK_ASSERT(sc); 709 710 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 711 IFF_DRV_RUNNING) 712 return; 713 714 if (sc->tsec_link == 0) 715 return; 716 717 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 718 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 719 720 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 721 /* Get packet from the queue */ 722 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 723 if (m0 == NULL) 724 break; 725 726 /* Insert TCP/IP Off-load frame control block */ 727 csum_flags = m0->m_pkthdr.csum_flags; 728 if (csum_flags) { 729 730 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT); 731 if (m0 == NULL) 732 break; 733 734 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 735 tx_fcb->flags = 0; 736 tx_fcb->l3_offset = ETHER_HDR_LEN; 737 tx_fcb->l4_offset = sizeof(struct ip); 738 739 if (csum_flags & CSUM_IP) 740 tx_fcb->flags |= TSEC_TX_FCB_IP4 | 741 TSEC_TX_FCB_CSUM_IP; 742 743 if (csum_flags & CSUM_TCP) 744 tx_fcb->flags |= TSEC_TX_FCB_TCP | 745 TSEC_TX_FCB_CSUM_TCP_UDP; 746 747 if (csum_flags & CSUM_UDP) 748 tx_fcb->flags |= TSEC_TX_FCB_UDP | 749 TSEC_TX_FCB_CSUM_TCP_UDP; 750 751 fcb_inserted = 1; 752 } 753 754 mtmp = m_defrag(m0, M_DONTWAIT); 755 if (mtmp) 756 m0 = mtmp; 757 758 if (tsec_encap(sc, m0, fcb_inserted)) { 759 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 760 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 761 break; 762 } 763 queued++; 764 BPF_MTAP(ifp, m0); 765 } 766 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 767 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 768 769 if (queued) { 770 /* Enable transmitter and watchdog timer */ 771 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 772 sc->tsec_watchdog = 5; 773 } 774 } 775 776 static int 777 tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 778 { 779 struct tsec_desc *tx_desc = NULL; 780 struct ifnet *ifp; 781 bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 782 bus_dmamap_t *mapp; 783 int csum_flag = 0, error, seg, nsegs; 784 785 TSEC_TRANSMIT_LOCK_ASSERT(sc); 786 787 ifp = sc->tsec_ifp; 788 789 if (TSEC_FREE_TX_DESC(sc) == 0) { 790 /* No free descriptors */ 791 return (-1); 792 } 793 794 /* Fetch unused map */ 795 mapp = TSEC_ALLOC_TX_MAP(sc); 796 797 /* Create mapping in DMA memory */ 798 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 799 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 800 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 801 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 802 TSEC_FREE_TX_MAP(sc, mapp); 803 return ((error != 0) ? error : -1); 804 } 805 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 806 807 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 808 if_printf(ifp, "TX buffer has %d segments\n", nsegs); 809 810 if (fcb_inserted) 811 csum_flag = TSEC_TXBD_TOE; 812 813 /* Everything is ok, now we can send buffers */ 814 for (seg = 0; seg < nsegs; seg++) { 815 tx_desc = TSEC_GET_CUR_TX_DESC(sc); 816 817 tx_desc->length = segs[seg].ds_len; 818 tx_desc->bufptr = segs[seg].ds_addr; 819 820 /* 821 * Set flags: 822 * - wrap 823 * - checksum 824 * - ready to send 825 * - transmit the CRC sequence after the last data byte 826 * - interrupt after the last buffer 827 */ 828 tx_desc->flags = 829 (tx_desc->flags & TSEC_TXBD_W) | 830 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 831 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 832 } 833 834 /* Save mbuf and DMA mapping for release at later stage */ 835 TSEC_PUT_TX_MBUF(sc, m0); 836 TSEC_PUT_TX_MAP(sc, mapp); 837 838 return (0); 839 } 840 841 static void 842 tsec_setfilter(struct tsec_softc *sc) 843 { 844 struct ifnet *ifp; 845 uint32_t flags; 846 847 ifp = sc->tsec_ifp; 848 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 849 850 /* Promiscuous mode */ 851 if (ifp->if_flags & IFF_PROMISC) 852 flags |= TSEC_RCTRL_PROM; 853 else 854 flags &= ~TSEC_RCTRL_PROM; 855 856 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 857 } 858 859 #ifdef DEVICE_POLLING 860 static poll_handler_t tsec_poll; 861 862 static int 863 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 864 { 865 uint32_t ie; 866 struct tsec_softc *sc = ifp->if_softc; 867 int rx_npkts; 868 869 rx_npkts = 0; 870 871 TSEC_GLOBAL_LOCK(sc); 872 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 873 TSEC_GLOBAL_UNLOCK(sc); 874 return (rx_npkts); 875 } 876 877 if (cmd == POLL_AND_CHECK_STATUS) { 878 tsec_error_intr_locked(sc, count); 879 880 /* Clear all events reported */ 881 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 882 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 883 } 884 885 tsec_transmit_intr_locked(sc); 886 887 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 888 889 rx_npkts = tsec_receive_intr_locked(sc, count); 890 891 TSEC_RECEIVE_UNLOCK(sc); 892 893 return (rx_npkts); 894 } 895 #endif /* DEVICE_POLLING */ 896 897 static int 898 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 899 { 900 struct tsec_softc *sc = ifp->if_softc; 901 struct ifreq *ifr = (struct ifreq *)data; 902 device_t dev; 903 int mask, error = 0; 904 905 dev = sc->dev; 906 907 switch (command) { 908 case SIOCSIFMTU: 909 TSEC_GLOBAL_LOCK(sc); 910 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 911 ifp->if_mtu = ifr->ifr_mtu; 912 else 913 error = EINVAL; 914 TSEC_GLOBAL_UNLOCK(sc); 915 break; 916 case SIOCSIFFLAGS: 917 TSEC_GLOBAL_LOCK(sc); 918 if (ifp->if_flags & IFF_UP) { 919 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 920 if ((sc->tsec_if_flags ^ ifp->if_flags) & 921 IFF_PROMISC) 922 tsec_setfilter(sc); 923 924 if ((sc->tsec_if_flags ^ ifp->if_flags) & 925 IFF_ALLMULTI) 926 tsec_setup_multicast(sc); 927 } else 928 tsec_init_locked(sc); 929 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 930 tsec_stop(sc); 931 932 sc->tsec_if_flags = ifp->if_flags; 933 TSEC_GLOBAL_UNLOCK(sc); 934 break; 935 case SIOCADDMULTI: 936 case SIOCDELMULTI: 937 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 938 TSEC_GLOBAL_LOCK(sc); 939 tsec_setup_multicast(sc); 940 TSEC_GLOBAL_UNLOCK(sc); 941 } 942 case SIOCGIFMEDIA: 943 case SIOCSIFMEDIA: 944 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 945 command); 946 break; 947 case SIOCSIFCAP: 948 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 949 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 950 TSEC_GLOBAL_LOCK(sc); 951 ifp->if_capenable &= ~IFCAP_HWCSUM; 952 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 953 tsec_offload_setup(sc); 954 TSEC_GLOBAL_UNLOCK(sc); 955 } 956 #ifdef DEVICE_POLLING 957 if (mask & IFCAP_POLLING) { 958 if (ifr->ifr_reqcap & IFCAP_POLLING) { 959 error = ether_poll_register(tsec_poll, ifp); 960 if (error) 961 return (error); 962 963 TSEC_GLOBAL_LOCK(sc); 964 /* Disable interrupts */ 965 tsec_intrs_ctl(sc, 0); 966 ifp->if_capenable |= IFCAP_POLLING; 967 TSEC_GLOBAL_UNLOCK(sc); 968 } else { 969 error = ether_poll_deregister(ifp); 970 TSEC_GLOBAL_LOCK(sc); 971 /* Enable interrupts */ 972 tsec_intrs_ctl(sc, 1); 973 ifp->if_capenable &= ~IFCAP_POLLING; 974 TSEC_GLOBAL_UNLOCK(sc); 975 } 976 } 977 #endif 978 break; 979 980 default: 981 error = ether_ioctl(ifp, command, data); 982 } 983 984 /* Flush buffers if not empty */ 985 if (ifp->if_flags & IFF_UP) 986 tsec_start(ifp); 987 return (error); 988 } 989 990 static int 991 tsec_ifmedia_upd(struct ifnet *ifp) 992 { 993 struct tsec_softc *sc = ifp->if_softc; 994 struct mii_data *mii; 995 996 TSEC_TRANSMIT_LOCK(sc); 997 998 mii = sc->tsec_mii; 999 mii_mediachg(mii); 1000 1001 TSEC_TRANSMIT_UNLOCK(sc); 1002 return (0); 1003 } 1004 1005 static void 1006 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1007 { 1008 struct tsec_softc *sc = ifp->if_softc; 1009 struct mii_data *mii; 1010 1011 TSEC_TRANSMIT_LOCK(sc); 1012 1013 mii = sc->tsec_mii; 1014 mii_pollstat(mii); 1015 1016 ifmr->ifm_active = mii->mii_media_active; 1017 ifmr->ifm_status = mii->mii_media_status; 1018 1019 TSEC_TRANSMIT_UNLOCK(sc); 1020 } 1021 1022 static int 1023 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1024 uint32_t *paddr) 1025 { 1026 struct mbuf *new_mbuf; 1027 bus_dma_segment_t seg[1]; 1028 int error, nsegs; 1029 1030 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1031 1032 new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1033 if (new_mbuf == NULL) 1034 return (ENOBUFS); 1035 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1036 1037 if (*mbufp) { 1038 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1039 bus_dmamap_unload(tag, map); 1040 } 1041 1042 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1043 BUS_DMA_NOWAIT); 1044 KASSERT(nsegs == 1, ("Too many segments returned!")); 1045 if (nsegs != 1 || error) 1046 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1047 1048 #if 0 1049 if (error) { 1050 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1051 error); 1052 m_freem(new_mbuf); 1053 return (ENOBUFS); 1054 } 1055 #endif 1056 1057 #if 0 1058 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1059 ("Wrong alignment of RX buffer!")); 1060 #endif 1061 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1062 1063 (*mbufp) = new_mbuf; 1064 (*paddr) = seg->ds_addr; 1065 return (0); 1066 } 1067 1068 static void 1069 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1070 { 1071 u_int32_t *paddr; 1072 1073 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1074 paddr = arg; 1075 *paddr = segs->ds_addr; 1076 } 1077 1078 static int 1079 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1080 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1081 { 1082 int error; 1083 1084 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1085 error = bus_dma_tag_create(NULL, /* parent */ 1086 PAGE_SIZE, 0, /* alignment, boundary */ 1087 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1088 BUS_SPACE_MAXADDR, /* highaddr */ 1089 NULL, NULL, /* filtfunc, filtfuncarg */ 1090 dsize, 1, /* maxsize, nsegments */ 1091 dsize, 0, /* maxsegsz, flags */ 1092 NULL, NULL, /* lockfunc, lockfuncarg */ 1093 dtag); /* dmat */ 1094 1095 if (error) { 1096 device_printf(dev, "failed to allocate busdma %s tag\n", 1097 dname); 1098 (*vaddr) = NULL; 1099 return (ENXIO); 1100 } 1101 1102 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1103 dmap); 1104 if (error) { 1105 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1106 dname); 1107 bus_dma_tag_destroy(*dtag); 1108 (*vaddr) = NULL; 1109 return (ENXIO); 1110 } 1111 1112 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1113 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1114 if (error) { 1115 device_printf(dev, "cannot get address of the %s " 1116 "descriptors\n", dname); 1117 bus_dmamem_free(*dtag, *vaddr, *dmap); 1118 bus_dma_tag_destroy(*dtag); 1119 (*vaddr) = NULL; 1120 return (ENXIO); 1121 } 1122 1123 return (0); 1124 } 1125 1126 static void 1127 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1128 { 1129 1130 if (vaddr == NULL) 1131 return; 1132 1133 /* Unmap descriptors from DMA memory */ 1134 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1135 BUS_DMASYNC_POSTWRITE); 1136 bus_dmamap_unload(dtag, dmap); 1137 1138 /* Free descriptors memory */ 1139 bus_dmamem_free(dtag, vaddr, dmap); 1140 1141 /* Destroy descriptors tag */ 1142 bus_dma_tag_destroy(dtag); 1143 } 1144 1145 static void 1146 tsec_free_dma(struct tsec_softc *sc) 1147 { 1148 int i; 1149 1150 /* Free TX maps */ 1151 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1152 if (sc->tx_map_data[i] != NULL) 1153 bus_dmamap_destroy(sc->tsec_tx_mtag, 1154 sc->tx_map_data[i]); 1155 /* Destroy tag for TX mbufs */ 1156 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1157 1158 /* Free RX mbufs and maps */ 1159 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1160 if (sc->rx_data[i].mbuf) { 1161 /* Unload buffer from DMA */ 1162 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1163 BUS_DMASYNC_POSTREAD); 1164 bus_dmamap_unload(sc->tsec_rx_mtag, 1165 sc->rx_data[i].map); 1166 1167 /* Free buffer */ 1168 m_freem(sc->rx_data[i].mbuf); 1169 } 1170 /* Destroy map for this buffer */ 1171 if (sc->rx_data[i].map != NULL) 1172 bus_dmamap_destroy(sc->tsec_rx_mtag, 1173 sc->rx_data[i].map); 1174 } 1175 /* Destroy tag for RX mbufs */ 1176 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1177 1178 /* Unload TX/RX descriptors */ 1179 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1180 sc->tsec_tx_vaddr); 1181 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1182 sc->tsec_rx_vaddr); 1183 } 1184 1185 static void 1186 tsec_stop(struct tsec_softc *sc) 1187 { 1188 struct ifnet *ifp; 1189 struct mbuf *m0; 1190 bus_dmamap_t *mapp; 1191 uint32_t tmpval; 1192 1193 TSEC_GLOBAL_LOCK_ASSERT(sc); 1194 1195 ifp = sc->tsec_ifp; 1196 1197 /* Disable interface and watchdog timer */ 1198 callout_stop(&sc->tsec_callout); 1199 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1200 sc->tsec_watchdog = 0; 1201 1202 /* Disable all interrupts and stop DMA */ 1203 tsec_intrs_ctl(sc, 0); 1204 tsec_dma_ctl(sc, 0); 1205 1206 /* Remove pending data from TX queue */ 1207 while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1208 m0 = TSEC_GET_TX_MBUF(sc); 1209 mapp = TSEC_GET_TX_MAP(sc); 1210 1211 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1212 BUS_DMASYNC_POSTWRITE); 1213 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1214 1215 TSEC_FREE_TX_MAP(sc, mapp); 1216 m_freem(m0); 1217 } 1218 1219 /* Disable RX and TX */ 1220 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1221 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1222 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1223 DELAY(10); 1224 } 1225 1226 static void 1227 tsec_tick(void *arg) 1228 { 1229 struct tsec_softc *sc = arg; 1230 struct ifnet *ifp; 1231 int link; 1232 1233 TSEC_GLOBAL_LOCK(sc); 1234 1235 tsec_watchdog(sc); 1236 1237 ifp = sc->tsec_ifp; 1238 link = sc->tsec_link; 1239 1240 mii_tick(sc->tsec_mii); 1241 1242 if (link == 0 && sc->tsec_link == 1 && 1243 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1244 tsec_start_locked(ifp); 1245 1246 /* Schedule another timeout one second from now. */ 1247 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1248 1249 TSEC_GLOBAL_UNLOCK(sc); 1250 } 1251 1252 /* 1253 * This is the core RX routine. It replenishes mbufs in the descriptor and 1254 * sends data which have been dma'ed into host memory to upper layer. 1255 * 1256 * Loops at most count times if count is > 0, or until done if count < 0. 1257 */ 1258 static int 1259 tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1260 { 1261 struct tsec_desc *rx_desc; 1262 struct ifnet *ifp; 1263 struct rx_data_type *rx_data; 1264 struct mbuf *m; 1265 device_t dev; 1266 uint32_t i; 1267 int c, rx_npkts; 1268 uint16_t flags; 1269 1270 TSEC_RECEIVE_LOCK_ASSERT(sc); 1271 1272 ifp = sc->tsec_ifp; 1273 rx_data = sc->rx_data; 1274 dev = sc->dev; 1275 rx_npkts = 0; 1276 1277 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1278 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1279 1280 for (c = 0; ; c++) { 1281 if (count >= 0 && count-- == 0) 1282 break; 1283 1284 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1285 flags = rx_desc->flags; 1286 1287 /* Check if there is anything to receive */ 1288 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1289 /* 1290 * Avoid generating another interrupt 1291 */ 1292 if (flags & TSEC_RXBD_E) 1293 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1294 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1295 /* 1296 * We didn't consume current descriptor and have to 1297 * return it to the queue 1298 */ 1299 TSEC_BACK_CUR_RX_DESC(sc); 1300 break; 1301 } 1302 1303 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1304 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1305 1306 rx_desc->length = 0; 1307 rx_desc->flags = (rx_desc->flags & 1308 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1309 1310 if (sc->frame != NULL) { 1311 m_free(sc->frame); 1312 sc->frame = NULL; 1313 } 1314 1315 continue; 1316 } 1317 1318 /* Ok... process frame */ 1319 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1320 m = rx_data[i].mbuf; 1321 m->m_len = rx_desc->length; 1322 1323 if (sc->frame != NULL) { 1324 if ((flags & TSEC_RXBD_L) != 0) 1325 m->m_len -= m_length(sc->frame, NULL); 1326 1327 m->m_flags &= ~M_PKTHDR; 1328 m_cat(sc->frame, m); 1329 } else { 1330 sc->frame = m; 1331 } 1332 1333 m = NULL; 1334 1335 if ((flags & TSEC_RXBD_L) != 0) { 1336 m = sc->frame; 1337 sc->frame = NULL; 1338 } 1339 1340 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1341 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1342 ifp->if_ierrors++; 1343 /* 1344 * We ran out of mbufs; didn't consume current 1345 * descriptor and have to return it to the queue. 1346 */ 1347 TSEC_BACK_CUR_RX_DESC(sc); 1348 break; 1349 } 1350 1351 /* Attach new buffer to descriptor and clear flags */ 1352 rx_desc->bufptr = rx_data[i].paddr; 1353 rx_desc->length = 0; 1354 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1355 TSEC_RXBD_E | TSEC_RXBD_I; 1356 1357 if (m != NULL) { 1358 m->m_pkthdr.rcvif = ifp; 1359 1360 m_fixhdr(m); 1361 m_adj(m, -ETHER_CRC_LEN); 1362 1363 if (sc->is_etsec) 1364 tsec_offload_process_frame(sc, m); 1365 1366 TSEC_RECEIVE_UNLOCK(sc); 1367 (*ifp->if_input)(ifp, m); 1368 TSEC_RECEIVE_LOCK(sc); 1369 rx_npkts++; 1370 } 1371 } 1372 1373 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1375 1376 /* 1377 * Make sure TSEC receiver is not halted. 1378 * 1379 * Various conditions can stop the TSEC receiver, but not all are 1380 * signaled and handled by error interrupt, so make sure the receiver 1381 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1382 * halted, and is harmless if already running. 1383 */ 1384 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1385 return (rx_npkts); 1386 } 1387 1388 void 1389 tsec_receive_intr(void *arg) 1390 { 1391 struct tsec_softc *sc = arg; 1392 1393 TSEC_RECEIVE_LOCK(sc); 1394 1395 #ifdef DEVICE_POLLING 1396 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1397 TSEC_RECEIVE_UNLOCK(sc); 1398 return; 1399 } 1400 #endif 1401 1402 /* Confirm the interrupt was received by driver */ 1403 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1404 tsec_receive_intr_locked(sc, -1); 1405 1406 TSEC_RECEIVE_UNLOCK(sc); 1407 } 1408 1409 static void 1410 tsec_transmit_intr_locked(struct tsec_softc *sc) 1411 { 1412 struct tsec_desc *tx_desc; 1413 struct ifnet *ifp; 1414 struct mbuf *m0; 1415 bus_dmamap_t *mapp; 1416 int send = 0; 1417 1418 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1419 1420 ifp = sc->tsec_ifp; 1421 1422 /* Update collision statistics */ 1423 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1424 1425 /* Reset collision counters in hardware */ 1426 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1427 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1428 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1429 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1430 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1431 1432 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1434 1435 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1436 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1437 if (tx_desc->flags & TSEC_TXBD_R) { 1438 TSEC_BACK_DIRTY_TX_DESC(sc); 1439 break; 1440 } 1441 1442 if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1443 continue; 1444 1445 /* 1446 * This is the last buf in this packet, so unmap and free it. 1447 */ 1448 m0 = TSEC_GET_TX_MBUF(sc); 1449 mapp = TSEC_GET_TX_MAP(sc); 1450 1451 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1452 BUS_DMASYNC_POSTWRITE); 1453 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1454 1455 TSEC_FREE_TX_MAP(sc, mapp); 1456 m_freem(m0); 1457 1458 ifp->if_opackets++; 1459 send = 1; 1460 } 1461 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1462 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1463 1464 if (send) { 1465 /* Now send anything that was pending */ 1466 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1467 tsec_start_locked(ifp); 1468 1469 /* Stop wathdog if all sent */ 1470 if (TSEC_EMPTYQ_TX_MBUF(sc)) 1471 sc->tsec_watchdog = 0; 1472 } 1473 } 1474 1475 void 1476 tsec_transmit_intr(void *arg) 1477 { 1478 struct tsec_softc *sc = arg; 1479 1480 TSEC_TRANSMIT_LOCK(sc); 1481 1482 #ifdef DEVICE_POLLING 1483 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1484 TSEC_TRANSMIT_UNLOCK(sc); 1485 return; 1486 } 1487 #endif 1488 /* Confirm the interrupt was received by driver */ 1489 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1490 tsec_transmit_intr_locked(sc); 1491 1492 TSEC_TRANSMIT_UNLOCK(sc); 1493 } 1494 1495 static void 1496 tsec_error_intr_locked(struct tsec_softc *sc, int count) 1497 { 1498 struct ifnet *ifp; 1499 uint32_t eflags; 1500 1501 TSEC_GLOBAL_LOCK_ASSERT(sc); 1502 1503 ifp = sc->tsec_ifp; 1504 1505 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1506 1507 /* Clear events bits in hardware */ 1508 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1509 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1510 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1511 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1512 1513 /* Check transmitter errors */ 1514 if (eflags & TSEC_IEVENT_TXE) { 1515 ifp->if_oerrors++; 1516 1517 if (eflags & TSEC_IEVENT_LC) 1518 ifp->if_collisions++; 1519 1520 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1521 } 1522 1523 /* Check receiver errors */ 1524 if (eflags & TSEC_IEVENT_BSY) { 1525 ifp->if_ierrors++; 1526 ifp->if_iqdrops++; 1527 1528 /* Get data from RX buffers */ 1529 tsec_receive_intr_locked(sc, count); 1530 } 1531 1532 if (ifp->if_flags & IFF_DEBUG) 1533 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1534 eflags); 1535 1536 if (eflags & TSEC_IEVENT_EBERR) { 1537 if_printf(ifp, "System bus error occurred during" 1538 "DMA transaction (flags: 0x%x)\n", eflags); 1539 tsec_init_locked(sc); 1540 } 1541 1542 if (eflags & TSEC_IEVENT_BABT) 1543 ifp->if_oerrors++; 1544 1545 if (eflags & TSEC_IEVENT_BABR) 1546 ifp->if_ierrors++; 1547 } 1548 1549 void 1550 tsec_error_intr(void *arg) 1551 { 1552 struct tsec_softc *sc = arg; 1553 1554 TSEC_GLOBAL_LOCK(sc); 1555 tsec_error_intr_locked(sc, -1); 1556 TSEC_GLOBAL_UNLOCK(sc); 1557 } 1558 1559 int 1560 tsec_miibus_readreg(device_t dev, int phy, int reg) 1561 { 1562 struct tsec_softc *sc; 1563 uint32_t timeout; 1564 1565 sc = tsec0_sc; 1566 1567 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1568 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1569 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1570 1571 timeout = TSEC_READ_RETRY; 1572 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) & 1573 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1574 DELAY(TSEC_READ_DELAY); 1575 1576 if (timeout == 0) 1577 device_printf(dev, "Timeout while reading from PHY!\n"); 1578 1579 return (TSEC_READ(sc, TSEC_REG_MIIMSTAT)); 1580 } 1581 1582 int 1583 tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1584 { 1585 struct tsec_softc *sc; 1586 uint32_t timeout; 1587 1588 sc = tsec0_sc; 1589 1590 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1591 TSEC_WRITE(sc, TSEC_REG_MIIMCON, value); 1592 1593 timeout = TSEC_READ_RETRY; 1594 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & 1595 TSEC_MIIMIND_BUSY)) 1596 DELAY(TSEC_READ_DELAY); 1597 1598 if (timeout == 0) 1599 device_printf(dev, "Timeout while writing to PHY!\n"); 1600 1601 return (0); 1602 } 1603 1604 void 1605 tsec_miibus_statchg(device_t dev) 1606 { 1607 struct tsec_softc *sc; 1608 struct mii_data *mii; 1609 uint32_t ecntrl, id, tmp; 1610 int link; 1611 1612 sc = device_get_softc(dev); 1613 mii = sc->tsec_mii; 1614 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1615 1616 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1617 1618 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1619 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1620 else 1621 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1622 1623 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1624 case IFM_1000_T: 1625 case IFM_1000_SX: 1626 tmp |= TSEC_MACCFG2_GMII; 1627 sc->tsec_link = link; 1628 break; 1629 case IFM_100_TX: 1630 case IFM_10_T: 1631 tmp |= TSEC_MACCFG2_MII; 1632 sc->tsec_link = link; 1633 break; 1634 case IFM_NONE: 1635 if (link) 1636 device_printf(dev, "No speed selected but link " 1637 "active!\n"); 1638 sc->tsec_link = 0; 1639 return; 1640 default: 1641 sc->tsec_link = 0; 1642 device_printf(dev, "Unknown speed (%d), link %s!\n", 1643 IFM_SUBTYPE(mii->mii_media_active), 1644 ((link) ? "up" : "down")); 1645 return; 1646 } 1647 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1648 1649 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1650 id = TSEC_READ(sc, TSEC_REG_ID2); 1651 if (id & 0xffff) { 1652 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1653 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1654 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1655 } 1656 } 1657 1658 static void 1659 tsec_add_sysctls(struct tsec_softc *sc) 1660 { 1661 struct sysctl_ctx_list *ctx; 1662 struct sysctl_oid_list *children; 1663 struct sysctl_oid *tree; 1664 1665 ctx = device_get_sysctl_ctx(sc->dev); 1666 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1667 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1668 CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1669 children = SYSCTL_CHILDREN(tree); 1670 1671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1672 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1673 "I", "IC RX time threshold (0-65535)"); 1674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1675 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1676 "I", "IC RX frame count threshold (0-255)"); 1677 1678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1679 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1680 "I", "IC TX time threshold (0-65535)"); 1681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1682 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1683 "I", "IC TX frame count threshold (0-255)"); 1684 } 1685 1686 /* 1687 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1688 * interrupt is raised either upon: 1689 * 1690 * - threshold-defined period of time elapsed, or 1691 * - threshold-defined number of frames is received/transmitted, 1692 * whichever occurs first. 1693 * 1694 * The following sysctls regulate IC behaviour (for TX/RX separately): 1695 * 1696 * dev.tsec.<unit>.int_coal.rx_time 1697 * dev.tsec.<unit>.int_coal.rx_count 1698 * dev.tsec.<unit>.int_coal.tx_time 1699 * dev.tsec.<unit>.int_coal.tx_count 1700 * 1701 * Values: 1702 * 1703 * - 0 for either time or count disables IC on the given TX/RX path 1704 * 1705 * - count: 1-255 (expresses frame count number; note that value of 1 is 1706 * effectively IC off) 1707 * 1708 * - time: 1-65535 (value corresponds to a real time period and is 1709 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1710 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1711 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1712 * TSEC reference manual. 1713 */ 1714 static int 1715 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1716 { 1717 int error; 1718 uint32_t time; 1719 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1720 1721 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1722 1723 error = sysctl_handle_int(oidp, &time, 0, req); 1724 if (error != 0) 1725 return (error); 1726 1727 if (time > 65535) 1728 return (EINVAL); 1729 1730 TSEC_IC_LOCK(sc); 1731 if (arg2 == TSEC_IC_RX) { 1732 sc->rx_ic_time = time; 1733 tsec_set_rxic(sc); 1734 } else { 1735 sc->tx_ic_time = time; 1736 tsec_set_txic(sc); 1737 } 1738 TSEC_IC_UNLOCK(sc); 1739 1740 return (0); 1741 } 1742 1743 static int 1744 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1745 { 1746 int error; 1747 uint32_t count; 1748 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1749 1750 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1751 1752 error = sysctl_handle_int(oidp, &count, 0, req); 1753 if (error != 0) 1754 return (error); 1755 1756 if (count > 255) 1757 return (EINVAL); 1758 1759 TSEC_IC_LOCK(sc); 1760 if (arg2 == TSEC_IC_RX) { 1761 sc->rx_ic_count = count; 1762 tsec_set_rxic(sc); 1763 } else { 1764 sc->tx_ic_count = count; 1765 tsec_set_txic(sc); 1766 } 1767 TSEC_IC_UNLOCK(sc); 1768 1769 return (0); 1770 } 1771 1772 static void 1773 tsec_set_rxic(struct tsec_softc *sc) 1774 { 1775 uint32_t rxic_val; 1776 1777 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1778 /* Disable RX IC */ 1779 rxic_val = 0; 1780 else { 1781 rxic_val = 0x80000000; 1782 rxic_val |= (sc->rx_ic_count << 21); 1783 rxic_val |= sc->rx_ic_time; 1784 } 1785 1786 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1787 } 1788 1789 static void 1790 tsec_set_txic(struct tsec_softc *sc) 1791 { 1792 uint32_t txic_val; 1793 1794 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1795 /* Disable TX IC */ 1796 txic_val = 0; 1797 else { 1798 txic_val = 0x80000000; 1799 txic_val |= (sc->tx_ic_count << 21); 1800 txic_val |= sc->tx_ic_time; 1801 } 1802 1803 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1804 } 1805 1806 static void 1807 tsec_offload_setup(struct tsec_softc *sc) 1808 { 1809 struct ifnet *ifp = sc->tsec_ifp; 1810 uint32_t reg; 1811 1812 TSEC_GLOBAL_LOCK_ASSERT(sc); 1813 1814 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1815 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1816 1817 if (ifp->if_capenable & IFCAP_TXCSUM) 1818 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1819 else 1820 ifp->if_hwassist = 0; 1821 1822 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1823 1824 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1825 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1826 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1827 1828 if (ifp->if_capenable & IFCAP_RXCSUM) 1829 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1830 TSEC_RCTRL_PRSDEP_PARSE_L234; 1831 1832 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1833 } 1834 1835 1836 static void 1837 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1838 { 1839 struct tsec_rx_fcb rx_fcb; 1840 int csum_flags = 0; 1841 int protocol, flags; 1842 1843 TSEC_RECEIVE_LOCK_ASSERT(sc); 1844 1845 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1846 flags = rx_fcb.flags; 1847 protocol = rx_fcb.protocol; 1848 1849 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1850 csum_flags |= CSUM_IP_CHECKED; 1851 1852 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1853 csum_flags |= CSUM_IP_VALID; 1854 } 1855 1856 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1857 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1858 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1859 1860 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1861 m->m_pkthdr.csum_data = 0xFFFF; 1862 } 1863 1864 m->m_pkthdr.csum_flags = csum_flags; 1865 1866 if (flags & TSEC_RX_FCB_VLAN) { 1867 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1868 m->m_flags |= M_VLANTAG; 1869 } 1870 1871 m_adj(m, sizeof(struct tsec_rx_fcb)); 1872 } 1873 1874 static void 1875 tsec_setup_multicast(struct tsec_softc *sc) 1876 { 1877 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1878 struct ifnet *ifp = sc->tsec_ifp; 1879 struct ifmultiaddr *ifma; 1880 uint32_t h; 1881 int i; 1882 1883 TSEC_GLOBAL_LOCK_ASSERT(sc); 1884 1885 if (ifp->if_flags & IFF_ALLMULTI) { 1886 for (i = 0; i < 8; i++) 1887 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1888 1889 return; 1890 } 1891 1892 if_maddr_rlock(ifp); 1893 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1894 1895 if (ifma->ifma_addr->sa_family != AF_LINK) 1896 continue; 1897 1898 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1899 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1900 1901 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1902 } 1903 if_maddr_runlock(ifp); 1904 1905 for (i = 0; i < 8; i++) 1906 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1907 } 1908 1909 static int 1910 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1911 { 1912 1913 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1914 1915 TSEC_GLOBAL_LOCK_ASSERT(sc); 1916 1917 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1918 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1919 return (mtu); 1920 } 1921 1922 return (0); 1923 }
Cache object: 40eba51863de31f4c0a3579c636bf9fa
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