Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_cl.h
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1 /* 2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/6.0/sys/dev/twa/tw_cl.h 144966 2005-04-12 22:07:11Z vkashyap $ 28 */ 29 30 /* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 */ 35 36 37 38 #ifndef TW_CL_H 39 40 #define TW_CL_H 41 42 43 /* 44 * Common Layer internal macros, structures and functions. 45 */ 46 47 48 #define TW_CLI_SECTOR_SIZE 0x200 49 #define TW_CLI_REQUEST_TIMEOUT_PERIOD 60 /* seconds */ 50 #define TW_CLI_RESET_TIMEOUT_PERIOD 60 /* seconds */ 51 #define TW_CLI_MAX_RESET_ATTEMPTS 2 52 53 #ifdef TW_OSL_FLASH_FIRMWARE 54 /* Number of chunks the fw image is broken into, while flashing. */ 55 #define TW_CLI_NUM_FW_IMAGE_CHUNKS 500 56 #endif /* TW_OSL_FLASH_FIRMWARE */ 57 58 /* Possible values of ctlr->state. */ 59 /* Initialization done, and controller is active. */ 60 #define TW_CLI_CTLR_STATE_ACTIVE (1<<0) 61 /* Interrupts on controller enabled. */ 62 #define TW_CLI_CTLR_STATE_INTR_ENABLED (1<<1) 63 /* Data buffer for internal requests in use. */ 64 #define TW_CLI_CTLR_STATE_INTERNAL_REQ_BUSY (1<<2) 65 /* More AEN's need to be retrieved. */ 66 #define TW_CLI_CTLR_STATE_GET_MORE_AENS (1<<3) 67 /* Controller is being reset. */ 68 #define TW_CLI_CTLR_STATE_RESET_IN_PROGRESS (1<<4) 69 70 /* Possible values of ctlr->ioctl_lock.lock. */ 71 #define TW_CLI_LOCK_FREE 0x0 /* lock is free */ 72 #define TW_CLI_LOCK_HELD 0x1 /* lock is held */ 73 74 /* Possible values of req->state. */ 75 #define TW_CLI_REQ_STATE_INIT 0x0 /* being initialized */ 76 #define TW_CLI_REQ_STATE_BUSY 0x1 /* submitted to controller */ 77 #define TW_CLI_REQ_STATE_PENDING 0x2 /* in pending queue */ 78 #define TW_CLI_REQ_STATE_COMPLETE 0x3 /* completed by controller */ 79 80 /* Possible values of req->flags. */ 81 #define TW_CLI_REQ_FLAGS_7K (1<<0) /* 7000 cmd pkt */ 82 #define TW_CLI_REQ_FLAGS_9K (1<<1) /* 9000 cmd pkt */ 83 #define TW_CLI_REQ_FLAGS_INTERNAL (1<<2) /* internal request */ 84 #define TW_CLI_REQ_FLAGS_PASSTHRU (1<<3) /* passthru request */ 85 #define TW_CLI_REQ_FLAGS_EXTERNAL (1<<4) /* external request */ 86 87 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 88 /* Register offsets in PCI config space. */ 89 #define TW_CLI_PCI_CONFIG_COMMAND_OFFSET 0x4 /* cmd register offset */ 90 #define TW_CLI_PCI_CONFIG_STATUS_OFFSET 0x6 /* status register offset */ 91 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 92 93 #pragma pack(1) 94 95 #ifdef TW_OSL_DEBUG 96 struct tw_cli_q_stats { 97 TW_UINT32 cur_len;/* current # of entries in q */ 98 TW_UINT32 max_len; /* max # of entries in q, ever reached */ 99 }; 100 #endif /* TW_OSL_DEBUG */ 101 102 103 /* Queues of CL internal request context packets. */ 104 #define TW_CLI_FREE_Q 0 /* free q */ 105 #define TW_CLI_BUSY_Q 1 /* q of reqs submitted to fw */ 106 #define TW_CLI_PENDING_Q 2 /* q of reqs deferred due to 'q full' */ 107 #define TW_CLI_COMPLETE_Q 3 /* q of reqs completed by fw */ 108 #define TW_CLI_Q_COUNT 4 /* total number of queues */ 109 110 111 /* CL's internal request context. */ 112 struct tw_cli_req_context { 113 struct tw_cl_req_handle *req_handle;/* handle to track requests between 114 OSL & CL */ 115 struct tw_cli_ctlr_context *ctlr; /* ptr to CL's controller context */ 116 struct tw_cl_command_packet *cmd_pkt;/* ptr to ctlr cmd pkt */ 117 TW_UINT64 cmd_pkt_phys; /* cmd pkt physical address */ 118 TW_VOID *data; /* ptr to data being passed to fw */ 119 TW_UINT32 length; /* length of data being passed to fw */ 120 TW_UINT64 data_phys; /* physical address of data */ 121 122 TW_UINT32 state; /* request state */ 123 TW_UINT32 flags; /* request flags */ 124 125 TW_UINT32 error_code; /* error encountered before submission 126 of request to fw, if any */ 127 128 TW_VOID *orig_req; /* ptr to original request for use 129 during callback */ 130 TW_VOID (*tw_cli_callback)(struct tw_cli_req_context *req); 131 /* CL internal callback */ 132 TW_UINT32 request_id; /* request id for tracking with fw */ 133 struct tw_cl_link link; /* to link this request in a list */ 134 }; 135 136 137 /* CL's internal controller context. */ 138 struct tw_cli_ctlr_context { 139 struct tw_cl_ctlr_handle *ctlr_handle; /* handle to track ctlr between 140 OSL & CL. */ 141 struct tw_cli_req_context *req_ctxt_buf;/* pointer to the array of CL's 142 internal request context pkts */ 143 144 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 145 146 TW_UINT32 free_req_ids[TW_CL_MAX_SIMULTANEOUS_REQUESTS]; 147 /* Array of free req_id's */ 148 struct tw_cli_req_context *busy_reqs[TW_CL_MAX_SIMULTANEOUS_REQUESTS + 1]; 149 /* Array of busy reqs -- index is req_id */ 150 TW_UINT32 free_req_head; 151 TW_UINT32 free_req_tail; 152 TW_UINT32 num_free_req_ids; 153 154 #endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */ 155 156 struct tw_cl_command_packet *cmd_pkt_buf;/* ptr to array of cmd pkts */ 157 158 TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */ 159 160 TW_UINT32 state; /* controller state */ 161 TW_UINT32 flags; /* controller settings */ 162 163 /* Request queues and arrays. */ 164 struct tw_cl_link req_q_head[TW_CLI_Q_COUNT]; 165 166 #ifdef TW_OSL_FLASH_FIRMWARE 167 TW_VOID *flash_dma_mem; /* mem for flashing fw image */ 168 TW_UINT64 flash_dma_mem_phys;/* flash_dma_mem phys addr */ 169 #endif /* TW_OSL_FLASH_FIRMWARE */ 170 171 TW_UINT8 *internal_req_data;/* internal req data buf */ 172 TW_UINT64 internal_req_data_phys;/* phys addr of internal 173 req data buf */ 174 TW_UINT32 max_simult_reqs; /* max simultaneous requests 175 supported */ 176 TW_UINT32 max_aens_supported;/* max AEN's supported */ 177 /* AEN handler fields. */ 178 struct tw_cl_event_packet *aen_queue; /* circular queue of AENs from 179 firmware/CL/OSL */ 180 TW_UINT32 aen_head; /* AEN queue head */ 181 TW_UINT32 aen_tail; /* AEN queue tail */ 182 TW_UINT32 aen_cur_seq_id; /* index of the last event+1 */ 183 TW_UINT32 aen_q_overflow; /* indicates if unretrieved 184 events were overwritten */ 185 TW_UINT32 aen_q_wrapped; /* indicates if AEN queue ever 186 wrapped */ 187 188 TW_UINT16 working_srl; /* driver & firmware negotiated 189 srl */ 190 TW_UINT16 working_branch; /* branch # of the firmware 191 that the driver is compatible with */ 192 TW_UINT16 working_build; /* build # of the firmware 193 that the driver is compatible with */ 194 TW_UINT32 operating_mode; /* base mode/current mode */ 195 196 TW_INT32 host_intr_pending;/* host intr processing 197 needed */ 198 TW_INT32 attn_intr_pending;/* attn intr processing 199 needed */ 200 TW_INT32 cmd_intr_pending;/* cmd intr processing 201 needed */ 202 TW_INT32 resp_intr_pending;/* resp intr processing 203 needed */ 204 205 TW_LOCK_HANDLE gen_lock_handle;/* general purpose lock */ 206 TW_LOCK_HANDLE *gen_lock;/* ptr to general purpose lock */ 207 TW_LOCK_HANDLE io_lock_handle; /* lock held during cmd 208 submission */ 209 TW_LOCK_HANDLE *io_lock;/* ptr to lock held during cmd 210 submission */ 211 TW_LOCK_HANDLE intr_lock_handle;/* lock held during 212 ISR/response intr processing */ 213 TW_LOCK_HANDLE *intr_lock;/* ptr to lock held during ISR/ 214 response intr processing */ 215 216 #ifdef TW_OSL_CAN_SLEEP 217 TW_SLEEP_HANDLE sleep_handle; /* handle to co-ordinate sleeps 218 & wakeups */ 219 #endif /* TW_OSL_CAN_SLEEP */ 220 221 struct { 222 TW_UINT32 lock; /* lock state */ 223 TW_TIME timeout; /* time at which the lock will 224 become available, even if not 225 explicitly released */ 226 } ioctl_lock; /* lock for use by user applications, for 227 synchronization between ioctl calls */ 228 #ifdef TW_OSL_DEBUG 229 struct tw_cli_q_stats q_stats[TW_CLI_Q_COUNT];/* queue statistics */ 230 #endif /* TW_OSL_DEBUG */ 231 }; 232 233 #pragma pack() 234 235 236 /* 237 * Queue primitives 238 */ 239 240 #ifdef TW_OSL_DEBUG 241 242 #define TW_CLI_Q_INIT(ctlr, q_type) do { \ 243 (ctlr)->q_stats[q_type].cur_len = 0; \ 244 (ctlr)->q_stats[q_type].max_len = 0; \ 245 } while (0) 246 247 248 #define TW_CLI_Q_INSERT(ctlr, q_type) do { \ 249 struct tw_cli_q_stats *q_stats = &((ctlr)->q_stats[q_type]); \ 250 \ 251 if (++(q_stats->cur_len) > q_stats->max_len) \ 252 q_stats->max_len = q_stats->cur_len; \ 253 } while (0) 254 255 256 #define TW_CLI_Q_REMOVE(ctlr, q_type) \ 257 (ctlr)->q_stats[q_type].cur_len-- 258 259 #else /* TW_OSL_DEBUG */ 260 261 #define TW_CLI_Q_INIT(ctlr, q_index) 262 #define TW_CLI_Q_INSERT(ctlr, q_index) 263 #define TW_CLI_Q_REMOVE(ctlr, q_index) 264 265 #endif /* TW_OSL_DEBUG */ 266 267 268 /* Initialize a queue of requests. */ 269 static __inline TW_VOID 270 tw_cli_req_q_init(struct tw_cli_ctlr_context *ctlr, TW_UINT8 q_type) 271 { 272 TW_CL_Q_INIT(&(ctlr->req_q_head[q_type])); 273 TW_CLI_Q_INIT(ctlr, q_type); 274 } 275 276 277 278 /* Insert the given request at the head of the given queue (q_type). */ 279 static __inline TW_VOID 280 tw_cli_req_q_insert_head(struct tw_cli_req_context *req, TW_UINT8 q_type) 281 { 282 struct tw_cli_ctlr_context *ctlr = req->ctlr; 283 284 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 285 if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) || 286 ((q_type == TW_CLI_PENDING_Q) && 287 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL)))) 288 return; 289 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 290 291 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 292 TW_CL_Q_INSERT_HEAD(&(ctlr->req_q_head[q_type]), &(req->link)); 293 TW_CLI_Q_INSERT(ctlr, q_type); 294 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 295 } 296 297 298 299 /* Insert the given request at the tail of the given queue (q_type). */ 300 static __inline TW_VOID 301 tw_cli_req_q_insert_tail(struct tw_cli_req_context *req, TW_UINT8 q_type) 302 { 303 struct tw_cli_ctlr_context *ctlr = req->ctlr; 304 305 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 306 if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) || 307 ((q_type == TW_CLI_PENDING_Q) && 308 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL)))) 309 return; 310 if ((q_type == TW_CLI_FREE_Q) && 311 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))) { 312 ctlr->free_req_ids[ctlr->free_req_tail] = req->request_id; 313 ctlr->busy_reqs[req->request_id] = TW_CL_NULL; 314 ctlr->free_req_tail = (ctlr->free_req_tail + 1) % 315 (ctlr->max_simult_reqs - 1); 316 ctlr->num_free_req_ids++; 317 return; 318 } 319 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 320 321 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 322 TW_CL_Q_INSERT_TAIL(&(ctlr->req_q_head[q_type]), &(req->link)); 323 TW_CLI_Q_INSERT(ctlr, q_type); 324 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 325 } 326 327 328 329 /* Remove and return the request at the head of the given queue (q_type). */ 330 static __inline struct tw_cli_req_context * 331 tw_cli_req_q_remove_head(struct tw_cli_ctlr_context *ctlr, TW_UINT8 q_type) 332 { 333 struct tw_cli_req_context *req = TW_CL_NULL; 334 struct tw_cl_link *link; 335 336 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 337 if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q)) 338 return(req); 339 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 340 341 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 342 if ((link = TW_CL_Q_FIRST_ITEM(&(ctlr->req_q_head[q_type]))) != 343 TW_CL_NULL) { 344 req = TW_CL_STRUCT_HEAD(link, 345 struct tw_cli_req_context, link); 346 TW_CL_Q_REMOVE_ITEM(&(ctlr->req_q_head[q_type]), &(req->link)); 347 TW_CLI_Q_REMOVE(ctlr, q_type); 348 } 349 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 350 return(req); 351 } 352 353 354 355 /* Remove the given request from the given queue (q_type). */ 356 static __inline TW_VOID 357 tw_cli_req_q_remove_item(struct tw_cli_req_context *req, TW_UINT8 q_type) 358 { 359 struct tw_cli_ctlr_context *ctlr = req->ctlr; 360 361 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 362 if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) || 363 ((q_type == TW_CLI_PENDING_Q) && 364 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL)))) 365 return; 366 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 367 368 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 369 TW_CL_Q_REMOVE_ITEM(&(ctlr->req_q_head[q_type]), &(req->link)); 370 TW_CLI_Q_REMOVE(ctlr, q_type); 371 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); 372 } 373 374 375 376 /* Create an event packet for an event/error posted by the controller. */ 377 #define tw_cli_create_ctlr_event(ctlr, event_src, cmd_hdr) do { \ 378 TW_UINT8 severity = \ 379 GET_SEVERITY((cmd_hdr)->status_block.res__severity); \ 380 \ 381 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_TRUE, event_src, \ 382 (cmd_hdr)->status_block.error, \ 383 severity, \ 384 tw_cli_severity_string_table[severity], \ 385 (cmd_hdr)->err_specific_desc + \ 386 tw_osl_strlen((cmd_hdr)->err_specific_desc) + 1, \ 387 (cmd_hdr)->err_specific_desc); \ 388 /* Print 18 bytes of sense information. */ \ 389 tw_cli_dbg_printf(2, ctlr->ctlr_handle, \ 390 tw_osl_cur_func(), \ 391 "sense info: %x %x %x %x %x %x %x %x %x " \ 392 "%x %x %x %x %x %x %x %x %x", \ 393 (cmd_hdr)->sense_data[0], (cmd_hdr)->sense_data[1], \ 394 (cmd_hdr)->sense_data[2], (cmd_hdr)->sense_data[3], \ 395 (cmd_hdr)->sense_data[4], (cmd_hdr)->sense_data[5], \ 396 (cmd_hdr)->sense_data[6], (cmd_hdr)->sense_data[7], \ 397 (cmd_hdr)->sense_data[8], (cmd_hdr)->sense_data[9], \ 398 (cmd_hdr)->sense_data[10], (cmd_hdr)->sense_data[11], \ 399 (cmd_hdr)->sense_data[12], (cmd_hdr)->sense_data[13], \ 400 (cmd_hdr)->sense_data[14], (cmd_hdr)->sense_data[15], \ 401 (cmd_hdr)->sense_data[16], (cmd_hdr)->sense_data[17]); \ 402 } while (0) 403 404 405 406 #endif /* TW_CL_H */
Cache object: 6d74cd8580f6391cbd8e44db30d1483d
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