Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_cl_fwif.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 5 * Copyright (c) 2004-05 Vinod Kashyap 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: releng/12.0/sys/dev/twa/tw_cl_fwif.h 326255 2017-11-27 14:52:40Z pfg $ 30 */ 31 32 /* 33 * AMCC'S 3ware driver for 9000 series storage controllers. 34 * 35 * Author: Vinod Kashyap 36 * Modifications by: Adam Radford 37 */ 38 39 40 41 #ifndef TW_CL_FWIF_H 42 43 #define TW_CL_FWIF_H 44 45 46 /* 47 * Macros and data structures for interfacing with the firmware. 48 */ 49 50 51 /* Register offsets from base address. */ 52 #define TWA_CONTROL_REGISTER_OFFSET 0x0 53 #define TWA_STATUS_REGISTER_OFFSET 0x4 54 #define TWA_COMMAND_QUEUE_OFFSET 0x8 55 #define TWA_RESPONSE_QUEUE_OFFSET 0xC 56 #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 57 #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 58 #define TWA_LARGE_RESPONSE_QUEUE_OFFSET 0x30 59 60 61 /* Control register bit definitions. */ 62 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 63 #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 64 #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 65 #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 66 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 67 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 68 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 69 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 70 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 71 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 72 #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 73 #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 74 #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 75 76 77 /* Status register bit definitions. */ 78 #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 79 #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 80 #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 81 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 82 #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 83 #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 84 #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 85 #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 86 #define TWA_STATUS_HOST_INTERRUPT 0x00080000 87 #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 88 #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 89 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 90 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 91 #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 92 #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 93 94 #define TWA_STATUS_UNEXPECTED_BITS 0x00D00000 95 96 97 /* PCI related defines. */ 98 #define TWA_IO_CONFIG_REG 0x10 99 100 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 101 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 102 103 #define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE 0xFFFF 104 #define TWA_RESET_PHASE1_WAIT_TIME_MS 500 105 106 107 /* Command packet opcodes. */ 108 #define TWA_FW_CMD_NOP 0x00 109 #define TWA_FW_CMD_INIT_CONNECTION 0x01 110 #define TWA_FW_CMD_READ 0x02 111 #define TWA_FW_CMD_WRITE 0x03 112 #define TWA_FW_CMD_READVERIFY 0x04 113 #define TWA_FW_CMD_VERIFY 0x05 114 #define TWA_FW_CMD_ZEROUNIT 0x08 115 #define TWA_FW_CMD_REPLACEUNIT 0x09 116 #define TWA_FW_CMD_HOTSWAP 0x0A 117 #define TWA_FW_CMD_SELFTESTS 0x0B 118 #define TWA_FW_CMD_SYNC_PARAM 0x0C 119 #define TWA_FW_CMD_REORDER_UNITS 0x0D 120 121 #define TWA_FW_CMD_EXECUTE_SCSI 0x10 122 #define TWA_FW_CMD_ATA_PASSTHROUGH 0x11 123 #define TWA_FW_CMD_GET_PARAM 0x12 124 #define TWA_FW_CMD_SET_PARAM 0x13 125 #define TWA_FW_CMD_CREATEUNIT 0x14 126 #define TWA_FW_CMD_DELETEUNIT 0x15 127 #define TWA_FW_CMD_DOWNLOAD_FIRMWARE 0x16 128 #define TWA_FW_CMD_REBUILDUNIT 0x17 129 #define TWA_FW_CMD_POWER_MANAGEMENT 0x18 130 131 #define TWA_FW_CMD_REMOTE_PRINT 0x1B 132 #define TWA_FW_CMD_HARD_RESET_FIRMWARE 0x1C 133 #define TWA_FW_CMD_DEBUG 0x1D 134 135 #define TWA_FW_CMD_DIAGNOSTICS 0x1F 136 137 138 /* Misc defines. */ 139 #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 140 #define TWA_64BIT_SG_ADDRESSES 0x00000001 141 #define TWA_EXTENDED_INIT_CONNECT 0x00000002 142 #define TWA_BASE_MODE 1 143 #define TWA_BASE_FW_SRL 24 144 #define TWA_BASE_FW_BRANCH 0 145 #define TWA_BASE_FW_BUILD 1 146 #define TWA_CURRENT_FW_SRL 41 147 #define TWA_CURRENT_FW_BRANCH_9K 4 148 #define TWA_CURRENT_FW_BUILD_9K 8 149 #define TWA_CURRENT_FW_BRANCH_9K_X 8 150 #define TWA_CURRENT_FW_BUILD_9K_X 4 151 #define TWA_MULTI_LUN_FW_SRL 28 152 #define TWA_ARCH_ID_9K 0x5 /* 9000 PCI controllers */ 153 #define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */ 154 #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 155 #define TWA_CTLR_FW_COMPATIBLE 0x00000002 156 #define TWA_SENSE_DATA_LENGTH 18 157 158 159 #define TWA_ARCH_ID(device_id) \ 160 (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K : \ 161 TWA_ARCH_ID_9K_X) 162 #define TWA_CURRENT_FW_BRANCH(arch_id) \ 163 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K : \ 164 TWA_CURRENT_FW_BRANCH_9K_X) 165 #define TWA_CURRENT_FW_BUILD(arch_id) \ 166 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K : \ 167 TWA_CURRENT_FW_BUILD_9K_X) 168 169 /* 170 * All SG addresses and DMA'able memory allocated by the OSL should be 171 * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of 172 * TWA_SG_ELEMENT_SIZE_FACTOR. 173 */ 174 #define TWA_ALIGNMENT(device_id) 0x4 175 #define TWA_SG_ELEMENT_SIZE_FACTOR(device_id) \ 176 (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4) 177 178 179 /* 180 * Some errors of interest (in cmd_hdr->status_block.error) when a command 181 * is completed by the firmware with a bad status. 182 */ 183 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 184 #define TWA_ERROR_UNIT_OFFLINE 0x0128 185 #define TWA_ERROR_MORE_DATA 0x0231 186 187 188 /* AEN codes of interest. */ 189 #define TWA_AEN_QUEUE_EMPTY 0x00 190 #define TWA_AEN_SOFT_RESET 0x01 191 #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 192 193 194 /* Table #'s and id's of parameters of interest in firmware's param table. */ 195 #define TWA_PARAM_VERSION_TABLE 0x0402 196 #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 197 #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 198 #define TWA_PARAM_CTLR_MODEL 8 /* Controller model [16] */ 199 200 #define TWA_PARAM_CONTROLLER_TABLE 0x0403 201 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */ 202 203 #define TWA_PARAM_TIME_TABLE 0x40A 204 #define TWA_PARAM_TIME_SCHED_TIME 0x3 205 206 #define TWA_9K_PARAM_DESCRIPTOR 0x8000 207 208 209 #pragma pack(1) 210 /* 7000 structures. */ 211 struct tw_cl_command_init_connect { 212 TW_UINT8 res1__opcode; /* 3:5 */ 213 TW_UINT8 size; 214 TW_UINT8 request_id; 215 TW_UINT8 res2; 216 TW_UINT8 status; 217 TW_UINT8 flags; 218 TW_UINT16 message_credits; 219 TW_UINT32 features; 220 TW_UINT16 fw_srl; 221 TW_UINT16 fw_arch_id; 222 TW_UINT16 fw_branch; 223 TW_UINT16 fw_build; 224 TW_UINT32 result; 225 }; 226 227 228 /* Structure for downloading firmware onto the controller. */ 229 struct tw_cl_command_download_firmware { 230 TW_UINT8 sgl_off__opcode;/* 3:5 */ 231 TW_UINT8 size; 232 TW_UINT8 request_id; 233 TW_UINT8 unit; 234 TW_UINT8 status; 235 TW_UINT8 flags; 236 TW_UINT16 param; 237 TW_UINT8 sgl[1]; 238 }; 239 240 241 /* Structure for hard resetting the controller. */ 242 struct tw_cl_command_reset_firmware { 243 TW_UINT8 res1__opcode; /* 3:5 */ 244 TW_UINT8 size; 245 TW_UINT8 request_id; 246 TW_UINT8 unit; 247 TW_UINT8 status; 248 TW_UINT8 flags; 249 TW_UINT8 res2; 250 TW_UINT8 param; 251 }; 252 253 254 /* Structure for sending get/set param commands. */ 255 struct tw_cl_command_param { 256 TW_UINT8 sgl_off__opcode;/* 3:5 */ 257 TW_UINT8 size; 258 TW_UINT8 request_id; 259 TW_UINT8 host_id__unit; /* 4:4 */ 260 TW_UINT8 status; 261 TW_UINT8 flags; 262 TW_UINT16 param_count; 263 TW_UINT8 sgl[1]; 264 }; 265 266 267 /* Generic command packet. */ 268 struct tw_cl_command_generic { 269 TW_UINT8 sgl_off__opcode;/* 3:5 */ 270 TW_UINT8 size; 271 TW_UINT8 request_id; 272 TW_UINT8 host_id__unit; /* 4:4 */ 273 TW_UINT8 status; 274 TW_UINT8 flags; 275 TW_UINT16 count; /* block cnt, parameter cnt, message credits */ 276 }; 277 278 279 /* Command packet header. */ 280 struct tw_cl_command_header { 281 TW_UINT8 sense_data[TWA_SENSE_DATA_LENGTH]; 282 struct { 283 TW_INT8 reserved[4]; 284 TW_UINT16 error; 285 TW_UINT8 padding; 286 TW_UINT8 res__severity; /* 5:3 */ 287 } status_block; 288 TW_UINT8 err_specific_desc[98]; 289 struct { 290 TW_UINT8 size_header; 291 TW_UINT16 reserved; 292 TW_UINT8 size_sense; 293 } header_desc; 294 }; 295 296 297 /* 7000 Command packet. */ 298 union tw_cl_command_7k { 299 struct tw_cl_command_init_connect init_connect; 300 struct tw_cl_command_download_firmware download_fw; 301 struct tw_cl_command_reset_firmware reset_fw; 302 struct tw_cl_command_param param; 303 struct tw_cl_command_generic generic; 304 TW_UINT8 padding[1024 - sizeof(struct tw_cl_command_header)]; 305 }; 306 307 308 /* 9000 Command Packet. */ 309 struct tw_cl_command_9k { 310 TW_UINT8 res__opcode; /* 3:5 */ 311 TW_UINT8 unit; 312 TW_UINT16 lun_l4__req_id; /* 4:12 */ 313 TW_UINT8 status; 314 TW_UINT8 sgl_offset; /* offset (in bytes) to sg_list, from the 315 end of sgl_entries */ 316 TW_UINT16 lun_h4__sgl_entries; 317 TW_UINT8 cdb[16]; 318 TW_UINT8 sg_list[872];/* total struct size = 319 1024-sizeof(cmd_hdr) */ 320 }; 321 322 323 /* Full command packet. */ 324 struct tw_cl_command_packet { 325 struct tw_cl_command_header cmd_hdr; 326 union { 327 union tw_cl_command_7k cmd_pkt_7k; 328 struct tw_cl_command_9k cmd_pkt_9k; 329 } command; 330 }; 331 332 333 /* Structure describing payload for get/set param commands. */ 334 struct tw_cl_param_9k { 335 TW_UINT16 table_id; 336 TW_UINT8 parameter_id; 337 TW_UINT8 reserved; 338 TW_UINT16 parameter_size_bytes; 339 TW_UINT16 parameter_actual_size_bytes; 340 TW_UINT8 data[1]; 341 }; 342 #pragma pack() 343 344 345 /* Functions to read from, and write to registers */ 346 #define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value) \ 347 tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4) 348 349 350 #define TW_CLI_READ_STATUS_REGISTER(ctlr_handle) \ 351 tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4) 352 353 354 #define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \ 355 if (ctlr->flags & TW_CL_64BIT_ADDRESSES) { \ 356 /* First write the low 4 bytes, then the high 4. */ \ 357 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 358 (TW_UINT32)(value), 4); \ 359 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 360 (TW_UINT32)(((TW_UINT64)value)>>32), 4); \ 361 } else \ 362 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \ 363 (TW_UINT32)(value), 4); \ 364 } while (0) 365 366 367 #define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle) \ 368 tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4) 369 370 371 #define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle) \ 372 tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4) 373 374 375 #define TW_CLI_SOFT_RESET(ctlr) \ 376 TW_CLI_WRITE_CONTROL_REGISTER(ctlr, \ 377 TWA_CONTROL_ISSUE_SOFT_RESET | \ 378 TWA_CONTROL_CLEAR_HOST_INTERRUPT | \ 379 TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 380 TWA_CONTROL_MASK_COMMAND_INTERRUPT | \ 381 TWA_CONTROL_MASK_RESPONSE_INTERRUPT | \ 382 TWA_CONTROL_DISABLE_INTERRUPTS) 383 384 /* Detect inconsistencies in the status register. */ 385 #define TW_CLI_STATUS_ERRORS(x) \ 386 ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 387 (x & TWA_STATUS_MICROCONTROLLER_READY)) 388 389 390 /* 391 * Functions for making transparent, the bit fields in firmware 392 * interface structures. 393 */ 394 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \ 395 ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 396 397 #define BUILD_RES__OPCODE(res, opcode) \ 398 ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 399 400 #define BUILD_HOST_ID__UNIT(host_id, unit) \ 401 ((host_id << 4) & 0xF0) | (unit & 0xF) /* 4:4 */ 402 403 #define BUILD_RES__SEVERITY(res, severity) \ 404 ((res << 3) & 0xF8) | (severity & 0x7) /* 5:3 */ 405 406 #define BUILD_LUN_L4__REQ_ID(lun, req_id) \ 407 (((lun << 12) & 0xF000) | (req_id & 0xFFF)) /* 4:12 */ 408 409 #define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries) \ 410 (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */ 411 412 413 #define GET_OPCODE(sgl_off__opcode) \ 414 (sgl_off__opcode & 0x1F) /* 3:5 */ 415 416 #define GET_SGL_OFF(sgl_off__opcode) \ 417 ((sgl_off__opcode >> 5) & 0x7) /* 3:5 */ 418 419 #define GET_UNIT(host_id__unit) \ 420 (host_id__unit & 0xF) /* 4:4 */ 421 422 #define GET_HOST_ID(host_id__unit) \ 423 ((host_id__unit >> 4) & 0xF) /* 4:4 */ 424 425 #define GET_SEVERITY(res__severity) \ 426 (res__severity & 0x7) /* 5:3 */ 427 428 #define GET_RESP_ID(undef2__resp_id__undef1) \ 429 ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */ 430 431 #define GET_RESP_ID_9K_X(undef2__resp_id) \ 432 ((undef2__resp_id) & 0xFFF) /* 20:12 */ 433 434 #define GET_LARGE_RESP_ID(misc__large_resp_id) \ 435 ((misc__large_resp_id) & 0xFFFF) /* 16:16 */ 436 437 #define GET_REQ_ID(lun_l4__req_id) \ 438 (lun_l4__req_id & 0xFFF) /* 4:12 */ 439 440 #define GET_LUN_L4(lun_l4__req_id) \ 441 ((lun_l4__req_id >> 12) & 0xF) /* 4:12 */ 442 443 #define GET_SGL_ENTRIES(lun_h4__sgl_entries) \ 444 (lun_h4__sgl_entries & 0xFFF) /* 4:12 */ 445 446 #define GET_LUN_H4(lun_h4__sgl_entries) \ 447 ((lun_h4__sgl_entries >> 12) & 0xF) /* 4:12 */ 448 449 450 451 #endif /* TW_CL_FWIF_H */
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