Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_cl_fwif.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 5 * Copyright (c) 2004-05 Vinod Kashyap 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * AMCC'S 3ware driver for 9000 series storage controllers. 34 * 35 * Author: Vinod Kashyap 36 * Modifications by: Adam Radford 37 */ 38 39 #ifndef TW_CL_FWIF_H 40 41 #define TW_CL_FWIF_H 42 43 /* 44 * Macros and data structures for interfacing with the firmware. 45 */ 46 47 /* Register offsets from base address. */ 48 #define TWA_CONTROL_REGISTER_OFFSET 0x0 49 #define TWA_STATUS_REGISTER_OFFSET 0x4 50 #define TWA_COMMAND_QUEUE_OFFSET 0x8 51 #define TWA_RESPONSE_QUEUE_OFFSET 0xC 52 #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 53 #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 54 #define TWA_LARGE_RESPONSE_QUEUE_OFFSET 0x30 55 56 /* Control register bit definitions. */ 57 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 58 #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 59 #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 60 #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 61 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 62 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 63 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 64 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 65 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 66 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 67 #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 68 #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 69 #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 70 71 /* Status register bit definitions. */ 72 #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 73 #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 74 #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 75 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 76 #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 77 #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 78 #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 79 #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 80 #define TWA_STATUS_HOST_INTERRUPT 0x00080000 81 #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 82 #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 83 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 84 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 85 #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 86 #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 87 88 #define TWA_STATUS_UNEXPECTED_BITS 0x00D00000 89 90 /* PCI related defines. */ 91 #define TWA_IO_CONFIG_REG 0x10 92 93 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 94 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 95 96 #define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE 0xFFFF 97 #define TWA_RESET_PHASE1_WAIT_TIME_MS 500 98 99 /* Command packet opcodes. */ 100 #define TWA_FW_CMD_NOP 0x00 101 #define TWA_FW_CMD_INIT_CONNECTION 0x01 102 #define TWA_FW_CMD_READ 0x02 103 #define TWA_FW_CMD_WRITE 0x03 104 #define TWA_FW_CMD_READVERIFY 0x04 105 #define TWA_FW_CMD_VERIFY 0x05 106 #define TWA_FW_CMD_ZEROUNIT 0x08 107 #define TWA_FW_CMD_REPLACEUNIT 0x09 108 #define TWA_FW_CMD_HOTSWAP 0x0A 109 #define TWA_FW_CMD_SELFTESTS 0x0B 110 #define TWA_FW_CMD_SYNC_PARAM 0x0C 111 #define TWA_FW_CMD_REORDER_UNITS 0x0D 112 113 #define TWA_FW_CMD_EXECUTE_SCSI 0x10 114 #define TWA_FW_CMD_ATA_PASSTHROUGH 0x11 115 #define TWA_FW_CMD_GET_PARAM 0x12 116 #define TWA_FW_CMD_SET_PARAM 0x13 117 #define TWA_FW_CMD_CREATEUNIT 0x14 118 #define TWA_FW_CMD_DELETEUNIT 0x15 119 #define TWA_FW_CMD_DOWNLOAD_FIRMWARE 0x16 120 #define TWA_FW_CMD_REBUILDUNIT 0x17 121 #define TWA_FW_CMD_POWER_MANAGEMENT 0x18 122 123 #define TWA_FW_CMD_REMOTE_PRINT 0x1B 124 #define TWA_FW_CMD_HARD_RESET_FIRMWARE 0x1C 125 #define TWA_FW_CMD_DEBUG 0x1D 126 127 #define TWA_FW_CMD_DIAGNOSTICS 0x1F 128 129 /* Misc defines. */ 130 #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 131 #define TWA_64BIT_SG_ADDRESSES 0x00000001 132 #define TWA_EXTENDED_INIT_CONNECT 0x00000002 133 #define TWA_BASE_MODE 1 134 #define TWA_BASE_FW_SRL 24 135 #define TWA_BASE_FW_BRANCH 0 136 #define TWA_BASE_FW_BUILD 1 137 #define TWA_CURRENT_FW_SRL 41 138 #define TWA_CURRENT_FW_BRANCH_9K 4 139 #define TWA_CURRENT_FW_BUILD_9K 8 140 #define TWA_CURRENT_FW_BRANCH_9K_X 8 141 #define TWA_CURRENT_FW_BUILD_9K_X 4 142 #define TWA_MULTI_LUN_FW_SRL 28 143 #define TWA_ARCH_ID_9K 0x5 /* 9000 PCI controllers */ 144 #define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */ 145 #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 146 #define TWA_CTLR_FW_COMPATIBLE 0x00000002 147 #define TWA_SENSE_DATA_LENGTH 18 148 149 #define TWA_ARCH_ID(device_id) \ 150 (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K : \ 151 TWA_ARCH_ID_9K_X) 152 #define TWA_CURRENT_FW_BRANCH(arch_id) \ 153 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K : \ 154 TWA_CURRENT_FW_BRANCH_9K_X) 155 #define TWA_CURRENT_FW_BUILD(arch_id) \ 156 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K : \ 157 TWA_CURRENT_FW_BUILD_9K_X) 158 159 /* 160 * All SG addresses and DMA'able memory allocated by the OSL should be 161 * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of 162 * TWA_SG_ELEMENT_SIZE_FACTOR. 163 */ 164 #define TWA_ALIGNMENT(device_id) 0x4 165 #define TWA_SG_ELEMENT_SIZE_FACTOR(device_id) \ 166 (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4) 167 168 /* 169 * Some errors of interest (in cmd_hdr->status_block.error) when a command 170 * is completed by the firmware with a bad status. 171 */ 172 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 173 #define TWA_ERROR_UNIT_OFFLINE 0x0128 174 #define TWA_ERROR_MORE_DATA 0x0231 175 176 /* AEN codes of interest. */ 177 #define TWA_AEN_QUEUE_EMPTY 0x00 178 #define TWA_AEN_SOFT_RESET 0x01 179 #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 180 181 /* Table #'s and id's of parameters of interest in firmware's param table. */ 182 #define TWA_PARAM_VERSION_TABLE 0x0402 183 #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 184 #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 185 #define TWA_PARAM_CTLR_MODEL 8 /* Controller model [16] */ 186 187 #define TWA_PARAM_CONTROLLER_TABLE 0x0403 188 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */ 189 190 #define TWA_PARAM_TIME_TABLE 0x40A 191 #define TWA_PARAM_TIME_SCHED_TIME 0x3 192 193 #define TWA_9K_PARAM_DESCRIPTOR 0x8000 194 195 #pragma pack(1) 196 /* 7000 structures. */ 197 struct tw_cl_command_init_connect { 198 TW_UINT8 res1__opcode; /* 3:5 */ 199 TW_UINT8 size; 200 TW_UINT8 request_id; 201 TW_UINT8 res2; 202 TW_UINT8 status; 203 TW_UINT8 flags; 204 TW_UINT16 message_credits; 205 TW_UINT32 features; 206 TW_UINT16 fw_srl; 207 TW_UINT16 fw_arch_id; 208 TW_UINT16 fw_branch; 209 TW_UINT16 fw_build; 210 TW_UINT32 result; 211 }; 212 213 /* Structure for downloading firmware onto the controller. */ 214 struct tw_cl_command_download_firmware { 215 TW_UINT8 sgl_off__opcode;/* 3:5 */ 216 TW_UINT8 size; 217 TW_UINT8 request_id; 218 TW_UINT8 unit; 219 TW_UINT8 status; 220 TW_UINT8 flags; 221 TW_UINT16 param; 222 TW_UINT8 sgl[1]; 223 }; 224 225 /* Structure for hard resetting the controller. */ 226 struct tw_cl_command_reset_firmware { 227 TW_UINT8 res1__opcode; /* 3:5 */ 228 TW_UINT8 size; 229 TW_UINT8 request_id; 230 TW_UINT8 unit; 231 TW_UINT8 status; 232 TW_UINT8 flags; 233 TW_UINT8 res2; 234 TW_UINT8 param; 235 }; 236 237 /* Structure for sending get/set param commands. */ 238 struct tw_cl_command_param { 239 TW_UINT8 sgl_off__opcode;/* 3:5 */ 240 TW_UINT8 size; 241 TW_UINT8 request_id; 242 TW_UINT8 host_id__unit; /* 4:4 */ 243 TW_UINT8 status; 244 TW_UINT8 flags; 245 TW_UINT16 param_count; 246 TW_UINT8 sgl[1]; 247 }; 248 249 /* Generic command packet. */ 250 struct tw_cl_command_generic { 251 TW_UINT8 sgl_off__opcode;/* 3:5 */ 252 TW_UINT8 size; 253 TW_UINT8 request_id; 254 TW_UINT8 host_id__unit; /* 4:4 */ 255 TW_UINT8 status; 256 TW_UINT8 flags; 257 TW_UINT16 count; /* block cnt, parameter cnt, message credits */ 258 }; 259 260 /* Command packet header. */ 261 struct tw_cl_command_header { 262 TW_UINT8 sense_data[TWA_SENSE_DATA_LENGTH]; 263 struct { 264 TW_INT8 reserved[4]; 265 TW_UINT16 error; 266 TW_UINT8 padding; 267 TW_UINT8 res__severity; /* 5:3 */ 268 } status_block; 269 TW_UINT8 err_specific_desc[98]; 270 struct { 271 TW_UINT8 size_header; 272 TW_UINT16 reserved; 273 TW_UINT8 size_sense; 274 } header_desc; 275 }; 276 277 /* 7000 Command packet. */ 278 union tw_cl_command_7k { 279 struct tw_cl_command_init_connect init_connect; 280 struct tw_cl_command_download_firmware download_fw; 281 struct tw_cl_command_reset_firmware reset_fw; 282 struct tw_cl_command_param param; 283 struct tw_cl_command_generic generic; 284 TW_UINT8 padding[1024 - sizeof(struct tw_cl_command_header)]; 285 }; 286 287 /* 9000 Command Packet. */ 288 struct tw_cl_command_9k { 289 TW_UINT8 res__opcode; /* 3:5 */ 290 TW_UINT8 unit; 291 TW_UINT16 lun_l4__req_id; /* 4:12 */ 292 TW_UINT8 status; 293 TW_UINT8 sgl_offset; /* offset (in bytes) to sg_list, from the 294 end of sgl_entries */ 295 TW_UINT16 lun_h4__sgl_entries; 296 TW_UINT8 cdb[16]; 297 TW_UINT8 sg_list[872];/* total struct size = 298 1024-sizeof(cmd_hdr) */ 299 }; 300 301 /* Full command packet. */ 302 struct tw_cl_command_packet { 303 struct tw_cl_command_header cmd_hdr; 304 union { 305 union tw_cl_command_7k cmd_pkt_7k; 306 struct tw_cl_command_9k cmd_pkt_9k; 307 } command; 308 }; 309 310 /* Structure describing payload for get/set param commands. */ 311 struct tw_cl_param_9k { 312 TW_UINT16 table_id; 313 TW_UINT8 parameter_id; 314 TW_UINT8 reserved; 315 TW_UINT16 parameter_size_bytes; 316 TW_UINT16 parameter_actual_size_bytes; 317 TW_UINT8 data[1]; 318 }; 319 #pragma pack() 320 321 /* Functions to read from, and write to registers */ 322 #define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value) \ 323 tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4) 324 325 #define TW_CLI_READ_STATUS_REGISTER(ctlr_handle) \ 326 tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4) 327 328 #define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \ 329 if (ctlr->flags & TW_CL_64BIT_ADDRESSES) { \ 330 /* First write the low 4 bytes, then the high 4. */ \ 331 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 332 (TW_UINT32)(value), 4); \ 333 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 334 (TW_UINT32)(((TW_UINT64)value)>>32), 4); \ 335 } else \ 336 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \ 337 (TW_UINT32)(value), 4); \ 338 } while (0) 339 340 #define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle) \ 341 tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4) 342 343 #define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle) \ 344 tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4) 345 346 #define TW_CLI_SOFT_RESET(ctlr) \ 347 TW_CLI_WRITE_CONTROL_REGISTER(ctlr, \ 348 TWA_CONTROL_ISSUE_SOFT_RESET | \ 349 TWA_CONTROL_CLEAR_HOST_INTERRUPT | \ 350 TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 351 TWA_CONTROL_MASK_COMMAND_INTERRUPT | \ 352 TWA_CONTROL_MASK_RESPONSE_INTERRUPT | \ 353 TWA_CONTROL_DISABLE_INTERRUPTS) 354 355 /* Detect inconsistencies in the status register. */ 356 #define TW_CLI_STATUS_ERRORS(x) \ 357 ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 358 (x & TWA_STATUS_MICROCONTROLLER_READY)) 359 360 /* 361 * Functions for making transparent, the bit fields in firmware 362 * interface structures. 363 */ 364 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \ 365 ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 366 367 #define BUILD_RES__OPCODE(res, opcode) \ 368 ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 369 370 #define BUILD_HOST_ID__UNIT(host_id, unit) \ 371 ((host_id << 4) & 0xF0) | (unit & 0xF) /* 4:4 */ 372 373 #define BUILD_RES__SEVERITY(res, severity) \ 374 ((res << 3) & 0xF8) | (severity & 0x7) /* 5:3 */ 375 376 #define BUILD_LUN_L4__REQ_ID(lun, req_id) \ 377 (((lun << 12) & 0xF000) | (req_id & 0xFFF)) /* 4:12 */ 378 379 #define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries) \ 380 (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */ 381 382 #define GET_OPCODE(sgl_off__opcode) \ 383 (sgl_off__opcode & 0x1F) /* 3:5 */ 384 385 #define GET_SGL_OFF(sgl_off__opcode) \ 386 ((sgl_off__opcode >> 5) & 0x7) /* 3:5 */ 387 388 #define GET_UNIT(host_id__unit) \ 389 (host_id__unit & 0xF) /* 4:4 */ 390 391 #define GET_HOST_ID(host_id__unit) \ 392 ((host_id__unit >> 4) & 0xF) /* 4:4 */ 393 394 #define GET_SEVERITY(res__severity) \ 395 (res__severity & 0x7) /* 5:3 */ 396 397 #define GET_RESP_ID(undef2__resp_id__undef1) \ 398 ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */ 399 400 #define GET_RESP_ID_9K_X(undef2__resp_id) \ 401 ((undef2__resp_id) & 0xFFF) /* 20:12 */ 402 403 #define GET_LARGE_RESP_ID(misc__large_resp_id) \ 404 ((misc__large_resp_id) & 0xFFFF) /* 16:16 */ 405 406 #define GET_REQ_ID(lun_l4__req_id) \ 407 (lun_l4__req_id & 0xFFF) /* 4:12 */ 408 409 #define GET_LUN_L4(lun_l4__req_id) \ 410 ((lun_l4__req_id >> 12) & 0xF) /* 4:12 */ 411 412 #define GET_SGL_ENTRIES(lun_h4__sgl_entries) \ 413 (lun_h4__sgl_entries & 0xFFF) /* 4:12 */ 414 415 #define GET_LUN_H4(lun_h4__sgl_entries) \ 416 ((lun_h4__sgl_entries >> 12) & 0xF) /* 4:12 */ 417 418 #endif /* TW_CL_FWIF_H */
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