The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_cl_fwif.h

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    1 /*
    2  * Copyright (c) 2004-05 Applied Micro Circuits Corporation.
    3  * Copyright (c) 2004-05 Vinod Kashyap
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  *      $FreeBSD: releng/6.2/sys/dev/twa/tw_cl_fwif.h 153207 2005-12-07 18:18:06Z vkashyap $
   28  */
   29 
   30 /*
   31  * AMCC'S 3ware driver for 9000 series storage controllers.
   32  *
   33  * Author: Vinod Kashyap
   34  */
   35 
   36 
   37 
   38 #ifndef TW_CL_FWIF_H
   39 
   40 #define TW_CL_FWIF_H
   41 
   42 
   43 /*
   44  * Macros and data structures for interfacing with the firmware.
   45  */
   46 
   47 
   48 /* Register offsets from base address. */
   49 #define TWA_CONTROL_REGISTER_OFFSET             0x0
   50 #define TWA_STATUS_REGISTER_OFFSET              0x4
   51 #define TWA_COMMAND_QUEUE_OFFSET                0x8
   52 #define TWA_RESPONSE_QUEUE_OFFSET               0xC
   53 #define TWA_COMMAND_QUEUE_OFFSET_LOW            0x20
   54 #define TWA_COMMAND_QUEUE_OFFSET_HIGH           0x24
   55 #define TWA_LARGE_RESPONSE_QUEUE_OFFSET         0x30
   56 
   57 
   58 /* Control register bit definitions. */
   59 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
   60 #define TWA_CONTROL_DISABLE_INTERRUPTS          0x00000040
   61 #define TWA_CONTROL_ENABLE_INTERRUPTS           0x00000080
   62 #define TWA_CONTROL_ISSUE_SOFT_RESET            0x00000100
   63 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
   64 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
   65 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
   66 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
   67 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
   68 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
   69 #define TWA_CONTROL_CLEAR_PCI_ABORT             0x00100000
   70 #define TWA_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
   71 #define TWA_CONTROL_CLEAR_PARITY_ERROR          0x00800000
   72 
   73 
   74 /* Status register bit definitions. */
   75 #define TWA_STATUS_ROM_BIOS_IN_SBUF             0x00000002
   76 #define TWA_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
   77 #define TWA_STATUS_MICROCONTROLLER_READY        0x00002000
   78 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
   79 #define TWA_STATUS_COMMAND_QUEUE_FULL           0x00008000
   80 #define TWA_STATUS_RESPONSE_INTERRUPT           0x00010000
   81 #define TWA_STATUS_COMMAND_INTERRUPT            0x00020000
   82 #define TWA_STATUS_ATTENTION_INTERRUPT          0x00040000
   83 #define TWA_STATUS_HOST_INTERRUPT               0x00080000
   84 #define TWA_STATUS_PCI_ABORT_INTERRUPT          0x00100000
   85 #define TWA_STATUS_MICROCONTROLLER_ERROR        0x00200000
   86 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT        0x00400000
   87 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT   0x00800000
   88 #define TWA_STATUS_MINOR_VERSION_MASK           0x0F000000
   89 #define TWA_STATUS_MAJOR_VERSION_MASK           0xF0000000
   90 
   91 #define TWA_STATUS_EXPECTED_BITS                0x00002000
   92 #define TWA_STATUS_UNEXPECTED_BITS              0x00F00000
   93 
   94 
   95 /* PCI related defines. */
   96 #define TWA_IO_CONFIG_REG                       0x10
   97 
   98 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR       0xc100
   99 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT          0x2000
  100 
  101 #define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE  0xFFFF
  102 #define TWA_RESET_PHASE1_WAIT_TIME_MS           500
  103 
  104 
  105 /* Command packet opcodes. */
  106 #define TWA_FW_CMD_NOP                          0x00
  107 #define TWA_FW_CMD_INIT_CONNECTION              0x01
  108 #define TWA_FW_CMD_READ                         0x02
  109 #define TWA_FW_CMD_WRITE                        0x03
  110 #define TWA_FW_CMD_READVERIFY                   0x04
  111 #define TWA_FW_CMD_VERIFY                       0x05
  112 #define TWA_FW_CMD_ZEROUNIT                     0x08
  113 #define TWA_FW_CMD_REPLACEUNIT                  0x09
  114 #define TWA_FW_CMD_HOTSWAP                      0x0A
  115 #define TWA_FW_CMD_SELFTESTS                    0x0B
  116 #define TWA_FW_CMD_SYNC_PARAM                   0x0C
  117 #define TWA_FW_CMD_REORDER_UNITS                0x0D
  118 
  119 #define TWA_FW_CMD_EXECUTE_SCSI                 0x10
  120 #define TWA_FW_CMD_ATA_PASSTHROUGH              0x11
  121 #define TWA_FW_CMD_GET_PARAM                    0x12
  122 #define TWA_FW_CMD_SET_PARAM                    0x13
  123 #define TWA_FW_CMD_CREATEUNIT                   0x14
  124 #define TWA_FW_CMD_DELETEUNIT                   0x15
  125 #define TWA_FW_CMD_DOWNLOAD_FIRMWARE            0x16
  126 #define TWA_FW_CMD_REBUILDUNIT                  0x17
  127 #define TWA_FW_CMD_POWER_MANAGEMENT             0x18
  128 
  129 #define TWA_FW_CMD_REMOTE_PRINT                 0x1B
  130 #define TWA_FW_CMD_HARD_RESET_FIRMWARE          0x1C
  131 #define TWA_FW_CMD_DEBUG                        0x1D
  132 
  133 #define TWA_FW_CMD_DIAGNOSTICS                  0x1F
  134 
  135 
  136 /* Misc defines. */
  137 #define TWA_BUNDLED_FW_VERSION_STRING   "3.02.00.004"
  138 #define TWA_SHUTDOWN_MESSAGE_CREDITS    0x001
  139 #define TWA_64BIT_SG_ADDRESSES          0x00000001
  140 #define TWA_EXTENDED_INIT_CONNECT       0x00000002
  141 #define TWA_BASE_MODE                   1
  142 #define TWA_BASE_FW_SRL                 24
  143 #define TWA_BASE_FW_BRANCH              0
  144 #define TWA_BASE_FW_BUILD               1
  145 #define TWA_CURRENT_FW_SRL              30
  146 #define TWA_CURRENT_FW_BRANCH_9K        4
  147 #define TWA_CURRENT_FW_BUILD_9K         8
  148 #define TWA_CURRENT_FW_BRANCH_9K_X      8
  149 #define TWA_CURRENT_FW_BUILD_9K_X       4
  150 #define TWA_MULTI_LUN_FW_SRL            28
  151 #define TWA_ARCH_ID_9K                  0x5     /* 9000 PCI controllers */
  152 #define TWA_ARCH_ID_9K_X                0x6     /* 9000 PCI-X controllers */
  153 #define TWA_CTLR_FW_SAME_OR_NEWER       0x00000001
  154 #define TWA_CTLR_FW_COMPATIBLE          0x00000002
  155 #define TWA_BUNDLED_FW_SAFE_TO_FLASH    0x00000004
  156 #define TWA_CTLR_FW_RECOMMENDS_FLASH    0x00000008
  157 #define TWA_SENSE_DATA_LENGTH           18
  158 
  159 
  160 #define TWA_ARCH_ID(device_id)                                          \
  161         (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K :         \
  162         TWA_ARCH_ID_9K_X)
  163 #define TWA_CURRENT_FW_BRANCH(arch_id)                                  \
  164         (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K :     \
  165         TWA_CURRENT_FW_BRANCH_9K_X)
  166 #define TWA_CURRENT_FW_BUILD(arch_id)                                   \
  167         (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K :      \
  168         TWA_CURRENT_FW_BUILD_9K_X)
  169 
  170 /*
  171  * All SG addresses and DMA'able memory allocated by the OSL should be
  172  * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of
  173  * TWA_SG_ELEMENT_SIZE_FACTOR.
  174  */
  175 #define TWA_ALIGNMENT(device_id)                        0x4
  176 #define TWA_SG_ELEMENT_SIZE_FACTOR(device_id)           \
  177         (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4)
  178 
  179 
  180 /*
  181  * Some errors of interest (in cmd_hdr->status_block.error) when a command
  182  * is completed by the firmware with a bad status.
  183  */
  184 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED    0x010a
  185 #define TWA_ERROR_UNIT_OFFLINE                  0x0128
  186 #define TWA_ERROR_MORE_DATA                     0x0231
  187 
  188 
  189 /* AEN codes of interest. */
  190 #define TWA_AEN_QUEUE_EMPTY             0x00
  191 #define TWA_AEN_SOFT_RESET              0x01
  192 #define TWA_AEN_SYNC_TIME_WITH_HOST     0x31
  193 
  194 
  195 /* Table #'s and id's of parameters of interest in firmware's param table. */
  196 #define TWA_PARAM_VERSION_TABLE         0x0402
  197 #define TWA_PARAM_VERSION_FW            3       /* firmware version [16] */
  198 #define TWA_PARAM_VERSION_BIOS          4       /* BIOSs version [16] */
  199 #define TWA_PARAM_CTLR_MODEL            8       /* Controller model [16] */
  200 
  201 #define TWA_PARAM_CONTROLLER_TABLE      0x0403
  202 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3       /* number of ports [1] */
  203 
  204 #define TWA_PARAM_TIME_TABLE            0x40A
  205 #define TWA_PARAM_TIME_SCHED_TIME       0x3
  206 
  207 #define TWA_9K_PARAM_DESCRIPTOR         0x8000
  208 
  209 
  210 #pragma pack(1)
  211 /* 7000 structures. */
  212 struct tw_cl_command_init_connect {
  213         TW_UINT8        res1__opcode;   /* 3:5 */
  214         TW_UINT8        size;
  215         TW_UINT8        request_id;
  216         TW_UINT8        res2;
  217         TW_UINT8        status;
  218         TW_UINT8        flags;
  219         TW_UINT16       message_credits;
  220         TW_UINT32       features;
  221         TW_UINT16       fw_srl;
  222         TW_UINT16       fw_arch_id;
  223         TW_UINT16       fw_branch;
  224         TW_UINT16       fw_build;
  225         TW_UINT32       result;
  226 };
  227 
  228 
  229 /* Structure for downloading firmware onto the controller. */
  230 struct tw_cl_command_download_firmware {
  231         TW_UINT8        sgl_off__opcode;/* 3:5 */
  232         TW_UINT8        size;
  233         TW_UINT8        request_id;
  234         TW_UINT8        unit;
  235         TW_UINT8        status;
  236         TW_UINT8        flags;
  237         TW_UINT16       param;
  238         TW_UINT8        sgl[1];
  239 };
  240 
  241 
  242 /* Structure for hard resetting the controller. */
  243 struct tw_cl_command_reset_firmware {
  244         TW_UINT8        res1__opcode;   /* 3:5 */
  245         TW_UINT8        size;
  246         TW_UINT8        request_id;
  247         TW_UINT8        unit;
  248         TW_UINT8        status;
  249         TW_UINT8        flags;
  250         TW_UINT8        res2;
  251         TW_UINT8        param;
  252 };
  253 
  254 
  255 /* Structure for sending get/set param commands. */
  256 struct tw_cl_command_param {
  257         TW_UINT8        sgl_off__opcode;/* 3:5 */
  258         TW_UINT8        size;
  259         TW_UINT8        request_id;
  260         TW_UINT8        host_id__unit;  /* 4:4 */
  261         TW_UINT8        status;
  262         TW_UINT8        flags;
  263         TW_UINT16       param_count;
  264         TW_UINT8        sgl[1];
  265 };
  266 
  267 
  268 /* Generic command packet. */
  269 struct tw_cl_command_generic {
  270         TW_UINT8        sgl_off__opcode;/* 3:5 */
  271         TW_UINT8        size;
  272         TW_UINT8        request_id;
  273         TW_UINT8        host_id__unit;  /* 4:4 */
  274         TW_UINT8        status;
  275         TW_UINT8        flags;
  276         TW_UINT16       count;  /* block cnt, parameter cnt, message credits */
  277 };
  278 
  279 
  280 /* Command packet header. */
  281 struct tw_cl_command_header {
  282         TW_UINT8        sense_data[TWA_SENSE_DATA_LENGTH];
  283         struct {
  284                 TW_INT8         reserved[4];
  285                 TW_UINT16       error;
  286                 TW_UINT8        padding;
  287                 TW_UINT8        res__severity;  /* 5:3 */
  288         } status_block;
  289         TW_UINT8        err_specific_desc[98];
  290         struct {
  291                 TW_UINT8        size_header;
  292                 TW_UINT16       reserved;
  293                 TW_UINT8        size_sense;
  294         } header_desc;
  295 };
  296 
  297 
  298 /* 7000 Command packet. */
  299 union tw_cl_command_7k {
  300         struct tw_cl_command_init_connect       init_connect;
  301         struct tw_cl_command_download_firmware  download_fw;
  302         struct tw_cl_command_reset_firmware     reset_fw;
  303         struct tw_cl_command_param              param;
  304         struct tw_cl_command_generic            generic;
  305         TW_UINT8        padding[1024 - sizeof(struct tw_cl_command_header)];
  306 };
  307 
  308 
  309 /* 9000 Command Packet. */
  310 struct tw_cl_command_9k {
  311         TW_UINT8        res__opcode;    /* 3:5 */
  312         TW_UINT8        unit;
  313         TW_UINT16       lun_l4__req_id; /* 4:12 */
  314         TW_UINT8        status;
  315         TW_UINT8        sgl_offset; /* offset (in bytes) to sg_list, from the
  316                                         end of sgl_entries */
  317         TW_UINT16       lun_h4__sgl_entries;
  318         TW_UINT8        cdb[16];
  319         TW_UINT8        sg_list[872];/* total struct size =
  320                                         1024-sizeof(cmd_hdr) */
  321 };
  322 
  323 
  324 /* Full command packet. */
  325 struct tw_cl_command_packet {
  326         struct tw_cl_command_header     cmd_hdr;
  327         union {
  328                 union tw_cl_command_7k  cmd_pkt_7k;
  329                 struct tw_cl_command_9k cmd_pkt_9k;
  330         } command;
  331 };
  332 
  333 
  334 /* Structure describing payload for get/set param commands. */
  335 struct tw_cl_param_9k {
  336         TW_UINT16       table_id;
  337         TW_UINT8        parameter_id;
  338         TW_UINT8        reserved;
  339         TW_UINT16       parameter_size_bytes;
  340         TW_UINT16       parameter_actual_size_bytes;
  341         TW_UINT8        data[1];
  342 };
  343 #pragma pack()
  344 
  345 
  346 /* Functions to read from, and write to registers */
  347 #define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value)               \
  348         tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4)
  349 
  350 
  351 #define TW_CLI_READ_STATUS_REGISTER(ctlr_handle)                        \
  352         tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4)
  353 
  354 
  355 #define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value)  do {            \
  356         if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {                      \
  357                 /* First write the low 4 bytes, then the high 4. */     \
  358                 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \
  359                         (TW_UINT32)(value), 4);                         \
  360                 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
  361                         (TW_UINT32)(((TW_UINT64)value)>>32), 4);        \
  362         } else                                                          \
  363                 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \
  364                                         (TW_UINT32)(value), 4);         \
  365 } while (0)
  366 
  367 
  368 #define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle)                         \
  369         tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4)
  370 
  371 
  372 #define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle)                   \
  373         tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4)
  374 
  375 
  376 #define TW_CLI_SOFT_RESET(ctlr)                                 \
  377         TW_CLI_WRITE_CONTROL_REGISTER(ctlr,                     \
  378                 TWA_CONTROL_ISSUE_SOFT_RESET |                  \
  379                 TWA_CONTROL_CLEAR_HOST_INTERRUPT |              \
  380                 TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT |         \
  381                 TWA_CONTROL_MASK_COMMAND_INTERRUPT |            \
  382                 TWA_CONTROL_MASK_RESPONSE_INTERRUPT |           \
  383                 TWA_CONTROL_DISABLE_INTERRUPTS)
  384 
  385 /* Detect inconsistencies in the status register. */
  386 #define TW_CLI_STATUS_ERRORS(x)                                 \
  387         ((x & TWA_STATUS_UNEXPECTED_BITS) &&                    \
  388          (x & TWA_STATUS_MICROCONTROLLER_READY))
  389 
  390 
  391 /*
  392  * Functions for making transparent, the bit fields in firmware
  393  * interface structures.
  394  */
  395 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode)  \
  396         ((sgl_off << 5) & 0xE0) | (opcode & 0x1F)       /* 3:5 */
  397 
  398 #define BUILD_RES__OPCODE(res, opcode)          \
  399         ((res << 5) & 0xE0) | (opcode & 0x1F)           /* 3:5 */
  400 
  401 #define BUILD_HOST_ID__UNIT(host_id, unit)      \
  402         ((host_id << 4) & 0xF0) | (unit & 0xF)          /* 4:4 */
  403 
  404 #define BUILD_RES__SEVERITY(res, severity)      \
  405         ((res << 3) & 0xF8) | (severity & 0x7)          /* 5:3 */
  406 
  407 #define BUILD_LUN_L4__REQ_ID(lun, req_id)       \
  408         (((lun << 12) & 0xF000) | (req_id & 0xFFF))     /* 4:12 */
  409 
  410 #define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries)     \
  411         (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */
  412 
  413 
  414 #define GET_OPCODE(sgl_off__opcode)     \
  415         (sgl_off__opcode & 0x1F)                /* 3:5 */
  416 
  417 #define GET_SGL_OFF(sgl_off__opcode)    \
  418         ((sgl_off__opcode >> 5) & 0x7)          /* 3:5 */
  419 
  420 #define GET_UNIT(host_id__unit)         \
  421         (host_id__unit & 0xF)                   /* 4:4 */
  422 
  423 #define GET_HOST_ID(host_id__unit)      \
  424         ((host_id__unit >> 4) & 0xF)            /* 4:4 */
  425 
  426 #define GET_SEVERITY(res__severity)     \
  427         (res__severity & 0x7)                   /* 5:3 */
  428 
  429 #define GET_RESP_ID(undef2__resp_id__undef1)    \
  430         ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */
  431 
  432 #define GET_RESP_ID_9K_X(undef2__resp_id)       \
  433         ((undef2__resp_id) & 0xFFF)             /* 20:12 */
  434 
  435 #define GET_LARGE_RESP_ID(misc__large_resp_id)  \
  436         ((misc__large_resp_id) & 0xFFFF)        /* 16:16 */
  437 
  438 #define GET_REQ_ID(lun_l4__req_id)      \
  439         (lun_l4__req_id & 0xFFF)                /* 4:12 */
  440 
  441 #define GET_LUN_L4(lun_l4__req_id)      \
  442         ((lun_l4__req_id >> 12) & 0xF)          /* 4:12 */
  443 
  444 #define GET_SGL_ENTRIES(lun_h4__sgl_entries)    \
  445         (lun_h4__sgl_entries & 0xFFF)           /* 4:12 */
  446 
  447 #define GET_LUN_H4(lun_h4__sgl_entries) \
  448         ((lun_h4__sgl_entries >> 12) & 0xF)     /* 4:12 */
  449 
  450 
  451 
  452 #endif /* TW_CL_FWIF_H */

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