The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_cl_fwif.h

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    1 /*
    2  * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
    3  * Copyright (c) 2004-05 Vinod Kashyap
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  *      $FreeBSD$
   28  */
   29 
   30 /*
   31  * AMCC'S 3ware driver for 9000 series storage controllers.
   32  *
   33  * Author: Vinod Kashyap
   34  * Modifications by: Adam Radford
   35  */
   36 
   37 
   38 
   39 #ifndef TW_CL_FWIF_H
   40 
   41 #define TW_CL_FWIF_H
   42 
   43 
   44 /*
   45  * Macros and data structures for interfacing with the firmware.
   46  */
   47 
   48 
   49 /* Register offsets from base address. */
   50 #define TWA_CONTROL_REGISTER_OFFSET             0x0
   51 #define TWA_STATUS_REGISTER_OFFSET              0x4
   52 #define TWA_COMMAND_QUEUE_OFFSET                0x8
   53 #define TWA_RESPONSE_QUEUE_OFFSET               0xC
   54 #define TWA_COMMAND_QUEUE_OFFSET_LOW            0x20
   55 #define TWA_COMMAND_QUEUE_OFFSET_HIGH           0x24
   56 #define TWA_LARGE_RESPONSE_QUEUE_OFFSET         0x30
   57 
   58 
   59 /* Control register bit definitions. */
   60 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
   61 #define TWA_CONTROL_DISABLE_INTERRUPTS          0x00000040
   62 #define TWA_CONTROL_ENABLE_INTERRUPTS           0x00000080
   63 #define TWA_CONTROL_ISSUE_SOFT_RESET            0x00000100
   64 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
   65 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
   66 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
   67 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
   68 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
   69 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
   70 #define TWA_CONTROL_CLEAR_PCI_ABORT             0x00100000
   71 #define TWA_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
   72 #define TWA_CONTROL_CLEAR_PARITY_ERROR          0x00800000
   73 
   74 
   75 /* Status register bit definitions. */
   76 #define TWA_STATUS_ROM_BIOS_IN_SBUF             0x00000002
   77 #define TWA_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
   78 #define TWA_STATUS_MICROCONTROLLER_READY        0x00002000
   79 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
   80 #define TWA_STATUS_COMMAND_QUEUE_FULL           0x00008000
   81 #define TWA_STATUS_RESPONSE_INTERRUPT           0x00010000
   82 #define TWA_STATUS_COMMAND_INTERRUPT            0x00020000
   83 #define TWA_STATUS_ATTENTION_INTERRUPT          0x00040000
   84 #define TWA_STATUS_HOST_INTERRUPT               0x00080000
   85 #define TWA_STATUS_PCI_ABORT_INTERRUPT          0x00100000
   86 #define TWA_STATUS_MICROCONTROLLER_ERROR        0x00200000
   87 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT        0x00400000
   88 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT   0x00800000
   89 #define TWA_STATUS_MINOR_VERSION_MASK           0x0F000000
   90 #define TWA_STATUS_MAJOR_VERSION_MASK           0xF0000000
   91 
   92 #define TWA_STATUS_EXPECTED_BITS                0x00002000
   93 #define TWA_STATUS_UNEXPECTED_BITS              0x00F00000
   94 
   95 
   96 /* PCI related defines. */
   97 #define TWA_IO_CONFIG_REG                       0x10
   98 
   99 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR       0xc100
  100 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT          0x2000
  101 
  102 #define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE  0xFFFF
  103 #define TWA_RESET_PHASE1_WAIT_TIME_MS           500
  104 
  105 
  106 /* Command packet opcodes. */
  107 #define TWA_FW_CMD_NOP                          0x00
  108 #define TWA_FW_CMD_INIT_CONNECTION              0x01
  109 #define TWA_FW_CMD_READ                         0x02
  110 #define TWA_FW_CMD_WRITE                        0x03
  111 #define TWA_FW_CMD_READVERIFY                   0x04
  112 #define TWA_FW_CMD_VERIFY                       0x05
  113 #define TWA_FW_CMD_ZEROUNIT                     0x08
  114 #define TWA_FW_CMD_REPLACEUNIT                  0x09
  115 #define TWA_FW_CMD_HOTSWAP                      0x0A
  116 #define TWA_FW_CMD_SELFTESTS                    0x0B
  117 #define TWA_FW_CMD_SYNC_PARAM                   0x0C
  118 #define TWA_FW_CMD_REORDER_UNITS                0x0D
  119 
  120 #define TWA_FW_CMD_EXECUTE_SCSI                 0x10
  121 #define TWA_FW_CMD_ATA_PASSTHROUGH              0x11
  122 #define TWA_FW_CMD_GET_PARAM                    0x12
  123 #define TWA_FW_CMD_SET_PARAM                    0x13
  124 #define TWA_FW_CMD_CREATEUNIT                   0x14
  125 #define TWA_FW_CMD_DELETEUNIT                   0x15
  126 #define TWA_FW_CMD_DOWNLOAD_FIRMWARE            0x16
  127 #define TWA_FW_CMD_REBUILDUNIT                  0x17
  128 #define TWA_FW_CMD_POWER_MANAGEMENT             0x18
  129 
  130 #define TWA_FW_CMD_REMOTE_PRINT                 0x1B
  131 #define TWA_FW_CMD_HARD_RESET_FIRMWARE          0x1C
  132 #define TWA_FW_CMD_DEBUG                        0x1D
  133 
  134 #define TWA_FW_CMD_DIAGNOSTICS                  0x1F
  135 
  136 
  137 /* Misc defines. */
  138 #define TWA_SHUTDOWN_MESSAGE_CREDITS    0x001
  139 #define TWA_64BIT_SG_ADDRESSES          0x00000001
  140 #define TWA_EXTENDED_INIT_CONNECT       0x00000002
  141 #define TWA_BASE_MODE                   1
  142 #define TWA_BASE_FW_SRL                 24
  143 #define TWA_BASE_FW_BRANCH              0
  144 #define TWA_BASE_FW_BUILD               1
  145 #define TWA_CURRENT_FW_SRL              30
  146 #define TWA_CURRENT_FW_BRANCH_9K        4
  147 #define TWA_CURRENT_FW_BUILD_9K         8
  148 #define TWA_CURRENT_FW_BRANCH_9K_X      8
  149 #define TWA_CURRENT_FW_BUILD_9K_X       4
  150 #define TWA_MULTI_LUN_FW_SRL            28
  151 #define TWA_ARCH_ID_9K                  0x5     /* 9000 PCI controllers */
  152 #define TWA_ARCH_ID_9K_X                0x6     /* 9000 PCI-X controllers */
  153 #define TWA_CTLR_FW_SAME_OR_NEWER       0x00000001
  154 #define TWA_CTLR_FW_COMPATIBLE          0x00000002
  155 #define TWA_SENSE_DATA_LENGTH           18
  156 
  157 
  158 #define TWA_ARCH_ID(device_id)                                          \
  159         (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K :         \
  160         TWA_ARCH_ID_9K_X)
  161 #define TWA_CURRENT_FW_BRANCH(arch_id)                                  \
  162         (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K :     \
  163         TWA_CURRENT_FW_BRANCH_9K_X)
  164 #define TWA_CURRENT_FW_BUILD(arch_id)                                   \
  165         (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K :      \
  166         TWA_CURRENT_FW_BUILD_9K_X)
  167 
  168 /*
  169  * All SG addresses and DMA'able memory allocated by the OSL should be
  170  * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of
  171  * TWA_SG_ELEMENT_SIZE_FACTOR.
  172  */
  173 #define TWA_ALIGNMENT(device_id)                        0x4
  174 #define TWA_SG_ELEMENT_SIZE_FACTOR(device_id)           \
  175         (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4)
  176 
  177 
  178 /*
  179  * Some errors of interest (in cmd_hdr->status_block.error) when a command
  180  * is completed by the firmware with a bad status.
  181  */
  182 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED    0x010a
  183 #define TWA_ERROR_UNIT_OFFLINE                  0x0128
  184 #define TWA_ERROR_MORE_DATA                     0x0231
  185 
  186 
  187 /* AEN codes of interest. */
  188 #define TWA_AEN_QUEUE_EMPTY             0x00
  189 #define TWA_AEN_SOFT_RESET              0x01
  190 #define TWA_AEN_SYNC_TIME_WITH_HOST     0x31
  191 
  192 
  193 /* Table #'s and id's of parameters of interest in firmware's param table. */
  194 #define TWA_PARAM_VERSION_TABLE         0x0402
  195 #define TWA_PARAM_VERSION_FW            3       /* firmware version [16] */
  196 #define TWA_PARAM_VERSION_BIOS          4       /* BIOSs version [16] */
  197 #define TWA_PARAM_CTLR_MODEL            8       /* Controller model [16] */
  198 
  199 #define TWA_PARAM_CONTROLLER_TABLE      0x0403
  200 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3       /* number of ports [1] */
  201 
  202 #define TWA_PARAM_TIME_TABLE            0x40A
  203 #define TWA_PARAM_TIME_SCHED_TIME       0x3
  204 
  205 #define TWA_9K_PARAM_DESCRIPTOR         0x8000
  206 
  207 
  208 #pragma pack(1)
  209 /* 7000 structures. */
  210 struct tw_cl_command_init_connect {
  211         TW_UINT8        res1__opcode;   /* 3:5 */
  212         TW_UINT8        size;
  213         TW_UINT8        request_id;
  214         TW_UINT8        res2;
  215         TW_UINT8        status;
  216         TW_UINT8        flags;
  217         TW_UINT16       message_credits;
  218         TW_UINT32       features;
  219         TW_UINT16       fw_srl;
  220         TW_UINT16       fw_arch_id;
  221         TW_UINT16       fw_branch;
  222         TW_UINT16       fw_build;
  223         TW_UINT32       result;
  224 };
  225 
  226 
  227 /* Structure for downloading firmware onto the controller. */
  228 struct tw_cl_command_download_firmware {
  229         TW_UINT8        sgl_off__opcode;/* 3:5 */
  230         TW_UINT8        size;
  231         TW_UINT8        request_id;
  232         TW_UINT8        unit;
  233         TW_UINT8        status;
  234         TW_UINT8        flags;
  235         TW_UINT16       param;
  236         TW_UINT8        sgl[1];
  237 };
  238 
  239 
  240 /* Structure for hard resetting the controller. */
  241 struct tw_cl_command_reset_firmware {
  242         TW_UINT8        res1__opcode;   /* 3:5 */
  243         TW_UINT8        size;
  244         TW_UINT8        request_id;
  245         TW_UINT8        unit;
  246         TW_UINT8        status;
  247         TW_UINT8        flags;
  248         TW_UINT8        res2;
  249         TW_UINT8        param;
  250 };
  251 
  252 
  253 /* Structure for sending get/set param commands. */
  254 struct tw_cl_command_param {
  255         TW_UINT8        sgl_off__opcode;/* 3:5 */
  256         TW_UINT8        size;
  257         TW_UINT8        request_id;
  258         TW_UINT8        host_id__unit;  /* 4:4 */
  259         TW_UINT8        status;
  260         TW_UINT8        flags;
  261         TW_UINT16       param_count;
  262         TW_UINT8        sgl[1];
  263 };
  264 
  265 
  266 /* Generic command packet. */
  267 struct tw_cl_command_generic {
  268         TW_UINT8        sgl_off__opcode;/* 3:5 */
  269         TW_UINT8        size;
  270         TW_UINT8        request_id;
  271         TW_UINT8        host_id__unit;  /* 4:4 */
  272         TW_UINT8        status;
  273         TW_UINT8        flags;
  274         TW_UINT16       count;  /* block cnt, parameter cnt, message credits */
  275 };
  276 
  277 
  278 /* Command packet header. */
  279 struct tw_cl_command_header {
  280         TW_UINT8        sense_data[TWA_SENSE_DATA_LENGTH];
  281         struct {
  282                 TW_INT8         reserved[4];
  283                 TW_UINT16       error;
  284                 TW_UINT8        padding;
  285                 TW_UINT8        res__severity;  /* 5:3 */
  286         } status_block;
  287         TW_UINT8        err_specific_desc[98];
  288         struct {
  289                 TW_UINT8        size_header;
  290                 TW_UINT16       reserved;
  291                 TW_UINT8        size_sense;
  292         } header_desc;
  293 };
  294 
  295 
  296 /* 7000 Command packet. */
  297 union tw_cl_command_7k {
  298         struct tw_cl_command_init_connect       init_connect;
  299         struct tw_cl_command_download_firmware  download_fw;
  300         struct tw_cl_command_reset_firmware     reset_fw;
  301         struct tw_cl_command_param              param;
  302         struct tw_cl_command_generic            generic;
  303         TW_UINT8        padding[1024 - sizeof(struct tw_cl_command_header)];
  304 };
  305 
  306 
  307 /* 9000 Command Packet. */
  308 struct tw_cl_command_9k {
  309         TW_UINT8        res__opcode;    /* 3:5 */
  310         TW_UINT8        unit;
  311         TW_UINT16       lun_l4__req_id; /* 4:12 */
  312         TW_UINT8        status;
  313         TW_UINT8        sgl_offset; /* offset (in bytes) to sg_list, from the
  314                                         end of sgl_entries */
  315         TW_UINT16       lun_h4__sgl_entries;
  316         TW_UINT8        cdb[16];
  317         TW_UINT8        sg_list[872];/* total struct size =
  318                                         1024-sizeof(cmd_hdr) */
  319 };
  320 
  321 
  322 /* Full command packet. */
  323 struct tw_cl_command_packet {
  324         struct tw_cl_command_header     cmd_hdr;
  325         union {
  326                 union tw_cl_command_7k  cmd_pkt_7k;
  327                 struct tw_cl_command_9k cmd_pkt_9k;
  328         } command;
  329 };
  330 
  331 
  332 /* Structure describing payload for get/set param commands. */
  333 struct tw_cl_param_9k {
  334         TW_UINT16       table_id;
  335         TW_UINT8        parameter_id;
  336         TW_UINT8        reserved;
  337         TW_UINT16       parameter_size_bytes;
  338         TW_UINT16       parameter_actual_size_bytes;
  339         TW_UINT8        data[1];
  340 };
  341 #pragma pack()
  342 
  343 
  344 /* Functions to read from, and write to registers */
  345 #define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value)               \
  346         tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4)
  347 
  348 
  349 #define TW_CLI_READ_STATUS_REGISTER(ctlr_handle)                        \
  350         tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4)
  351 
  352 
  353 #define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value)  do {            \
  354         if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {                      \
  355                 /* First write the low 4 bytes, then the high 4. */     \
  356                 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \
  357                         (TW_UINT32)(value), 4);                         \
  358                 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
  359                         (TW_UINT32)(((TW_UINT64)value)>>32), 4);        \
  360         } else                                                          \
  361                 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \
  362                                         (TW_UINT32)(value), 4);         \
  363 } while (0)
  364 
  365 
  366 #define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle)                         \
  367         tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4)
  368 
  369 
  370 #define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle)                   \
  371         tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4)
  372 
  373 
  374 #define TW_CLI_SOFT_RESET(ctlr)                                 \
  375         TW_CLI_WRITE_CONTROL_REGISTER(ctlr,                     \
  376                 TWA_CONTROL_ISSUE_SOFT_RESET |                  \
  377                 TWA_CONTROL_CLEAR_HOST_INTERRUPT |              \
  378                 TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT |         \
  379                 TWA_CONTROL_MASK_COMMAND_INTERRUPT |            \
  380                 TWA_CONTROL_MASK_RESPONSE_INTERRUPT |           \
  381                 TWA_CONTROL_DISABLE_INTERRUPTS)
  382 
  383 /* Detect inconsistencies in the status register. */
  384 #define TW_CLI_STATUS_ERRORS(x)                                 \
  385         ((x & TWA_STATUS_UNEXPECTED_BITS) &&                    \
  386          (x & TWA_STATUS_MICROCONTROLLER_READY))
  387 
  388 
  389 /*
  390  * Functions for making transparent, the bit fields in firmware
  391  * interface structures.
  392  */
  393 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode)  \
  394         ((sgl_off << 5) & 0xE0) | (opcode & 0x1F)       /* 3:5 */
  395 
  396 #define BUILD_RES__OPCODE(res, opcode)          \
  397         ((res << 5) & 0xE0) | (opcode & 0x1F)           /* 3:5 */
  398 
  399 #define BUILD_HOST_ID__UNIT(host_id, unit)      \
  400         ((host_id << 4) & 0xF0) | (unit & 0xF)          /* 4:4 */
  401 
  402 #define BUILD_RES__SEVERITY(res, severity)      \
  403         ((res << 3) & 0xF8) | (severity & 0x7)          /* 5:3 */
  404 
  405 #define BUILD_LUN_L4__REQ_ID(lun, req_id)       \
  406         (((lun << 12) & 0xF000) | (req_id & 0xFFF))     /* 4:12 */
  407 
  408 #define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries)     \
  409         (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */
  410 
  411 
  412 #define GET_OPCODE(sgl_off__opcode)     \
  413         (sgl_off__opcode & 0x1F)                /* 3:5 */
  414 
  415 #define GET_SGL_OFF(sgl_off__opcode)    \
  416         ((sgl_off__opcode >> 5) & 0x7)          /* 3:5 */
  417 
  418 #define GET_UNIT(host_id__unit)         \
  419         (host_id__unit & 0xF)                   /* 4:4 */
  420 
  421 #define GET_HOST_ID(host_id__unit)      \
  422         ((host_id__unit >> 4) & 0xF)            /* 4:4 */
  423 
  424 #define GET_SEVERITY(res__severity)     \
  425         (res__severity & 0x7)                   /* 5:3 */
  426 
  427 #define GET_RESP_ID(undef2__resp_id__undef1)    \
  428         ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */
  429 
  430 #define GET_RESP_ID_9K_X(undef2__resp_id)       \
  431         ((undef2__resp_id) & 0xFFF)             /* 20:12 */
  432 
  433 #define GET_LARGE_RESP_ID(misc__large_resp_id)  \
  434         ((misc__large_resp_id) & 0xFFFF)        /* 16:16 */
  435 
  436 #define GET_REQ_ID(lun_l4__req_id)      \
  437         (lun_l4__req_id & 0xFFF)                /* 4:12 */
  438 
  439 #define GET_LUN_L4(lun_l4__req_id)      \
  440         ((lun_l4__req_id >> 12) & 0xF)          /* 4:12 */
  441 
  442 #define GET_SGL_ENTRIES(lun_h4__sgl_entries)    \
  443         (lun_h4__sgl_entries & 0xFFF)           /* 4:12 */
  444 
  445 #define GET_LUN_H4(lun_h4__sgl_entries) \
  446         ((lun_h4__sgl_entries >> 12) & 0xF)     /* 4:12 */
  447 
  448 
  449 
  450 #endif /* TW_CL_FWIF_H */

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