The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_cl_share.h

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    1 /*
    2  * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
    3  * Copyright (c) 2004-05 Vinod Kashyap
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  *      $FreeBSD: releng/11.0/sys/dev/twa/tw_cl_share.h 212008 2010-08-30 19:15:04Z delphij $
   28  */
   29 
   30 /*
   31  * AMCC'S 3ware driver for 9000 series storage controllers.
   32  *
   33  * Author: Vinod Kashyap
   34  * Modifications by: Adam Radford
   35  * Modifications by: Manjunath Ranganathaiah
   36  */
   37 
   38 
   39 
   40 #ifndef TW_CL_SHARE_H
   41 
   42 #define TW_CL_SHARE_H
   43 
   44 
   45 /*
   46  * Macros, structures and functions shared between OSL and CL,
   47  * and defined by CL.
   48  */
   49 
   50 #define TW_CL_NULL                      ((TW_VOID *)0)
   51 #define TW_CL_TRUE                      1
   52 #define TW_CL_FALSE                     0
   53 
   54 #define TW_CL_VENDOR_ID                 0x13C1  /* 3ware vendor id */
   55 #define TW_CL_DEVICE_ID_9K              0x1002  /* 9000 PCI series device id */
   56 #define TW_CL_DEVICE_ID_9K_X            0x1003  /* 9000 PCI-X series device id */
   57 #define TW_CL_DEVICE_ID_9K_E            0x1004  /* 9000 PCIe series device id */
   58 #define TW_CL_DEVICE_ID_9K_SA           0x1005  /* 9000 PCIe SAS series device id */
   59 
   60 #define TW_CL_BAR_TYPE_IO               1       /* I/O base address */
   61 #define TW_CL_BAR_TYPE_MEM              2       /* memory base address */
   62 #define TW_CL_BAR_TYPE_SBUF             3       /* SBUF base address */
   63 
   64 #ifdef TW_OSL_ENCLOSURE_SUPPORT
   65 #define TW_CL_MAX_NUM_UNITS             65      /* max # of units we support
   66                                                 -- enclosure target id is 64 */
   67 #else /* TW_OSL_ENCLOSURE_SUPPORT */
   68 #define TW_CL_MAX_NUM_UNITS             32      /* max # of units we support */
   69 #endif /* TW_OSL_ENCLOSURE_SUPPORT */
   70 
   71 #define TW_CL_MAX_NUM_LUNS              16      /* max # of LUN's we support */
   72 #define TW_CL_MAX_IO_SIZE               0x20000 /* 128K */
   73 
   74 /*
   75  * Though we can support 256 simultaneous requests, we advertise as capable
   76  * of supporting only 255, since we want to keep one CL internal request
   77  * context packet always available for internal requests.
   78  */
   79 #define TW_CL_MAX_SIMULTANEOUS_REQUESTS 256     /* max simult reqs supported */
   80 
   81 #define TW_CL_MAX_32BIT_SG_ELEMENTS     109     /* max 32-bit sg elements */
   82 #define TW_CL_MAX_64BIT_SG_ELEMENTS     72      /* max 64-bit sg elements */
   83 
   84 
   85 /* Possible values of ctlr->flags */
   86 #define TW_CL_64BIT_ADDRESSES   (1<<0) /* 64 bit cmdpkt & SG addresses */
   87 #define TW_CL_64BIT_SG_LENGTH   (1<<1) /* 64 bit SG length */
   88 #define TW_CL_START_CTLR_ONLY   (1<<2) /* Start ctlr only */
   89 #define TW_CL_STOP_CTLR_ONLY    (1<<3) /* Stop ctlr only */
   90 #define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */
   91 
   92 /* Possible error values from the Common Layer. */
   93 #define TW_CL_ERR_REQ_SUCCESS                   0
   94 #define TW_CL_ERR_REQ_GENERAL_FAILURE           (1<<0)
   95 #define TW_CL_ERR_REQ_INVALID_TARGET            (1<<1)
   96 #define TW_CL_ERR_REQ_INVALID_LUN               (1<<2)
   97 #define TW_CL_ERR_REQ_SCSI_ERROR                (1<<3)
   98 #define TW_CL_ERR_REQ_AUTO_SENSE_VALID          (1<<4)
   99 #define TW_CL_ERR_REQ_BUS_RESET                 (1<<5)
  100 #define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND  (1<<6)
  101 
  102 
  103 /* Possible values of req_pkt->flags */
  104 #define TW_CL_REQ_RETRY_ON_BUSY         (1<<0)
  105 #define TW_CL_REQ_CALLBACK_FOR_SGLIST   (1<<1)
  106 
  107 
  108 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR   3
  109 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT   4
  110 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21
  111 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22
  112 #define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER     5
  113 #define TW_CL_MESSAGE_SOURCE_FREEBSD_OS         8
  114 #define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER     7
  115 #define TW_CL_MESSAGE_SOURCE_WINDOWS_OS         10
  116 
  117 #define TW_CL_SEVERITY_ERROR            0x1
  118 #define TW_CL_SEVERITY_WARNING          0x2
  119 #define TW_CL_SEVERITY_INFO             0x3
  120 #define TW_CL_SEVERITY_DEBUG            0x4
  121 
  122 #define TW_CL_SEVERITY_ERROR_STRING     "ERROR"
  123 #define TW_CL_SEVERITY_WARNING_STRING   "WARNING"
  124 #define TW_CL_SEVERITY_INFO_STRING      "INFO"
  125 #define TW_CL_SEVERITY_DEBUG_STRING     "DEBUG"
  126 
  127 
  128 
  129 /*
  130  * Structure, a pointer to which is used as the controller handle in
  131  * communications between the OS Layer and the Common Layer.
  132  */
  133 struct tw_cl_ctlr_handle {
  134         TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */
  135         TW_VOID *cl_ctlr_ctxt;  /* CL's ctlr context */
  136 };
  137 
  138 
  139 /*
  140  * Structure, a pointer to which is used as the request handle in
  141  * communications between the OS Layer and the Common Layer.
  142  */
  143 struct tw_cl_req_handle {
  144         TW_VOID *osl_req_ctxt;  /* OSL's request context */
  145         TW_VOID *cl_req_ctxt;   /* CL's request context */
  146         TW_UINT8 is_io;         /* Only freeze/release simq for IOs */
  147 };
  148 
  149 
  150 /* Structure used to describe SCSI requests to CL. */
  151 struct tw_cl_scsi_req_packet {
  152         TW_UINT32       unit;           /* unit # to send cmd to */
  153         TW_UINT32       lun;            /* LUN to send cmd to */
  154         TW_UINT8        *cdb;           /* ptr to SCSI cdb */
  155         TW_UINT32       cdb_len;        /* # of valid cdb bytes */
  156         TW_UINT32       sense_len;      /* # of bytes of valid sense info */
  157         TW_UINT8        *sense_data;    /* ptr to sense data, if any */
  158         TW_UINT32       scsi_status;    /* SCSI status returned by fw */
  159         TW_UINT32       sgl_entries;    /* # of SG descriptors */
  160         TW_UINT8        *sg_list;       /* ptr to SG list */
  161 };
  162 
  163 
  164 /* Structure used to describe pass through command packets to CL. */
  165 struct tw_cl_passthru_req_packet {
  166         TW_UINT8        *cmd_pkt;       /* ptr to passthru cmd pkt */
  167         TW_UINT32       cmd_pkt_length; /* size of cmd pkt */
  168         TW_UINT32       sgl_entries;    /* # of SG descriptors */
  169         TW_UINT8        *sg_list;       /* ptr to SG list */
  170 };
  171 
  172 
  173 /* Request packet submitted to the Common Layer, by the OS Layer. */
  174 struct tw_cl_req_packet {
  175         TW_UINT32       cmd;            /* Common Layer cmd */
  176         TW_UINT32       flags;          /* flags describing request */
  177         TW_UINT32       status;         /* Common Layer returned status */
  178         TW_VOID         (*tw_osl_callback)(struct tw_cl_req_handle *req_handle);
  179                         /* OSL routine to be called by CL on req completion */
  180         TW_VOID         (*tw_osl_sgl_callback)(
  181                         struct tw_cl_req_handle *req_handle, TW_VOID *sg_list,
  182                         TW_UINT32 *num_sgl_entries);
  183                         /* OSL callback to get SG list. */
  184 
  185         union {
  186                 struct tw_cl_scsi_req_packet            scsi_req; /* SCSI req */
  187                 struct tw_cl_passthru_req_packet        pt_req;/*Passthru req*/
  188         } gen_req_pkt;
  189 };
  190 
  191 
  192 #pragma pack(1)
  193 /*
  194  * Packet that describes an AEN/error generated by the controller,
  195  * Common Layer, or even the OS Layer.
  196  */
  197 struct tw_cl_event_packet {
  198         TW_UINT32       sequence_id;
  199         TW_UINT32       time_stamp_sec;
  200         TW_UINT16       aen_code;
  201         TW_UINT8        severity;
  202         TW_UINT8        retrieved;
  203         TW_UINT8        repeat_count;
  204         TW_UINT8        parameter_len;
  205         TW_UINT8        parameter_data[98];
  206         TW_UINT32       event_src;
  207         TW_UINT8        severity_str[20];
  208 };
  209 #pragma pack()
  210 
  211 
  212 /* Structure to link 2 adjacent elements in a list. */
  213 struct tw_cl_link {
  214         struct tw_cl_link       *next;
  215         struct tw_cl_link       *prev;
  216 };
  217 
  218 
  219 #pragma pack(1)
  220 /* Scatter/Gather list entry with 32 bit addresses. */
  221 struct tw_cl_sg_desc32 {
  222         TW_UINT32       address;
  223         TW_UINT32       length;
  224 };
  225 
  226 
  227 /* Scatter/Gather list entry with 64 bit addresses. */
  228 struct tw_cl_sg_desc64 {
  229         TW_UINT64       address;
  230         TW_UINT32       length;
  231 };
  232 
  233 #pragma pack()
  234 
  235 
  236 /* Byte swap functions.  Valid only if running on big endian platforms. */
  237 #ifdef TW_OSL_BIG_ENDIAN
  238 
  239 #define TW_CL_SWAP16_WITH_CAST(x)                                       \
  240         ((x << 8) | (x >> 8))
  241 
  242 
  243 #define TW_CL_SWAP32_WITH_CAST(x)                                       \
  244         ((x << 24) | ((x << 8) & (0xFF0000)) |                          \
  245         ((x >> 8) & (0xFF00)) | (x >> 24))
  246 
  247 
  248 #define TW_CL_SWAP64_WITH_CAST(x)                                       \
  249         ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\
  250         ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0]))))
  251 
  252 
  253 #else /* TW_OSL_BIG_ENDIAN */
  254 
  255 #define TW_CL_SWAP16_WITH_CAST(x)       x
  256 #define TW_CL_SWAP32_WITH_CAST(x)       x
  257 #define TW_CL_SWAP64_WITH_CAST(x)       x
  258 
  259 #endif /* TW_OSL_BIG_ENDIAN */
  260 
  261 #define TW_CL_SWAP16(x)         TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x))
  262 #define TW_CL_SWAP32(x)         TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x))
  263 #define TW_CL_SWAP64(x)         TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x))
  264 
  265 
  266 /* Queue manipulation functions. */
  267 
  268 /* Initialize a queue. */
  269 #define TW_CL_Q_INIT(head)      do {            \
  270         (head)->prev = (head)->next = head;     \
  271 } while (0)
  272 
  273 
  274 /* Insert an item at the head of the queue. */
  275 #define TW_CL_Q_INSERT_HEAD(head, item) do {    \
  276         (item)->next = (head)->next;            \
  277         (item)->prev = head;                    \
  278         (head)->next->prev = item;              \
  279         (head)->next = item;                    \
  280 } while (0)
  281 
  282 
  283 /* Insert an item at the tail of the queue. */
  284 #define TW_CL_Q_INSERT_TAIL(head, item) do {    \
  285         (item)->next = head;                    \
  286         (item)->prev = (head)->prev;            \
  287         (head)->prev->next = item;              \
  288         (head)->prev = item;                    \
  289 } while (0)
  290 
  291 
  292 /* Remove an item from the head of the queue. */
  293 #define TW_CL_Q_REMOVE_ITEM(head, item) do {    \
  294         (item)->prev->next = (item)->next;      \
  295         (item)->next->prev = (item)->prev;      \
  296 } while (0)
  297 
  298 
  299 /* Retrieve the item at the head of the queue. */
  300 #define TW_CL_Q_FIRST_ITEM(head)                \
  301         (((head)->next != head) ? ((head)->next) : TW_CL_NULL)
  302 
  303 
  304 /* Retrieve the item at the tail of the queue. */
  305 #define TW_CL_Q_LAST_ITEM(head)                 \
  306         (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL)
  307 
  308 
  309 /* Retrieve the item next to a given item in the queue. */
  310 #define TW_CL_Q_NEXT_ITEM(head, item)           \
  311         (((item)->next != head) ? ((item)->next) : TW_CL_NULL)
  312 
  313 
  314 /* Retrieve the item previous to a given item in the queue. */
  315 #define TW_CL_Q_PREV_ITEM(head, item)           \
  316         (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL)
  317 
  318 
  319 /* Determine the offset of a field from the head of the structure it is in. */
  320 #define TW_CL_STRUCT_OFFSET(struct_type, field) \
  321         (TW_INT8 *)(&((struct_type *)0)->field)
  322 
  323 
  324 /*
  325  * Determine the address of the head of a structure, given the address of a
  326  * field within it.
  327  */
  328 #define TW_CL_STRUCT_HEAD(addr, struct_type, field)     \
  329         (struct_type *)((TW_INT8 *)addr -               \
  330         TW_CL_STRUCT_OFFSET(struct_type, field))
  331 
  332 
  333 
  334 #ifndef TW_BUILDING_API
  335 
  336 #include "tw_osl_inline.h"
  337 
  338 
  339 
  340 /*
  341  * The following are extern declarations of OS Layer defined functions called
  342  * by the Common Layer.  If any function has been defined as a macro in
  343  * tw_osl_share.h, we will not make the extern declaration here.
  344  */
  345 
  346 #ifndef tw_osl_breakpoint
  347 /* Allows setting breakpoints in the CL code for debugging purposes. */
  348 extern TW_VOID  tw_osl_breakpoint(TW_VOID);
  349 #endif
  350 
  351 
  352 #ifndef tw_osl_timeout
  353 /* Start OS timeout() routine after controller reset sequence */
  354 extern TW_VOID  tw_osl_timeout(struct tw_cl_req_handle *req_handle);
  355 #endif
  356 
  357 #ifndef tw_osl_untimeout
  358 /* Stop OS timeout() routine during controller reset sequence */
  359 extern TW_VOID  tw_osl_untimeout(struct tw_cl_req_handle *req_handle);
  360 #endif
  361 
  362 
  363 #ifndef tw_osl_cur_func
  364 /* Text name of current function. */
  365 extern TW_INT8  *tw_osl_cur_func(TW_VOID);
  366 #endif
  367 
  368 
  369 #ifdef TW_OSL_DEBUG
  370 #ifndef tw_osl_dbg_printf
  371 /* Print to syslog/event log/debug console, as applicable. */
  372 extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle,
  373         const TW_INT8 *fmt, ...);
  374 #endif
  375 #endif /* TW_OSL_DEBUG */
  376 
  377 
  378 #ifndef tw_osl_delay
  379 /* Cause a delay of usecs micro-seconds. */
  380 extern TW_VOID  tw_osl_delay(TW_INT32 usecs);
  381 #endif
  382 
  383 
  384 #ifndef tw_osl_destroy_lock
  385 /* Create/initialize a lock for CL's use. */
  386 extern TW_VOID  tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle,
  387         TW_LOCK_HANDLE *lock);
  388 #endif
  389 
  390 
  391 #ifndef tw_osl_free_lock
  392 /* Free a previously held lock. */
  393 extern TW_VOID  tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle,
  394         TW_LOCK_HANDLE *lock);
  395 #endif
  396 
  397 
  398 #ifndef tw_osl_get_local_time
  399 /* Get local time. */
  400 extern TW_TIME  tw_osl_get_local_time(TW_VOID);
  401 #endif
  402 
  403 
  404 #ifndef tw_osl_get_lock
  405 /* Acquire a lock. */
  406 extern TW_VOID  tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle,
  407         TW_LOCK_HANDLE *lock);
  408 #endif
  409 
  410 
  411 #ifndef tw_osl_init_lock
  412 /* Create/initialize a lock for CL's use. */
  413 extern TW_VOID  tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle,
  414         TW_INT8 *lock_name, TW_LOCK_HANDLE *lock);
  415 #endif
  416 
  417 
  418 #ifndef tw_osl_memcpy
  419 /* Copy 'size' bytes from 'src' to 'dest'. */
  420 extern TW_VOID  tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size);
  421 #endif
  422 
  423 
  424 #ifndef tw_osl_memzero
  425 /* Zero 'size' bytes starting at 'addr'. */
  426 extern TW_VOID  tw_osl_memzero(TW_VOID *addr, TW_INT32 size);
  427 #endif
  428 
  429 
  430 #ifndef tw_osl_notify_event
  431 /* Notify OSL of a controller/CL (or even OSL) event. */
  432 extern TW_VOID  tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle,
  433         struct tw_cl_event_packet *event);
  434 #endif
  435 
  436 
  437 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
  438 #ifndef tw_osl_read_pci_config
  439 /* Read 'size' bytes from 'offset' in the PCI config space. */
  440 extern TW_UINT32 tw_osl_read_pci_config(
  441         struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size);
  442 #endif
  443 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
  444 
  445 
  446 #ifndef tw_osl_read_reg
  447 /* Read 'size' bytes at 'offset' from base address of this controller. */
  448 extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle,
  449         TW_INT32 offset, TW_INT32 size);
  450 #endif
  451 
  452 
  453 #ifndef tw_osl_scan_bus
  454 /* Request OSL for a bus scan. */
  455 extern TW_VOID  tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle);
  456 #endif
  457 
  458 
  459 #ifdef TW_OSL_CAN_SLEEP
  460 #ifndef tw_osl_sleep
  461 /* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */
  462 extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle,
  463         TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout);
  464 #endif
  465 #endif /* TW_OSL_CAN_SLEEP */
  466 
  467 
  468 #ifndef tw_osl_sprintf
  469 /* Standard sprintf. */
  470 extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...);
  471 #endif
  472 
  473 
  474 #ifndef tw_osl_strcpy
  475 /* Copy string 'src' to 'dest'. */
  476 extern TW_INT8  *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src);
  477 #endif
  478 
  479 
  480 #ifndef tw_osl_strlen
  481 /* Return length of string pointed at by 'str'. */
  482 extern TW_INT32 tw_osl_strlen(TW_VOID *str);
  483 #endif
  484 
  485 #ifndef tw_osl_vsprintf
  486 /* Standard vsprintf. */
  487 extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap);
  488 #endif
  489 
  490 
  491 #ifdef TW_OSL_CAN_SLEEP
  492 #ifndef tw_osl_wakeup
  493 /* Wake up a thread sleeping by a call to tw_osl_sleep. */
  494 extern TW_VOID  tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle,
  495         TW_SLEEP_HANDLE *sleep_handle);
  496 #endif
  497 #endif /* TW_OSL_CAN_SLEEP */
  498 
  499 
  500 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
  501 #ifndef tw_osl_write_pci_config
  502 /* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */
  503 extern TW_VOID  tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle,
  504         TW_INT32 offset, TW_INT32 value, TW_INT32 size);
  505 #endif
  506 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
  507 
  508 
  509 #ifndef tw_osl_write_reg
  510 /*
  511  * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of
  512  * this controller.
  513  */
  514 extern TW_VOID  tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle,
  515         TW_INT32 offset, TW_INT32 value, TW_INT32 size);
  516 #endif
  517 
  518 
  519 
  520 /* Functions in the Common Layer */
  521 
  522 /* Creates and queues AEN's.  Also notifies OS Layer. */
  523 extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle,
  524         TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code,
  525         TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc,
  526         TW_UINT8 *event_specific_desc, ...);
  527 
  528 /* Indicates whether a ctlr is supported by CL. */
  529 extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id);
  530 
  531 
  532 /* Submit a firmware cmd packet. */
  533 extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
  534         struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
  535 
  536 
  537 /* Find out how much memory CL needs. */
  538 extern TW_INT32 tw_cl_get_mem_requirements(
  539         struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
  540         TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
  541         TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
  542         TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
  543         );
  544 
  545 
  546 /* Return PCI BAR info. */
  547 extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
  548         TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size);
  549 
  550 
  551 /* Initialize Common Layer for a given controller. */
  552 extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
  553         TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
  554         TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem,
  555         TW_UINT64 dma_mem_phys
  556         );
  557 
  558 
  559 extern TW_VOID  tw_cl_set_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle);
  560 extern TW_INT32 tw_cl_is_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle);
  561 extern TW_INT32 tw_cl_is_active(struct tw_cl_ctlr_handle *ctlr_handle);
  562 
  563 /* CL's interrupt handler. */
  564 extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle);
  565 
  566 
  567 /* CL's ioctl handler. */
  568 extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle,
  569         u_long cmd, TW_VOID *buf);
  570 
  571 
  572 #ifdef TW_OSL_DEBUG
  573 /* Print CL's state/statistics for a controller. */
  574 extern TW_VOID  tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle);
  575 
  576 /* Prints CL internal details of a given request. */
  577 extern TW_VOID  tw_cl_print_req_info(struct tw_cl_req_handle *req_handle);
  578 #endif /* TW_OSL_DEBUG */
  579 
  580 
  581 /* Soft reset controller. */
  582 extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle);
  583 
  584 
  585 #ifdef TW_OSL_DEBUG
  586 /* Reset CL's statistics for a controller. */
  587 extern TW_VOID  tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle);
  588 #endif /* TW_OSL_DEBUG */
  589 
  590 
  591 /* Stop a controller. */
  592 extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
  593         TW_UINT32 flags);
  594 
  595 
  596 /* Submit a SCSI I/O request. */
  597 extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
  598         struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
  599 
  600 
  601 #endif /* TW_BUILDING_API */
  602 
  603 #endif /* TW_CL_SHARE_H */

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