1 /*
2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/twa/tw_cl_share.h,v 1.1.2.2 2005/12/07 18:20:37 vkashyap Exp $
28 */
29
30 /*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 */
35
36
37
38 #ifndef TW_CL_SHARE_H
39
40 #define TW_CL_SHARE_H
41
42
43 /*
44 * Macros, structures and functions shared between OSL and CL,
45 * and defined by CL.
46 */
47
48
49 #define TW_CL_VERSION_STRING "1.00.01.011"
50
51 #define TW_CL_NULL ((TW_VOID *)0)
52 #define TW_CL_TRUE 1
53 #define TW_CL_FALSE 0
54
55 #define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */
56 #define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */
57 #define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */
58
59 #define TW_CL_BAR_TYPE_IO 1 /* I/O base address */
60 #define TW_CL_BAR_TYPE_MEM 2 /* memory base address */
61 #define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */
62
63 #ifdef TW_OSL_ENCLOSURE_SUPPORT
64 #define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support
65 -- enclosure target id is 64 */
66 #else /* TW_OSL_ENCLOSURE_SUPPORT */
67 #define TW_CL_MAX_NUM_UNITS 16 /* max # of units we support */
68 #endif /* TW_OSL_ENCLOSURE_SUPPORT */
69
70 #define TW_CL_MAX_NUM_LUNS 16 /* max # of LUN's we support */
71 #define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */
72
73 /*
74 * Though we can support 256 simultaneous requests, we advertise as capable
75 * of supporting only 255, since we want to keep one CL internal request
76 * context packet always available for internal requests.
77 */
78 #define TW_CL_MAX_SIMULTANEOUS_REQUESTS 0xFF /* max simult reqs supported */
79
80 #define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */
81 #define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */
82
83
84 /* Possible values of ctlr->flags */
85 #define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */
86 #define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */
87 #define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */
88 #define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */
89 #define TW_CL_FLASH_FIRMWARE (1<<4) /* Flash firmware */
90 #define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */
91
92 /* Possible error values from the Common Layer. */
93 #define TW_CL_ERR_REQ_SUCCESS 0
94 #define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0)
95 #define TW_CL_ERR_REQ_INVALID_TARGET (1<<1)
96 #define TW_CL_ERR_REQ_INVALID_LUN (1<<2)
97 #define TW_CL_ERR_REQ_SCSI_ERROR (1<<3)
98 #define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4)
99 #define TW_CL_ERR_REQ_BUS_RESET (1<<5)
100 #define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6)
101
102
103 /* Possible values of req_pkt->flags */
104 #ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
105 #define TW_CL_REQ_RETRY_ON_BUSY (1<<0)
106 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
107 #define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1)
108
109
110 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3
111 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4
112 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21
113 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22
114 #define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5
115 #define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8
116 #define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7
117 #define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10
118
119 #define TW_CL_SEVERITY_ERROR 0x1
120 #define TW_CL_SEVERITY_WARNING 0x2
121 #define TW_CL_SEVERITY_INFO 0x3
122 #define TW_CL_SEVERITY_DEBUG 0x4
123
124 #define TW_CL_SEVERITY_ERROR_STRING "ERROR"
125 #define TW_CL_SEVERITY_WARNING_STRING "WARNING"
126 #define TW_CL_SEVERITY_INFO_STRING "INFO"
127 #define TW_CL_SEVERITY_DEBUG_STRING "DEBUG"
128
129
130 #pragma pack(1)
131
132 /*
133 * Structure, a pointer to which is used as the controller handle in
134 * communications between the OS Layer and the Common Layer.
135 */
136 struct tw_cl_ctlr_handle {
137 TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */
138 TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */
139 };
140
141
142 /*
143 * Structure, a pointer to which is used as the request handle in
144 * communications between the OS Layer and the Common Layer.
145 */
146 struct tw_cl_req_handle {
147 TW_VOID *osl_req_ctxt; /* OSL's request context */
148 TW_VOID *cl_req_ctxt; /* CL's request context */
149 };
150
151
152 /* Structure used to describe SCSI requests to CL. */
153 struct tw_cl_scsi_req_packet {
154 TW_UINT32 unit; /* unit # to send cmd to */
155 TW_UINT32 lun; /* LUN to send cmd to */
156 TW_UINT8 *cdb; /* ptr to SCSI cdb */
157 TW_UINT32 cdb_len; /* # of valid cdb bytes */
158 TW_UINT32 sense_len; /* # of bytes of valid sense info */
159 TW_UINT8 *sense_data; /* ptr to sense data, if any */
160 TW_UINT32 scsi_status; /* SCSI status returned by fw */
161 TW_UINT32 sgl_entries; /* # of SG descriptors */
162 TW_UINT8 *sg_list; /* ptr to SG list */
163 };
164
165
166 /* Structure used to describe pass through command packets to CL. */
167 struct tw_cl_passthru_req_packet {
168 TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */
169 TW_UINT32 cmd_pkt_length; /* size of cmd pkt */
170 TW_UINT32 sgl_entries; /* # of SG descriptors */
171 TW_UINT8 *sg_list; /* ptr to SG list */
172 };
173
174
175 /* Request packet submitted to the Common Layer, by the OS Layer. */
176 struct tw_cl_req_packet {
177 TW_UINT32 cmd; /* Common Layer cmd */
178 TW_UINT32 flags; /* flags describing request */
179 TW_UINT32 status; /* Common Layer returned status */
180 TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle);
181 /* OSL routine to be called by CL on req completion */
182 TW_VOID (*tw_osl_sgl_callback)(
183 struct tw_cl_req_handle *req_handle, TW_VOID *sg_list,
184 TW_UINT32 *num_sgl_entries);
185 /* OSL callback to get SG list. */
186
187 #ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
188
189 TW_VOID *dma_mem;
190 TW_UINT64 dma_mem_phys;
191
192 #endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
193
194 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
195
196 TW_VOID *non_dma_mem;
197
198 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
199
200 union {
201 struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */
202 struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/
203 } gen_req_pkt;
204 };
205
206
207 /*
208 * Packet that describes an AEN/error generated by the controller,
209 * Common Layer, or even the OS Layer.
210 */
211 struct tw_cl_event_packet {
212 TW_UINT32 sequence_id;
213 TW_UINT32 time_stamp_sec;
214 TW_UINT16 aen_code;
215 TW_UINT8 severity;
216 TW_UINT8 retrieved;
217 TW_UINT8 repeat_count;
218 TW_UINT8 parameter_len;
219 TW_UINT8 parameter_data[98];
220 TW_UINT32 event_src;
221 TW_UINT8 severity_str[20];
222 };
223
224
225 /* Structure to link 2 adjacent elements in a list. */
226 struct tw_cl_link {
227 struct tw_cl_link *next;
228 struct tw_cl_link *prev;
229 };
230
231
232 /* Scatter/Gather list entry with 32 bit addresses. */
233 struct tw_cl_sg_desc32 {
234 TW_UINT32 address;
235 TW_UINT32 length;
236 };
237
238
239 /* Scatter/Gather list entry with 64 bit addresses. */
240 struct tw_cl_sg_desc64 {
241 TW_UINT64 address;
242 TW_UINT32 length;
243 };
244
245 #pragma pack()
246
247
248 /* Byte swap functions. Valid only if running on big endian platforms. */
249 #ifdef TW_OSL_BIG_ENDIAN
250
251 #define TW_CL_SWAP16_WITH_CAST(x) \
252 ((x << 8) | (x >> 8))
253
254
255 #define TW_CL_SWAP32_WITH_CAST(x) \
256 ((x << 24) | ((x << 8) & (0xFF0000)) | \
257 ((x >> 8) & (0xFF00)) | (x >> 24))
258
259
260 #define TW_CL_SWAP64_WITH_CAST(x) \
261 ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\
262 ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0]))))
263
264
265 #else /* TW_OSL_BIG_ENDIAN */
266
267 #define TW_CL_SWAP16_WITH_CAST(x) x
268 #define TW_CL_SWAP32_WITH_CAST(x) x
269 #define TW_CL_SWAP64_WITH_CAST(x) x
270
271 #endif /* TW_OSL_BIG_ENDIAN */
272
273 #define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x))
274 #define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x))
275 #define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x))
276
277
278 /* Queue manipulation functions. */
279
280 /* Initialize a queue. */
281 #define TW_CL_Q_INIT(head) do { \
282 (head)->prev = (head)->next = head; \
283 } while (0)
284
285
286 /* Insert an item at the head of the queue. */
287 #define TW_CL_Q_INSERT_HEAD(head, item) do { \
288 (item)->next = (head)->next; \
289 (item)->prev = head; \
290 (head)->next->prev = item; \
291 (head)->next = item; \
292 } while (0)
293
294
295 /* Insert an item at the tail of the queue. */
296 #define TW_CL_Q_INSERT_TAIL(head, item) do { \
297 (item)->next = head; \
298 (item)->prev = (head)->prev; \
299 (head)->prev->next = item; \
300 (head)->prev = item; \
301 } while (0)
302
303
304 /* Remove an item from the head of the queue. */
305 #define TW_CL_Q_REMOVE_ITEM(head, item) do { \
306 (item)->prev->next = (item)->next; \
307 (item)->next->prev = (item)->prev; \
308 } while (0)
309
310
311 /* Retrieve the item at the head of the queue. */
312 #define TW_CL_Q_FIRST_ITEM(head) \
313 (((head)->next != head) ? ((head)->next) : TW_CL_NULL)
314
315
316 /* Retrieve the item at the tail of the queue. */
317 #define TW_CL_Q_LAST_ITEM(head) \
318 (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL)
319
320
321 /* Retrieve the item next to a given item in the queue. */
322 #define TW_CL_Q_NEXT_ITEM(head, item) \
323 (((item)->next != head) ? ((item)->next) : TW_CL_NULL)
324
325
326 /* Retrieve the item previous to a given item in the queue. */
327 #define TW_CL_Q_PREV_ITEM(head, item) \
328 (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL)
329
330
331 /* Determine the offset of a field from the head of the structure it is in. */
332 #define TW_CL_STRUCT_OFFSET(struct_type, field) \
333 (TW_INT8 *)(&((struct_type *)0)->field)
334
335
336 /*
337 * Determine the address of the head of a structure, given the address of a
338 * field within it.
339 */
340 #define TW_CL_STRUCT_HEAD(addr, struct_type, field) \
341 (struct_type *)((TW_INT8 *)addr - \
342 TW_CL_STRUCT_OFFSET(struct_type, field))
343
344
345
346 #ifndef TW_BUILDING_API
347
348 #include "tw_osl_inline.h"
349
350
351
352 /*
353 * The following are extern declarations of OS Layer defined functions called
354 * by the Common Layer. If any function has been defined as a macro in
355 * tw_osl_share.h, we will not make the extern declaration here.
356 */
357
358 #ifndef tw_osl_breakpoint
359 /* Allows setting breakpoints in the CL code for debugging purposes. */
360 extern TW_VOID tw_osl_breakpoint(TW_VOID);
361 #endif
362
363
364 #ifndef tw_osl_ctlr_busy
365 /* Called when CL is too busy to accept new requests. */
366 extern TW_VOID tw_osl_ctlr_busy(struct tw_cl_ctlr_handle *ctlr_handle,
367 struct tw_cl_req_handle *req_handle);
368 #endif
369
370
371 #ifndef tw_osl_ctlr_ready
372 /* Called on cmd interrupt. Allows re-submission of any pending requests. */
373 extern TW_VOID tw_osl_ctlr_ready(struct tw_cl_ctlr_handle *ctlr_handle);
374 #endif
375
376
377 #ifndef tw_osl_cur_func
378 /* Text name of current function. */
379 extern TW_INT8 *tw_osl_cur_func(TW_VOID);
380 #endif
381
382
383 #ifdef TW_OSL_DEBUG
384 #ifndef tw_osl_dbg_printf
385 /* Print to syslog/event log/debug console, as applicable. */
386 extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle,
387 const TW_INT8 *fmt, ...);
388 #endif
389 #endif /* TW_OSL_DEBUG */
390
391
392 #ifndef tw_osl_delay
393 /* Cause a delay of usecs micro-seconds. */
394 extern TW_VOID tw_osl_delay(TW_INT32 usecs);
395 #endif
396
397
398 #ifndef tw_osl_destroy_lock
399 /* Create/initialize a lock for CL's use. */
400 extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle,
401 TW_LOCK_HANDLE *lock);
402 #endif
403
404
405 #ifndef tw_osl_free_lock
406 /* Free a previously held lock. */
407 extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle,
408 TW_LOCK_HANDLE *lock);
409 #endif
410
411
412 #ifndef tw_osl_get_local_time
413 /* Get local time. */
414 extern TW_TIME tw_osl_get_local_time(TW_VOID);
415 #endif
416
417
418 #ifndef tw_osl_get_lock
419 /* Acquire a lock. */
420 extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle,
421 TW_LOCK_HANDLE *lock);
422 #endif
423
424
425 #ifndef tw_osl_init_lock
426 /* Create/initialize a lock for CL's use. */
427 extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle,
428 TW_INT8 *lock_name, TW_LOCK_HANDLE *lock);
429 #endif
430
431
432 #ifndef tw_osl_memcpy
433 /* Copy 'size' bytes from 'src' to 'dest'. */
434 extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size);
435 #endif
436
437
438 #ifndef tw_osl_memzero
439 /* Zero 'size' bytes starting at 'addr'. */
440 extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size);
441 #endif
442
443
444 #ifndef tw_osl_notify_event
445 /* Notify OSL of a controller/CL (or even OSL) event. */
446 extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle,
447 struct tw_cl_event_packet *event);
448 #endif
449
450
451 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
452 #ifndef tw_osl_read_pci_config
453 /* Read 'size' bytes from 'offset' in the PCI config space. */
454 extern TW_UINT32 tw_osl_read_pci_config(
455 struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size);
456 #endif
457 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
458
459
460 #ifndef tw_osl_read_reg
461 /* Read 'size' bytes at 'offset' from base address of this controller. */
462 extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle,
463 TW_INT32 offset, TW_INT32 size);
464 #endif
465
466
467 #ifndef tw_osl_scan_bus
468 /* Request OSL for a bus scan. */
469 extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle);
470 #endif
471
472
473 #ifdef TW_OSL_CAN_SLEEP
474 #ifndef tw_osl_sleep
475 /* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */
476 extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle,
477 TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout);
478 #endif
479 #endif /* TW_OSL_CAN_SLEEP */
480
481
482 #ifndef tw_osl_sprintf
483 /* Standard sprintf. */
484 extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...);
485 #endif
486
487
488 #ifndef tw_osl_strcpy
489 /* Copy string 'src' to 'dest'. */
490 extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src);
491 #endif
492
493
494 #ifndef tw_osl_strlen
495 /* Return length of string pointed at by 'str'. */
496 extern TW_INT32 tw_osl_strlen(TW_VOID *str);
497 #endif
498
499
500 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
501
502 #ifndef tw_osl_sync_io_block
503 /* Block new I/O requests from being sent by the OS Layer. */
504 extern TW_VOID tw_osl_sync_io_block(struct tw_cl_ctlr_handle *ctlr_handle,
505 TW_SYNC_HANDLE *sync_handle);
506 #endif
507
508
509 #ifndef tw_osl_sync_io_unblock
510 /* Allow new I/O requests from the OS Layer. */
511 extern TW_VOID tw_osl_sync_io_unblock(struct tw_cl_ctlr_handle *ctlr_handle,
512 TW_SYNC_HANDLE *sync_handle);
513 #endif
514
515
516 #ifndef tw_osl_sync_isr_block
517 /* Block the ISR from being called by the OS Layer. */
518 extern TW_VOID tw_osl_sync_isr_block(struct tw_cl_ctlr_handle *ctlr_handle,
519 TW_SYNC_HANDLE *sync_handle);
520 #endif
521
522
523 #ifndef tw_osl_sync_isr_unblock
524 /* Allow calls to the ISR from the OS Layer. */
525 extern TW_VOID tw_osl_sync_isr_unblock(struct tw_cl_ctlr_handle *ctlr_handle,
526 TW_SYNC_HANDLE *sync_handle);
527 #endif
528
529 #endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
530
531
532 #ifndef tw_osl_vsprintf
533 /* Standard vsprintf. */
534 extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap);
535 #endif
536
537
538 #ifdef TW_OSL_CAN_SLEEP
539 #ifndef tw_osl_wakeup
540 /* Wake up a thread sleeping by a call to tw_osl_sleep. */
541 extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle,
542 TW_SLEEP_HANDLE *sleep_handle);
543 #endif
544 #endif /* TW_OSL_CAN_SLEEP */
545
546
547 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
548 #ifndef tw_osl_write_pci_config
549 /* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */
550 extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle,
551 TW_INT32 offset, TW_INT32 value, TW_INT32 size);
552 #endif
553 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
554
555
556 #ifndef tw_osl_write_reg
557 /*
558 * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of
559 * this controller.
560 */
561 extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle,
562 TW_INT32 offset, TW_INT32 value, TW_INT32 size);
563 #endif
564
565
566
567 /* Functions in the Common Layer */
568
569 /* Creates and queues AEN's. Also notifies OS Layer. */
570 extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle,
571 TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code,
572 TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc,
573 TW_UINT8 *event_specific_desc, ...);
574
575 /* Indicates whether a ctlr is supported by CL. */
576 extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id);
577
578
579 /* Deferred interrupt handler. */
580 extern TW_VOID tw_cl_deferred_interrupt(struct tw_cl_ctlr_handle *ctlr_handle);
581
582
583 /* Submit a firmware cmd packet. */
584 extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
585 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
586
587
588 /* Find out how much memory CL needs. */
589 extern TW_INT32 tw_cl_get_mem_requirements(
590 struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
591 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
592 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
593 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
594 #ifdef TW_OSL_FLASH_FIRMWARE
595 , TW_UINT32 *flash_dma_mem_size
596 #endif /* TW_OSL_FLASH_FIRMWARE */
597 #ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
598 , TW_UINT32 *per_req_dma_mem_size
599 #endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
600 #ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
601 , TW_UINT32 *per_req_non_dma_mem_size
602 #endif /* TW_OSL_N0N_DMA_MEM_ALLOC_PER_REQUEST */
603 );
604
605
606 /* Return PCI BAR info. */
607 extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
608 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size);
609
610
611 /* Initialize Common Layer for a given controller. */
612 extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
613 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
614 TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem,
615 TW_UINT64 dma_mem_phys
616 #ifdef TW_OSL_FLASH_FIRMWARE
617 , TW_VOID *flash_dma_mem, TW_UINT64 flash_dma_mem_phys
618 #endif /* TW_OSL_FLASH_FIRMWARE */
619 );
620
621
622 /* CL's interrupt handler. */
623 extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle);
624
625
626 /* CL's ioctl handler. */
627 extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle,
628 TW_INT32 cmd, TW_VOID *buf);
629
630
631 #ifdef TW_OSL_DEBUG
632 /* Print CL's state/statistics for a controller. */
633 extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle);
634
635 /* Prints CL internal details of a given request. */
636 extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle);
637 #endif /* TW_OSL_DEBUG */
638
639
640 /* Soft reset controller. */
641 extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle);
642
643
644 #ifdef TW_OSL_DEBUG
645 /* Reset CL's statistics for a controller. */
646 extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle);
647 #endif /* TW_OSL_DEBUG */
648
649
650 /* Stop a controller. */
651 extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
652 TW_UINT32 flags);
653
654
655 /* Submit a SCSI I/O request. */
656 extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
657 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
658
659
660 #endif /* TW_BUILDING_API */
661
662 #endif /* TW_CL_SHARE_H */
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