FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/tw_osl.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
5 * Copyright (c) 2004-05 Vinod Kashyap.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 /*
33 * AMCC'S 3ware driver for 9000 series storage controllers.
34 *
35 * Author: Vinod Kashyap
36 * Modifications by: Adam Radford
37 * Modifications by: Manjunath Ranganathaiah
38 */
39
40
41
42 #ifndef TW_OSL_H
43
44 #define TW_OSL_H
45
46
47 /*
48 * OS Layer internal macros, structures and functions.
49 */
50
51
52 #define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
53
54 #define TW_OSLI_MALLOC_CLASS M_TWA
55 #define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS
56 /* Reserve two command packets. One for ioctls and one for AENs */
57 #define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2)
58 #define TW_OSLI_MAX_NUM_AENS 0x100
59
60 #ifdef PAE
61 #define TW_OSLI_DMA_BOUNDARY (1u << 31)
62 #else
63 #define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32))
64 #endif
65
66 /* Possible values of req->state. */
67 #define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
68 #define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
69 #define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
70 #define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
71
72 /* Possible values of req->flags. */
73 #define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
74 #define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
75 #define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
76 have to copy to/from private buffer */
77 #define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
78 #define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
79 EINPROGRESS */
80 #define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
81 #define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
82 #define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */
83 #define TW_OSLI_REQ_FLAGS_CCB (1<<8) /* req is ccb. */
84
85
86 #ifdef TW_OSL_DEBUG
87 struct tw_osli_q_stats {
88 TW_UINT32 cur_len; /* current # of items in q */
89 TW_UINT32 max_len; /* max value reached by q_length */
90 };
91 #endif /* TW_OSL_DEBUG */
92
93
94 /* Queues of OSL internal request context packets. */
95 #define TW_OSLI_FREE_Q 0 /* free q */
96 #define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
97 #define TW_OSLI_Q_COUNT 2 /* total number of queues */
98
99 /* Driver's request packet. */
100 struct tw_osli_req_context {
101 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
102 struct mtx ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */
103 struct mtx *ioctl_wake_timeout_lock;/* ptr to above lock */
104 struct twa_softc *ctlr; /* ptr to OSL's controller context */
105 TW_VOID *data; /* ptr to data being passed to CL */
106 TW_UINT32 length; /* length of buf being passed to CL */
107 TW_UINT64 deadline;/* request timeout (in absolute time) */
108
109 /*
110 * ptr to, and length of data passed to us from above, in case a buffer
111 * copy was done due to non-compliance to alignment requirements
112 */
113 TW_VOID *real_data;
114 TW_UINT32 real_length;
115
116 TW_UINT32 state; /* request state */
117 TW_UINT32 flags; /* request flags */
118
119 /* error encountered before request submission to CL */
120 TW_UINT32 error_code;
121
122 /* ptr to orig req for use during callback */
123 TW_VOID *orig_req;
124
125 struct tw_cl_link link; /* to link this request in a list */
126 bus_dmamap_t dma_map;/* DMA map for data */
127 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
128 };
129
130
131 /* Per-controller structure. */
132 struct twa_softc {
133 struct tw_cl_ctlr_handle ctlr_handle;
134 struct tw_osli_req_context *req_ctx_buf;
135
136 /* Controller state. */
137 TW_UINT8 open;
138 TW_UINT32 flags;
139
140 TW_INT32 device_id;
141 TW_UINT32 alignment;
142 TW_UINT32 sg_size_factor;
143
144 TW_VOID *non_dma_mem;
145 TW_VOID *dma_mem;
146 TW_UINT64 dma_mem_phys;
147
148 /* Request queues and arrays. */
149 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
150
151 struct task deferred_intr_callback;/* taskqueue function */
152 struct mtx io_lock_handle;/* general purpose lock */
153 struct mtx *io_lock;/* ptr to general purpose lock */
154 struct mtx q_lock_handle; /* queue manipulation lock */
155 struct mtx *q_lock;/* ptr to queue manipulation lock */
156 struct mtx sim_lock_handle;/* sim lock shared with cam */
157 struct mtx *sim_lock;/* ptr to sim lock */
158
159 struct callout watchdog_callout[2]; /* For command timeout */
160 TW_UINT32 watchdog_index;
161
162 #ifdef TW_OSL_DEBUG
163 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
164 #endif /* TW_OSL_DEBUG */
165
166 device_t bus_dev; /* bus device */
167 struct cdev *ctrl_dev; /* control device */
168 struct resource *reg_res; /* register interface window */
169 TW_INT32 reg_res_id; /* register resource id */
170 bus_space_handle_t bus_handle; /* bus space handle */
171 bus_space_tag_t bus_tag; /* bus space tag */
172 bus_dma_tag_t parent_tag; /* parent DMA tag */
173 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
174 bus_dma_tag_t dma_tag; /* data buffer DMA tag */
175 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
176 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
177 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
178 struct resource *irq_res; /* interrupt resource */
179 TW_INT32 irq_res_id; /* register resource id */
180 TW_VOID *intr_handle; /* interrupt handle */
181
182 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */
183 struct sysctl_oid *sysctl_tree; /* sysctl oid */
184
185 struct cam_sim *sim; /* sim for this controller */
186 struct cam_path *path; /* peripheral, path, tgt, lun
187 associated with this controller */
188 };
189
190
191
192 /*
193 * Queue primitives.
194 */
195
196 #ifdef TW_OSL_DEBUG
197
198 #define TW_OSLI_Q_INIT(sc, q_type) do { \
199 (sc)->q_stats[q_type].cur_len = 0; \
200 (sc)->q_stats[q_type].max_len = 0; \
201 } while(0)
202
203
204 #define TW_OSLI_Q_INSERT(sc, q_type) do { \
205 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
206 \
207 if (++(q_stats->cur_len) > q_stats->max_len) \
208 q_stats->max_len = q_stats->cur_len; \
209 } while(0)
210
211
212 #define TW_OSLI_Q_REMOVE(sc, q_type) \
213 (sc)->q_stats[q_type].cur_len--
214
215
216 #else /* TW_OSL_DEBUG */
217
218 #define TW_OSLI_Q_INIT(sc, q_index)
219 #define TW_OSLI_Q_INSERT(sc, q_index)
220 #define TW_OSLI_Q_REMOVE(sc, q_index)
221
222 #endif /* TW_OSL_DEBUG */
223
224
225
226 /* Initialize a queue of requests. */
227 static __inline TW_VOID
228 tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
229 {
230 TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
231 TW_OSLI_Q_INIT(sc, q_type);
232 }
233
234
235
236 /* Insert the given request at the head of the given queue (q_type). */
237 static __inline TW_VOID
238 tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
239 {
240 mtx_lock_spin(req->ctlr->q_lock);
241 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
242 TW_OSLI_Q_INSERT(req->ctlr, q_type);
243 mtx_unlock_spin(req->ctlr->q_lock);
244 }
245
246
247
248 /* Insert the given request at the tail of the given queue (q_type). */
249 static __inline TW_VOID
250 tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
251 {
252 mtx_lock_spin(req->ctlr->q_lock);
253 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
254 TW_OSLI_Q_INSERT(req->ctlr, q_type);
255 mtx_unlock_spin(req->ctlr->q_lock);
256 }
257
258
259
260 /* Remove and return the request at the head of the given queue (q_type). */
261 static __inline struct tw_osli_req_context *
262 tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
263 {
264 struct tw_osli_req_context *req = NULL;
265 struct tw_cl_link *link;
266
267 mtx_lock_spin(sc->q_lock);
268 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
269 TW_CL_NULL) {
270 req = TW_CL_STRUCT_HEAD(link,
271 struct tw_osli_req_context, link);
272 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
273 TW_OSLI_Q_REMOVE(sc, q_type);
274 }
275 mtx_unlock_spin(sc->q_lock);
276 return(req);
277 }
278
279
280
281 /* Remove the given request from the given queue (q_type). */
282 static __inline TW_VOID
283 tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
284 {
285 mtx_lock_spin(req->ctlr->q_lock);
286 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
287 TW_OSLI_Q_REMOVE(req->ctlr, q_type);
288 mtx_unlock_spin(req->ctlr->q_lock);
289 }
290
291
292
293 #ifdef TW_OSL_DEBUG
294
295 extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
296
297 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
298 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
299 device_printf(sc->bus_dev, "%s: " fmt "\n", \
300 __func__, ##args)
301
302
303 #define tw_osli_dbg_printf(dbg_level, fmt, args...) \
304 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
305 printf("%s: " fmt "\n", __func__, ##args)
306
307 #else /* TW_OSL_DEBUG */
308
309 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...)
310 #define tw_osli_dbg_printf(dbg_level, fmt, args...)
311
312 #endif /* TW_OSL_DEBUG */
313
314
315 /* For regular printing. */
316 #define twa_printf(sc, fmt, args...) \
317 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
318
319 /* For printing in the "consistent error reporting" format. */
320 #define tw_osli_printf(sc, err_specific_desc, args...) \
321 device_printf((sc)->bus_dev, \
322 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
323
324
325
326 #endif /* TW_OSL_H */
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