The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/twa/twa_reg.h

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    1 /*-
    2  * Copyright (c) 2003-04 3ware, Inc.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  *      $FreeBSD: releng/5.3/sys/dev/twa/twa_reg.h 134297 2004-08-25 17:15:26Z vkashyap $
   27  */
   28 
   29 /*
   30  * 3ware driver for 9000 series storage controllers.
   31  *
   32  * Author: Vinod Kashyap
   33  */
   34 
   35 /*
   36  * The following macro has no business being in twa_reg.h.  It should probably
   37  * be defined in twa_includes.h, before the #include twa_reg.h....  But that
   38  * causes the API to run into build errors.  Will leave it here for now...
   39  */
   40 #define TWA_64BIT_ADDRESSES     ((sizeof(bus_addr_t) == 8) ? 1 : 0)
   41 
   42 /* Register offsets from base address. */
   43 #define TWA_CONTROL_REGISTER_OFFSET             0x0
   44 #define TWA_STATUS_REGISTER_OFFSET              0x4
   45 #define TWA_COMMAND_QUEUE_OFFSET                0x8
   46 #define TWA_RESPONSE_QUEUE_OFFSET               0xC
   47 #define TWA_COMMAND_QUEUE_OFFSET_LOW            0x20
   48 #define TWA_COMMAND_QUEUE_OFFSET_HIGH           0x24
   49 
   50 /* Functions to read from, and write to registers */
   51 #define TWA_WRITE_CONTROL_REGISTER(sc, val)     \
   52         TWA_WRITE_REGISTER(sc, TWA_CONTROL_REGISTER_OFFSET, val)
   53 #define TWA_READ_STATUS_REGISTER(sc)            \
   54         TWA_READ_REGISTER(sc, TWA_STATUS_REGISTER_OFFSET)
   55 #define TWA_WRITE_COMMAND_QUEUE(sc, val)                                \
   56         do {                                                            \
   57                 if (TWA_64BIT_ADDRESSES) {                              \
   58                         /* First write the low 4 bytes, then the high 4. */  \
   59                         TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \
   60                                                 (u_int32_t)(val));      \
   61                         TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
   62                                         (u_int32_t)(((u_int64_t)val)>>32));  \
   63                 } else                                                  \
   64                         TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\
   65                                                 (u_int32_t)(val)); \
   66         } while (0)
   67 #define TWA_READ_RESPONSE_QUEUE(sc)             \
   68         (union twa_response_queue)TWA_READ_REGISTER(sc, TWA_RESPONSE_QUEUE_OFFSET)
   69 
   70 /* Control register bit definitions. */
   71 #define TWA_CONTROL_CLEAR_SBUF_WRITE_ERROR      0x00000008
   72 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
   73 #define TWA_CONTROL_DISABLE_INTERRUPTS          0x00000040
   74 #define TWA_CONTROL_ENABLE_INTERRUPTS           0x00000080
   75 #define TWA_CONTROL_ISSUE_SOFT_RESET            0x00000100
   76 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
   77 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
   78 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
   79 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
   80 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
   81 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
   82 #define TWA_CONTROL_CLEAR_PCI_ABORT             0x00100000
   83 #define TWA_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
   84 #define TWA_CONTROL_CLEAR_PARITY_ERROR          0x00800000
   85 
   86 
   87 #define TWA_SOFT_RESET(sc)                                              \
   88                 TWA_WRITE_CONTROL_REGISTER(sc,                          \
   89                         TWA_CONTROL_ISSUE_SOFT_RESET |                  \
   90                         TWA_CONTROL_CLEAR_HOST_INTERRUPT |              \
   91                         TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT |         \
   92                         TWA_CONTROL_MASK_COMMAND_INTERRUPT |            \
   93                         TWA_CONTROL_MASK_RESPONSE_INTERRUPT |           \
   94                         TWA_CONTROL_DISABLE_INTERRUPTS)
   95 
   96 /* Status register bit definitions. */
   97 #define TWA_STATUS_ROM_BIOS_IN_SBUF             0x00000002
   98 #define TWA_STATUS_SBUF_WRITE_ERROR             0x00000008
   99 #define TWA_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
  100 #define TWA_STATUS_MICROCONTROLLER_READY        0x00002000
  101 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
  102 #define TWA_STATUS_COMMAND_QUEUE_FULL           0x00008000
  103 #define TWA_STATUS_RESPONSE_INTERRUPT           0x00010000
  104 #define TWA_STATUS_COMMAND_INTERRUPT            0x00020000
  105 #define TWA_STATUS_ATTENTION_INTERRUPT          0x00040000
  106 #define TWA_STATUS_HOST_INTERRUPT               0x00080000
  107 #define TWA_STATUS_PCI_ABORT_INTERRUPT          0x00100000
  108 #define TWA_STATUS_MICROCONTROLLER_ERROR        0x00200000
  109 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT        0x00400000
  110 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT   0x00800000
  111 #define TWA_STATUS_MINOR_VERSION_MASK           0x0F000000
  112 #define TWA_STATUS_MAJOR_VERSION_MASK           0xF0000000
  113 
  114 #define TWA_STATUS_EXPECTED_BITS                0x00002000
  115 #define TWA_STATUS_UNEXPECTED_BITS              0x00F00000
  116 
  117 /* For use with the %b printf format. */
  118 #define TWA_STATUS_BITS_DESCRIPTION \
  119         "\2\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n"
  120 
  121 /* Detect inconsistencies in the status register. */
  122 #define TWA_STATUS_ERRORS(x)                    \
  123         ((x & TWA_STATUS_UNEXPECTED_BITS) &&    \
  124          (x & TWA_STATUS_MICROCONTROLLER_READY))
  125 
  126 /* PCI related defines. */
  127 #define TWA_IO_CONFIG_REG               0x10
  128 #define TWA_DEVICE_NAME                 "3ware 9000 series Storage Controller"
  129 #define TWA_VENDOR_ID                   0x13C1
  130 #define TWA_DEVICE_ID_9K                0x1002
  131 
  132 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR       0xc100
  133 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT          0x2000
  134 
  135 /* Command packet opcodes. */
  136 #define TWA_OP_NOP                      0x00
  137 #define TWA_OP_INIT_CONNECTION          0x01
  138 #define TWA_OP_READ                     0x02
  139 #define TWA_OP_WRITE                    0x03
  140 #define TWA_OP_READVERIFY               0x04
  141 #define TWA_OP_VERIFY                   0x05
  142 #define TWA_OP_ZEROUNIT                 0x08
  143 #define TWA_OP_REPLACEUNIT              0x09
  144 #define TWA_OP_HOTSWAP                  0x0A
  145 #define TWA_OP_SELFTESTS                0x0B
  146 #define TWA_OP_SYNC_PARAM               0x0C
  147 #define TWA_OP_REORDER_UNITS            0x0D
  148 
  149 #define TWA_OP_EXECUTE_SCSI_COMMAND     0x10
  150 #define TWA_OP_ATA_PASSTHROUGH          0x11
  151 #define TWA_OP_GET_PARAM                0x12
  152 #define TWA_OP_SET_PARAM                0x13
  153 #define TWA_OP_CREATEUNIT               0x14
  154 #define TWA_OP_DELETEUNIT               0x15
  155 #define TWA_OP_DOWNLOAD_FIRMWARE        0x16
  156 #define TWA_OP_REBUILDUNIT              0x17
  157 #define TWA_OP_POWER_MANAGEMENT         0x18
  158 
  159 #define TWA_OP_REMOTE_PRINT             0x1B
  160 #define TWA_OP_RESET_FIRMWARE           0x1C
  161 #define TWA_OP_DEBUG                    0x1D
  162 
  163 #define TWA_OP_DIAGNOSTICS              0x1F
  164 
  165 /* Misc defines. */
  166 #define TWA_ALIGNMENT                   0x4
  167 #define TWA_MAX_UNITS                   16
  168 #define TWA_INIT_MESSAGE_CREDITS        0x100
  169 #define TWA_SHUTDOWN_MESSAGE_CREDITS    0x001
  170 #define TWA_64BIT_SG_ADDRESSES          0x00000001
  171 #define TWA_EXTENDED_INIT_CONNECT       0x00000002
  172 #define TWA_BASE_MODE                   1
  173 #define TWA_BASE_FW_SRL                 0x17
  174 #define TWA_BASE_FW_BRANCH              0
  175 #define TWA_BASE_FW_BUILD               1
  176 #define TWA_CURRENT_FW_SRL              0x18
  177 #define TWA_CURRENT_FW_BRANCH           1
  178 #define TWA_CURRENT_FW_BUILD            9
  179 #define TWA_9000_ARCH_ID                0x5     /* 9000 series controllers */
  180 #define TWA_CTLR_FW_SAME_OR_NEWER       0x00000001
  181 #define TWA_CTLR_FW_COMPATIBLE          0x00000002
  182 #define TWA_BUNDLED_FW_SAFE_TO_FLASH    0x00000004
  183 #define TWA_CTLR_FW_RECOMMENDS_FLASH    0x00000008
  184 #define NUM_FW_IMAGE_CHUNKS             5
  185 #define TWA_MAX_IO_SIZE                 0x20000 /* 128K */
  186 #define TWA_MAX_SG_ELEMENTS             (TWA_64BIT_ADDRESSES ? 70 : 105)
  187 #define TWA_MAX_ATA_SG_ELEMENTS         60
  188 #define TWA_Q_LENGTH                    TWA_INIT_MESSAGE_CREDITS
  189 #define TWA_MAX_RESET_TRIES             3
  190 #define TWA_SECTOR_SIZE                 0x200   /* generic I/O bufffer */
  191 #define TWA_SENSE_DATA_LENGTH           18
  192 
  193 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED    0x010a
  194 #define TWA_ERROR_UNIT_OFFLINE                  0x0128
  195 #define TWA_ERROR_MORE_DATA                     0x0231
  196 
  197 #pragma pack(1)
  198 /* Scatter/Gather list entry. */
  199 struct twa_sg {
  200         bus_addr_t      address;
  201         u_int32_t       length;
  202 } __attribute__ ((packed));
  203 
  204 
  205 /* 7000 structures. */
  206 struct twa_command_init_connect {
  207         u_int8_t        opcode:5;       /* TWA_OP_INITCONNECTION */
  208         u_int8_t        res1:3;         
  209         u_int8_t        size;
  210         u_int8_t        request_id;
  211         u_int8_t        res2;
  212         u_int8_t        status;
  213         u_int8_t        flags;
  214         u_int16_t       message_credits;
  215         u_int32_t       features;
  216         u_int16_t       fw_srl;
  217         u_int16_t       fw_arch_id;
  218         u_int16_t       fw_branch;
  219         u_int16_t       fw_build;
  220         u_int32_t       result;
  221 } __attribute__ ((packed));
  222 
  223 
  224 struct twa_command_download_firmware {
  225         u_int8_t        opcode:5;       /* TWA_DOWNLOAD_FIRMWARE */
  226         u_int8_t        sgl_offset:3;
  227         u_int8_t        size;
  228         u_int8_t        request_id;
  229         u_int8_t        unit;
  230         u_int8_t        status;
  231         u_int8_t        flags;
  232         u_int16_t       param;
  233         struct twa_sg   sgl[TWA_MAX_SG_ELEMENTS];
  234 } __attribute__ ((packed));
  235 
  236 
  237 struct twa_command_reset_firmware {
  238         u_int8_t        opcode:5;       /* TWA_OP_RESET_FIRMWARE */
  239         u_int8_t        res1:3;
  240         u_int8_t        size;
  241         u_int8_t        request_id;
  242         u_int8_t        unit;
  243         u_int8_t        status;
  244         u_int8_t        flags;
  245         u_int8_t        res2;
  246         u_int8_t        param;
  247 } __attribute__ ((packed));
  248 
  249 
  250 struct twa_command_io {
  251         u_int8_t        opcode:5;       /* TWA_OP_READ/TWA_OP_WRITE */
  252         u_int8_t        sgl_offset:3;
  253         u_int8_t        size;
  254         u_int8_t        request_id;
  255         u_int8_t        unit:4;
  256         u_int8_t        host_id:4;
  257         u_int8_t        status;
  258         u_int8_t        flags;
  259         u_int16_t       block_count;
  260         u_int32_t       lba;
  261         struct twa_sg   sgl[TWA_MAX_SG_ELEMENTS];
  262 } __attribute__ ((packed));
  263 
  264 
  265 struct twa_command_hotswap {
  266         u_int8_t        opcode:5;       /* TWA_OP_HOTSWAP */
  267         u_int8_t        res1:3;
  268         u_int8_t        size;
  269         u_int8_t        request_id;
  270         u_int8_t        unit:4;
  271         u_int8_t        host_id:4;
  272         u_int8_t        status;
  273         u_int8_t        flags;
  274         u_int8_t        action;
  275 #define TWA_OP_HOTSWAP_REMOVE           0x00    /* remove assumed-degraded unit */
  276 #define TWA_OP_HOTSWAP_ADD_CBOD         0x01    /* add CBOD to empty port */
  277 #define TWA_OP_HOTSWAP_ADD_SPARE        0x02    /* add spare to empty port */
  278         u_int8_t        aport;
  279 } __attribute__ ((packed));
  280 
  281 
  282 struct twa_command_param {
  283         u_int8_t        opcode:5;       /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */
  284         u_int8_t        sgl_offset:3;
  285         u_int8_t        size;
  286         u_int8_t        request_id;
  287         u_int8_t        unit:4;
  288         u_int8_t        host_id:4;
  289         u_int8_t        status;
  290         u_int8_t        flags;
  291         u_int16_t       param_count;
  292         struct twa_sg   sgl[TWA_MAX_SG_ELEMENTS];
  293 } __attribute__ ((packed));
  294 
  295 
  296 struct twa_command_rebuildunit {
  297         u_int8_t        opcode:5;       /* TWA_OP_REBUILDUNIT */
  298         u_int8_t        res1:3;
  299         u_int8_t        size;
  300         u_int8_t        request_id;
  301         u_int8_t        src_unit:4;
  302         u_int8_t        host_id:4;
  303         u_int8_t        status;
  304         u_int8_t        flags;
  305         u_int8_t        action:7;
  306 #define TWA_OP_REBUILDUNIT_NOP          0
  307 #define TWA_OP_REBUILDUNIT_STOP         2       /* stop all rebuilds */
  308 #define TWA_OP_REBUILDUNIT_START        4       /* start rebuild with lowest unit */
  309 #define TWA_OP_REBUILDUNIT_STARTUNIT    5       /* rebuild src_unit (not supported) */
  310         u_int8_t        cs:1;                   /* request state change on src_unit */
  311         u_int8_t        logical_subunit;        /* for RAID10 rebuild of logical subunit */
  312 } __attribute__ ((packed));
  313 
  314 
  315 struct twa_command_ata {
  316         u_int8_t        opcode:5;       /* TWA_OP_ATA_PASSTHROUGH */
  317         u_int8_t        sgl_offset:3;
  318         u_int8_t        size;
  319         u_int8_t        request_id;
  320         u_int8_t        unit:4;
  321         u_int8_t        host_id:4;
  322         u_int8_t        status;
  323         u_int8_t        flags;
  324         u_int16_t       param;
  325         u_int16_t       features;
  326         u_int16_t       sector_count;
  327         u_int16_t       sector_num;
  328         u_int16_t       cylinder_lo;
  329         u_int16_t       cylinder_hi;
  330         u_int8_t        drive_head;
  331         u_int8_t        command;
  332         struct twa_sg   sgl[TWA_MAX_ATA_SG_ELEMENTS];
  333 } __attribute__ ((packed));
  334 
  335 
  336 struct twa_command_generic {
  337         u_int8_t        opcode:5;
  338         u_int8_t        sgl_offset:3;
  339         u_int8_t        size;
  340         u_int8_t        request_id;
  341         u_int8_t        unit:4;
  342         u_int8_t        host_id:4;
  343         u_int8_t        status;
  344         u_int8_t        flags;
  345 #define TWA_FLAGS_SUCCESS       0x00
  346 #define TWA_FLAGS_INFORMATIONAL 0x01
  347 #define TWA_FLAGS_WARNING       0x02
  348 #define TWA_FLAGS_FATAL         0x03
  349 #define TWA_FLAGS_PERCENTAGE    (1<<8)  /* bits 0-6 indicate completion percentage */
  350         u_int16_t       count;          /* block count, parameter count, message credits */
  351 } __attribute__ ((packed));
  352 
  353 
  354 /* Command packet - must be TWA_ALIGNMENT aligned. */
  355 union twa_command_7k {
  356         struct twa_command_init_connect         init_connect;
  357         struct twa_command_download_firmware    download_fw;
  358         struct twa_command_reset_firmware       reset_fw;
  359         struct twa_command_io                   io;
  360         struct twa_command_hotswap              hotswap;
  361         struct twa_command_param                param;
  362         struct twa_command_rebuildunit          rebuildunit;
  363         struct twa_command_ata                  ata;
  364         struct twa_command_generic              generic;
  365 } __attribute__ ((packed));
  366 
  367 
  368 /* 9000 structures. */
  369 
  370 /* Command Packet. */
  371 struct twa_command_9k {
  372         struct {
  373                 u_int8_t        opcode:5;
  374                 u_int8_t        reserved:3;
  375         } command;
  376         u_int8_t        unit;
  377         u_int16_t       request_id;
  378         u_int8_t        status;
  379         u_int8_t        sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */
  380         u_int16_t       sgl_entries;
  381         u_int8_t        cdb[16];
  382         struct twa_sg   sg_list[TWA_MAX_SG_ELEMENTS];
  383         u_int8_t        padding[32];
  384 } __attribute__ ((packed));
  385 
  386 
  387 /* Command packet header. */
  388 struct twa_command_header {
  389         u_int8_t        sense_data[TWA_SENSE_DATA_LENGTH];
  390         struct {
  391                 int8_t          reserved[4];
  392                 u_int16_t       error;
  393                 u_int8_t        padding;
  394                 struct {
  395                         u_int8_t        severity:3;
  396                         u_int8_t        reserved:5;
  397                 } substatus_block;
  398         } status_block;
  399         u_int8_t        err_specific_desc[98];
  400         struct {
  401                 u_int8_t        size_header;
  402                 u_int16_t       reserved;
  403                 u_int8_t        size_sense;
  404         } header_desc;
  405 } __attribute__ ((packed));
  406 
  407 
  408 /* Full command packet. */
  409 struct twa_command_packet {
  410         struct twa_command_header       cmd_hdr;
  411         union {
  412                 union twa_command_7k    cmd_pkt_7k;
  413                 struct twa_command_9k   cmd_pkt_9k;
  414         } command;
  415 } __attribute__ ((packed));
  416 
  417 
  418 /* Response queue entry. */
  419 union twa_response_queue {
  420         struct {
  421                 u_int32_t       undefined_1:4;
  422                 u_int32_t       response_id:8;
  423                 u_int32_t       undefined_2:20;
  424         } u;
  425         u_int32_t       value;
  426 } __attribute__ ((packed));
  427 
  428 
  429 #define TWA_AEN_QUEUE_EMPTY             0x00
  430 #define TWA_AEN_SOFT_RESET              0x01
  431 #define TWA_AEN_SYNC_TIME_WITH_HOST     0x31
  432 #define TWA_AEN_SEVERITY_ERROR          0x1
  433 #define TWA_AEN_SEVERITY_WARNING        0x1
  434 #define TWA_AEN_SEVERITY_INFO           0x1
  435 #define TWA_AEN_SEVERITY_DEBUG          0x4
  436 
  437 #define TWA_PARAM_VERSION_TABLE         0x0402
  438 #define TWA_PARAM_VERSION_MONITOR       2       /* monitor version [16] */
  439 #define TWA_PARAM_VERSION_FW            3       /* firmware version [16] */
  440 #define TWA_PARAM_VERSION_BIOS          4       /* BIOSs version [16] */
  441 #define TWA_PARAM_VERSION_PCBA          5       /* PCB version [8] */
  442 #define TWA_PARAM_VERSION_ATA           6       /* A-chip version [8] */
  443 #define TWA_PARAM_VERSION_PCI           7       /* P-chip version [8] */
  444 
  445 #define TWA_PARAM_CONTROLLER_TABLE      0x0403
  446 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3       /* number of ports [1] */
  447 
  448 #define TWA_PARAM_TIME_TABLE            0x40A
  449 #define TWA_PARAM_TIME_SchedulerTime    0x3
  450 
  451 #define TWA_9K_PARAM_DESCRIPTOR         0x8000
  452 
  453 
  454 struct twa_param_9k {
  455         u_int16_t       table_id;
  456         u_int8_t        parameter_id;
  457         u_int8_t        reserved;
  458         u_int16_t       parameter_size_bytes;
  459         u_int16_t       parameter_actual_size_bytes;
  460         u_int8_t        data[1];
  461 } __attribute__ ((packed));
  462 #pragma pack()
  463 

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