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sys/dev/tx/if_tx.c
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1 /*- 2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/5.3/sys/dev/tx/if_tx.c 133700 2004-08-13 23:52:33Z rwatson $"); 29 30 /* 31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie) 32 * 33 * These cards are based on SMC83c17x (EPIC) chip and one of the various 34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on 35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full- 36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also 37 * supports fibre optics. 38 * 39 * Thanks are going to Steve Bauer and Jason Wright. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #include <net/bpf.h> 58 59 #include <net/if_vlan_var.h> 60 61 #include <machine/bus_memio.h> 62 #include <machine/bus_pio.h> 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <machine/clock.h> /* for DELAY */ 66 #include <sys/bus.h> 67 #include <sys/rman.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include "miidevs.h" 75 76 #include <dev/mii/lxtphyreg.h> 77 78 #include "miibus_if.h" 79 80 #include <dev/tx/if_txreg.h> 81 #include <dev/tx/if_txvar.h> 82 83 MODULE_DEPEND(tx, pci, 1, 1, 1); 84 MODULE_DEPEND(tx, ether, 1, 1, 1); 85 MODULE_DEPEND(tx, miibus, 1, 1, 1); 86 87 static int epic_ifioctl(struct ifnet *, u_long, caddr_t); 88 static void epic_intr(void *); 89 static void epic_tx_underrun(epic_softc_t *); 90 static void epic_ifstart(struct ifnet *); 91 static void epic_ifwatchdog(struct ifnet *); 92 static void epic_stats_update(epic_softc_t *); 93 static void epic_init(void *); 94 static void epic_stop(epic_softc_t *); 95 static void epic_rx_done(epic_softc_t *); 96 static void epic_tx_done(epic_softc_t *); 97 static int epic_init_rings(epic_softc_t *); 98 static void epic_free_rings(epic_softc_t *); 99 static void epic_stop_activity(epic_softc_t *); 100 static int epic_queue_last_packet(epic_softc_t *); 101 static void epic_start_activity(epic_softc_t *); 102 static void epic_set_rx_mode(epic_softc_t *); 103 static void epic_set_tx_mode(epic_softc_t *); 104 static void epic_set_mc_table(epic_softc_t *); 105 static int epic_read_eeprom(epic_softc_t *,u_int16_t); 106 static void epic_output_eepromw(epic_softc_t *, u_int16_t); 107 static u_int16_t epic_input_eepromw(epic_softc_t *); 108 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t); 109 static void epic_write_eepromreg(epic_softc_t *,u_int8_t); 110 static u_int8_t epic_read_eepromreg(epic_softc_t *); 111 112 static int epic_read_phy_reg(epic_softc_t *, int, int); 113 static void epic_write_phy_reg(epic_softc_t *, int, int, int); 114 115 static int epic_miibus_readreg(device_t, int, int); 116 static int epic_miibus_writereg(device_t, int, int, int); 117 static void epic_miibus_statchg(device_t); 118 static void epic_miibus_mediainit(device_t); 119 120 static int epic_ifmedia_upd(struct ifnet *); 121 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *); 122 123 static int epic_probe(device_t); 124 static int epic_attach(device_t); 125 static void epic_shutdown(device_t); 126 static int epic_detach(device_t); 127 static void epic_release(epic_softc_t *); 128 static struct epic_type *epic_devtype(device_t); 129 130 static device_method_t epic_methods[] = { 131 /* Device interface */ 132 DEVMETHOD(device_probe, epic_probe), 133 DEVMETHOD(device_attach, epic_attach), 134 DEVMETHOD(device_detach, epic_detach), 135 DEVMETHOD(device_shutdown, epic_shutdown), 136 137 /* MII interface */ 138 DEVMETHOD(miibus_readreg, epic_miibus_readreg), 139 DEVMETHOD(miibus_writereg, epic_miibus_writereg), 140 DEVMETHOD(miibus_statchg, epic_miibus_statchg), 141 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit), 142 143 { 0, 0 } 144 }; 145 146 static driver_t epic_driver = { 147 "tx", 148 epic_methods, 149 sizeof(epic_softc_t) 150 }; 151 152 static devclass_t epic_devclass; 153 154 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0); 155 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0); 156 157 static struct epic_type epic_devs[] = { 158 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" }, 159 { 0, 0, NULL } 160 }; 161 162 static int 163 epic_probe(dev) 164 device_t dev; 165 { 166 struct epic_type *t; 167 168 t = epic_devtype(dev); 169 170 if (t != NULL) { 171 device_set_desc(dev, t->name); 172 return (0); 173 } 174 175 return (ENXIO); 176 } 177 178 static struct epic_type * 179 epic_devtype(dev) 180 device_t dev; 181 { 182 struct epic_type *t; 183 184 t = epic_devs; 185 186 while (t->name != NULL) { 187 if ((pci_get_vendor(dev) == t->ven_id) && 188 (pci_get_device(dev) == t->dev_id)) { 189 return (t); 190 } 191 t++; 192 } 193 return (NULL); 194 } 195 196 #ifdef EPIC_USEIOSPACE 197 #define EPIC_RES SYS_RES_IOPORT 198 #define EPIC_RID PCIR_BASEIO 199 #else 200 #define EPIC_RES SYS_RES_MEMORY 201 #define EPIC_RID PCIR_BASEMEM 202 #endif 203 204 static void 205 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 206 { 207 u_int32_t *addr; 208 209 if (error) 210 return; 211 212 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 213 addr = arg; 214 *addr = segs->ds_addr; 215 } 216 217 /* 218 * Attach routine: map registers, allocate softc, rings and descriptors. 219 * Reset to known state. 220 */ 221 static int 222 epic_attach(dev) 223 device_t dev; 224 { 225 struct ifnet *ifp; 226 epic_softc_t *sc; 227 int unit, error; 228 int i, s, rid, tmp; 229 230 s = splimp(); 231 232 sc = device_get_softc(dev); 233 unit = device_get_unit(dev); 234 235 /* Preinitialize softc structure. */ 236 sc->unit = unit; 237 sc->dev = dev; 238 239 /* Fill ifnet structure. */ 240 ifp = &sc->sc_if; 241 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 242 ifp->if_softc = sc; 243 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST|IFF_NEEDSGIANT; 244 ifp->if_ioctl = epic_ifioctl; 245 ifp->if_start = epic_ifstart; 246 ifp->if_watchdog = epic_ifwatchdog; 247 ifp->if_init = epic_init; 248 ifp->if_timer = 0; 249 ifp->if_baudrate = 10000000; 250 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1; 251 252 /* Enable busmastering. */ 253 pci_enable_busmaster(dev); 254 255 rid = EPIC_RID; 256 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE); 257 if (sc->res == NULL) { 258 device_printf(dev, "couldn't map ports/memory\n"); 259 error = ENXIO; 260 goto fail; 261 } 262 263 sc->sc_st = rman_get_bustag(sc->res); 264 sc->sc_sh = rman_get_bushandle(sc->res); 265 266 /* Allocate interrupt. */ 267 rid = 0; 268 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 269 RF_SHAREABLE | RF_ACTIVE); 270 if (sc->irq == NULL) { 271 device_printf(dev, "couldn't map interrupt\n"); 272 error = ENXIO; 273 goto fail; 274 } 275 276 /* Allocate DMA tags. */ 277 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 278 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * EPIC_MAX_FRAGS, 279 EPIC_MAX_FRAGS, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->mtag); 280 if (error) { 281 device_printf(dev, "couldn't allocate dma tag\n"); 282 goto fail; 283 } 284 285 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 286 BUS_SPACE_MAXADDR, NULL, NULL, 287 sizeof(struct epic_rx_desc) * RX_RING_SIZE, 288 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, busdma_lock_mutex, 289 &Giant, &sc->rtag); 290 if (error) { 291 device_printf(dev, "couldn't allocate dma tag\n"); 292 goto fail; 293 } 294 295 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 296 BUS_SPACE_MAXADDR, NULL, NULL, 297 sizeof(struct epic_tx_desc) * TX_RING_SIZE, 298 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0, 299 busdma_lock_mutex, &Giant, &sc->ttag); 300 if (error) { 301 device_printf(dev, "couldn't allocate dma tag\n"); 302 goto fail; 303 } 304 305 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 306 BUS_SPACE_MAXADDR, NULL, NULL, 307 sizeof(struct epic_frag_list) * TX_RING_SIZE, 308 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0, 309 busdma_lock_mutex, &Giant, &sc->ftag); 310 if (error) { 311 device_printf(dev, "couldn't allocate dma tag\n"); 312 goto fail; 313 } 314 315 /* Allocate DMA safe memory and get the DMA addresses. */ 316 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist, 317 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap); 318 if (error) { 319 device_printf(dev, "couldn't allocate dma memory\n"); 320 goto fail; 321 } 322 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist, 323 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr, 324 &sc->frag_addr, 0); 325 if (error) { 326 device_printf(dev, "couldn't map dma memory\n"); 327 goto fail; 328 } 329 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc, 330 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap); 331 if (error) { 332 device_printf(dev, "couldn't allocate dma memory\n"); 333 goto fail; 334 } 335 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc, 336 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr, 337 &sc->tx_addr, 0); 338 if (error) { 339 device_printf(dev, "couldn't map dma memory\n"); 340 goto fail; 341 } 342 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc, 343 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap); 344 if (error) { 345 device_printf(dev, "couldn't allocate dma memory\n"); 346 goto fail; 347 } 348 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc, 349 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr, 350 &sc->rx_addr, 0); 351 if (error) { 352 device_printf(dev, "couldn't map dma memory\n"); 353 goto fail; 354 } 355 356 /* Bring the chip out of low-power mode. */ 357 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 358 DELAY(500); 359 360 /* Workaround for Application Note 7-15. */ 361 for (i = 0; i < 16; i++) 362 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 363 364 /* Read MAC address from EEPROM. */ 365 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++) 366 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i); 367 368 /* Set Non-Volatile Control Register from EEPROM. */ 369 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); 370 371 /* Set defaults. */ 372 sc->tx_threshold = TRANSMIT_THRESHOLD; 373 sc->txcon = TXCON_DEFAULT; 374 sc->miicfg = MIICFG_SMI_ENABLE; 375 sc->phyid = EPIC_UNKN_PHY; 376 sc->serinst = -1; 377 378 /* Fetch card id. */ 379 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2); 380 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2); 381 382 if (sc->cardvend != SMC_VENDORID) 383 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend); 384 385 /* Do ifmedia setup. */ 386 if (mii_phy_probe(dev, &sc->miibus, 387 epic_ifmedia_upd, epic_ifmedia_sts)) { 388 device_printf(dev, "ERROR! MII without any PHY!?\n"); 389 error = ENXIO; 390 goto fail; 391 } 392 393 /* board type and ... */ 394 printf(" type "); 395 for(i = 0x2c; i < 0x32; i++) { 396 tmp = epic_read_eeprom(sc, i); 397 if (' ' == (u_int8_t)tmp) 398 break; 399 printf("%c", (u_int8_t)tmp); 400 tmp >>= 8; 401 if (' ' == (u_int8_t)tmp) 402 break; 403 printf("%c", (u_int8_t)tmp); 404 } 405 printf("\n"); 406 407 /* Initialize rings. */ 408 if (epic_init_rings(sc)) { 409 device_printf(dev, "failed to init rings\n"); 410 error = ENXIO; 411 goto fail; 412 } 413 414 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 415 ifp->if_capabilities |= IFCAP_VLAN_MTU; 416 ifp->if_capenable |= IFCAP_VLAN_MTU; 417 callout_handle_init(&sc->stat_ch); 418 419 /* Activate our interrupt handler. */ 420 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 421 epic_intr, sc, &sc->sc_ih); 422 if (error) { 423 device_printf(dev, "couldn't set up irq\n"); 424 goto fail; 425 } 426 427 /* Attach to OS's managers. */ 428 ether_ifattach(ifp, sc->sc_macaddr); 429 430 splx(s); 431 return (0); 432 fail: 433 epic_release(sc); 434 splx(s); 435 return (error); 436 } 437 438 /* 439 * Free any resources allocated by the driver. 440 */ 441 static void 442 epic_release(epic_softc_t *sc) 443 { 444 445 if (sc->irq) 446 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 447 if (sc->res) 448 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res); 449 epic_free_rings(sc); 450 if (sc->tx_flist) { 451 bus_dmamap_unload(sc->ftag, sc->fmap); 452 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap); 453 bus_dmamap_destroy(sc->ftag, sc->fmap); 454 } 455 if (sc->tx_desc) { 456 bus_dmamap_unload(sc->ttag, sc->tmap); 457 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap); 458 bus_dmamap_destroy(sc->ttag, sc->tmap); 459 } 460 if (sc->rx_desc) { 461 bus_dmamap_unload(sc->rtag, sc->rmap); 462 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap); 463 bus_dmamap_destroy(sc->rtag, sc->rmap); 464 } 465 if (sc->mtag) 466 bus_dma_tag_destroy(sc->mtag); 467 if (sc->ftag) 468 bus_dma_tag_destroy(sc->ftag); 469 if (sc->ttag) 470 bus_dma_tag_destroy(sc->ttag); 471 if (sc->rtag) 472 bus_dma_tag_destroy(sc->rtag); 473 } 474 475 /* 476 * Detach driver and free resources. 477 */ 478 static int 479 epic_detach(dev) 480 device_t dev; 481 { 482 struct ifnet *ifp; 483 epic_softc_t *sc; 484 int s; 485 486 s = splimp(); 487 488 sc = device_get_softc(dev); 489 ifp = &sc->arpcom.ac_if; 490 491 ether_ifdetach(ifp); 492 493 epic_stop(sc); 494 495 bus_generic_detach(dev); 496 device_delete_child(dev, sc->miibus); 497 498 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 499 epic_release(sc); 500 splx(s); 501 return (0); 502 } 503 504 #undef EPIC_RES 505 #undef EPIC_RID 506 507 /* 508 * Stop all chip I/O so that the kernel's probe routines don't 509 * get confused by errant DMAs when rebooting. 510 */ 511 static void 512 epic_shutdown(dev) 513 device_t dev; 514 { 515 epic_softc_t *sc; 516 517 sc = device_get_softc(dev); 518 519 epic_stop(sc); 520 } 521 522 /* 523 * This is if_ioctl handler. 524 */ 525 static int 526 epic_ifioctl(ifp, command, data) 527 struct ifnet *ifp; 528 u_long command; 529 caddr_t data; 530 { 531 epic_softc_t *sc = ifp->if_softc; 532 struct mii_data *mii; 533 struct ifreq *ifr = (struct ifreq *) data; 534 int x, error = 0; 535 536 x = splimp(); 537 538 switch (command) { 539 case SIOCSIFMTU: 540 if (ifp->if_mtu == ifr->ifr_mtu) 541 break; 542 543 /* XXX Though the datasheet doesn't imply any 544 * limitations on RX and TX sizes beside max 64Kb 545 * DMA transfer, seems we can't send more then 1600 546 * data bytes per ethernet packet (transmitter hangs 547 * up if more data is sent). 548 */ 549 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) { 550 ifp->if_mtu = ifr->ifr_mtu; 551 epic_stop(sc); 552 epic_init(sc); 553 } else 554 error = EINVAL; 555 break; 556 557 case SIOCSIFFLAGS: 558 /* 559 * If the interface is marked up and stopped, then start it. 560 * If it is marked down and running, then stop it. 561 */ 562 if (ifp->if_flags & IFF_UP) { 563 if ((ifp->if_flags & IFF_RUNNING) == 0) { 564 epic_init(sc); 565 break; 566 } 567 } else { 568 if (ifp->if_flags & IFF_RUNNING) { 569 epic_stop(sc); 570 break; 571 } 572 } 573 574 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */ 575 epic_stop_activity(sc); 576 epic_set_mc_table(sc); 577 epic_set_rx_mode(sc); 578 epic_start_activity(sc); 579 break; 580 581 case SIOCADDMULTI: 582 case SIOCDELMULTI: 583 epic_set_mc_table(sc); 584 error = 0; 585 break; 586 587 case SIOCSIFMEDIA: 588 case SIOCGIFMEDIA: 589 mii = device_get_softc(sc->miibus); 590 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 591 break; 592 593 default: 594 error = ether_ioctl(ifp, command, data); 595 break; 596 } 597 splx(x); 598 return (error); 599 } 600 601 static void 602 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 603 bus_size_t mapsize, int error) 604 { 605 struct epic_frag_list *flist; 606 int i; 607 608 if (error) 609 return; 610 611 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments")); 612 flist = arg; 613 /* Fill fragments list. */ 614 for (i = 0; i < nseg; i++) { 615 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 616 flist->frag[i].fraglen = segs[i].ds_len; 617 flist->frag[i].fragaddr = segs[i].ds_addr; 618 } 619 flist->numfrags = nseg; 620 } 621 622 static void 623 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 624 bus_size_t mapsize, int error) 625 { 626 struct epic_rx_desc *desc; 627 628 if (error) 629 return; 630 631 KASSERT(nseg == 1, ("too many DMA segments")); 632 desc = arg; 633 desc->bufaddr = segs->ds_addr; 634 } 635 636 /* 637 * This is if_start handler. It takes mbufs from if_snd queue 638 * and queue them for transmit, one by one, until TX ring become full 639 * or queue become empty. 640 */ 641 static void 642 epic_ifstart(ifp) 643 struct ifnet * ifp; 644 { 645 epic_softc_t *sc = ifp->if_softc; 646 struct epic_tx_buffer *buf; 647 struct epic_tx_desc *desc; 648 struct epic_frag_list *flist; 649 struct mbuf *m0, *m; 650 int error; 651 652 while (sc->pending_txs < TX_RING_SIZE) { 653 buf = sc->tx_buffer + sc->cur_tx; 654 desc = sc->tx_desc + sc->cur_tx; 655 flist = sc->tx_flist + sc->cur_tx; 656 657 /* Get next packet to send. */ 658 IF_DEQUEUE(&ifp->if_snd, m0); 659 660 /* If nothing to send, return. */ 661 if (m0 == NULL) 662 return; 663 664 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0, 665 epic_dma_map_txbuf, flist, 0); 666 667 if (error && error != EFBIG) { 668 m_freem(m0); 669 ifp->if_oerrors++; 670 continue; 671 } 672 673 /* 674 * If packet was more than EPIC_MAX_FRAGS parts, 675 * recopy packet to a newly allocated mbuf cluster. 676 */ 677 if (error) { 678 m = m_defrag(m0, M_DONTWAIT); 679 if (m == NULL) { 680 m_freem(m0); 681 ifp->if_oerrors++; 682 continue; 683 } 684 m_freem(m0); 685 m0 = m; 686 687 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m, 688 epic_dma_map_txbuf, flist, 0); 689 if (error) { 690 m_freem(m); 691 ifp->if_oerrors++; 692 continue; 693 } 694 } 695 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE); 696 697 buf->mbuf = m0; 698 sc->pending_txs++; 699 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 700 desc->control = 0x01; 701 desc->txlength = 702 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN); 703 desc->status = 0x8000; 704 bus_dmamap_sync(sc->ttag, sc->tmap, 705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 706 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE); 707 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); 708 709 /* Set watchdog timer. */ 710 ifp->if_timer = 8; 711 712 BPF_MTAP(ifp, m0); 713 } 714 715 ifp->if_flags |= IFF_OACTIVE; 716 } 717 718 /* 719 * Synopsis: Finish all received frames. 720 */ 721 static void 722 epic_rx_done(sc) 723 epic_softc_t *sc; 724 { 725 struct ifnet *ifp = &sc->sc_if; 726 u_int16_t len; 727 struct epic_rx_buffer *buf; 728 struct epic_rx_desc *desc; 729 struct mbuf *m; 730 bus_dmamap_t map; 731 int error; 732 733 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD); 734 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) { 735 buf = sc->rx_buffer + sc->cur_rx; 736 desc = sc->rx_desc + sc->cur_rx; 737 738 /* Switch to next descriptor. */ 739 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK; 740 741 /* 742 * Check for RX errors. This should only happen if 743 * SAVE_ERRORED_PACKETS is set. RX errors generate 744 * RXE interrupt usually. 745 */ 746 if ((desc->status & 1) == 0) { 747 ifp->if_ierrors++; 748 desc->status = 0x8000; 749 continue; 750 } 751 752 /* Save packet length and mbuf contained packet. */ 753 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD); 754 len = desc->rxlength - ETHER_CRC_LEN; 755 m = buf->mbuf; 756 757 /* Try to get an mbuf cluster. */ 758 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 759 if (buf->mbuf == NULL) { 760 buf->mbuf = m; 761 desc->status = 0x8000; 762 ifp->if_ierrors++; 763 continue; 764 } 765 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES; 766 m_adj(buf->mbuf, ETHER_ALIGN); 767 768 /* Point to new mbuf, and give descriptor to chip. */ 769 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf, 770 epic_dma_map_rxbuf, desc, 0); 771 if (error) { 772 buf->mbuf = m; 773 desc->status = 0x8000; 774 ifp->if_ierrors++; 775 continue; 776 } 777 778 desc->status = 0x8000; 779 bus_dmamap_unload(sc->mtag, buf->map); 780 map = buf->map; 781 buf->map = sc->sparemap; 782 sc->sparemap = map; 783 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD); 784 785 /* First mbuf in packet holds the ethernet and packet headers */ 786 m->m_pkthdr.rcvif = ifp; 787 m->m_pkthdr.len = m->m_len = len; 788 789 /* Give mbuf to OS. */ 790 (*ifp->if_input)(ifp, m); 791 792 /* Successfuly received frame */ 793 ifp->if_ipackets++; 794 } 795 bus_dmamap_sync(sc->rtag, sc->rmap, 796 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 797 } 798 799 /* 800 * Synopsis: Do last phase of transmission. I.e. if desc is 801 * transmitted, decrease pending_txs counter, free mbuf contained 802 * packet, switch to next descriptor and repeat until no packets 803 * are pending or descriptor is not transmitted yet. 804 */ 805 static void 806 epic_tx_done(sc) 807 epic_softc_t *sc; 808 { 809 struct epic_tx_buffer *buf; 810 struct epic_tx_desc *desc; 811 u_int16_t status; 812 813 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD); 814 while (sc->pending_txs > 0) { 815 buf = sc->tx_buffer + sc->dirty_tx; 816 desc = sc->tx_desc + sc->dirty_tx; 817 status = desc->status; 818 819 /* 820 * If packet is not transmitted, thou followed 821 * packets are not transmitted too. 822 */ 823 if (status & 0x8000) 824 break; 825 826 /* Packet is transmitted. Switch to next and free mbuf. */ 827 sc->pending_txs--; 828 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK; 829 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE); 830 bus_dmamap_unload(sc->mtag, buf->map); 831 m_freem(buf->mbuf); 832 buf->mbuf = NULL; 833 834 /* Check for errors and collisions. */ 835 if (status & 0x0001) 836 sc->sc_if.if_opackets++; 837 else 838 sc->sc_if.if_oerrors++; 839 sc->sc_if.if_collisions += (status >> 8) & 0x1F; 840 #ifdef EPIC_DIAG 841 if ((status & 0x1001) == 0x1001) 842 device_printf(sc->dev, 843 "Tx ERROR: excessive coll. number\n"); 844 #endif 845 } 846 847 if (sc->pending_txs < TX_RING_SIZE) 848 sc->sc_if.if_flags &= ~IFF_OACTIVE; 849 bus_dmamap_sync(sc->ttag, sc->tmap, 850 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 851 } 852 853 /* 854 * Interrupt function 855 */ 856 static void 857 epic_intr(arg) 858 void *arg; 859 { 860 epic_softc_t *sc; 861 int status, i; 862 863 sc = arg; 864 i = 4; 865 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { 866 CSR_WRITE_4(sc, INTSTAT, status); 867 868 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) { 869 epic_rx_done(sc); 870 if (status & (INTSTAT_RQE|INTSTAT_OVW)) { 871 #ifdef EPIC_DIAG 872 if (status & INTSTAT_OVW) 873 device_printf(sc->dev, "RX buffer overflow\n"); 874 if (status & INTSTAT_RQE) 875 device_printf(sc->dev, "RX FIFO overflow\n"); 876 #endif 877 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0) 878 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); 879 sc->sc_if.if_ierrors++; 880 } 881 } 882 883 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) { 884 epic_tx_done(sc); 885 if (sc->sc_if.if_snd.ifq_head != NULL) 886 epic_ifstart(&sc->sc_if); 887 } 888 889 /* Check for rare errors */ 890 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 891 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) { 892 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 893 INTSTAT_APE|INTSTAT_DPE)) { 894 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n", 895 (status & INTSTAT_PMA) ? "PMA " : "", 896 (status & INTSTAT_PTA) ? "PTA " : "", 897 (status & INTSTAT_APE) ? "APE " : "", 898 (status & INTSTAT_DPE) ? "DPE" : ""); 899 900 epic_stop(sc); 901 epic_init(sc); 902 break; 903 } 904 905 if (status & INTSTAT_RXE) { 906 #ifdef EPIC_DIAG 907 device_printf(sc->dev, "CRC/Alignment error\n"); 908 #endif 909 sc->sc_if.if_ierrors++; 910 } 911 912 if (status & INTSTAT_TXU) { 913 epic_tx_underrun(sc); 914 sc->sc_if.if_oerrors++; 915 } 916 } 917 } 918 919 /* If no packets are pending, then no timeouts. */ 920 if (sc->pending_txs == 0) 921 sc->sc_if.if_timer = 0; 922 } 923 924 /* 925 * Handle the TX underrun error: increase the TX threshold 926 * and restart the transmitter. 927 */ 928 static void 929 epic_tx_underrun(sc) 930 epic_softc_t *sc; 931 { 932 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) { 933 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE; 934 #ifdef EPIC_DIAG 935 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n"); 936 #endif 937 } else { 938 sc->tx_threshold += 0x40; 939 #ifdef EPIC_DIAG 940 device_printf(sc->dev, 941 "Tx UNDERRUN: TX threshold increased to %d\n", 942 sc->tx_threshold); 943 #endif 944 } 945 946 /* We must set TXUGO to reset the stuck transmitter. */ 947 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); 948 949 /* Update the TX threshold */ 950 epic_stop_activity(sc); 951 epic_set_tx_mode(sc); 952 epic_start_activity(sc); 953 } 954 955 /* 956 * Synopsis: This one is called if packets wasn't transmitted 957 * during timeout. Try to deallocate transmitted packets, and 958 * if success continue to work. 959 */ 960 static void 961 epic_ifwatchdog(ifp) 962 struct ifnet *ifp; 963 { 964 epic_softc_t *sc; 965 int x; 966 967 x = splimp(); 968 sc = ifp->if_softc; 969 970 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs); 971 972 /* Try to finish queued packets. */ 973 epic_tx_done(sc); 974 975 /* If not successful. */ 976 if (sc->pending_txs > 0) { 977 ifp->if_oerrors += sc->pending_txs; 978 979 /* Reinitialize board. */ 980 device_printf(sc->dev, "reinitialization\n"); 981 epic_stop(sc); 982 epic_init(sc); 983 } else 984 device_printf(sc->dev, "seems we can continue normaly\n"); 985 986 /* Start output. */ 987 if (ifp->if_snd.ifq_head) 988 epic_ifstart(ifp); 989 990 splx(x); 991 } 992 993 /* 994 * Despite the name of this function, it doesn't update statistics, it only 995 * helps in autonegotiation process. 996 */ 997 static void 998 epic_stats_update(epic_softc_t * sc) 999 { 1000 struct mii_data * mii; 1001 int s; 1002 1003 s = splimp(); 1004 1005 mii = device_get_softc(sc->miibus); 1006 mii_tick(mii); 1007 1008 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz); 1009 1010 splx(s); 1011 } 1012 1013 /* 1014 * Set media options. 1015 */ 1016 static int 1017 epic_ifmedia_upd(ifp) 1018 struct ifnet *ifp; 1019 { 1020 epic_softc_t *sc; 1021 struct mii_data *mii; 1022 struct ifmedia *ifm; 1023 struct mii_softc *miisc; 1024 int cfg, media; 1025 1026 sc = ifp->if_softc; 1027 mii = device_get_softc(sc->miibus); 1028 ifm = &mii->mii_media; 1029 media = ifm->ifm_cur->ifm_media; 1030 1031 /* Do not do anything if interface is not up. */ 1032 if ((ifp->if_flags & IFF_UP) == 0) 1033 return (0); 1034 1035 /* 1036 * Lookup current selected PHY. 1037 */ 1038 if (IFM_INST(media) == sc->serinst) { 1039 sc->phyid = EPIC_SERIAL; 1040 sc->physc = NULL; 1041 } else { 1042 /* If we're not selecting serial interface, select MII mode. */ 1043 sc->miicfg &= ~MIICFG_SERIAL_ENABLE; 1044 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1045 1046 /* Default to unknown PHY. */ 1047 sc->phyid = EPIC_UNKN_PHY; 1048 1049 /* Lookup selected PHY. */ 1050 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1051 miisc = LIST_NEXT(miisc, mii_list)) { 1052 if (IFM_INST(media) == miisc->mii_inst) { 1053 sc->physc = miisc; 1054 break; 1055 } 1056 } 1057 1058 /* Identify selected PHY. */ 1059 if (sc->physc) { 1060 int id1, id2, model, oui; 1061 1062 id1 = PHY_READ(sc->physc, MII_PHYIDR1); 1063 id2 = PHY_READ(sc->physc, MII_PHYIDR2); 1064 1065 oui = MII_OUI(id1, id2); 1066 model = MII_MODEL(id2); 1067 switch (oui) { 1068 case MII_OUI_QUALSEMI: 1069 if (model == MII_MODEL_QUALSEMI_QS6612) 1070 sc->phyid = EPIC_QS6612_PHY; 1071 break; 1072 case MII_OUI_xxALTIMA: 1073 if (model == MII_MODEL_xxALTIMA_AC101) 1074 sc->phyid = EPIC_AC101_PHY; 1075 break; 1076 case MII_OUI_xxLEVEL1: 1077 if (model == MII_MODEL_xxLEVEL1_LXT970) 1078 sc->phyid = EPIC_LXT970_PHY; 1079 break; 1080 } 1081 } 1082 } 1083 1084 /* 1085 * Do PHY specific card setup. 1086 */ 1087 1088 /* 1089 * Call this, to isolate all not selected PHYs and 1090 * set up selected. 1091 */ 1092 mii_mediachg(mii); 1093 1094 /* Do our own setup. */ 1095 switch (sc->phyid) { 1096 case EPIC_QS6612_PHY: 1097 break; 1098 case EPIC_AC101_PHY: 1099 /* We have to powerup fiber tranceivers. */ 1100 if (IFM_SUBTYPE(media) == IFM_100_FX) 1101 sc->miicfg |= MIICFG_694_ENABLE; 1102 else 1103 sc->miicfg &= ~MIICFG_694_ENABLE; 1104 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1105 1106 break; 1107 case EPIC_LXT970_PHY: 1108 /* We have to powerup fiber tranceivers. */ 1109 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG); 1110 if (IFM_SUBTYPE(media) == IFM_100_FX) 1111 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0; 1112 else 1113 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1114 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg); 1115 1116 break; 1117 case EPIC_SERIAL: 1118 /* Select serial PHY (10base2/BNC usually). */ 1119 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE; 1120 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1121 1122 /* There is no driver to fill this. */ 1123 mii->mii_media_active = media; 1124 mii->mii_media_status = 0; 1125 1126 /* 1127 * We need to call this manually as it wasn't called 1128 * in mii_mediachg(). 1129 */ 1130 epic_miibus_statchg(sc->dev); 1131 break; 1132 default: 1133 device_printf(sc->dev, "ERROR! Unknown PHY selected\n"); 1134 return (EINVAL); 1135 } 1136 1137 return (0); 1138 } 1139 1140 /* 1141 * Report current media status. 1142 */ 1143 static void 1144 epic_ifmedia_sts(ifp, ifmr) 1145 struct ifnet *ifp; 1146 struct ifmediareq *ifmr; 1147 { 1148 epic_softc_t *sc; 1149 struct mii_data *mii; 1150 struct ifmedia *ifm; 1151 1152 sc = ifp->if_softc; 1153 mii = device_get_softc(sc->miibus); 1154 ifm = &mii->mii_media; 1155 1156 /* Nothing should be selected if interface is down. */ 1157 if ((ifp->if_flags & IFF_UP) == 0) { 1158 ifmr->ifm_active = IFM_NONE; 1159 ifmr->ifm_status = 0; 1160 return; 1161 } 1162 1163 /* Call underlying pollstat, if not serial PHY. */ 1164 if (sc->phyid != EPIC_SERIAL) 1165 mii_pollstat(mii); 1166 1167 /* Simply copy media info. */ 1168 ifmr->ifm_active = mii->mii_media_active; 1169 ifmr->ifm_status = mii->mii_media_status; 1170 } 1171 1172 /* 1173 * Callback routine, called on media change. 1174 */ 1175 static void 1176 epic_miibus_statchg(dev) 1177 device_t dev; 1178 { 1179 epic_softc_t *sc; 1180 struct mii_data *mii; 1181 int media; 1182 1183 sc = device_get_softc(dev); 1184 mii = device_get_softc(sc->miibus); 1185 media = mii->mii_media_active; 1186 1187 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX); 1188 1189 /* 1190 * If we are in full-duplex mode or loopback operation, 1191 * we need to decouple receiver and transmitter. 1192 */ 1193 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP)) 1194 sc->txcon |= TXCON_FULL_DUPLEX; 1195 1196 /* On some cards we need manualy set fullduplex led. */ 1197 if (sc->cardid == SMC9432FTX || 1198 sc->cardid == SMC9432FTX_SC) { 1199 if (IFM_OPTIONS(media) & IFM_FDX) 1200 sc->miicfg |= MIICFG_694_ENABLE; 1201 else 1202 sc->miicfg &= ~MIICFG_694_ENABLE; 1203 1204 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1205 } 1206 1207 /* Update baudrate. */ 1208 if (IFM_SUBTYPE(media) == IFM_100_TX || 1209 IFM_SUBTYPE(media) == IFM_100_FX) 1210 sc->sc_if.if_baudrate = 100000000; 1211 else 1212 sc->sc_if.if_baudrate = 10000000; 1213 1214 epic_stop_activity(sc); 1215 epic_set_tx_mode(sc); 1216 epic_start_activity(sc); 1217 } 1218 1219 static void 1220 epic_miibus_mediainit(dev) 1221 device_t dev; 1222 { 1223 epic_softc_t *sc; 1224 struct mii_data *mii; 1225 struct ifmedia *ifm; 1226 int media; 1227 1228 sc = device_get_softc(dev); 1229 mii = device_get_softc(sc->miibus); 1230 ifm = &mii->mii_media; 1231 1232 /* 1233 * Add Serial Media Interface if present, this applies to 1234 * SMC9432BTX serie. 1235 */ 1236 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) { 1237 /* Store its instance. */ 1238 sc->serinst = mii->mii_instance++; 1239 1240 /* Add as 10base2/BNC media. */ 1241 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst); 1242 ifmedia_add(ifm, media, 0, NULL); 1243 1244 /* Report to user. */ 1245 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n"); 1246 } 1247 } 1248 1249 /* 1250 * Reset chip and update media. 1251 */ 1252 static void 1253 epic_init(xsc) 1254 void *xsc; 1255 { 1256 epic_softc_t *sc = xsc; 1257 struct ifnet *ifp = &sc->sc_if; 1258 int s, i; 1259 1260 s = splimp(); 1261 1262 /* If interface is already running, then we need not do anything. */ 1263 if (ifp->if_flags & IFF_RUNNING) { 1264 splx(s); 1265 return; 1266 } 1267 1268 /* Soft reset the chip (we have to power up card before). */ 1269 CSR_WRITE_4(sc, GENCTL, 0); 1270 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1271 1272 /* 1273 * Reset takes 15 pci ticks which depends on PCI bus speed. 1274 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec. 1275 */ 1276 DELAY(500); 1277 1278 /* Wake up */ 1279 CSR_WRITE_4(sc, GENCTL, 0); 1280 1281 /* Workaround for Application Note 7-15 */ 1282 for (i = 0; i < 16; i++) 1283 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 1284 1285 /* Give rings to EPIC */ 1286 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr); 1287 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr); 1288 1289 /* Put node address to EPIC. */ 1290 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]); 1291 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]); 1292 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]); 1293 1294 /* Set tx mode, includeing transmit threshold. */ 1295 epic_set_tx_mode(sc); 1296 1297 /* Compute and set RXCON. */ 1298 epic_set_rx_mode(sc); 1299 1300 /* Set multicast table. */ 1301 epic_set_mc_table(sc); 1302 1303 /* Enable interrupts by setting the interrupt mask. */ 1304 CSR_WRITE_4(sc, INTMASK, 1305 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */ 1306 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU | 1307 INTSTAT_FATAL); 1308 1309 /* Acknowledge all pending interrupts. */ 1310 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); 1311 1312 /* Enable interrupts, set for PCI read multiple and etc */ 1313 CSR_WRITE_4(sc, GENCTL, 1314 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE | 1315 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64); 1316 1317 /* Mark interface running ... */ 1318 if (ifp->if_flags & IFF_UP) 1319 ifp->if_flags |= IFF_RUNNING; 1320 else 1321 ifp->if_flags &= ~IFF_RUNNING; 1322 1323 /* ... and free */ 1324 ifp->if_flags &= ~IFF_OACTIVE; 1325 1326 /* Start Rx process */ 1327 epic_start_activity(sc); 1328 1329 /* Set appropriate media */ 1330 epic_ifmedia_upd(ifp); 1331 1332 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz); 1333 1334 splx(s); 1335 } 1336 1337 /* 1338 * Synopsis: calculate and set Rx mode. Chip must be in idle state to 1339 * access RXCON. 1340 */ 1341 static void 1342 epic_set_rx_mode(sc) 1343 epic_softc_t *sc; 1344 { 1345 u_int32_t flags; 1346 u_int32_t rxcon; 1347 1348 flags = sc->sc_if.if_flags; 1349 rxcon = RXCON_DEFAULT; 1350 1351 #ifdef EPIC_EARLY_RX 1352 rxcon |= RXCON_EARLY_RX; 1353 #endif 1354 1355 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0; 1356 1357 CSR_WRITE_4(sc, RXCON, rxcon); 1358 } 1359 1360 /* 1361 * Synopsis: Set transmit control register. Chip must be in idle state to 1362 * access TXCON. 1363 */ 1364 static void 1365 epic_set_tx_mode(sc) 1366 epic_softc_t *sc; 1367 { 1368 1369 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE) 1370 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold); 1371 1372 CSR_WRITE_4(sc, TXCON, sc->txcon); 1373 } 1374 1375 /* 1376 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC 1377 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch 1378 * individual frames, multicast filter must be manually programmed). 1379 * 1380 * Note: EPIC must be in idle state. 1381 */ 1382 static void 1383 epic_set_mc_table(sc) 1384 epic_softc_t *sc; 1385 { 1386 struct ifnet *ifp; 1387 struct ifmultiaddr *ifma; 1388 u_int16_t filter[4]; 1389 u_int8_t h; 1390 1391 ifp = &sc->sc_if; 1392 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1393 CSR_WRITE_4(sc, MC0, 0xFFFF); 1394 CSR_WRITE_4(sc, MC1, 0xFFFF); 1395 CSR_WRITE_4(sc, MC2, 0xFFFF); 1396 CSR_WRITE_4(sc, MC3, 0xFFFF); 1397 return; 1398 } 1399 1400 filter[0] = 0; 1401 filter[1] = 0; 1402 filter[2] = 0; 1403 filter[3] = 0; 1404 1405 #if __FreeBSD_version < 500000 1406 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1407 #else 1408 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1409 #endif 1410 if (ifma->ifma_addr->sa_family != AF_LINK) 1411 continue; 1412 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1413 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 1414 filter[h >> 4] |= 1 << (h & 0xF); 1415 } 1416 1417 CSR_WRITE_4(sc, MC0, filter[0]); 1418 CSR_WRITE_4(sc, MC1, filter[1]); 1419 CSR_WRITE_4(sc, MC2, filter[2]); 1420 CSR_WRITE_4(sc, MC3, filter[3]); 1421 } 1422 1423 1424 /* 1425 * Synopsis: Start receive process and transmit one, if they need. 1426 */ 1427 static void 1428 epic_start_activity(sc) 1429 epic_softc_t *sc; 1430 { 1431 1432 /* Start rx process. */ 1433 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX | 1434 (sc->pending_txs ? COMMAND_TXQUEUED : 0)); 1435 } 1436 1437 /* 1438 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional 1439 * packet needs to be queued to stop Tx DMA. 1440 */ 1441 static void 1442 epic_stop_activity(sc) 1443 epic_softc_t *sc; 1444 { 1445 int status, i; 1446 1447 /* Stop Tx and Rx DMA. */ 1448 CSR_WRITE_4(sc, COMMAND, 1449 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA); 1450 1451 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */ 1452 for (i = 0; i < 0x1000; i++) { 1453 status = CSR_READ_4(sc, INTSTAT) & 1454 (INTSTAT_TXIDLE | INTSTAT_RXIDLE); 1455 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE)) 1456 break; 1457 DELAY(1); 1458 } 1459 1460 /* Catch all finished packets. */ 1461 epic_rx_done(sc); 1462 epic_tx_done(sc); 1463 1464 status = CSR_READ_4(sc, INTSTAT); 1465 1466 if ((status & INTSTAT_RXIDLE) == 0) 1467 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n"); 1468 1469 if ((status & INTSTAT_TXIDLE) == 0) 1470 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n"); 1471 1472 /* 1473 * May need to queue one more packet if TQE, this is rare 1474 * but existing case. 1475 */ 1476 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE)) 1477 (void)epic_queue_last_packet(sc); 1478 } 1479 1480 /* 1481 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until 1482 * a packet from current descriptor will be copied to internal RAM. We 1483 * compose a dummy packet here and queue it for transmission. 1484 * 1485 * XXX the packet will then be actually sent over network... 1486 */ 1487 static int 1488 epic_queue_last_packet(sc) 1489 epic_softc_t *sc; 1490 { 1491 struct epic_tx_desc *desc; 1492 struct epic_frag_list *flist; 1493 struct epic_tx_buffer *buf; 1494 struct mbuf *m0; 1495 int error, i; 1496 1497 device_printf(sc->dev, "queue last packet\n"); 1498 1499 desc = sc->tx_desc + sc->cur_tx; 1500 flist = sc->tx_flist + sc->cur_tx; 1501 buf = sc->tx_buffer + sc->cur_tx; 1502 1503 if ((desc->status & 0x8000) || (buf->mbuf != NULL)) 1504 return (EBUSY); 1505 1506 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1507 if (m0 == NULL) 1508 return (ENOBUFS); 1509 1510 /* Prepare mbuf. */ 1511 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN); 1512 m0->m_pkthdr.len = m0->m_len; 1513 m0->m_pkthdr.rcvif = &sc->sc_if; 1514 bzero(mtod(m0, caddr_t), m0->m_len); 1515 1516 /* Fill fragments list. */ 1517 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0, 1518 epic_dma_map_txbuf, flist, 0); 1519 if (error) { 1520 m_freem(m0); 1521 return (error); 1522 } 1523 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE); 1524 1525 /* Fill in descriptor. */ 1526 buf->mbuf = m0; 1527 sc->pending_txs++; 1528 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 1529 desc->control = 0x01; 1530 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN); 1531 desc->status = 0x8000; 1532 bus_dmamap_sync(sc->ttag, sc->tmap, 1533 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1534 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE); 1535 1536 /* Launch transmission. */ 1537 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED); 1538 1539 /* Wait Tx DMA to stop (for how long??? XXX) */ 1540 for (i = 0; i < 1000; i++) { 1541 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) 1542 break; 1543 DELAY(1); 1544 } 1545 1546 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) 1547 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n"); 1548 else 1549 epic_tx_done(sc); 1550 1551 return (0); 1552 } 1553 1554 /* 1555 * Synopsis: Shut down board and deallocates rings. 1556 */ 1557 static void 1558 epic_stop(sc) 1559 epic_softc_t *sc; 1560 { 1561 int s; 1562 1563 s = splimp(); 1564 1565 sc->sc_if.if_timer = 0; 1566 1567 untimeout((timeout_t *)epic_stats_update, sc, sc->stat_ch); 1568 1569 /* Disable interrupts */ 1570 CSR_WRITE_4(sc, INTMASK, 0); 1571 CSR_WRITE_4(sc, GENCTL, 0); 1572 1573 /* Try to stop Rx and TX processes */ 1574 epic_stop_activity(sc); 1575 1576 /* Reset chip */ 1577 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1578 DELAY(1000); 1579 1580 /* Make chip go to bed */ 1581 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN); 1582 1583 /* Mark as stoped */ 1584 sc->sc_if.if_flags &= ~IFF_RUNNING; 1585 1586 splx(s); 1587 } 1588 1589 /* 1590 * Synopsis: This function should free all memory allocated for rings. 1591 */ 1592 static void 1593 epic_free_rings(sc) 1594 epic_softc_t *sc; 1595 { 1596 int i; 1597 1598 for (i = 0; i < RX_RING_SIZE; i++) { 1599 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1600 struct epic_rx_desc *desc = sc->rx_desc + i; 1601 1602 desc->status = 0; 1603 desc->buflength = 0; 1604 desc->bufaddr = 0; 1605 1606 if (buf->mbuf) { 1607 bus_dmamap_unload(sc->mtag, buf->map); 1608 bus_dmamap_destroy(sc->mtag, buf->map); 1609 m_freem(buf->mbuf); 1610 } 1611 buf->mbuf = NULL; 1612 } 1613 1614 if (sc->sparemap != NULL) 1615 bus_dmamap_destroy(sc->mtag, sc->sparemap); 1616 1617 for (i = 0; i < TX_RING_SIZE; i++) { 1618 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1619 struct epic_tx_desc *desc = sc->tx_desc + i; 1620 1621 desc->status = 0; 1622 desc->buflength = 0; 1623 desc->bufaddr = 0; 1624 1625 if (buf->mbuf) { 1626 bus_dmamap_unload(sc->mtag, buf->map); 1627 bus_dmamap_destroy(sc->mtag, buf->map); 1628 m_freem(buf->mbuf); 1629 } 1630 buf->mbuf = NULL; 1631 } 1632 } 1633 1634 /* 1635 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them. 1636 * Point Tx descs to fragment lists. Check that all descs and fraglists 1637 * are bounded and aligned properly. 1638 */ 1639 static int 1640 epic_init_rings(sc) 1641 epic_softc_t *sc; 1642 { 1643 int error, i; 1644 1645 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0; 1646 1647 /* Initialize the RX descriptor ring. */ 1648 for (i = 0; i < RX_RING_SIZE; i++) { 1649 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1650 struct epic_rx_desc *desc = sc->rx_desc + i; 1651 1652 desc->status = 0; /* Owned by driver */ 1653 desc->next = sc->rx_addr + 1654 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc); 1655 1656 if ((desc->next & 3) || 1657 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1658 epic_free_rings(sc); 1659 return (EFAULT); 1660 } 1661 1662 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1663 if (buf->mbuf == NULL) { 1664 epic_free_rings(sc); 1665 return (ENOBUFS); 1666 } 1667 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES; 1668 m_adj(buf->mbuf, ETHER_ALIGN); 1669 1670 error = bus_dmamap_create(sc->mtag, 0, &buf->map); 1671 if (error) { 1672 epic_free_rings(sc); 1673 return (error); 1674 } 1675 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf, 1676 epic_dma_map_rxbuf, desc, 0); 1677 if (error) { 1678 epic_free_rings(sc); 1679 return (error); 1680 } 1681 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD); 1682 1683 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */ 1684 desc->status = 0x8000; /* Set owner bit to NIC */ 1685 } 1686 bus_dmamap_sync(sc->rtag, sc->rmap, 1687 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1688 1689 /* Create the spare DMA map. */ 1690 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap); 1691 if (error) { 1692 epic_free_rings(sc); 1693 return (error); 1694 } 1695 1696 /* Initialize the TX descriptor ring. */ 1697 for (i = 0; i < TX_RING_SIZE; i++) { 1698 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1699 struct epic_tx_desc *desc = sc->tx_desc + i; 1700 1701 desc->status = 0; 1702 desc->next = sc->tx_addr + 1703 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc); 1704 1705 if ((desc->next & 3) || 1706 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1707 epic_free_rings(sc); 1708 return (EFAULT); 1709 } 1710 1711 buf->mbuf = NULL; 1712 desc->bufaddr = sc->frag_addr + 1713 i * sizeof(struct epic_frag_list); 1714 1715 if ((desc->bufaddr & 3) || 1716 ((desc->bufaddr & PAGE_MASK) + 1717 sizeof(struct epic_frag_list)) > PAGE_SIZE) { 1718 epic_free_rings(sc); 1719 return (EFAULT); 1720 } 1721 1722 error = bus_dmamap_create(sc->mtag, 0, &buf->map); 1723 if (error) { 1724 epic_free_rings(sc); 1725 return (error); 1726 } 1727 } 1728 bus_dmamap_sync(sc->ttag, sc->tmap, 1729 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1730 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE); 1731 1732 return (0); 1733 } 1734 1735 /* 1736 * EEPROM operation functions 1737 */ 1738 static void 1739 epic_write_eepromreg(sc, val) 1740 epic_softc_t *sc; 1741 u_int8_t val; 1742 { 1743 u_int16_t i; 1744 1745 CSR_WRITE_1(sc, EECTL, val); 1746 1747 for (i = 0; i < 0xFF; i++) { 1748 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) 1749 break; 1750 } 1751 } 1752 1753 static u_int8_t 1754 epic_read_eepromreg(sc) 1755 epic_softc_t *sc; 1756 { 1757 1758 return (CSR_READ_1(sc, EECTL)); 1759 } 1760 1761 static u_int8_t 1762 epic_eeprom_clock(sc, val) 1763 epic_softc_t *sc; 1764 u_int8_t val; 1765 { 1766 1767 epic_write_eepromreg(sc, val); 1768 epic_write_eepromreg(sc, (val | 0x4)); 1769 epic_write_eepromreg(sc, val); 1770 1771 return (epic_read_eepromreg(sc)); 1772 } 1773 1774 static void 1775 epic_output_eepromw(sc, val) 1776 epic_softc_t *sc; 1777 u_int16_t val; 1778 { 1779 int i; 1780 1781 for (i = 0xF; i >= 0; i--) { 1782 if (val & (1 << i)) 1783 epic_eeprom_clock(sc, 0x0B); 1784 else 1785 epic_eeprom_clock(sc, 0x03); 1786 } 1787 } 1788 1789 static u_int16_t 1790 epic_input_eepromw(sc) 1791 epic_softc_t *sc; 1792 { 1793 u_int16_t retval = 0; 1794 int i; 1795 1796 for (i = 0xF; i >= 0; i--) { 1797 if (epic_eeprom_clock(sc, 0x3) & 0x10) 1798 retval |= (1 << i); 1799 } 1800 1801 return (retval); 1802 } 1803 1804 static int 1805 epic_read_eeprom(sc, loc) 1806 epic_softc_t *sc; 1807 u_int16_t loc; 1808 { 1809 u_int16_t dataval; 1810 u_int16_t read_cmd; 1811 1812 epic_write_eepromreg(sc, 3); 1813 1814 if (epic_read_eepromreg(sc) & 0x40) 1815 read_cmd = (loc & 0x3F) | 0x180; 1816 else 1817 read_cmd = (loc & 0xFF) | 0x600; 1818 1819 epic_output_eepromw(sc, read_cmd); 1820 1821 dataval = epic_input_eepromw(sc); 1822 1823 epic_write_eepromreg(sc, 1); 1824 1825 return (dataval); 1826 } 1827 1828 /* 1829 * Here goes MII read/write routines. 1830 */ 1831 static int 1832 epic_read_phy_reg(sc, phy, reg) 1833 epic_softc_t *sc; 1834 int phy, reg; 1835 { 1836 int i; 1837 1838 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01)); 1839 1840 for (i = 0; i < 0x100; i++) { 1841 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) 1842 break; 1843 DELAY(1); 1844 } 1845 1846 return (CSR_READ_4(sc, MIIDATA)); 1847 } 1848 1849 static void 1850 epic_write_phy_reg(sc, phy, reg, val) 1851 epic_softc_t *sc; 1852 int phy, reg, val; 1853 { 1854 int i; 1855 1856 CSR_WRITE_4(sc, MIIDATA, val); 1857 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02)); 1858 1859 for(i = 0; i < 0x100; i++) { 1860 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) 1861 break; 1862 DELAY(1); 1863 } 1864 } 1865 1866 static int 1867 epic_miibus_readreg(dev, phy, reg) 1868 device_t dev; 1869 int phy, reg; 1870 { 1871 epic_softc_t *sc; 1872 1873 sc = device_get_softc(dev); 1874 1875 return (PHY_READ_2(sc, phy, reg)); 1876 } 1877 1878 static int 1879 epic_miibus_writereg(dev, phy, reg, data) 1880 device_t dev; 1881 int phy, reg, data; 1882 { 1883 epic_softc_t *sc; 1884 1885 sc = device_get_softc(dev); 1886 1887 PHY_WRITE_2(sc, phy, reg, data); 1888 1889 return (0); 1890 }
Cache object: d049e9ee38a74239ec61ce16dbe3721b
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