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sys/dev/uart/uart_dev_ns8250.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <machine/bus.h> 43 44 #ifdef FDT 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #endif 49 50 #include <dev/uart/uart.h> 51 #include <dev/uart/uart_cpu.h> 52 #ifdef FDT 53 #include <dev/uart/uart_cpu_fdt.h> 54 #endif 55 #include <dev/uart/uart_bus.h> 56 #include <dev/uart/uart_dev_ns8250.h> 57 #include <dev/uart/uart_ppstypes.h> 58 #ifdef DEV_ACPI 59 #include <dev/uart/uart_cpu_acpi.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #endif 62 63 #include <dev/ic/ns16550.h> 64 65 #include "uart_if.h" 66 67 #define DEFAULT_RCLK 1843200 68 69 /* 70 * Set the default baudrate tolerance to 3.0%. 71 * 72 * Some embedded boards have odd reference clocks (eg 25MHz) 73 * and we need to handle higher variances in the target baud rate. 74 */ 75 #ifndef UART_DEV_TOLERANCE_PCT 76 #define UART_DEV_TOLERANCE_PCT 30 77 #endif /* UART_DEV_TOLERANCE_PCT */ 78 79 static int broken_txfifo = 0; 80 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 81 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 82 83 /* 84 * Clear pending interrupts. THRE is cleared by reading IIR. Data 85 * that may have been received gets lost here. 86 */ 87 static void 88 ns8250_clrint(struct uart_bas *bas) 89 { 90 uint8_t iir, lsr; 91 92 iir = uart_getreg(bas, REG_IIR); 93 while ((iir & IIR_NOPEND) == 0) { 94 iir &= IIR_IMASK; 95 if (iir == IIR_RLS) { 96 lsr = uart_getreg(bas, REG_LSR); 97 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 98 (void)uart_getreg(bas, REG_DATA); 99 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 100 (void)uart_getreg(bas, REG_DATA); 101 else if (iir == IIR_MLSC) 102 (void)uart_getreg(bas, REG_MSR); 103 uart_barrier(bas); 104 iir = uart_getreg(bas, REG_IIR); 105 } 106 } 107 108 static int 109 ns8250_delay(struct uart_bas *bas) 110 { 111 int divisor; 112 u_char lcr; 113 114 lcr = uart_getreg(bas, REG_LCR); 115 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 116 uart_barrier(bas); 117 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 118 uart_barrier(bas); 119 uart_setreg(bas, REG_LCR, lcr); 120 uart_barrier(bas); 121 122 /* 1/10th the time to transmit 1 character (estimate). */ 123 if (divisor <= 134) 124 return (16000000 * divisor / bas->rclk); 125 return (16000 * divisor / (bas->rclk / 1000)); 126 } 127 128 static int 129 ns8250_divisor(int rclk, int baudrate) 130 { 131 int actual_baud, divisor; 132 int error; 133 134 if (baudrate == 0) 135 return (0); 136 137 divisor = (rclk / (baudrate << 3) + 1) >> 1; 138 if (divisor == 0 || divisor >= 65536) 139 return (0); 140 actual_baud = rclk / (divisor << 4); 141 142 /* 10 times error in percent: */ 143 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 144 145 /* enforce maximum error tolerance: */ 146 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 147 return (0); 148 149 return (divisor); 150 } 151 152 static int 153 ns8250_drain(struct uart_bas *bas, int what) 154 { 155 int delay, limit; 156 157 delay = ns8250_delay(bas); 158 159 if (what & UART_DRAIN_TRANSMITTER) { 160 /* 161 * Pick an arbitrary high limit to avoid getting stuck in 162 * an infinite loop when the hardware is broken. Make the 163 * limit high enough to handle large FIFOs. 164 */ 165 limit = 10*1024; 166 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 167 DELAY(delay); 168 if (limit == 0) { 169 /* printf("ns8250: transmitter appears stuck... "); */ 170 return (EIO); 171 } 172 } 173 174 if (what & UART_DRAIN_RECEIVER) { 175 /* 176 * Pick an arbitrary high limit to avoid getting stuck in 177 * an infinite loop when the hardware is broken. Make the 178 * limit high enough to handle large FIFOs and integrated 179 * UARTs. The HP rx2600 for example has 3 UARTs on the 180 * management board that tend to get a lot of data send 181 * to it when the UART is first activated. Assume that we 182 * have finished draining if LSR_RXRDY is not asserted both 183 * prior to and after a DELAY; but as long as LSR_RXRDY is 184 * asserted, read (and discard) characters as quickly as 185 * possible. 186 */ 187 limit=10*4096; 188 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 189 do { 190 (void)uart_getreg(bas, REG_DATA); 191 uart_barrier(bas); 192 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 193 uart_barrier(bas); 194 DELAY(delay << 2); 195 } 196 if (limit == 0) { 197 /* printf("ns8250: receiver appears broken... "); */ 198 return (EIO); 199 } 200 } 201 202 return (0); 203 } 204 205 /* 206 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 207 * drained. WARNING: this function clobbers the FIFO setting! 208 */ 209 static void 210 ns8250_flush(struct uart_bas *bas, int what) 211 { 212 uint8_t fcr; 213 uint8_t lsr; 214 int drain = 0; 215 216 fcr = FCR_ENABLE; 217 #ifdef CPU_XBURST 218 fcr |= FCR_UART_ON; 219 #endif 220 if (what & UART_FLUSH_TRANSMITTER) 221 fcr |= FCR_XMT_RST; 222 if (what & UART_FLUSH_RECEIVER) 223 fcr |= FCR_RCV_RST; 224 uart_setreg(bas, REG_FCR, fcr); 225 uart_barrier(bas); 226 227 /* 228 * Detect and work around emulated UARTs which don't implement the 229 * FCR register; on these systems we need to drain the FIFO since 230 * the flush we request doesn't happen. One such system is the 231 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 232 * https://github.com/rust-vmm/vm-superio/issues/83 233 */ 234 lsr = uart_getreg(bas, REG_LSR); 235 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 236 drain |= UART_DRAIN_TRANSMITTER; 237 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 238 drain |= UART_DRAIN_RECEIVER; 239 if (drain != 0) { 240 printf("ns8250: UART FCR is broken\n"); 241 ns8250_drain(bas, drain); 242 } 243 } 244 245 static int 246 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 247 int parity) 248 { 249 int divisor; 250 uint8_t lcr; 251 252 lcr = 0; 253 if (databits >= 8) 254 lcr |= LCR_8BITS; 255 else if (databits == 7) 256 lcr |= LCR_7BITS; 257 else if (databits == 6) 258 lcr |= LCR_6BITS; 259 else 260 lcr |= LCR_5BITS; 261 if (stopbits > 1) 262 lcr |= LCR_STOPB; 263 lcr |= parity << 3; 264 265 /* Set baudrate. */ 266 if (baudrate > 0) { 267 divisor = ns8250_divisor(bas->rclk, baudrate); 268 if (divisor == 0) 269 return (EINVAL); 270 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 271 uart_barrier(bas); 272 uart_setreg(bas, REG_DLL, divisor & 0xff); 273 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 274 uart_barrier(bas); 275 } 276 277 /* Set LCR and clear DLAB. */ 278 uart_setreg(bas, REG_LCR, lcr); 279 uart_barrier(bas); 280 return (0); 281 } 282 283 /* 284 * Low-level UART interface. 285 */ 286 static int ns8250_probe(struct uart_bas *bas); 287 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 288 static void ns8250_term(struct uart_bas *bas); 289 static void ns8250_putc(struct uart_bas *bas, int); 290 static int ns8250_rxready(struct uart_bas *bas); 291 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 292 293 struct uart_ops uart_ns8250_ops = { 294 .probe = ns8250_probe, 295 .init = ns8250_init, 296 .term = ns8250_term, 297 .putc = ns8250_putc, 298 .rxready = ns8250_rxready, 299 .getc = ns8250_getc, 300 }; 301 302 static int 303 ns8250_probe(struct uart_bas *bas) 304 { 305 u_char val; 306 307 #ifdef CPU_XBURST 308 uart_setreg(bas, REG_FCR, FCR_UART_ON); 309 #endif 310 311 /* Check known 0 bits that don't depend on DLAB. */ 312 val = uart_getreg(bas, REG_IIR); 313 if (val & 0x30) 314 return (ENXIO); 315 /* 316 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 317 * chip, but otherwise doesn't seem to have a function. In 318 * other words, uart(4) works regardless. Ignore that bit so 319 * the probe succeeds. 320 */ 321 val = uart_getreg(bas, REG_MCR); 322 if (val & 0xa0) 323 return (ENXIO); 324 325 return (0); 326 } 327 328 static void 329 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 330 int parity) 331 { 332 u_char ier, val; 333 334 if (bas->rclk == 0) 335 bas->rclk = DEFAULT_RCLK; 336 ns8250_param(bas, baudrate, databits, stopbits, parity); 337 338 /* Disable all interrupt sources. */ 339 /* 340 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 341 * UARTs split the receive time-out interrupt bit out separately as 342 * 0x10. This gets handled by ier_mask and ier_rxbits below. 343 */ 344 ier = uart_getreg(bas, REG_IER) & 0xe0; 345 uart_setreg(bas, REG_IER, ier); 346 uart_barrier(bas); 347 348 /* Disable the FIFO (if present). */ 349 val = 0; 350 #ifdef CPU_XBURST 351 val |= FCR_UART_ON; 352 #endif 353 uart_setreg(bas, REG_FCR, val); 354 uart_barrier(bas); 355 356 /* Set RTS & DTR. */ 357 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 358 uart_barrier(bas); 359 360 ns8250_clrint(bas); 361 } 362 363 static void 364 ns8250_term(struct uart_bas *bas) 365 { 366 367 /* Clear RTS & DTR. */ 368 uart_setreg(bas, REG_MCR, MCR_IE); 369 uart_barrier(bas); 370 } 371 372 static void 373 ns8250_putc(struct uart_bas *bas, int c) 374 { 375 int limit; 376 377 limit = 250000; 378 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 379 DELAY(4); 380 uart_setreg(bas, REG_DATA, c); 381 uart_barrier(bas); 382 } 383 384 static int 385 ns8250_rxready(struct uart_bas *bas) 386 { 387 388 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 389 } 390 391 static int 392 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 393 { 394 int c; 395 396 uart_lock(hwmtx); 397 398 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 399 uart_unlock(hwmtx); 400 DELAY(4); 401 uart_lock(hwmtx); 402 } 403 404 c = uart_getreg(bas, REG_DATA); 405 406 uart_unlock(hwmtx); 407 408 return (c); 409 } 410 411 static kobj_method_t ns8250_methods[] = { 412 KOBJMETHOD(uart_attach, ns8250_bus_attach), 413 KOBJMETHOD(uart_detach, ns8250_bus_detach), 414 KOBJMETHOD(uart_flush, ns8250_bus_flush), 415 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 416 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 417 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 418 KOBJMETHOD(uart_param, ns8250_bus_param), 419 KOBJMETHOD(uart_probe, ns8250_bus_probe), 420 KOBJMETHOD(uart_receive, ns8250_bus_receive), 421 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 422 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 423 KOBJMETHOD(uart_grab, ns8250_bus_grab), 424 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 425 { 0, 0 } 426 }; 427 428 struct uart_class uart_ns8250_class = { 429 "ns8250", 430 ns8250_methods, 431 sizeof(struct ns8250_softc), 432 .uc_ops = &uart_ns8250_ops, 433 .uc_range = 8, 434 .uc_rclk = DEFAULT_RCLK, 435 .uc_rshift = 0 436 }; 437 438 /* 439 * XXX -- refactor out ACPI and FDT ifdefs 440 */ 441 #ifdef DEV_ACPI 442 static struct acpi_uart_compat_data acpi_compat_data[] = { 443 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 444 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 445 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 446 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 447 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 448 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 449 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 450 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 451 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 452 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 453 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 454 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 455 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 456 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 457 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 458 }; 459 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 460 #endif 461 462 #ifdef FDT 463 static struct ofw_compat_data compat_data[] = { 464 {"ns16550", (uintptr_t)&uart_ns8250_class}, 465 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 466 {NULL, (uintptr_t)NULL}, 467 }; 468 UART_FDT_CLASS_AND_DEVICE(compat_data); 469 #endif 470 471 /* Use token-pasting to form SER_ and MSR_ named constants. */ 472 #define SER(sig) SER_##sig 473 #define SERD(sig) SER_D##sig 474 #define MSR(sig) MSR_##sig 475 #define MSRD(sig) MSR_D##sig 476 477 /* 478 * Detect signal changes using software delta detection. The previous state of 479 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 480 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 481 * new state of both the signal and the delta bits. 482 */ 483 #define SIGCHGSW(var, msr, sig) \ 484 if ((msr) & MSR(sig)) { \ 485 if ((var & SER(sig)) == 0) \ 486 var |= SERD(sig) | SER(sig); \ 487 } else { \ 488 if ((var & SER(sig)) != 0) \ 489 var = SERD(sig) | (var & ~SER(sig)); \ 490 } 491 492 /* 493 * Detect signal changes using the hardware msr delta bits. This is currently 494 * used only when PPS timing information is being captured using the "narrow 495 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 496 * by time the interrupt handler is invoked. The hardware will latch the fact 497 * that it changed in the delta bits. 498 */ 499 #define SIGCHGHW(var, msr, sig) \ 500 if ((msr) & MSRD(sig)) { \ 501 if (((msr) & MSR(sig)) != 0) \ 502 var |= SERD(sig) | SER(sig); \ 503 else \ 504 var = SERD(sig) | (var & ~SER(sig)); \ 505 } 506 507 int 508 ns8250_bus_attach(struct uart_softc *sc) 509 { 510 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 511 struct uart_bas *bas; 512 unsigned int ivar; 513 #ifdef FDT 514 phandle_t node; 515 pcell_t cell; 516 #endif 517 518 #ifdef FDT 519 /* Check whether uart has a broken txfifo. */ 520 node = ofw_bus_get_node(sc->sc_dev); 521 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 522 broken_txfifo = cell ? 1 : 0; 523 #endif 524 525 bas = &sc->sc_bas; 526 527 ns8250->busy_detect = bas->busy_detect; 528 ns8250->mcr = uart_getreg(bas, REG_MCR); 529 ns8250->fcr = FCR_ENABLE; 530 #ifdef CPU_XBURST 531 ns8250->fcr |= FCR_UART_ON; 532 #endif 533 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 534 &ivar)) { 535 if (UART_FLAGS_FCR_RX_LOW(ivar)) 536 ns8250->fcr |= FCR_RX_LOW; 537 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 538 ns8250->fcr |= FCR_RX_MEDL; 539 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 540 ns8250->fcr |= FCR_RX_HIGH; 541 else 542 ns8250->fcr |= FCR_RX_MEDH; 543 } else 544 ns8250->fcr |= FCR_RX_MEDH; 545 546 /* Get IER mask */ 547 ivar = 0xf0; 548 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 549 &ivar); 550 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 551 552 /* Get IER RX interrupt bits */ 553 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 554 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 555 &ivar); 556 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 557 558 uart_setreg(bas, REG_FCR, ns8250->fcr); 559 uart_barrier(bas); 560 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 561 562 if (ns8250->mcr & MCR_DTR) 563 sc->sc_hwsig |= SER_DTR; 564 if (ns8250->mcr & MCR_RTS) 565 sc->sc_hwsig |= SER_RTS; 566 ns8250_bus_getsig(sc); 567 568 ns8250_clrint(bas); 569 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 570 ns8250->ier |= ns8250->ier_rxbits; 571 uart_setreg(bas, REG_IER, ns8250->ier); 572 uart_barrier(bas); 573 574 /* 575 * Timing of the H/W access was changed with r253161 of uart_core.c 576 * It has been observed that an ITE IT8513E would signal a break 577 * condition with pretty much every character it received, unless 578 * it had enough time to settle between ns8250_bus_attach() and 579 * ns8250_bus_ipend() -- which it accidentally had before r253161. 580 * It's not understood why the UART chip behaves this way and it 581 * could very well be that the DELAY make the H/W work in the same 582 * accidental manner as before. More analysis is warranted, but 583 * at least now we fixed a known regression. 584 */ 585 DELAY(200); 586 return (0); 587 } 588 589 int 590 ns8250_bus_detach(struct uart_softc *sc) 591 { 592 struct ns8250_softc *ns8250; 593 struct uart_bas *bas; 594 u_char ier; 595 596 ns8250 = (struct ns8250_softc *)sc; 597 bas = &sc->sc_bas; 598 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 599 uart_setreg(bas, REG_IER, ier); 600 uart_barrier(bas); 601 ns8250_clrint(bas); 602 return (0); 603 } 604 605 int 606 ns8250_bus_flush(struct uart_softc *sc, int what) 607 { 608 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 609 struct uart_bas *bas; 610 int error; 611 612 bas = &sc->sc_bas; 613 uart_lock(sc->sc_hwmtx); 614 if (sc->sc_rxfifosz > 1) { 615 ns8250_flush(bas, what); 616 uart_setreg(bas, REG_FCR, ns8250->fcr); 617 uart_barrier(bas); 618 error = 0; 619 } else 620 error = ns8250_drain(bas, what); 621 uart_unlock(sc->sc_hwmtx); 622 return (error); 623 } 624 625 int 626 ns8250_bus_getsig(struct uart_softc *sc) 627 { 628 uint32_t old, sig; 629 uint8_t msr; 630 631 /* 632 * The delta bits are reputed to be broken on some hardware, so use 633 * software delta detection by default. Use the hardware delta bits 634 * when capturing PPS pulses which are too narrow for software detection 635 * to see the edges. Hardware delta for RI doesn't work like the 636 * others, so always use software for it. Other threads may be changing 637 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 638 * update without other changes happening. Note that the SIGCHGxx() 639 * macros carefully preserve the delta bits when we have to loop several 640 * times and a signal transitions between iterations. 641 */ 642 do { 643 old = sc->sc_hwsig; 644 sig = old; 645 uart_lock(sc->sc_hwmtx); 646 msr = uart_getreg(&sc->sc_bas, REG_MSR); 647 uart_unlock(sc->sc_hwmtx); 648 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 649 SIGCHGHW(sig, msr, DSR); 650 SIGCHGHW(sig, msr, CTS); 651 SIGCHGHW(sig, msr, DCD); 652 } else { 653 SIGCHGSW(sig, msr, DSR); 654 SIGCHGSW(sig, msr, CTS); 655 SIGCHGSW(sig, msr, DCD); 656 } 657 SIGCHGSW(sig, msr, RI); 658 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 659 return (sig); 660 } 661 662 int 663 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 664 { 665 struct uart_bas *bas; 666 int baudrate, divisor, error; 667 uint8_t efr, lcr; 668 669 bas = &sc->sc_bas; 670 error = 0; 671 uart_lock(sc->sc_hwmtx); 672 switch (request) { 673 case UART_IOCTL_BREAK: 674 lcr = uart_getreg(bas, REG_LCR); 675 if (data) 676 lcr |= LCR_SBREAK; 677 else 678 lcr &= ~LCR_SBREAK; 679 uart_setreg(bas, REG_LCR, lcr); 680 uart_barrier(bas); 681 break; 682 case UART_IOCTL_IFLOW: 683 lcr = uart_getreg(bas, REG_LCR); 684 uart_barrier(bas); 685 uart_setreg(bas, REG_LCR, 0xbf); 686 uart_barrier(bas); 687 efr = uart_getreg(bas, REG_EFR); 688 if (data) 689 efr |= EFR_RTS; 690 else 691 efr &= ~EFR_RTS; 692 uart_setreg(bas, REG_EFR, efr); 693 uart_barrier(bas); 694 uart_setreg(bas, REG_LCR, lcr); 695 uart_barrier(bas); 696 break; 697 case UART_IOCTL_OFLOW: 698 lcr = uart_getreg(bas, REG_LCR); 699 uart_barrier(bas); 700 uart_setreg(bas, REG_LCR, 0xbf); 701 uart_barrier(bas); 702 efr = uart_getreg(bas, REG_EFR); 703 if (data) 704 efr |= EFR_CTS; 705 else 706 efr &= ~EFR_CTS; 707 uart_setreg(bas, REG_EFR, efr); 708 uart_barrier(bas); 709 uart_setreg(bas, REG_LCR, lcr); 710 uart_barrier(bas); 711 break; 712 case UART_IOCTL_BAUD: 713 lcr = uart_getreg(bas, REG_LCR); 714 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 715 uart_barrier(bas); 716 divisor = uart_getreg(bas, REG_DLL) | 717 (uart_getreg(bas, REG_DLH) << 8); 718 uart_barrier(bas); 719 uart_setreg(bas, REG_LCR, lcr); 720 uart_barrier(bas); 721 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 722 if (baudrate > 0) 723 *(int*)data = baudrate; 724 else 725 error = ENXIO; 726 break; 727 default: 728 error = EINVAL; 729 break; 730 } 731 uart_unlock(sc->sc_hwmtx); 732 return (error); 733 } 734 735 int 736 ns8250_bus_ipend(struct uart_softc *sc) 737 { 738 struct uart_bas *bas; 739 struct ns8250_softc *ns8250; 740 int ipend; 741 uint8_t iir, lsr; 742 743 ns8250 = (struct ns8250_softc *)sc; 744 bas = &sc->sc_bas; 745 uart_lock(sc->sc_hwmtx); 746 iir = uart_getreg(bas, REG_IIR); 747 748 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 749 (void)uart_getreg(bas, DW_REG_USR); 750 uart_unlock(sc->sc_hwmtx); 751 return (0); 752 } 753 if (iir & IIR_NOPEND) { 754 uart_unlock(sc->sc_hwmtx); 755 return (0); 756 } 757 ipend = 0; 758 if (iir & IIR_RXRDY) { 759 lsr = uart_getreg(bas, REG_LSR); 760 if (lsr & LSR_OE) 761 ipend |= SER_INT_OVERRUN; 762 if (lsr & LSR_BI) 763 ipend |= SER_INT_BREAK; 764 if (lsr & LSR_RXRDY) 765 ipend |= SER_INT_RXREADY; 766 } else { 767 if (iir & IIR_TXRDY) { 768 ipend |= SER_INT_TXIDLE; 769 ns8250->ier &= ~IER_ETXRDY; 770 uart_setreg(bas, REG_IER, ns8250->ier); 771 uart_barrier(bas); 772 } else 773 ipend |= SER_INT_SIGCHG; 774 } 775 if (ipend == 0) 776 ns8250_clrint(bas); 777 uart_unlock(sc->sc_hwmtx); 778 return (ipend); 779 } 780 781 int 782 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 783 int stopbits, int parity) 784 { 785 struct ns8250_softc *ns8250; 786 struct uart_bas *bas; 787 int error, limit; 788 789 ns8250 = (struct ns8250_softc*)sc; 790 bas = &sc->sc_bas; 791 uart_lock(sc->sc_hwmtx); 792 /* 793 * When using DW UART with BUSY detection it is necessary to wait 794 * until all serial transfers are finished before manipulating the 795 * line control. LCR will not be affected when UART is busy. 796 */ 797 if (ns8250->busy_detect != 0) { 798 /* 799 * Pick an arbitrary high limit to avoid getting stuck in 800 * an infinite loop in case when the hardware is broken. 801 */ 802 limit = 10 * 1024; 803 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 804 --limit) 805 DELAY(4); 806 807 if (limit <= 0) { 808 /* UART appears to be stuck */ 809 uart_unlock(sc->sc_hwmtx); 810 return (EIO); 811 } 812 } 813 814 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 815 uart_unlock(sc->sc_hwmtx); 816 return (error); 817 } 818 819 int 820 ns8250_bus_probe(struct uart_softc *sc) 821 { 822 struct uart_bas *bas; 823 int count, delay, error, limit; 824 uint8_t lsr, mcr, ier; 825 uint8_t val; 826 827 bas = &sc->sc_bas; 828 829 error = ns8250_probe(bas); 830 if (error) 831 return (error); 832 833 mcr = MCR_IE; 834 if (sc->sc_sysdev == NULL) { 835 /* By using ns8250_init() we also set DTR and RTS. */ 836 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 837 } else 838 mcr |= MCR_DTR | MCR_RTS; 839 840 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 841 if (error) 842 return (error); 843 844 /* 845 * Set loopback mode. This avoids having garbage on the wire and 846 * also allows us send and receive data. We set DTR and RTS to 847 * avoid the possibility that automatic flow-control prevents 848 * any data from being sent. 849 */ 850 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 851 uart_barrier(bas); 852 853 /* 854 * Enable FIFOs. And check that the UART has them. If not, we're 855 * done. Since this is the first time we enable the FIFOs, we reset 856 * them. 857 */ 858 val = FCR_ENABLE; 859 #ifdef CPU_XBURST 860 val |= FCR_UART_ON; 861 #endif 862 uart_setreg(bas, REG_FCR, val); 863 uart_barrier(bas); 864 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 865 /* 866 * NS16450 or INS8250. We don't bother to differentiate 867 * between them. They're too old to be interesting. 868 */ 869 uart_setreg(bas, REG_MCR, mcr); 870 uart_barrier(bas); 871 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 872 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 873 return (0); 874 } 875 876 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 877 #ifdef CPU_XBURST 878 val |= FCR_UART_ON; 879 #endif 880 uart_setreg(bas, REG_FCR, val); 881 uart_barrier(bas); 882 883 count = 0; 884 delay = ns8250_delay(bas); 885 886 /* We have FIFOs. Drain the transmitter and receiver. */ 887 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 888 if (error) { 889 uart_setreg(bas, REG_MCR, mcr); 890 val = 0; 891 #ifdef CPU_XBURST 892 val |= FCR_UART_ON; 893 #endif 894 uart_setreg(bas, REG_FCR, val); 895 uart_barrier(bas); 896 goto describe; 897 } 898 899 /* 900 * We should have a sufficiently clean "pipe" to determine the 901 * size of the FIFOs. We send as much characters as is reasonable 902 * and wait for the overflow bit in the LSR register to be 903 * asserted, counting the characters as we send them. Based on 904 * that count we know the FIFO size. 905 */ 906 do { 907 uart_setreg(bas, REG_DATA, 0); 908 uart_barrier(bas); 909 count++; 910 911 limit = 30; 912 lsr = 0; 913 /* 914 * LSR bits are cleared upon read, so we must accumulate 915 * them to be able to test LSR_OE below. 916 */ 917 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 918 --limit) 919 DELAY(delay); 920 if (limit == 0) { 921 /* See the comment in ns8250_init(). */ 922 ier = uart_getreg(bas, REG_IER) & 0xe0; 923 uart_setreg(bas, REG_IER, ier); 924 uart_setreg(bas, REG_MCR, mcr); 925 val = 0; 926 #ifdef CPU_XBURST 927 val |= FCR_UART_ON; 928 #endif 929 uart_setreg(bas, REG_FCR, val); 930 uart_barrier(bas); 931 count = 0; 932 goto describe; 933 } 934 } while ((lsr & LSR_OE) == 0 && count < 260); 935 count--; 936 937 uart_setreg(bas, REG_MCR, mcr); 938 939 /* Reset FIFOs. */ 940 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 941 942 describe: 943 if (count >= 14 && count <= 16) { 944 sc->sc_rxfifosz = 16; 945 device_set_desc(sc->sc_dev, "16550 or compatible"); 946 } else if (count >= 28 && count <= 32) { 947 sc->sc_rxfifosz = 32; 948 device_set_desc(sc->sc_dev, "16650 or compatible"); 949 } else if (count >= 56 && count <= 64) { 950 sc->sc_rxfifosz = 64; 951 device_set_desc(sc->sc_dev, "16750 or compatible"); 952 } else if (count >= 112 && count <= 128) { 953 sc->sc_rxfifosz = 128; 954 device_set_desc(sc->sc_dev, "16950 or compatible"); 955 } else if (count >= 224 && count <= 256) { 956 sc->sc_rxfifosz = 256; 957 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 958 } else { 959 sc->sc_rxfifosz = 16; 960 device_set_desc(sc->sc_dev, 961 "Non-standard ns8250 class UART with FIFOs"); 962 } 963 964 /* 965 * Force the Tx FIFO size to 16 bytes for now. We don't program the 966 * Tx trigger. Also, we assume that all data has been sent when the 967 * interrupt happens. 968 */ 969 sc->sc_txfifosz = 16; 970 971 #if 0 972 /* 973 * XXX there are some issues related to hardware flow control and 974 * it's likely that uart(4) is the cause. This basically needs more 975 * investigation, but we avoid using for hardware flow control 976 * until then. 977 */ 978 /* 16650s or higher have automatic flow control. */ 979 if (sc->sc_rxfifosz > 16) { 980 sc->sc_hwiflow = 1; 981 sc->sc_hwoflow = 1; 982 } 983 #endif 984 985 return (0); 986 } 987 988 int 989 ns8250_bus_receive(struct uart_softc *sc) 990 { 991 struct uart_bas *bas; 992 int xc; 993 uint8_t lsr; 994 995 bas = &sc->sc_bas; 996 uart_lock(sc->sc_hwmtx); 997 lsr = uart_getreg(bas, REG_LSR); 998 while (lsr & LSR_RXRDY) { 999 if (uart_rx_full(sc)) { 1000 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1001 break; 1002 } 1003 xc = uart_getreg(bas, REG_DATA); 1004 if (lsr & LSR_FE) 1005 xc |= UART_STAT_FRAMERR; 1006 if (lsr & LSR_PE) 1007 xc |= UART_STAT_PARERR; 1008 uart_rx_put(sc, xc); 1009 lsr = uart_getreg(bas, REG_LSR); 1010 } 1011 /* Discard everything left in the Rx FIFO. */ 1012 while (lsr & LSR_RXRDY) { 1013 (void)uart_getreg(bas, REG_DATA); 1014 uart_barrier(bas); 1015 lsr = uart_getreg(bas, REG_LSR); 1016 } 1017 uart_unlock(sc->sc_hwmtx); 1018 return (0); 1019 } 1020 1021 int 1022 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1023 { 1024 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1025 struct uart_bas *bas; 1026 uint32_t new, old; 1027 1028 bas = &sc->sc_bas; 1029 do { 1030 old = sc->sc_hwsig; 1031 new = old; 1032 if (sig & SER_DDTR) { 1033 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1034 } 1035 if (sig & SER_DRTS) { 1036 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1037 } 1038 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1039 uart_lock(sc->sc_hwmtx); 1040 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1041 if (new & SER_DTR) 1042 ns8250->mcr |= MCR_DTR; 1043 if (new & SER_RTS) 1044 ns8250->mcr |= MCR_RTS; 1045 uart_setreg(bas, REG_MCR, ns8250->mcr); 1046 uart_barrier(bas); 1047 uart_unlock(sc->sc_hwmtx); 1048 return (0); 1049 } 1050 1051 int 1052 ns8250_bus_transmit(struct uart_softc *sc) 1053 { 1054 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1055 struct uart_bas *bas; 1056 int i; 1057 1058 bas = &sc->sc_bas; 1059 uart_lock(sc->sc_hwmtx); 1060 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1061 DELAY(4); 1062 for (i = 0; i < sc->sc_txdatasz; i++) { 1063 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1064 uart_barrier(bas); 1065 } 1066 if (!broken_txfifo) 1067 ns8250->ier |= IER_ETXRDY; 1068 uart_setreg(bas, REG_IER, ns8250->ier); 1069 uart_barrier(bas); 1070 if (broken_txfifo) 1071 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1072 else 1073 sc->sc_txbusy = 1; 1074 uart_unlock(sc->sc_hwmtx); 1075 if (broken_txfifo) 1076 uart_sched_softih(sc, SER_INT_TXIDLE); 1077 return (0); 1078 } 1079 1080 void 1081 ns8250_bus_grab(struct uart_softc *sc) 1082 { 1083 struct uart_bas *bas = &sc->sc_bas; 1084 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1085 u_char ier; 1086 1087 /* 1088 * turn off all interrupts to enter polling mode. Leave the 1089 * saved mask alone. We'll restore whatever it was in ungrab. 1090 * All pending interrupt signals are reset when IER is set to 0. 1091 */ 1092 uart_lock(sc->sc_hwmtx); 1093 ier = uart_getreg(bas, REG_IER); 1094 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1095 uart_barrier(bas); 1096 uart_unlock(sc->sc_hwmtx); 1097 } 1098 1099 void 1100 ns8250_bus_ungrab(struct uart_softc *sc) 1101 { 1102 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1103 struct uart_bas *bas = &sc->sc_bas; 1104 1105 /* 1106 * Restore previous interrupt mask 1107 */ 1108 uart_lock(sc->sc_hwmtx); 1109 uart_setreg(bas, REG_IER, ns8250->ier); 1110 uart_barrier(bas); 1111 uart_unlock(sc->sc_hwmtx); 1112 }
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