The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/uart/uart_dev_ns8250.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2003 Marcel Moolenaar
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  *
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 #include "opt_acpi.h"
   30 #include "opt_platform.h"
   31 #include "opt_uart.h"
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD$");
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/bus.h>
   39 #include <sys/conf.h>
   40 #include <sys/kernel.h>
   41 #include <sys/sysctl.h>
   42 #include <machine/bus.h>
   43 
   44 #ifdef FDT
   45 #include <dev/fdt/fdt_common.h>
   46 #include <dev/ofw/ofw_bus.h>
   47 #include <dev/ofw/ofw_bus_subr.h>
   48 #endif
   49 
   50 #include <dev/uart/uart.h>
   51 #include <dev/uart/uart_cpu.h>
   52 #ifdef FDT
   53 #include <dev/uart/uart_cpu_fdt.h>
   54 #endif
   55 #include <dev/uart/uart_bus.h>
   56 #include <dev/uart/uart_dev_ns8250.h>
   57 #include <dev/uart/uart_ppstypes.h>
   58 #ifdef DEV_ACPI
   59 #include <dev/uart/uart_cpu_acpi.h>
   60 #include <contrib/dev/acpica/include/acpi.h>
   61 #endif
   62 
   63 #include <dev/ic/ns16550.h>
   64 
   65 #include "uart_if.h"
   66 
   67 #define DEFAULT_RCLK    1843200
   68 
   69 /*
   70  * Set the default baudrate tolerance to 3.0%.
   71  *
   72  * Some embedded boards have odd reference clocks (eg 25MHz)
   73  * and we need to handle higher variances in the target baud rate.
   74  */
   75 #ifndef UART_DEV_TOLERANCE_PCT
   76 #define UART_DEV_TOLERANCE_PCT  30
   77 #endif  /* UART_DEV_TOLERANCE_PCT */
   78 
   79 static int broken_txfifo = 0;
   80 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
   81         &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
   82 
   83 /*
   84  * Clear pending interrupts. THRE is cleared by reading IIR. Data
   85  * that may have been received gets lost here.
   86  */
   87 static void
   88 ns8250_clrint(struct uart_bas *bas)
   89 {
   90         uint8_t iir, lsr;
   91 
   92         iir = uart_getreg(bas, REG_IIR);
   93         while ((iir & IIR_NOPEND) == 0) {
   94                 iir &= IIR_IMASK;
   95                 if (iir == IIR_RLS) {
   96                         lsr = uart_getreg(bas, REG_LSR);
   97                         if (lsr & (LSR_BI|LSR_FE|LSR_PE))
   98                                 (void)uart_getreg(bas, REG_DATA);
   99                 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
  100                         (void)uart_getreg(bas, REG_DATA);
  101                 else if (iir == IIR_MLSC)
  102                         (void)uart_getreg(bas, REG_MSR);
  103                 uart_barrier(bas);
  104                 iir = uart_getreg(bas, REG_IIR);
  105         }
  106 }
  107 
  108 static int
  109 ns8250_delay(struct uart_bas *bas)
  110 {
  111         int divisor;
  112         u_char lcr;
  113 
  114         lcr = uart_getreg(bas, REG_LCR);
  115         uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
  116         uart_barrier(bas);
  117         divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
  118         uart_barrier(bas);
  119         uart_setreg(bas, REG_LCR, lcr);
  120         uart_barrier(bas);
  121 
  122         /* 1/10th the time to transmit 1 character (estimate). */
  123         if (divisor <= 134)
  124                 return (16000000 * divisor / bas->rclk);
  125         return (16000 * divisor / (bas->rclk / 1000));
  126 }
  127 
  128 static int
  129 ns8250_divisor(int rclk, int baudrate)
  130 {
  131         int actual_baud, divisor;
  132         int error;
  133 
  134         if (baudrate == 0)
  135                 return (0);
  136 
  137         divisor = (rclk / (baudrate << 3) + 1) >> 1;
  138         if (divisor == 0 || divisor >= 65536)
  139                 return (0);
  140         actual_baud = rclk / (divisor << 4);
  141 
  142         /* 10 times error in percent: */
  143         error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
  144 
  145         /* enforce maximum error tolerance: */
  146         if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
  147                 return (0);
  148 
  149         return (divisor);
  150 }
  151 
  152 static int
  153 ns8250_drain(struct uart_bas *bas, int what)
  154 {
  155         int delay, limit;
  156 
  157         delay = ns8250_delay(bas);
  158 
  159         if (what & UART_DRAIN_TRANSMITTER) {
  160                 /*
  161                  * Pick an arbitrary high limit to avoid getting stuck in
  162                  * an infinite loop when the hardware is broken. Make the
  163                  * limit high enough to handle large FIFOs.
  164                  */
  165                 limit = 10*1024;
  166                 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
  167                         DELAY(delay);
  168                 if (limit == 0) {
  169                         /* printf("ns8250: transmitter appears stuck... "); */
  170                         return (EIO);
  171                 }
  172         }
  173 
  174         if (what & UART_DRAIN_RECEIVER) {
  175                 /*
  176                  * Pick an arbitrary high limit to avoid getting stuck in
  177                  * an infinite loop when the hardware is broken. Make the
  178                  * limit high enough to handle large FIFOs and integrated
  179                  * UARTs. The HP rx2600 for example has 3 UARTs on the
  180                  * management board that tend to get a lot of data send
  181                  * to it when the UART is first activated.
  182                  */
  183                 limit=10*4096;
  184                 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
  185                         (void)uart_getreg(bas, REG_DATA);
  186                         uart_barrier(bas);
  187                         DELAY(delay << 2);
  188                 }
  189                 if (limit == 0) {
  190                         /* printf("ns8250: receiver appears broken... "); */
  191                         return (EIO);
  192                 }
  193         }
  194 
  195         return (0);
  196 }
  197 
  198 /*
  199  * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
  200  * drained. WARNING: this function clobbers the FIFO setting!
  201  */
  202 static void
  203 ns8250_flush(struct uart_bas *bas, int what)
  204 {
  205         uint8_t fcr;
  206 
  207         fcr = FCR_ENABLE;
  208 #ifdef CPU_XBURST
  209         fcr |= FCR_UART_ON;
  210 #endif
  211         if (what & UART_FLUSH_TRANSMITTER)
  212                 fcr |= FCR_XMT_RST;
  213         if (what & UART_FLUSH_RECEIVER)
  214                 fcr |= FCR_RCV_RST;
  215         uart_setreg(bas, REG_FCR, fcr);
  216         uart_barrier(bas);
  217 }
  218 
  219 static int
  220 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
  221     int parity)
  222 {
  223         int divisor;
  224         uint8_t lcr;
  225 
  226         lcr = 0;
  227         if (databits >= 8)
  228                 lcr |= LCR_8BITS;
  229         else if (databits == 7)
  230                 lcr |= LCR_7BITS;
  231         else if (databits == 6)
  232                 lcr |= LCR_6BITS;
  233         else
  234                 lcr |= LCR_5BITS;
  235         if (stopbits > 1)
  236                 lcr |= LCR_STOPB;
  237         lcr |= parity << 3;
  238 
  239         /* Set baudrate. */
  240         if (baudrate > 0) {
  241                 divisor = ns8250_divisor(bas->rclk, baudrate);
  242                 if (divisor == 0)
  243                         return (EINVAL);
  244                 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
  245                 uart_barrier(bas);
  246                 uart_setreg(bas, REG_DLL, divisor & 0xff);
  247                 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
  248                 uart_barrier(bas);
  249         }
  250 
  251         /* Set LCR and clear DLAB. */
  252         uart_setreg(bas, REG_LCR, lcr);
  253         uart_barrier(bas);
  254         return (0);
  255 }
  256 
  257 /*
  258  * Low-level UART interface.
  259  */
  260 static int ns8250_probe(struct uart_bas *bas);
  261 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
  262 static void ns8250_term(struct uart_bas *bas);
  263 static void ns8250_putc(struct uart_bas *bas, int);
  264 static int ns8250_rxready(struct uart_bas *bas);
  265 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
  266 
  267 struct uart_ops uart_ns8250_ops = {
  268         .probe = ns8250_probe,
  269         .init = ns8250_init,
  270         .term = ns8250_term,
  271         .putc = ns8250_putc,
  272         .rxready = ns8250_rxready,
  273         .getc = ns8250_getc,
  274 };
  275 
  276 static int
  277 ns8250_probe(struct uart_bas *bas)
  278 {
  279         u_char val;
  280 
  281 #ifdef CPU_XBURST
  282         uart_setreg(bas, REG_FCR, FCR_UART_ON);
  283 #endif
  284 
  285         /* Check known 0 bits that don't depend on DLAB. */
  286         val = uart_getreg(bas, REG_IIR);
  287         if (val & 0x30)
  288                 return (ENXIO);
  289         /*
  290          * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
  291          * chip, but otherwise doesn't seem to have a function. In
  292          * other words, uart(4) works regardless. Ignore that bit so
  293          * the probe succeeds.
  294          */
  295         val = uart_getreg(bas, REG_MCR);
  296         if (val & 0xa0)
  297                 return (ENXIO);
  298 
  299         return (0);
  300 }
  301 
  302 static void
  303 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
  304     int parity)
  305 {
  306         u_char ier, val;
  307 
  308         if (bas->rclk == 0)
  309                 bas->rclk = DEFAULT_RCLK;
  310         ns8250_param(bas, baudrate, databits, stopbits, parity);
  311 
  312         /* Disable all interrupt sources. */
  313         /*
  314          * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
  315          * UARTs split the receive time-out interrupt bit out separately as
  316          * 0x10.  This gets handled by ier_mask and ier_rxbits below.
  317          */
  318         ier = uart_getreg(bas, REG_IER) & 0xe0;
  319         uart_setreg(bas, REG_IER, ier);
  320         uart_barrier(bas);
  321 
  322         /* Disable the FIFO (if present). */
  323         val = 0;
  324 #ifdef CPU_XBURST
  325         val |= FCR_UART_ON;
  326 #endif
  327         uart_setreg(bas, REG_FCR, val);
  328         uart_barrier(bas);
  329 
  330         /* Set RTS & DTR. */
  331         uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
  332         uart_barrier(bas);
  333 
  334         ns8250_clrint(bas);
  335 }
  336 
  337 static void
  338 ns8250_term(struct uart_bas *bas)
  339 {
  340 
  341         /* Clear RTS & DTR. */
  342         uart_setreg(bas, REG_MCR, MCR_IE);
  343         uart_barrier(bas);
  344 }
  345 
  346 static void
  347 ns8250_putc(struct uart_bas *bas, int c)
  348 {
  349         int limit;
  350 
  351         limit = 250000;
  352         while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
  353                 DELAY(4);
  354         uart_setreg(bas, REG_DATA, c);
  355         uart_barrier(bas);
  356 }
  357 
  358 static int
  359 ns8250_rxready(struct uart_bas *bas)
  360 {
  361 
  362         return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
  363 }
  364 
  365 static int
  366 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
  367 {
  368         int c;
  369 
  370         uart_lock(hwmtx);
  371 
  372         while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
  373                 uart_unlock(hwmtx);
  374                 DELAY(4);
  375                 uart_lock(hwmtx);
  376         }
  377 
  378         c = uart_getreg(bas, REG_DATA);
  379 
  380         uart_unlock(hwmtx);
  381 
  382         return (c);
  383 }
  384 
  385 static kobj_method_t ns8250_methods[] = {
  386         KOBJMETHOD(uart_attach,         ns8250_bus_attach),
  387         KOBJMETHOD(uart_detach,         ns8250_bus_detach),
  388         KOBJMETHOD(uart_flush,          ns8250_bus_flush),
  389         KOBJMETHOD(uart_getsig,         ns8250_bus_getsig),
  390         KOBJMETHOD(uart_ioctl,          ns8250_bus_ioctl),
  391         KOBJMETHOD(uart_ipend,          ns8250_bus_ipend),
  392         KOBJMETHOD(uart_param,          ns8250_bus_param),
  393         KOBJMETHOD(uart_probe,          ns8250_bus_probe),
  394         KOBJMETHOD(uart_receive,        ns8250_bus_receive),
  395         KOBJMETHOD(uart_setsig,         ns8250_bus_setsig),
  396         KOBJMETHOD(uart_transmit,       ns8250_bus_transmit),
  397         KOBJMETHOD(uart_grab,           ns8250_bus_grab),
  398         KOBJMETHOD(uart_ungrab,         ns8250_bus_ungrab),
  399         { 0, 0 }
  400 };
  401 
  402 struct uart_class uart_ns8250_class = {
  403         "ns8250",
  404         ns8250_methods,
  405         sizeof(struct ns8250_softc),
  406         .uc_ops = &uart_ns8250_ops,
  407         .uc_range = 8,
  408         .uc_rclk = DEFAULT_RCLK,
  409         .uc_rshift = 0
  410 };
  411 
  412 /*
  413  * XXX -- refactor out ACPI and FDT ifdefs
  414  */
  415 #ifdef DEV_ACPI
  416 static struct acpi_uart_compat_data acpi_compat_data[] = {
  417         {"AMD0020",     &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
  418         {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
  419         {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
  420         {"SCX0006",  &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
  421         {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
  422         {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
  423         {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
  424         {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
  425         {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
  426         {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
  427         {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
  428         {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
  429         {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
  430         {NULL,                  NULL, 0, 0 , 0, 0, 0, NULL},
  431 };
  432 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
  433 #endif
  434 
  435 #ifdef FDT
  436 static struct ofw_compat_data compat_data[] = {
  437         {"ns16550",             (uintptr_t)&uart_ns8250_class},
  438         {"ns16550a",            (uintptr_t)&uart_ns8250_class},
  439         {NULL,                  (uintptr_t)NULL},
  440 };
  441 UART_FDT_CLASS_AND_DEVICE(compat_data);
  442 #endif
  443 
  444 /* Use token-pasting to form SER_ and MSR_ named constants. */
  445 #define SER(sig)        SER_##sig
  446 #define SERD(sig)       SER_D##sig
  447 #define MSR(sig)        MSR_##sig
  448 #define MSRD(sig)       MSR_D##sig
  449 
  450 /*
  451  * Detect signal changes using software delta detection.  The previous state of
  452  * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
  453  * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
  454  * new state of both the signal and the delta bits.
  455  */
  456 #define SIGCHGSW(var, msr, sig)                                 \
  457         if ((msr) & MSR(sig)) {                                 \
  458                 if ((var & SER(sig)) == 0)                      \
  459                         var |= SERD(sig) | SER(sig);            \
  460         } else {                                                \
  461                 if ((var & SER(sig)) != 0)                      \
  462                         var = SERD(sig) | (var & ~SER(sig));    \
  463         }
  464 
  465 /*
  466  * Detect signal changes using the hardware msr delta bits.  This is currently
  467  * used only when PPS timing information is being captured using the "narrow
  468  * pulse" option.  With a narrow PPS pulse the signal may not still be asserted
  469  * by time the interrupt handler is invoked.  The hardware will latch the fact
  470  * that it changed in the delta bits.
  471  */
  472 #define SIGCHGHW(var, msr, sig)                                 \
  473         if ((msr) & MSRD(sig)) {                                \
  474                 if (((msr) & MSR(sig)) != 0)                    \
  475                         var |= SERD(sig) | SER(sig);            \
  476                 else                                            \
  477                         var = SERD(sig) | (var & ~SER(sig));    \
  478         }
  479 
  480 int
  481 ns8250_bus_attach(struct uart_softc *sc)
  482 {
  483         struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
  484         struct uart_bas *bas;
  485         unsigned int ivar;
  486 #ifdef FDT
  487         phandle_t node;
  488         pcell_t cell;
  489 #endif
  490 
  491 #ifdef FDT
  492         /* Check whether uart has a broken txfifo. */
  493         node = ofw_bus_get_node(sc->sc_dev);
  494         if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
  495                 broken_txfifo =  cell ? 1 : 0;
  496 #endif
  497 
  498         bas = &sc->sc_bas;
  499 
  500         ns8250->busy_detect = bas->busy_detect;
  501         ns8250->mcr = uart_getreg(bas, REG_MCR);
  502         ns8250->fcr = FCR_ENABLE;
  503 #ifdef CPU_XBURST
  504         ns8250->fcr |= FCR_UART_ON;
  505 #endif
  506         if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
  507             &ivar)) {
  508                 if (UART_FLAGS_FCR_RX_LOW(ivar)) 
  509                         ns8250->fcr |= FCR_RX_LOW;
  510                 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 
  511                         ns8250->fcr |= FCR_RX_MEDL;
  512                 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 
  513                         ns8250->fcr |= FCR_RX_HIGH;
  514                 else
  515                         ns8250->fcr |= FCR_RX_MEDH;
  516         } else 
  517                 ns8250->fcr |= FCR_RX_MEDH;
  518 
  519         /* Get IER mask */
  520         ivar = 0xf0;
  521         resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
  522             &ivar);
  523         ns8250->ier_mask = (uint8_t)(ivar & 0xff);
  524 
  525         /* Get IER RX interrupt bits */
  526         ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
  527         resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
  528             &ivar);
  529         ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
  530 
  531         uart_setreg(bas, REG_FCR, ns8250->fcr);
  532         uart_barrier(bas);
  533         ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
  534 
  535         if (ns8250->mcr & MCR_DTR)
  536                 sc->sc_hwsig |= SER_DTR;
  537         if (ns8250->mcr & MCR_RTS)
  538                 sc->sc_hwsig |= SER_RTS;
  539         ns8250_bus_getsig(sc);
  540 
  541         ns8250_clrint(bas);
  542         ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
  543         ns8250->ier |= ns8250->ier_rxbits;
  544         uart_setreg(bas, REG_IER, ns8250->ier);
  545         uart_barrier(bas);
  546 
  547         /*
  548          * Timing of the H/W access was changed with r253161 of uart_core.c
  549          * It has been observed that an ITE IT8513E would signal a break
  550          * condition with pretty much every character it received, unless
  551          * it had enough time to settle between ns8250_bus_attach() and
  552          * ns8250_bus_ipend() -- which it accidentally had before r253161.
  553          * It's not understood why the UART chip behaves this way and it
  554          * could very well be that the DELAY make the H/W work in the same
  555          * accidental manner as before. More analysis is warranted, but
  556          * at least now we fixed a known regression.
  557          */
  558         DELAY(200);
  559         return (0);
  560 }
  561 
  562 int
  563 ns8250_bus_detach(struct uart_softc *sc)
  564 {
  565         struct ns8250_softc *ns8250;
  566         struct uart_bas *bas;
  567         u_char ier;
  568 
  569         ns8250 = (struct ns8250_softc *)sc;
  570         bas = &sc->sc_bas;
  571         ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
  572         uart_setreg(bas, REG_IER, ier);
  573         uart_barrier(bas);
  574         ns8250_clrint(bas);
  575         return (0);
  576 }
  577 
  578 int
  579 ns8250_bus_flush(struct uart_softc *sc, int what)
  580 {
  581         struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
  582         struct uart_bas *bas;
  583         int error;
  584 
  585         bas = &sc->sc_bas;
  586         uart_lock(sc->sc_hwmtx);
  587         if (sc->sc_rxfifosz > 1) {
  588                 ns8250_flush(bas, what);
  589                 uart_setreg(bas, REG_FCR, ns8250->fcr);
  590                 uart_barrier(bas);
  591                 error = 0;
  592         } else
  593                 error = ns8250_drain(bas, what);
  594         uart_unlock(sc->sc_hwmtx);
  595         return (error);
  596 }
  597 
  598 int
  599 ns8250_bus_getsig(struct uart_softc *sc)
  600 {
  601         uint32_t old, sig;
  602         uint8_t msr;
  603 
  604         /*
  605          * The delta bits are reputed to be broken on some hardware, so use
  606          * software delta detection by default.  Use the hardware delta bits
  607          * when capturing PPS pulses which are too narrow for software detection
  608          * to see the edges.  Hardware delta for RI doesn't work like the
  609          * others, so always use software for it.  Other threads may be changing
  610          * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
  611          * update without other changes happening.  Note that the SIGCHGxx()
  612          * macros carefully preserve the delta bits when we have to loop several
  613          * times and a signal transitions between iterations.
  614          */
  615         do {
  616                 old = sc->sc_hwsig;
  617                 sig = old;
  618                 uart_lock(sc->sc_hwmtx);
  619                 msr = uart_getreg(&sc->sc_bas, REG_MSR);
  620                 uart_unlock(sc->sc_hwmtx);
  621                 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
  622                         SIGCHGHW(sig, msr, DSR);
  623                         SIGCHGHW(sig, msr, CTS);
  624                         SIGCHGHW(sig, msr, DCD);
  625                 } else {
  626                         SIGCHGSW(sig, msr, DSR);
  627                         SIGCHGSW(sig, msr, CTS);
  628                         SIGCHGSW(sig, msr, DCD);
  629                 }
  630                 SIGCHGSW(sig, msr, RI);
  631         } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
  632         return (sig);
  633 }
  634 
  635 int
  636 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
  637 {
  638         struct uart_bas *bas;
  639         int baudrate, divisor, error;
  640         uint8_t efr, lcr;
  641 
  642         bas = &sc->sc_bas;
  643         error = 0;
  644         uart_lock(sc->sc_hwmtx);
  645         switch (request) {
  646         case UART_IOCTL_BREAK:
  647                 lcr = uart_getreg(bas, REG_LCR);
  648                 if (data)
  649                         lcr |= LCR_SBREAK;
  650                 else
  651                         lcr &= ~LCR_SBREAK;
  652                 uart_setreg(bas, REG_LCR, lcr);
  653                 uart_barrier(bas);
  654                 break;
  655         case UART_IOCTL_IFLOW:
  656                 lcr = uart_getreg(bas, REG_LCR);
  657                 uart_barrier(bas);
  658                 uart_setreg(bas, REG_LCR, 0xbf);
  659                 uart_barrier(bas);
  660                 efr = uart_getreg(bas, REG_EFR);
  661                 if (data)
  662                         efr |= EFR_RTS;
  663                 else
  664                         efr &= ~EFR_RTS;
  665                 uart_setreg(bas, REG_EFR, efr);
  666                 uart_barrier(bas);
  667                 uart_setreg(bas, REG_LCR, lcr);
  668                 uart_barrier(bas);
  669                 break;
  670         case UART_IOCTL_OFLOW:
  671                 lcr = uart_getreg(bas, REG_LCR);
  672                 uart_barrier(bas);
  673                 uart_setreg(bas, REG_LCR, 0xbf);
  674                 uart_barrier(bas);
  675                 efr = uart_getreg(bas, REG_EFR);
  676                 if (data)
  677                         efr |= EFR_CTS;
  678                 else
  679                         efr &= ~EFR_CTS;
  680                 uart_setreg(bas, REG_EFR, efr);
  681                 uart_barrier(bas);
  682                 uart_setreg(bas, REG_LCR, lcr);
  683                 uart_barrier(bas);
  684                 break;
  685         case UART_IOCTL_BAUD:
  686                 lcr = uart_getreg(bas, REG_LCR);
  687                 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
  688                 uart_barrier(bas);
  689                 divisor = uart_getreg(bas, REG_DLL) |
  690                     (uart_getreg(bas, REG_DLH) << 8);
  691                 uart_barrier(bas);
  692                 uart_setreg(bas, REG_LCR, lcr);
  693                 uart_barrier(bas);
  694                 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
  695                 if (baudrate > 0)
  696                         *(int*)data = baudrate;
  697                 else
  698                         error = ENXIO;
  699                 break;
  700         default:
  701                 error = EINVAL;
  702                 break;
  703         }
  704         uart_unlock(sc->sc_hwmtx);
  705         return (error);
  706 }
  707 
  708 int
  709 ns8250_bus_ipend(struct uart_softc *sc)
  710 {
  711         struct uart_bas *bas;
  712         struct ns8250_softc *ns8250;
  713         int ipend;
  714         uint8_t iir, lsr;
  715 
  716         ns8250 = (struct ns8250_softc *)sc;
  717         bas = &sc->sc_bas;
  718         uart_lock(sc->sc_hwmtx);
  719         iir = uart_getreg(bas, REG_IIR);
  720 
  721         if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
  722                 (void)uart_getreg(bas, DW_REG_USR);
  723                 uart_unlock(sc->sc_hwmtx);
  724                 return (0);
  725         }
  726         if (iir & IIR_NOPEND) {
  727                 uart_unlock(sc->sc_hwmtx);
  728                 return (0);
  729         }
  730         ipend = 0;
  731         if (iir & IIR_RXRDY) {
  732                 lsr = uart_getreg(bas, REG_LSR);
  733                 if (lsr & LSR_OE)
  734                         ipend |= SER_INT_OVERRUN;
  735                 if (lsr & LSR_BI)
  736                         ipend |= SER_INT_BREAK;
  737                 if (lsr & LSR_RXRDY)
  738                         ipend |= SER_INT_RXREADY;
  739         } else {
  740                 if (iir & IIR_TXRDY) {
  741                         ipend |= SER_INT_TXIDLE;
  742                         ns8250->ier &= ~IER_ETXRDY;
  743                         uart_setreg(bas, REG_IER, ns8250->ier);
  744                         uart_barrier(bas);
  745                 } else
  746                         ipend |= SER_INT_SIGCHG;
  747         }
  748         if (ipend == 0)
  749                 ns8250_clrint(bas);
  750         uart_unlock(sc->sc_hwmtx);
  751         return (ipend);
  752 }
  753 
  754 int
  755 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
  756     int stopbits, int parity)
  757 {
  758         struct ns8250_softc *ns8250;
  759         struct uart_bas *bas;
  760         int error, limit;
  761 
  762         ns8250 = (struct ns8250_softc*)sc;
  763         bas = &sc->sc_bas;
  764         uart_lock(sc->sc_hwmtx);
  765         /*
  766          * When using DW UART with BUSY detection it is necessary to wait
  767          * until all serial transfers are finished before manipulating the
  768          * line control. LCR will not be affected when UART is busy.
  769          */
  770         if (ns8250->busy_detect != 0) {
  771                 /*
  772                  * Pick an arbitrary high limit to avoid getting stuck in
  773                  * an infinite loop in case when the hardware is broken.
  774                  */
  775                 limit = 10 * 1024;
  776                 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
  777                     --limit)
  778                         DELAY(4);
  779 
  780                 if (limit <= 0) {
  781                         /* UART appears to be stuck */
  782                         uart_unlock(sc->sc_hwmtx);
  783                         return (EIO);
  784                 }
  785         }
  786 
  787         error = ns8250_param(bas, baudrate, databits, stopbits, parity);
  788         uart_unlock(sc->sc_hwmtx);
  789         return (error);
  790 }
  791 
  792 int
  793 ns8250_bus_probe(struct uart_softc *sc)
  794 {
  795         struct uart_bas *bas;
  796         int count, delay, error, limit;
  797         uint8_t lsr, mcr, ier;
  798         uint8_t val;
  799 
  800         bas = &sc->sc_bas;
  801 
  802         error = ns8250_probe(bas);
  803         if (error)
  804                 return (error);
  805 
  806         mcr = MCR_IE;
  807         if (sc->sc_sysdev == NULL) {
  808                 /* By using ns8250_init() we also set DTR and RTS. */
  809                 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
  810         } else
  811                 mcr |= MCR_DTR | MCR_RTS;
  812 
  813         error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
  814         if (error)
  815                 return (error);
  816 
  817         /*
  818          * Set loopback mode. This avoids having garbage on the wire and
  819          * also allows us send and receive data. We set DTR and RTS to
  820          * avoid the possibility that automatic flow-control prevents
  821          * any data from being sent.
  822          */
  823         uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
  824         uart_barrier(bas);
  825 
  826         /*
  827          * Enable FIFOs. And check that the UART has them. If not, we're
  828          * done. Since this is the first time we enable the FIFOs, we reset
  829          * them.
  830          */
  831         val = FCR_ENABLE;
  832 #ifdef CPU_XBURST
  833         val |= FCR_UART_ON;
  834 #endif
  835         uart_setreg(bas, REG_FCR, val);
  836         uart_barrier(bas);
  837         if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
  838                 /*
  839                  * NS16450 or INS8250. We don't bother to differentiate
  840                  * between them. They're too old to be interesting.
  841                  */
  842                 uart_setreg(bas, REG_MCR, mcr);
  843                 uart_barrier(bas);
  844                 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
  845                 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
  846                 return (0);
  847         }
  848 
  849         val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
  850 #ifdef CPU_XBURST
  851         val |= FCR_UART_ON;
  852 #endif
  853         uart_setreg(bas, REG_FCR, val);
  854         uart_barrier(bas);
  855 
  856         count = 0;
  857         delay = ns8250_delay(bas);
  858 
  859         /* We have FIFOs. Drain the transmitter and receiver. */
  860         error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
  861         if (error) {
  862                 uart_setreg(bas, REG_MCR, mcr);
  863                 val = 0;
  864 #ifdef CPU_XBURST
  865                 val |= FCR_UART_ON;
  866 #endif
  867                 uart_setreg(bas, REG_FCR, val);
  868                 uart_barrier(bas);
  869                 goto describe;
  870         }
  871 
  872         /*
  873          * We should have a sufficiently clean "pipe" to determine the
  874          * size of the FIFOs. We send as much characters as is reasonable
  875          * and wait for the overflow bit in the LSR register to be
  876          * asserted, counting the characters as we send them. Based on
  877          * that count we know the FIFO size.
  878          */
  879         do {
  880                 uart_setreg(bas, REG_DATA, 0);
  881                 uart_barrier(bas);
  882                 count++;
  883 
  884                 limit = 30;
  885                 lsr = 0;
  886                 /*
  887                  * LSR bits are cleared upon read, so we must accumulate
  888                  * them to be able to test LSR_OE below.
  889                  */
  890                 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
  891                     --limit)
  892                         DELAY(delay);
  893                 if (limit == 0) {
  894                         /* See the comment in ns8250_init(). */
  895                         ier = uart_getreg(bas, REG_IER) & 0xe0;
  896                         uart_setreg(bas, REG_IER, ier);
  897                         uart_setreg(bas, REG_MCR, mcr);
  898                         val = 0;
  899 #ifdef CPU_XBURST
  900                         val |= FCR_UART_ON;
  901 #endif
  902                         uart_setreg(bas, REG_FCR, val);
  903                         uart_barrier(bas);
  904                         count = 0;
  905                         goto describe;
  906                 }
  907         } while ((lsr & LSR_OE) == 0 && count < 260);
  908         count--;
  909 
  910         uart_setreg(bas, REG_MCR, mcr);
  911 
  912         /* Reset FIFOs. */
  913         ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
  914 
  915  describe:
  916         if (count >= 14 && count <= 16) {
  917                 sc->sc_rxfifosz = 16;
  918                 device_set_desc(sc->sc_dev, "16550 or compatible");
  919         } else if (count >= 28 && count <= 32) {
  920                 sc->sc_rxfifosz = 32;
  921                 device_set_desc(sc->sc_dev, "16650 or compatible");
  922         } else if (count >= 56 && count <= 64) {
  923                 sc->sc_rxfifosz = 64;
  924                 device_set_desc(sc->sc_dev, "16750 or compatible");
  925         } else if (count >= 112 && count <= 128) {
  926                 sc->sc_rxfifosz = 128;
  927                 device_set_desc(sc->sc_dev, "16950 or compatible");
  928         } else if (count >= 224 && count <= 256) {
  929                 sc->sc_rxfifosz = 256;
  930                 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
  931         } else {
  932                 sc->sc_rxfifosz = 16;
  933                 device_set_desc(sc->sc_dev,
  934                     "Non-standard ns8250 class UART with FIFOs");
  935         }
  936 
  937         /*
  938          * Force the Tx FIFO size to 16 bytes for now. We don't program the
  939          * Tx trigger. Also, we assume that all data has been sent when the
  940          * interrupt happens.
  941          */
  942         sc->sc_txfifosz = 16;
  943 
  944 #if 0
  945         /*
  946          * XXX there are some issues related to hardware flow control and
  947          * it's likely that uart(4) is the cause. This basically needs more
  948          * investigation, but we avoid using for hardware flow control
  949          * until then.
  950          */
  951         /* 16650s or higher have automatic flow control. */
  952         if (sc->sc_rxfifosz > 16) {
  953                 sc->sc_hwiflow = 1;
  954                 sc->sc_hwoflow = 1;
  955         }
  956 #endif
  957 
  958         return (0);
  959 }
  960 
  961 int
  962 ns8250_bus_receive(struct uart_softc *sc)
  963 {
  964         struct uart_bas *bas;
  965         int xc;
  966         uint8_t lsr;
  967 
  968         bas = &sc->sc_bas;
  969         uart_lock(sc->sc_hwmtx);
  970         lsr = uart_getreg(bas, REG_LSR);
  971         while (lsr & LSR_RXRDY) {
  972                 if (uart_rx_full(sc)) {
  973                         sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
  974                         break;
  975                 }
  976                 xc = uart_getreg(bas, REG_DATA);
  977                 if (lsr & LSR_FE)
  978                         xc |= UART_STAT_FRAMERR;
  979                 if (lsr & LSR_PE)
  980                         xc |= UART_STAT_PARERR;
  981                 uart_rx_put(sc, xc);
  982                 lsr = uart_getreg(bas, REG_LSR);
  983         }
  984         /* Discard everything left in the Rx FIFO. */
  985         while (lsr & LSR_RXRDY) {
  986                 (void)uart_getreg(bas, REG_DATA);
  987                 uart_barrier(bas);
  988                 lsr = uart_getreg(bas, REG_LSR);
  989         }
  990         uart_unlock(sc->sc_hwmtx);
  991         return (0);
  992 }
  993 
  994 int
  995 ns8250_bus_setsig(struct uart_softc *sc, int sig)
  996 {
  997         struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
  998         struct uart_bas *bas;
  999         uint32_t new, old;
 1000 
 1001         bas = &sc->sc_bas;
 1002         do {
 1003                 old = sc->sc_hwsig;
 1004                 new = old;
 1005                 if (sig & SER_DDTR) {
 1006                         new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
 1007                 }
 1008                 if (sig & SER_DRTS) {
 1009                         new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
 1010                 }
 1011         } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
 1012         uart_lock(sc->sc_hwmtx);
 1013         ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
 1014         if (new & SER_DTR)
 1015                 ns8250->mcr |= MCR_DTR;
 1016         if (new & SER_RTS)
 1017                 ns8250->mcr |= MCR_RTS;
 1018         uart_setreg(bas, REG_MCR, ns8250->mcr);
 1019         uart_barrier(bas);
 1020         uart_unlock(sc->sc_hwmtx);
 1021         return (0);
 1022 }
 1023 
 1024 int
 1025 ns8250_bus_transmit(struct uart_softc *sc)
 1026 {
 1027         struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
 1028         struct uart_bas *bas;
 1029         int i;
 1030 
 1031         bas = &sc->sc_bas;
 1032         uart_lock(sc->sc_hwmtx);
 1033         while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
 1034                 DELAY(4);
 1035         for (i = 0; i < sc->sc_txdatasz; i++) {
 1036                 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
 1037                 uart_barrier(bas);
 1038         }
 1039         if (!broken_txfifo)
 1040                 ns8250->ier |= IER_ETXRDY;
 1041         uart_setreg(bas, REG_IER, ns8250->ier);
 1042         uart_barrier(bas);
 1043         if (broken_txfifo)
 1044                 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
 1045         else
 1046                 sc->sc_txbusy = 1;
 1047         uart_unlock(sc->sc_hwmtx);
 1048         if (broken_txfifo)
 1049                 uart_sched_softih(sc, SER_INT_TXIDLE);
 1050         return (0);
 1051 }
 1052 
 1053 void
 1054 ns8250_bus_grab(struct uart_softc *sc)
 1055 {
 1056         struct uart_bas *bas = &sc->sc_bas;
 1057         struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
 1058         u_char ier;
 1059 
 1060         /*
 1061          * turn off all interrupts to enter polling mode. Leave the
 1062          * saved mask alone. We'll restore whatever it was in ungrab.
 1063          * All pending interrupt signals are reset when IER is set to 0.
 1064          */
 1065         uart_lock(sc->sc_hwmtx);
 1066         ier = uart_getreg(bas, REG_IER);
 1067         uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
 1068         uart_barrier(bas);
 1069         uart_unlock(sc->sc_hwmtx);
 1070 }
 1071 
 1072 void
 1073 ns8250_bus_ungrab(struct uart_softc *sc)
 1074 {
 1075         struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
 1076         struct uart_bas *bas = &sc->sc_bas;
 1077 
 1078         /*
 1079          * Restore previous interrupt mask
 1080          */
 1081         uart_lock(sc->sc_hwmtx);
 1082         uart_setreg(bas, REG_IER, ns8250->ier);
 1083         uart_barrier(bas);
 1084         uart_unlock(sc->sc_hwmtx);
 1085 }

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