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sys/dev/uart/uart_dev_ns8250.c
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1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/sysctl.h> 36 #include <machine/bus.h> 37 38 #include <dev/uart/uart.h> 39 #include <dev/uart/uart_cpu.h> 40 #include <dev/uart/uart_bus.h> 41 42 #include <dev/ic/ns16550.h> 43 44 #include "uart_if.h" 45 46 #define DEFAULT_RCLK 1843200 47 48 /* 49 * Clear pending interrupts. THRE is cleared by reading IIR. Data 50 * that may have been received gets lost here. 51 */ 52 static void 53 ns8250_clrint(struct uart_bas *bas) 54 { 55 uint8_t iir, lsr; 56 57 iir = uart_getreg(bas, REG_IIR); 58 while ((iir & IIR_NOPEND) == 0) { 59 iir &= IIR_IMASK; 60 if (iir == IIR_RLS) { 61 lsr = uart_getreg(bas, REG_LSR); 62 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 63 (void)uart_getreg(bas, REG_DATA); 64 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 65 (void)uart_getreg(bas, REG_DATA); 66 else if (iir == IIR_MLSC) 67 (void)uart_getreg(bas, REG_MSR); 68 uart_barrier(bas); 69 iir = uart_getreg(bas, REG_IIR); 70 } 71 } 72 73 static int 74 ns8250_delay(struct uart_bas *bas) 75 { 76 int divisor; 77 u_char lcr; 78 79 lcr = uart_getreg(bas, REG_LCR); 80 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 81 uart_barrier(bas); 82 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 83 uart_barrier(bas); 84 uart_setreg(bas, REG_LCR, lcr); 85 uart_barrier(bas); 86 87 /* 1/10th the time to transmit 1 character (estimate). */ 88 if (divisor <= 134) 89 return (16000000 * divisor / bas->rclk); 90 return (16000 * divisor / (bas->rclk / 1000)); 91 } 92 93 static int 94 ns8250_divisor(int rclk, int baudrate) 95 { 96 int actual_baud, divisor; 97 int error; 98 99 if (baudrate == 0) 100 return (0); 101 102 divisor = (rclk / (baudrate << 3) + 1) >> 1; 103 if (divisor == 0 || divisor >= 65536) 104 return (0); 105 actual_baud = rclk / (divisor << 4); 106 107 /* 10 times error in percent: */ 108 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 109 110 /* 3.0% maximum error tolerance: */ 111 if (error < -30 || error > 30) 112 return (0); 113 114 return (divisor); 115 } 116 117 static int 118 ns8250_drain(struct uart_bas *bas, int what) 119 { 120 int delay, limit; 121 122 delay = ns8250_delay(bas); 123 124 if (what & UART_DRAIN_TRANSMITTER) { 125 /* 126 * Pick an arbitrary high limit to avoid getting stuck in 127 * an infinite loop when the hardware is broken. Make the 128 * limit high enough to handle large FIFOs. 129 */ 130 limit = 10*1024; 131 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 132 DELAY(delay); 133 if (limit == 0) { 134 /* printf("ns8250: transmitter appears stuck... "); */ 135 return (EIO); 136 } 137 } 138 139 if (what & UART_DRAIN_RECEIVER) { 140 /* 141 * Pick an arbitrary high limit to avoid getting stuck in 142 * an infinite loop when the hardware is broken. Make the 143 * limit high enough to handle large FIFOs and integrated 144 * UARTs. The HP rx2600 for example has 3 UARTs on the 145 * management board that tend to get a lot of data send 146 * to it when the UART is first activated. 147 */ 148 limit=10*4096; 149 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 150 (void)uart_getreg(bas, REG_DATA); 151 uart_barrier(bas); 152 DELAY(delay << 2); 153 } 154 if (limit == 0) { 155 /* printf("ns8250: receiver appears broken... "); */ 156 return (EIO); 157 } 158 } 159 160 return (0); 161 } 162 163 /* 164 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 165 * drained. WARNING: this function clobbers the FIFO setting! 166 */ 167 static void 168 ns8250_flush(struct uart_bas *bas, int what) 169 { 170 uint8_t fcr; 171 172 fcr = FCR_ENABLE; 173 if (what & UART_FLUSH_TRANSMITTER) 174 fcr |= FCR_XMT_RST; 175 if (what & UART_FLUSH_RECEIVER) 176 fcr |= FCR_RCV_RST; 177 uart_setreg(bas, REG_FCR, fcr); 178 uart_barrier(bas); 179 } 180 181 static int 182 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 183 int parity) 184 { 185 int divisor; 186 uint8_t lcr; 187 188 lcr = 0; 189 if (databits >= 8) 190 lcr |= LCR_8BITS; 191 else if (databits == 7) 192 lcr |= LCR_7BITS; 193 else if (databits == 6) 194 lcr |= LCR_6BITS; 195 else 196 lcr |= LCR_5BITS; 197 if (stopbits > 1) 198 lcr |= LCR_STOPB; 199 lcr |= parity << 3; 200 201 /* Set baudrate. */ 202 if (baudrate > 0) { 203 divisor = ns8250_divisor(bas->rclk, baudrate); 204 if (divisor == 0) 205 return (EINVAL); 206 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 207 uart_barrier(bas); 208 uart_setreg(bas, REG_DLL, divisor & 0xff); 209 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 210 uart_barrier(bas); 211 } 212 213 /* Set LCR and clear DLAB. */ 214 uart_setreg(bas, REG_LCR, lcr); 215 uart_barrier(bas); 216 return (0); 217 } 218 219 /* 220 * Low-level UART interface. 221 */ 222 static int ns8250_probe(struct uart_bas *bas); 223 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 224 static void ns8250_term(struct uart_bas *bas); 225 static void ns8250_putc(struct uart_bas *bas, int); 226 static int ns8250_rxready(struct uart_bas *bas); 227 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 228 229 static struct uart_ops uart_ns8250_ops = { 230 .probe = ns8250_probe, 231 .init = ns8250_init, 232 .term = ns8250_term, 233 .putc = ns8250_putc, 234 .rxready = ns8250_rxready, 235 .getc = ns8250_getc, 236 }; 237 238 static int 239 ns8250_probe(struct uart_bas *bas) 240 { 241 u_char val; 242 243 /* Check known 0 bits that don't depend on DLAB. */ 244 val = uart_getreg(bas, REG_IIR); 245 if (val & 0x30) 246 return (ENXIO); 247 /* 248 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 249 * chip, but otherwise doesn't seem to have a function. In 250 * other words, uart(4) works regardless. Ignore that bit so 251 * the probe succeeds. 252 */ 253 val = uart_getreg(bas, REG_MCR); 254 if (val & 0xa0) 255 return (ENXIO); 256 257 return (0); 258 } 259 260 static void 261 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 262 int parity) 263 { 264 u_char ier; 265 266 if (bas->rclk == 0) 267 bas->rclk = DEFAULT_RCLK; 268 ns8250_param(bas, baudrate, databits, stopbits, parity); 269 270 /* Disable all interrupt sources. */ 271 /* 272 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 273 * UARTs split the receive time-out interrupt bit out separately as 274 * 0x10. This gets handled by ier_mask and ier_rxbits below. 275 */ 276 ier = uart_getreg(bas, REG_IER) & 0xe0; 277 uart_setreg(bas, REG_IER, ier); 278 uart_barrier(bas); 279 280 /* Disable the FIFO (if present). */ 281 uart_setreg(bas, REG_FCR, 0); 282 uart_barrier(bas); 283 284 /* Set RTS & DTR. */ 285 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 286 uart_barrier(bas); 287 288 ns8250_clrint(bas); 289 } 290 291 static void 292 ns8250_term(struct uart_bas *bas) 293 { 294 295 /* Clear RTS & DTR. */ 296 uart_setreg(bas, REG_MCR, MCR_IE); 297 uart_barrier(bas); 298 } 299 300 static void 301 ns8250_putc(struct uart_bas *bas, int c) 302 { 303 int limit; 304 305 limit = 250000; 306 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 307 DELAY(4); 308 uart_setreg(bas, REG_DATA, c); 309 uart_barrier(bas); 310 limit = 250000; 311 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 312 DELAY(4); 313 } 314 315 static int 316 ns8250_rxready(struct uart_bas *bas) 317 { 318 319 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 320 } 321 322 static int 323 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 324 { 325 int c; 326 327 uart_lock(hwmtx); 328 329 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 330 uart_unlock(hwmtx); 331 DELAY(4); 332 uart_lock(hwmtx); 333 } 334 335 c = uart_getreg(bas, REG_DATA); 336 337 uart_unlock(hwmtx); 338 339 return (c); 340 } 341 342 /* 343 * High-level UART interface. 344 */ 345 struct ns8250_softc { 346 struct uart_softc base; 347 uint8_t fcr; 348 uint8_t ier; 349 uint8_t mcr; 350 351 uint8_t ier_mask; 352 uint8_t ier_rxbits; 353 }; 354 355 static int ns8250_bus_attach(struct uart_softc *); 356 static int ns8250_bus_detach(struct uart_softc *); 357 static int ns8250_bus_flush(struct uart_softc *, int); 358 static int ns8250_bus_getsig(struct uart_softc *); 359 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 360 static int ns8250_bus_ipend(struct uart_softc *); 361 static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 362 static int ns8250_bus_probe(struct uart_softc *); 363 static int ns8250_bus_receive(struct uart_softc *); 364 static int ns8250_bus_setsig(struct uart_softc *, int); 365 static int ns8250_bus_transmit(struct uart_softc *); 366 367 static kobj_method_t ns8250_methods[] = { 368 KOBJMETHOD(uart_attach, ns8250_bus_attach), 369 KOBJMETHOD(uart_detach, ns8250_bus_detach), 370 KOBJMETHOD(uart_flush, ns8250_bus_flush), 371 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 372 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 373 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 374 KOBJMETHOD(uart_param, ns8250_bus_param), 375 KOBJMETHOD(uart_probe, ns8250_bus_probe), 376 KOBJMETHOD(uart_receive, ns8250_bus_receive), 377 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 378 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 379 { 0, 0 } 380 }; 381 382 struct uart_class uart_ns8250_class = { 383 "ns8250", 384 ns8250_methods, 385 sizeof(struct ns8250_softc), 386 .uc_ops = &uart_ns8250_ops, 387 .uc_range = 8, 388 .uc_rclk = DEFAULT_RCLK 389 }; 390 391 #define SIGCHG(c, i, s, d) \ 392 if (c) { \ 393 i |= (i & s) ? s : s | d; \ 394 } else { \ 395 i = (i & s) ? (i & ~s) | d : i; \ 396 } 397 398 static int 399 ns8250_bus_attach(struct uart_softc *sc) 400 { 401 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 402 struct uart_bas *bas; 403 unsigned int ivar; 404 405 bas = &sc->sc_bas; 406 407 ns8250->mcr = uart_getreg(bas, REG_MCR); 408 ns8250->fcr = FCR_ENABLE; 409 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 410 &ivar)) { 411 if (UART_FLAGS_FCR_RX_LOW(ivar)) 412 ns8250->fcr |= FCR_RX_LOW; 413 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 414 ns8250->fcr |= FCR_RX_MEDL; 415 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 416 ns8250->fcr |= FCR_RX_HIGH; 417 else 418 ns8250->fcr |= FCR_RX_MEDH; 419 } else 420 ns8250->fcr |= FCR_RX_MEDH; 421 422 /* Get IER mask */ 423 ivar = 0xf0; 424 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 425 &ivar); 426 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 427 428 /* Get IER RX interrupt bits */ 429 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 430 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 431 &ivar); 432 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 433 434 uart_setreg(bas, REG_FCR, ns8250->fcr); 435 uart_barrier(bas); 436 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 437 438 if (ns8250->mcr & MCR_DTR) 439 sc->sc_hwsig |= SER_DTR; 440 if (ns8250->mcr & MCR_RTS) 441 sc->sc_hwsig |= SER_RTS; 442 ns8250_bus_getsig(sc); 443 444 ns8250_clrint(bas); 445 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 446 ns8250->ier |= ns8250->ier_rxbits; 447 uart_setreg(bas, REG_IER, ns8250->ier); 448 uart_barrier(bas); 449 450 return (0); 451 } 452 453 static int 454 ns8250_bus_detach(struct uart_softc *sc) 455 { 456 struct ns8250_softc *ns8250; 457 struct uart_bas *bas; 458 u_char ier; 459 460 ns8250 = (struct ns8250_softc *)sc; 461 bas = &sc->sc_bas; 462 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 463 uart_setreg(bas, REG_IER, ier); 464 uart_barrier(bas); 465 ns8250_clrint(bas); 466 return (0); 467 } 468 469 static int 470 ns8250_bus_flush(struct uart_softc *sc, int what) 471 { 472 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 473 struct uart_bas *bas; 474 int error; 475 476 bas = &sc->sc_bas; 477 uart_lock(sc->sc_hwmtx); 478 if (sc->sc_rxfifosz > 1) { 479 ns8250_flush(bas, what); 480 uart_setreg(bas, REG_FCR, ns8250->fcr); 481 uart_barrier(bas); 482 error = 0; 483 } else 484 error = ns8250_drain(bas, what); 485 uart_unlock(sc->sc_hwmtx); 486 return (error); 487 } 488 489 static int 490 ns8250_bus_getsig(struct uart_softc *sc) 491 { 492 uint32_t new, old, sig; 493 uint8_t msr; 494 495 do { 496 old = sc->sc_hwsig; 497 sig = old; 498 uart_lock(sc->sc_hwmtx); 499 msr = uart_getreg(&sc->sc_bas, REG_MSR); 500 uart_unlock(sc->sc_hwmtx); 501 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 502 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 503 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 504 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 505 new = sig & ~SER_MASK_DELTA; 506 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 507 return (sig); 508 } 509 510 static int 511 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 512 { 513 struct uart_bas *bas; 514 int baudrate, divisor, error; 515 uint8_t efr, lcr; 516 517 bas = &sc->sc_bas; 518 error = 0; 519 uart_lock(sc->sc_hwmtx); 520 switch (request) { 521 case UART_IOCTL_BREAK: 522 lcr = uart_getreg(bas, REG_LCR); 523 if (data) 524 lcr |= LCR_SBREAK; 525 else 526 lcr &= ~LCR_SBREAK; 527 uart_setreg(bas, REG_LCR, lcr); 528 uart_barrier(bas); 529 break; 530 case UART_IOCTL_IFLOW: 531 lcr = uart_getreg(bas, REG_LCR); 532 uart_barrier(bas); 533 uart_setreg(bas, REG_LCR, 0xbf); 534 uart_barrier(bas); 535 efr = uart_getreg(bas, REG_EFR); 536 if (data) 537 efr |= EFR_RTS; 538 else 539 efr &= ~EFR_RTS; 540 uart_setreg(bas, REG_EFR, efr); 541 uart_barrier(bas); 542 uart_setreg(bas, REG_LCR, lcr); 543 uart_barrier(bas); 544 break; 545 case UART_IOCTL_OFLOW: 546 lcr = uart_getreg(bas, REG_LCR); 547 uart_barrier(bas); 548 uart_setreg(bas, REG_LCR, 0xbf); 549 uart_barrier(bas); 550 efr = uart_getreg(bas, REG_EFR); 551 if (data) 552 efr |= EFR_CTS; 553 else 554 efr &= ~EFR_CTS; 555 uart_setreg(bas, REG_EFR, efr); 556 uart_barrier(bas); 557 uart_setreg(bas, REG_LCR, lcr); 558 uart_barrier(bas); 559 break; 560 case UART_IOCTL_BAUD: 561 lcr = uart_getreg(bas, REG_LCR); 562 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 563 uart_barrier(bas); 564 divisor = uart_getreg(bas, REG_DLL) | 565 (uart_getreg(bas, REG_DLH) << 8); 566 uart_barrier(bas); 567 uart_setreg(bas, REG_LCR, lcr); 568 uart_barrier(bas); 569 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 570 if (baudrate > 0) 571 *(int*)data = baudrate; 572 else 573 error = ENXIO; 574 break; 575 default: 576 error = EINVAL; 577 break; 578 } 579 uart_unlock(sc->sc_hwmtx); 580 return (error); 581 } 582 583 static int 584 ns8250_bus_ipend(struct uart_softc *sc) 585 { 586 struct uart_bas *bas; 587 int ipend; 588 uint8_t iir, lsr; 589 590 bas = &sc->sc_bas; 591 uart_lock(sc->sc_hwmtx); 592 iir = uart_getreg(bas, REG_IIR); 593 if (iir & IIR_NOPEND) { 594 uart_unlock(sc->sc_hwmtx); 595 return (0); 596 } 597 ipend = 0; 598 if (iir & IIR_RXRDY) { 599 lsr = uart_getreg(bas, REG_LSR); 600 if (lsr & LSR_OE) 601 ipend |= SER_INT_OVERRUN; 602 if (lsr & LSR_BI) 603 ipend |= SER_INT_BREAK; 604 if (lsr & LSR_RXRDY) 605 ipend |= SER_INT_RXREADY; 606 } else { 607 if (iir & IIR_TXRDY) 608 ipend |= SER_INT_TXIDLE; 609 else 610 ipend |= SER_INT_SIGCHG; 611 } 612 if (ipend == 0) 613 ns8250_clrint(bas); 614 uart_unlock(sc->sc_hwmtx); 615 return (ipend); 616 } 617 618 static int 619 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 620 int stopbits, int parity) 621 { 622 struct uart_bas *bas; 623 int error; 624 625 bas = &sc->sc_bas; 626 uart_lock(sc->sc_hwmtx); 627 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 628 uart_unlock(sc->sc_hwmtx); 629 return (error); 630 } 631 632 static int 633 ns8250_bus_probe(struct uart_softc *sc) 634 { 635 struct ns8250_softc *ns8250; 636 struct uart_bas *bas; 637 int count, delay, error, limit; 638 uint8_t lsr, mcr, ier; 639 640 ns8250 = (struct ns8250_softc *)sc; 641 bas = &sc->sc_bas; 642 643 error = ns8250_probe(bas); 644 if (error) 645 return (error); 646 647 mcr = MCR_IE; 648 if (sc->sc_sysdev == NULL) { 649 /* By using ns8250_init() we also set DTR and RTS. */ 650 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 651 } else 652 mcr |= MCR_DTR | MCR_RTS; 653 654 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 655 if (error) 656 return (error); 657 658 /* 659 * Set loopback mode. This avoids having garbage on the wire and 660 * also allows us send and receive data. We set DTR and RTS to 661 * avoid the possibility that automatic flow-control prevents 662 * any data from being sent. 663 */ 664 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 665 uart_barrier(bas); 666 667 /* 668 * Enable FIFOs. And check that the UART has them. If not, we're 669 * done. Since this is the first time we enable the FIFOs, we reset 670 * them. 671 */ 672 uart_setreg(bas, REG_FCR, FCR_ENABLE); 673 uart_barrier(bas); 674 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 675 /* 676 * NS16450 or INS8250. We don't bother to differentiate 677 * between them. They're too old to be interesting. 678 */ 679 uart_setreg(bas, REG_MCR, mcr); 680 uart_barrier(bas); 681 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 682 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 683 return (0); 684 } 685 686 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 687 uart_barrier(bas); 688 689 count = 0; 690 delay = ns8250_delay(bas); 691 692 /* We have FIFOs. Drain the transmitter and receiver. */ 693 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 694 if (error) { 695 uart_setreg(bas, REG_MCR, mcr); 696 uart_setreg(bas, REG_FCR, 0); 697 uart_barrier(bas); 698 goto describe; 699 } 700 701 /* 702 * We should have a sufficiently clean "pipe" to determine the 703 * size of the FIFOs. We send as much characters as is reasonable 704 * and wait for the overflow bit in the LSR register to be 705 * asserted, counting the characters as we send them. Based on 706 * that count we know the FIFO size. 707 */ 708 do { 709 uart_setreg(bas, REG_DATA, 0); 710 uart_barrier(bas); 711 count++; 712 713 limit = 30; 714 lsr = 0; 715 /* 716 * LSR bits are cleared upon read, so we must accumulate 717 * them to be able to test LSR_OE below. 718 */ 719 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 720 --limit) 721 DELAY(delay); 722 if (limit == 0) { 723 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 724 uart_setreg(bas, REG_IER, ier); 725 uart_setreg(bas, REG_MCR, mcr); 726 uart_setreg(bas, REG_FCR, 0); 727 uart_barrier(bas); 728 count = 0; 729 goto describe; 730 } 731 } while ((lsr & LSR_OE) == 0 && count < 130); 732 count--; 733 734 uart_setreg(bas, REG_MCR, mcr); 735 736 /* Reset FIFOs. */ 737 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 738 739 describe: 740 if (count >= 14 && count <= 16) { 741 sc->sc_rxfifosz = 16; 742 device_set_desc(sc->sc_dev, "16550 or compatible"); 743 } else if (count >= 28 && count <= 32) { 744 sc->sc_rxfifosz = 32; 745 device_set_desc(sc->sc_dev, "16650 or compatible"); 746 } else if (count >= 56 && count <= 64) { 747 sc->sc_rxfifosz = 64; 748 device_set_desc(sc->sc_dev, "16750 or compatible"); 749 } else if (count >= 112 && count <= 128) { 750 sc->sc_rxfifosz = 128; 751 device_set_desc(sc->sc_dev, "16950 or compatible"); 752 } else { 753 sc->sc_rxfifosz = 16; 754 device_set_desc(sc->sc_dev, 755 "Non-standard ns8250 class UART with FIFOs"); 756 } 757 758 /* 759 * Force the Tx FIFO size to 16 bytes for now. We don't program the 760 * Tx trigger. Also, we assume that all data has been sent when the 761 * interrupt happens. 762 */ 763 sc->sc_txfifosz = 16; 764 765 #if 0 766 /* 767 * XXX there are some issues related to hardware flow control and 768 * it's likely that uart(4) is the cause. This basicly needs more 769 * investigation, but we avoid using for hardware flow control 770 * until then. 771 */ 772 /* 16650s or higher have automatic flow control. */ 773 if (sc->sc_rxfifosz > 16) { 774 sc->sc_hwiflow = 1; 775 sc->sc_hwoflow = 1; 776 } 777 #endif 778 779 return (0); 780 } 781 782 static int 783 ns8250_bus_receive(struct uart_softc *sc) 784 { 785 struct uart_bas *bas; 786 int xc; 787 uint8_t lsr; 788 789 bas = &sc->sc_bas; 790 uart_lock(sc->sc_hwmtx); 791 lsr = uart_getreg(bas, REG_LSR); 792 while (lsr & LSR_RXRDY) { 793 if (uart_rx_full(sc)) { 794 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 795 break; 796 } 797 xc = uart_getreg(bas, REG_DATA); 798 if (lsr & LSR_FE) 799 xc |= UART_STAT_FRAMERR; 800 if (lsr & LSR_PE) 801 xc |= UART_STAT_PARERR; 802 uart_rx_put(sc, xc); 803 lsr = uart_getreg(bas, REG_LSR); 804 } 805 /* Discard everything left in the Rx FIFO. */ 806 while (lsr & LSR_RXRDY) { 807 (void)uart_getreg(bas, REG_DATA); 808 uart_barrier(bas); 809 lsr = uart_getreg(bas, REG_LSR); 810 } 811 uart_unlock(sc->sc_hwmtx); 812 return (0); 813 } 814 815 static int 816 ns8250_bus_setsig(struct uart_softc *sc, int sig) 817 { 818 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 819 struct uart_bas *bas; 820 uint32_t new, old; 821 822 bas = &sc->sc_bas; 823 do { 824 old = sc->sc_hwsig; 825 new = old; 826 if (sig & SER_DDTR) { 827 SIGCHG(sig & SER_DTR, new, SER_DTR, 828 SER_DDTR); 829 } 830 if (sig & SER_DRTS) { 831 SIGCHG(sig & SER_RTS, new, SER_RTS, 832 SER_DRTS); 833 } 834 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 835 uart_lock(sc->sc_hwmtx); 836 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 837 if (new & SER_DTR) 838 ns8250->mcr |= MCR_DTR; 839 if (new & SER_RTS) 840 ns8250->mcr |= MCR_RTS; 841 uart_setreg(bas, REG_MCR, ns8250->mcr); 842 uart_barrier(bas); 843 uart_unlock(sc->sc_hwmtx); 844 return (0); 845 } 846 847 static int broken_txfifo = 0; 848 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 849 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 850 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 851 852 static int 853 ns8250_bus_transmit(struct uart_softc *sc) 854 { 855 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 856 struct uart_bas *bas; 857 int i; 858 859 bas = &sc->sc_bas; 860 uart_lock(sc->sc_hwmtx); 861 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 862 ; 863 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 864 uart_barrier(bas); 865 for (i = 0; i < sc->sc_txdatasz; i++) { 866 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 867 uart_barrier(bas); 868 } 869 if (broken_txfifo) 870 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 871 else 872 sc->sc_txbusy = 1; 873 uart_unlock(sc->sc_hwmtx); 874 if (broken_txfifo) 875 uart_sched_softih(sc, SER_INT_TXIDLE); 876 return (0); 877 }
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