The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ubsec/ubsec.c

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    1 /*      $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $       */
    2 
    3 /*-
    4  * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
    5  * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
    6  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
    7  *
    8  * All rights reserved.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by Jason L. Wright
   21  * 4. The name of the author may not be used to endorse or promote products
   22  *    derived from this software without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   27  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   33  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   34  * POSSIBILITY OF SUCH DAMAGE.
   35  *
   36  * Effort sponsored in part by the Defense Advanced Research Projects
   37  * Agency (DARPA) and Air Force Research Laboratory, Air Force
   38  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/11.2/sys/dev/ubsec/ubsec.c 331722 2018-03-29 02:50:57Z eadler $");
   43 
   44 /*
   45  * uBsec 5[56]01, 58xx hardware crypto accelerator
   46  */
   47 
   48 #include "opt_ubsec.h"
   49 
   50 #include <sys/param.h>
   51 #include <sys/systm.h>
   52 #include <sys/proc.h>
   53 #include <sys/errno.h>
   54 #include <sys/malloc.h>
   55 #include <sys/kernel.h>
   56 #include <sys/module.h>
   57 #include <sys/mbuf.h>
   58 #include <sys/lock.h>
   59 #include <sys/mutex.h>
   60 #include <sys/sysctl.h>
   61 #include <sys/endian.h>
   62 
   63 #include <vm/vm.h>
   64 #include <vm/pmap.h>
   65 
   66 #include <machine/bus.h>
   67 #include <machine/resource.h>
   68 #include <sys/bus.h>
   69 #include <sys/rman.h>
   70 
   71 #include <crypto/sha1.h>
   72 #include <opencrypto/cryptodev.h>
   73 #include <opencrypto/cryptosoft.h>
   74 #include <sys/md5.h>
   75 #include <sys/random.h>
   76 #include <sys/kobj.h>
   77 
   78 #include "cryptodev_if.h"
   79 
   80 #include <dev/pci/pcivar.h>
   81 #include <dev/pci/pcireg.h>
   82 
   83 /* grr, #defines for gratuitous incompatibility in queue.h */
   84 #define SIMPLEQ_HEAD            STAILQ_HEAD
   85 #define SIMPLEQ_ENTRY           STAILQ_ENTRY
   86 #define SIMPLEQ_INIT            STAILQ_INIT
   87 #define SIMPLEQ_INSERT_TAIL     STAILQ_INSERT_TAIL
   88 #define SIMPLEQ_EMPTY           STAILQ_EMPTY
   89 #define SIMPLEQ_FIRST           STAILQ_FIRST
   90 #define SIMPLEQ_REMOVE_HEAD     STAILQ_REMOVE_HEAD
   91 #define SIMPLEQ_FOREACH         STAILQ_FOREACH
   92 /* ditto for endian.h */
   93 #define letoh16(x)              le16toh(x)
   94 #define letoh32(x)              le32toh(x)
   95 
   96 #ifdef UBSEC_RNDTEST
   97 #include <dev/rndtest/rndtest.h>
   98 #endif
   99 #include <dev/ubsec/ubsecreg.h>
  100 #include <dev/ubsec/ubsecvar.h>
  101 
  102 /*
  103  * Prototypes and count for the pci_device structure
  104  */
  105 static  int ubsec_probe(device_t);
  106 static  int ubsec_attach(device_t);
  107 static  int ubsec_detach(device_t);
  108 static  int ubsec_suspend(device_t);
  109 static  int ubsec_resume(device_t);
  110 static  int ubsec_shutdown(device_t);
  111 
  112 static  int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
  113 static  int ubsec_freesession(device_t, u_int64_t);
  114 static  int ubsec_process(device_t, struct cryptop *, int);
  115 static  int ubsec_kprocess(device_t, struct cryptkop *, int);
  116 
  117 static device_method_t ubsec_methods[] = {
  118         /* Device interface */
  119         DEVMETHOD(device_probe,         ubsec_probe),
  120         DEVMETHOD(device_attach,        ubsec_attach),
  121         DEVMETHOD(device_detach,        ubsec_detach),
  122         DEVMETHOD(device_suspend,       ubsec_suspend),
  123         DEVMETHOD(device_resume,        ubsec_resume),
  124         DEVMETHOD(device_shutdown,      ubsec_shutdown),
  125 
  126         /* crypto device methods */
  127         DEVMETHOD(cryptodev_newsession, ubsec_newsession),
  128         DEVMETHOD(cryptodev_freesession,ubsec_freesession),
  129         DEVMETHOD(cryptodev_process,    ubsec_process),
  130         DEVMETHOD(cryptodev_kprocess,   ubsec_kprocess),
  131 
  132         DEVMETHOD_END
  133 };
  134 static driver_t ubsec_driver = {
  135         "ubsec",
  136         ubsec_methods,
  137         sizeof (struct ubsec_softc)
  138 };
  139 static devclass_t ubsec_devclass;
  140 
  141 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
  142 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
  143 #ifdef UBSEC_RNDTEST
  144 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
  145 #endif
  146 
  147 static  void ubsec_intr(void *);
  148 static  void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
  149 static  void ubsec_feed(struct ubsec_softc *);
  150 static  void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
  151 static  void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
  152 static  int ubsec_feed2(struct ubsec_softc *);
  153 static  void ubsec_rng(void *);
  154 static  int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
  155                              struct ubsec_dma_alloc *, int);
  156 #define ubsec_dma_sync(_dma, _flags) \
  157         bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
  158 static  void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
  159 static  int ubsec_dmamap_aligned(struct ubsec_operand *op);
  160 
  161 static  void ubsec_reset_board(struct ubsec_softc *sc);
  162 static  void ubsec_init_board(struct ubsec_softc *sc);
  163 static  void ubsec_init_pciregs(device_t dev);
  164 static  void ubsec_totalreset(struct ubsec_softc *sc);
  165 
  166 static  int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
  167 
  168 static  int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
  169 static  int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
  170 static  int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
  171 static  void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
  172 static  int ubsec_ksigbits(struct crparam *);
  173 static  void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
  174 static  void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
  175 
  176 static SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0,
  177     "Broadcom driver parameters");
  178 
  179 #ifdef UBSEC_DEBUG
  180 static  void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
  181 static  void ubsec_dump_mcr(struct ubsec_mcr *);
  182 static  void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
  183 
  184 static  int ubsec_debug = 0;
  185 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
  186             0, "control debugging msgs");
  187 #endif
  188 
  189 #define READ_REG(sc,r) \
  190         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
  191 
  192 #define WRITE_REG(sc,reg,val) \
  193         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
  194 
  195 #define SWAP32(x) (x) = htole32(ntohl((x)))
  196 #define HTOLE32(x) (x) = htole32(x)
  197 
  198 struct ubsec_stats ubsecstats;
  199 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
  200             ubsec_stats, "driver statistics");
  201 
  202 static int
  203 ubsec_probe(device_t dev)
  204 {
  205         if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
  206             (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
  207              pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
  208                 return (BUS_PROBE_DEFAULT);
  209         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
  210             (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
  211              pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
  212                 return (BUS_PROBE_DEFAULT);
  213         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
  214             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
  215              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
  216              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
  217              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
  218              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
  219              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
  220              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
  221              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825
  222              ))
  223                 return (BUS_PROBE_DEFAULT);
  224         return (ENXIO);
  225 }
  226 
  227 static const char*
  228 ubsec_partname(struct ubsec_softc *sc)
  229 {
  230         /* XXX sprintf numbers when not decoded */
  231         switch (pci_get_vendor(sc->sc_dev)) {
  232         case PCI_VENDOR_BROADCOM:
  233                 switch (pci_get_device(sc->sc_dev)) {
  234                 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
  235                 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
  236                 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
  237                 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
  238                 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
  239                 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
  240                 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
  241                 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825";
  242                 }
  243                 return "Broadcom unknown-part";
  244         case PCI_VENDOR_BLUESTEEL:
  245                 switch (pci_get_device(sc->sc_dev)) {
  246                 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
  247                 }
  248                 return "Bluesteel unknown-part";
  249         case PCI_VENDOR_SUN:
  250                 switch (pci_get_device(sc->sc_dev)) {
  251                 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
  252                 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
  253                 }
  254                 return "Sun unknown-part";
  255         }
  256         return "Unknown-vendor unknown-part";
  257 }
  258 
  259 static void
  260 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
  261 {
  262         /* MarkM: FIX!! Check that this does not swamp the harvester! */
  263         random_harvest_queue(buf, count, count*NBBY/2, RANDOM_PURE_UBSEC);
  264 }
  265 
  266 static int
  267 ubsec_attach(device_t dev)
  268 {
  269         struct ubsec_softc *sc = device_get_softc(dev);
  270         struct ubsec_dma *dmap;
  271         u_int32_t i;
  272         int rid;
  273 
  274         bzero(sc, sizeof (*sc));
  275         sc->sc_dev = dev;
  276 
  277         SIMPLEQ_INIT(&sc->sc_queue);
  278         SIMPLEQ_INIT(&sc->sc_qchip);
  279         SIMPLEQ_INIT(&sc->sc_queue2);
  280         SIMPLEQ_INIT(&sc->sc_qchip2);
  281         SIMPLEQ_INIT(&sc->sc_q2free);
  282 
  283         /* XXX handle power management */
  284 
  285         sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
  286 
  287         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
  288             pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
  289                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
  290 
  291         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
  292             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
  293              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
  294                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
  295 
  296         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
  297             pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
  298                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
  299                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
  300 
  301         if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
  302              (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
  303               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
  304               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
  305               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) ||
  306             (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
  307              (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
  308               pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
  309                 /* NB: the 5821/5822 defines some additional status bits */
  310                 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
  311                     BS_STAT_MCR2_ALLEMPTY;
  312                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
  313                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
  314         }
  315 
  316         pci_enable_busmaster(dev);
  317 
  318         /*
  319          * Setup memory-mapping of PCI registers.
  320          */
  321         rid = BS_BAR;
  322         sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  323                                            RF_ACTIVE);
  324         if (sc->sc_sr == NULL) {
  325                 device_printf(dev, "cannot map register space\n");
  326                 goto bad;
  327         }
  328         sc->sc_st = rman_get_bustag(sc->sc_sr);
  329         sc->sc_sh = rman_get_bushandle(sc->sc_sr);
  330 
  331         /*
  332          * Arrange interrupt line.
  333          */
  334         rid = 0;
  335         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  336                                             RF_SHAREABLE|RF_ACTIVE);
  337         if (sc->sc_irq == NULL) {
  338                 device_printf(dev, "could not map interrupt\n");
  339                 goto bad1;
  340         }
  341         /*
  342          * NB: Network code assumes we are blocked with splimp()
  343          *     so make sure the IRQ is mapped appropriately.
  344          */
  345         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
  346                            NULL, ubsec_intr, sc, &sc->sc_ih)) {
  347                 device_printf(dev, "could not establish interrupt\n");
  348                 goto bad2;
  349         }
  350 
  351         sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
  352         if (sc->sc_cid < 0) {
  353                 device_printf(dev, "could not get crypto driver id\n");
  354                 goto bad3;
  355         }
  356 
  357         /*
  358          * Setup DMA descriptor area.
  359          */
  360         if (bus_dma_tag_create(bus_get_dma_tag(dev),    /* parent */
  361                                1, 0,                    /* alignment, bounds */
  362                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
  363                                BUS_SPACE_MAXADDR,       /* highaddr */
  364                                NULL, NULL,              /* filter, filterarg */
  365                                0x3ffff,                 /* maxsize */
  366                                UBS_MAX_SCATTER,         /* nsegments */
  367                                0xffff,                  /* maxsegsize */
  368                                BUS_DMA_ALLOCNOW,        /* flags */
  369                                NULL, NULL,              /* lockfunc, lockarg */
  370                                &sc->sc_dmat)) {
  371                 device_printf(dev, "cannot allocate DMA tag\n");
  372                 goto bad4;
  373         }
  374         SIMPLEQ_INIT(&sc->sc_freequeue);
  375         dmap = sc->sc_dmaa;
  376         for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
  377                 struct ubsec_q *q;
  378 
  379                 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
  380                     M_DEVBUF, M_NOWAIT);
  381                 if (q == NULL) {
  382                         device_printf(dev, "cannot allocate queue buffers\n");
  383                         break;
  384                 }
  385 
  386                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
  387                     &dmap->d_alloc, 0)) {
  388                         device_printf(dev, "cannot allocate dma buffers\n");
  389                         free(q, M_DEVBUF);
  390                         break;
  391                 }
  392                 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
  393 
  394                 q->q_dma = dmap;
  395                 sc->sc_queuea[i] = q;
  396 
  397                 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
  398         }
  399         mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
  400                 "mcr1 operations", MTX_DEF);
  401         mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
  402                 "mcr1 free q", MTX_DEF);
  403 
  404         device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
  405 
  406         crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
  407         crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
  408         crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
  409         crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
  410 
  411         /*
  412          * Reset Broadcom chip
  413          */
  414         ubsec_reset_board(sc);
  415 
  416         /*
  417          * Init Broadcom specific PCI settings
  418          */
  419         ubsec_init_pciregs(dev);
  420 
  421         /*
  422          * Init Broadcom chip
  423          */
  424         ubsec_init_board(sc);
  425 
  426 #ifndef UBSEC_NO_RNG
  427         if (sc->sc_flags & UBS_FLAGS_RNG) {
  428                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
  429 #ifdef UBSEC_RNDTEST
  430                 sc->sc_rndtest = rndtest_attach(dev);
  431                 if (sc->sc_rndtest)
  432                         sc->sc_harvest = rndtest_harvest;
  433                 else
  434                         sc->sc_harvest = default_harvest;
  435 #else
  436                 sc->sc_harvest = default_harvest;
  437 #endif
  438 
  439                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
  440                     &sc->sc_rng.rng_q.q_mcr, 0))
  441                         goto skip_rng;
  442 
  443                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
  444                     &sc->sc_rng.rng_q.q_ctx, 0)) {
  445                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
  446                         goto skip_rng;
  447                 }
  448 
  449                 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
  450                     UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
  451                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
  452                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
  453                         goto skip_rng;
  454                 }
  455 
  456                 if (hz >= 100)
  457                         sc->sc_rnghz = hz / 100;
  458                 else
  459                         sc->sc_rnghz = 1;
  460                 callout_init(&sc->sc_rngto, 1);
  461                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
  462 skip_rng:
  463         ;
  464         }
  465 #endif /* UBSEC_NO_RNG */
  466         mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
  467                 "mcr2 operations", MTX_DEF);
  468 
  469         if (sc->sc_flags & UBS_FLAGS_KEY) {
  470                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
  471 
  472                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
  473 #if 0
  474                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
  475 #endif
  476         }
  477         return (0);
  478 bad4:
  479         crypto_unregister_all(sc->sc_cid);
  480 bad3:
  481         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
  482 bad2:
  483         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
  484 bad1:
  485         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
  486 bad:
  487         return (ENXIO);
  488 }
  489 
  490 /*
  491  * Detach a device that successfully probed.
  492  */
  493 static int
  494 ubsec_detach(device_t dev)
  495 {
  496         struct ubsec_softc *sc = device_get_softc(dev);
  497 
  498         /* XXX wait/abort active ops */
  499 
  500         /* disable interrupts */
  501         WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
  502                 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
  503 
  504         callout_stop(&sc->sc_rngto);
  505 
  506         crypto_unregister_all(sc->sc_cid);
  507 
  508 #ifdef UBSEC_RNDTEST
  509         if (sc->sc_rndtest)
  510                 rndtest_detach(sc->sc_rndtest);
  511 #endif
  512 
  513         while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
  514                 struct ubsec_q *q;
  515 
  516                 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
  517                 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
  518                 ubsec_dma_free(sc, &q->q_dma->d_alloc);
  519                 free(q, M_DEVBUF);
  520         }
  521         mtx_destroy(&sc->sc_mcr1lock);
  522         mtx_destroy(&sc->sc_freeqlock);
  523 #ifndef UBSEC_NO_RNG
  524         if (sc->sc_flags & UBS_FLAGS_RNG) {
  525                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
  526                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
  527                 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
  528         }
  529 #endif /* UBSEC_NO_RNG */
  530         mtx_destroy(&sc->sc_mcr2lock);
  531 
  532         bus_generic_detach(dev);
  533         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
  534         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
  535 
  536         bus_dma_tag_destroy(sc->sc_dmat);
  537         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
  538 
  539         return (0);
  540 }
  541 
  542 /*
  543  * Stop all chip i/o so that the kernel's probe routines don't
  544  * get confused by errant DMAs when rebooting.
  545  */
  546 static int
  547 ubsec_shutdown(device_t dev)
  548 {
  549 #ifdef notyet
  550         ubsec_stop(device_get_softc(dev));
  551 #endif
  552         return (0);
  553 }
  554 
  555 /*
  556  * Device suspend routine.
  557  */
  558 static int
  559 ubsec_suspend(device_t dev)
  560 {
  561         struct ubsec_softc *sc = device_get_softc(dev);
  562 
  563 #ifdef notyet
  564         /* XXX stop the device and save PCI settings */
  565 #endif
  566         sc->sc_suspended = 1;
  567 
  568         return (0);
  569 }
  570 
  571 static int
  572 ubsec_resume(device_t dev)
  573 {
  574         struct ubsec_softc *sc = device_get_softc(dev);
  575 
  576 #ifdef notyet
  577         /* XXX retore PCI settings and start the device */
  578 #endif
  579         sc->sc_suspended = 0;
  580         return (0);
  581 }
  582 
  583 /*
  584  * UBSEC Interrupt routine
  585  */
  586 static void
  587 ubsec_intr(void *arg)
  588 {
  589         struct ubsec_softc *sc = arg;
  590         volatile u_int32_t stat;
  591         struct ubsec_q *q;
  592         struct ubsec_dma *dmap;
  593         int npkts = 0, i;
  594 
  595         stat = READ_REG(sc, BS_STAT);
  596         stat &= sc->sc_statmask;
  597         if (stat == 0)
  598                 return;
  599 
  600         WRITE_REG(sc, BS_STAT, stat);           /* IACK */
  601 
  602         /*
  603          * Check to see if we have any packets waiting for us
  604          */
  605         if ((stat & BS_STAT_MCR1_DONE)) {
  606                 mtx_lock(&sc->sc_mcr1lock);
  607                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
  608                         q = SIMPLEQ_FIRST(&sc->sc_qchip);
  609                         dmap = q->q_dma;
  610 
  611                         if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
  612                                 break;
  613 
  614                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
  615 
  616                         npkts = q->q_nstacked_mcrs;
  617                         sc->sc_nqchip -= 1+npkts;
  618                         /*
  619                          * search for further sc_qchip ubsec_q's that share
  620                          * the same MCR, and complete them too, they must be
  621                          * at the top.
  622                          */
  623                         for (i = 0; i < npkts; i++) {
  624                                 if(q->q_stacked_mcr[i]) {
  625                                         ubsec_callback(sc, q->q_stacked_mcr[i]);
  626                                 } else {
  627                                         break;
  628                                 }
  629                         }
  630                         ubsec_callback(sc, q);
  631                 }
  632                 /*
  633                  * Don't send any more packet to chip if there has been
  634                  * a DMAERR.
  635                  */
  636                 if (!(stat & BS_STAT_DMAERR))
  637                         ubsec_feed(sc);
  638                 mtx_unlock(&sc->sc_mcr1lock);
  639         }
  640 
  641         /*
  642          * Check to see if we have any key setups/rng's waiting for us
  643          */
  644         if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
  645             (stat & BS_STAT_MCR2_DONE)) {
  646                 struct ubsec_q2 *q2;
  647                 struct ubsec_mcr *mcr;
  648 
  649                 mtx_lock(&sc->sc_mcr2lock);
  650                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
  651                         q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
  652 
  653                         ubsec_dma_sync(&q2->q_mcr,
  654                             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  655 
  656                         mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
  657                         if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
  658                                 ubsec_dma_sync(&q2->q_mcr,
  659                                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  660                                 break;
  661                         }
  662                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
  663                         ubsec_callback2(sc, q2);
  664                         /*
  665                          * Don't send any more packet to chip if there has been
  666                          * a DMAERR.
  667                          */
  668                         if (!(stat & BS_STAT_DMAERR))
  669                                 ubsec_feed2(sc);
  670                 }
  671                 mtx_unlock(&sc->sc_mcr2lock);
  672         }
  673 
  674         /*
  675          * Check to see if we got any DMA Error
  676          */
  677         if (stat & BS_STAT_DMAERR) {
  678 #ifdef UBSEC_DEBUG
  679                 if (ubsec_debug) {
  680                         volatile u_int32_t a = READ_REG(sc, BS_ERR);
  681 
  682                         printf("dmaerr %s@%08x\n",
  683                             (a & BS_ERR_READ) ? "read" : "write",
  684                             a & BS_ERR_ADDR);
  685                 }
  686 #endif /* UBSEC_DEBUG */
  687                 ubsecstats.hst_dmaerr++;
  688                 mtx_lock(&sc->sc_mcr1lock);
  689                 ubsec_totalreset(sc);
  690                 ubsec_feed(sc);
  691                 mtx_unlock(&sc->sc_mcr1lock);
  692         }
  693 
  694         if (sc->sc_needwakeup) {                /* XXX check high watermark */
  695                 int wakeup;
  696 
  697                 mtx_lock(&sc->sc_freeqlock);
  698                 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
  699 #ifdef UBSEC_DEBUG
  700                 if (ubsec_debug)
  701                         device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
  702                                 sc->sc_needwakeup);
  703 #endif /* UBSEC_DEBUG */
  704                 sc->sc_needwakeup &= ~wakeup;
  705                 mtx_unlock(&sc->sc_freeqlock);
  706                 crypto_unblock(sc->sc_cid, wakeup);
  707         }
  708 }
  709 
  710 /*
  711  * ubsec_feed() - aggregate and post requests to chip
  712  */
  713 static void
  714 ubsec_feed(struct ubsec_softc *sc)
  715 {
  716         struct ubsec_q *q, *q2;
  717         int npkts, i;
  718         void *v;
  719         u_int32_t stat;
  720 
  721         /*
  722          * Decide how many ops to combine in a single MCR.  We cannot
  723          * aggregate more than UBS_MAX_AGGR because this is the number
  724          * of slots defined in the data structure.  Note that
  725          * aggregation only happens if ops are marked batch'able.
  726          * Aggregating ops reduces the number of interrupts to the host
  727          * but also (potentially) increases the latency for processing
  728          * completed ops as we only get an interrupt when all aggregated
  729          * ops have completed.
  730          */
  731         if (sc->sc_nqueue == 0)
  732                 return;
  733         if (sc->sc_nqueue > 1) {
  734                 npkts = 0;
  735                 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
  736                         npkts++;
  737                         if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
  738                                 break;
  739                 }
  740         } else
  741                 npkts = 1;
  742         /*
  743          * Check device status before going any further.
  744          */
  745         if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
  746                 if (stat & BS_STAT_DMAERR) {
  747                         ubsec_totalreset(sc);
  748                         ubsecstats.hst_dmaerr++;
  749                 } else
  750                         ubsecstats.hst_mcr1full++;
  751                 return;
  752         }
  753         if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
  754                 ubsecstats.hst_maxqueue = sc->sc_nqueue;
  755         if (npkts > UBS_MAX_AGGR)
  756                 npkts = UBS_MAX_AGGR;
  757         if (npkts < 2)                          /* special case 1 op */
  758                 goto feed1;
  759 
  760         ubsecstats.hst_totbatch += npkts-1;
  761 #ifdef UBSEC_DEBUG
  762         if (ubsec_debug)
  763                 printf("merging %d records\n", npkts);
  764 #endif /* UBSEC_DEBUG */
  765 
  766         q = SIMPLEQ_FIRST(&sc->sc_queue);
  767         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
  768         --sc->sc_nqueue;
  769 
  770         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
  771         if (q->q_dst_map != NULL)
  772                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
  773 
  774         q->q_nstacked_mcrs = npkts - 1;         /* Number of packets stacked */
  775 
  776         for (i = 0; i < q->q_nstacked_mcrs; i++) {
  777                 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
  778                 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
  779                     BUS_DMASYNC_PREWRITE);
  780                 if (q2->q_dst_map != NULL)
  781                         bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
  782                             BUS_DMASYNC_PREREAD);
  783                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
  784                 --sc->sc_nqueue;
  785 
  786                 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
  787                     sizeof(struct ubsec_mcr_add));
  788                 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
  789                 q->q_stacked_mcr[i] = q2;
  790         }
  791         q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
  792         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
  793         sc->sc_nqchip += npkts;
  794         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
  795                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
  796         ubsec_dma_sync(&q->q_dma->d_alloc,
  797             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  798         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
  799             offsetof(struct ubsec_dmachunk, d_mcr));
  800         return;
  801 feed1:
  802         q = SIMPLEQ_FIRST(&sc->sc_queue);
  803 
  804         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
  805         if (q->q_dst_map != NULL)
  806                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
  807         ubsec_dma_sync(&q->q_dma->d_alloc,
  808             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  809 
  810         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
  811             offsetof(struct ubsec_dmachunk, d_mcr));
  812 #ifdef UBSEC_DEBUG
  813         if (ubsec_debug)
  814                 printf("feed1: q->chip %p %08x stat %08x\n",
  815                       q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
  816                       stat);
  817 #endif /* UBSEC_DEBUG */
  818         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
  819         --sc->sc_nqueue;
  820         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
  821         sc->sc_nqchip++;
  822         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
  823                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
  824         return;
  825 }
  826 
  827 static void
  828 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
  829 {
  830 
  831         /* Go ahead and compute key in ubsec's byte order */
  832         if (algo == CRYPTO_DES_CBC) {
  833                 bcopy(key, &ses->ses_deskey[0], 8);
  834                 bcopy(key, &ses->ses_deskey[2], 8);
  835                 bcopy(key, &ses->ses_deskey[4], 8);
  836         } else
  837                 bcopy(key, ses->ses_deskey, 24);
  838 
  839         SWAP32(ses->ses_deskey[0]);
  840         SWAP32(ses->ses_deskey[1]);
  841         SWAP32(ses->ses_deskey[2]);
  842         SWAP32(ses->ses_deskey[3]);
  843         SWAP32(ses->ses_deskey[4]);
  844         SWAP32(ses->ses_deskey[5]);
  845 }
  846 
  847 static void
  848 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
  849 {
  850         MD5_CTX md5ctx;
  851         SHA1_CTX sha1ctx;
  852         int i;
  853 
  854         for (i = 0; i < klen; i++)
  855                 key[i] ^= HMAC_IPAD_VAL;
  856 
  857         if (algo == CRYPTO_MD5_HMAC) {
  858                 MD5Init(&md5ctx);
  859                 MD5Update(&md5ctx, key, klen);
  860                 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
  861                 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
  862         } else {
  863                 SHA1Init(&sha1ctx);
  864                 SHA1Update(&sha1ctx, key, klen);
  865                 SHA1Update(&sha1ctx, hmac_ipad_buffer,
  866                     SHA1_HMAC_BLOCK_LEN - klen);
  867                 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
  868         }
  869 
  870         for (i = 0; i < klen; i++)
  871                 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
  872 
  873         if (algo == CRYPTO_MD5_HMAC) {
  874                 MD5Init(&md5ctx);
  875                 MD5Update(&md5ctx, key, klen);
  876                 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
  877                 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
  878         } else {
  879                 SHA1Init(&sha1ctx);
  880                 SHA1Update(&sha1ctx, key, klen);
  881                 SHA1Update(&sha1ctx, hmac_opad_buffer,
  882                     SHA1_HMAC_BLOCK_LEN - klen);
  883                 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
  884         }
  885 
  886         for (i = 0; i < klen; i++)
  887                 key[i] ^= HMAC_OPAD_VAL;
  888 }
  889 
  890 /*
  891  * Allocate a new 'session' and return an encoded session id.  'sidp'
  892  * contains our registration id, and should contain an encoded session
  893  * id on successful allocation.
  894  */
  895 static int
  896 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
  897 {
  898         struct ubsec_softc *sc = device_get_softc(dev);
  899         struct cryptoini *c, *encini = NULL, *macini = NULL;
  900         struct ubsec_session *ses = NULL;
  901         int sesn;
  902 
  903         if (sidp == NULL || cri == NULL || sc == NULL)
  904                 return (EINVAL);
  905 
  906         for (c = cri; c != NULL; c = c->cri_next) {
  907                 if (c->cri_alg == CRYPTO_MD5_HMAC ||
  908                     c->cri_alg == CRYPTO_SHA1_HMAC) {
  909                         if (macini)
  910                                 return (EINVAL);
  911                         macini = c;
  912                 } else if (c->cri_alg == CRYPTO_DES_CBC ||
  913                     c->cri_alg == CRYPTO_3DES_CBC) {
  914                         if (encini)
  915                                 return (EINVAL);
  916                         encini = c;
  917                 } else
  918                         return (EINVAL);
  919         }
  920         if (encini == NULL && macini == NULL)
  921                 return (EINVAL);
  922 
  923         if (sc->sc_sessions == NULL) {
  924                 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
  925                     sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
  926                 if (ses == NULL)
  927                         return (ENOMEM);
  928                 sesn = 0;
  929                 sc->sc_nsessions = 1;
  930         } else {
  931                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
  932                         if (sc->sc_sessions[sesn].ses_used == 0) {
  933                                 ses = &sc->sc_sessions[sesn];
  934                                 break;
  935                         }
  936                 }
  937 
  938                 if (ses == NULL) {
  939                         sesn = sc->sc_nsessions;
  940                         ses = (struct ubsec_session *)malloc((sesn + 1) *
  941                             sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
  942                         if (ses == NULL)
  943                                 return (ENOMEM);
  944                         bcopy(sc->sc_sessions, ses, sesn *
  945                             sizeof(struct ubsec_session));
  946                         bzero(sc->sc_sessions, sesn *
  947                             sizeof(struct ubsec_session));
  948                         free(sc->sc_sessions, M_DEVBUF);
  949                         sc->sc_sessions = ses;
  950                         ses = &sc->sc_sessions[sesn];
  951                         sc->sc_nsessions++;
  952                 }
  953         }
  954         bzero(ses, sizeof(struct ubsec_session));
  955         ses->ses_used = 1;
  956 
  957         if (encini) {
  958                 /* get an IV, network byte order */
  959                 /* XXX may read fewer than requested */
  960                 read_random(ses->ses_iv, sizeof(ses->ses_iv));
  961 
  962                 if (encini->cri_key != NULL) {
  963                         ubsec_setup_enckey(ses, encini->cri_alg,
  964                             encini->cri_key);
  965                 }
  966         }
  967 
  968         if (macini) {
  969                 ses->ses_mlen = macini->cri_mlen;
  970                 if (ses->ses_mlen == 0) {
  971                         if (macini->cri_alg == CRYPTO_MD5_HMAC)
  972                                 ses->ses_mlen = MD5_HASH_LEN;
  973                         else
  974                                 ses->ses_mlen = SHA1_HASH_LEN;
  975                 }
  976 
  977                 if (macini->cri_key != NULL) {
  978                         ubsec_setup_mackey(ses, macini->cri_alg,
  979                             macini->cri_key, macini->cri_klen / 8);
  980                 }
  981         }
  982 
  983         *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
  984         return (0);
  985 }
  986 
  987 /*
  988  * Deallocate a session.
  989  */
  990 static int
  991 ubsec_freesession(device_t dev, u_int64_t tid)
  992 {
  993         struct ubsec_softc *sc = device_get_softc(dev);
  994         int session, ret;
  995         u_int32_t sid = CRYPTO_SESID2LID(tid);
  996 
  997         if (sc == NULL)
  998                 return (EINVAL);
  999 
 1000         session = UBSEC_SESSION(sid);
 1001         if (session < sc->sc_nsessions) {
 1002                 bzero(&sc->sc_sessions[session],
 1003                         sizeof(sc->sc_sessions[session]));
 1004                 ret = 0;
 1005         } else
 1006                 ret = EINVAL;
 1007 
 1008         return (ret);
 1009 }
 1010 
 1011 static void
 1012 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
 1013 {
 1014         struct ubsec_operand *op = arg;
 1015 
 1016         KASSERT(nsegs <= UBS_MAX_SCATTER,
 1017                 ("Too many DMA segments returned when mapping operand"));
 1018 #ifdef UBSEC_DEBUG
 1019         if (ubsec_debug)
 1020                 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
 1021                         (u_int) mapsize, nsegs, error);
 1022 #endif
 1023         if (error != 0)
 1024                 return;
 1025         op->mapsize = mapsize;
 1026         op->nsegs = nsegs;
 1027         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
 1028 }
 1029 
 1030 static int
 1031 ubsec_process(device_t dev, struct cryptop *crp, int hint)
 1032 {
 1033         struct ubsec_softc *sc = device_get_softc(dev);
 1034         struct ubsec_q *q = NULL;
 1035         int err = 0, i, j, nicealign;
 1036         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
 1037         int encoffset = 0, macoffset = 0, cpskip, cpoffset;
 1038         int sskip, dskip, stheend, dtheend;
 1039         int16_t coffset;
 1040         struct ubsec_session *ses;
 1041         struct ubsec_pktctx ctx;
 1042         struct ubsec_dma *dmap = NULL;
 1043 
 1044         if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
 1045                 ubsecstats.hst_invalid++;
 1046                 return (EINVAL);
 1047         }
 1048         if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
 1049                 ubsecstats.hst_badsession++;
 1050                 return (EINVAL);
 1051         }
 1052 
 1053         mtx_lock(&sc->sc_freeqlock);
 1054         if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
 1055                 ubsecstats.hst_queuefull++;
 1056                 sc->sc_needwakeup |= CRYPTO_SYMQ;
 1057                 mtx_unlock(&sc->sc_freeqlock);
 1058                 return (ERESTART);
 1059         }
 1060         q = SIMPLEQ_FIRST(&sc->sc_freequeue);
 1061         SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
 1062         mtx_unlock(&sc->sc_freeqlock);
 1063 
 1064         dmap = q->q_dma; /* Save dma pointer */
 1065         bzero(q, sizeof(struct ubsec_q));
 1066         bzero(&ctx, sizeof(ctx));
 1067 
 1068         q->q_sesn = UBSEC_SESSION(crp->crp_sid);
 1069         q->q_dma = dmap;
 1070         ses = &sc->sc_sessions[q->q_sesn];
 1071 
 1072         if (crp->crp_flags & CRYPTO_F_IMBUF) {
 1073                 q->q_src_m = (struct mbuf *)crp->crp_buf;
 1074                 q->q_dst_m = (struct mbuf *)crp->crp_buf;
 1075         } else if (crp->crp_flags & CRYPTO_F_IOV) {
 1076                 q->q_src_io = (struct uio *)crp->crp_buf;
 1077                 q->q_dst_io = (struct uio *)crp->crp_buf;
 1078         } else {
 1079                 ubsecstats.hst_badflags++;
 1080                 err = EINVAL;
 1081                 goto errout;    /* XXX we don't handle contiguous blocks! */
 1082         }
 1083 
 1084         bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
 1085 
 1086         dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
 1087         dmap->d_dma->d_mcr.mcr_flags = 0;
 1088         q->q_crp = crp;
 1089 
 1090         crd1 = crp->crp_desc;
 1091         if (crd1 == NULL) {
 1092                 ubsecstats.hst_nodesc++;
 1093                 err = EINVAL;
 1094                 goto errout;
 1095         }
 1096         crd2 = crd1->crd_next;
 1097 
 1098         if (crd2 == NULL) {
 1099                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
 1100                     crd1->crd_alg == CRYPTO_SHA1_HMAC) {
 1101                         maccrd = crd1;
 1102                         enccrd = NULL;
 1103                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
 1104                     crd1->crd_alg == CRYPTO_3DES_CBC) {
 1105                         maccrd = NULL;
 1106                         enccrd = crd1;
 1107                 } else {
 1108                         ubsecstats.hst_badalg++;
 1109                         err = EINVAL;
 1110                         goto errout;
 1111                 }
 1112         } else {
 1113                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
 1114                     crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
 1115                     (crd2->crd_alg == CRYPTO_DES_CBC ||
 1116                         crd2->crd_alg == CRYPTO_3DES_CBC) &&
 1117                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
 1118                         maccrd = crd1;
 1119                         enccrd = crd2;
 1120                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
 1121                     crd1->crd_alg == CRYPTO_3DES_CBC) &&
 1122                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
 1123                         crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
 1124                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
 1125                         enccrd = crd1;
 1126                         maccrd = crd2;
 1127                 } else {
 1128                         /*
 1129                          * We cannot order the ubsec as requested
 1130                          */
 1131                         ubsecstats.hst_badalg++;
 1132                         err = EINVAL;
 1133                         goto errout;
 1134                 }
 1135         }
 1136 
 1137         if (enccrd) {
 1138                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
 1139                         ubsec_setup_enckey(ses, enccrd->crd_alg,
 1140                             enccrd->crd_key);
 1141                 }
 1142 
 1143                 encoffset = enccrd->crd_skip;
 1144                 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
 1145 
 1146                 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
 1147                         q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
 1148 
 1149                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
 1150                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
 1151                         else {
 1152                                 ctx.pc_iv[0] = ses->ses_iv[0];
 1153                                 ctx.pc_iv[1] = ses->ses_iv[1];
 1154                         }
 1155 
 1156                         if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
 1157                                 crypto_copyback(crp->crp_flags, crp->crp_buf,
 1158                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
 1159                         }
 1160                 } else {
 1161                         ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
 1162 
 1163                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
 1164                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
 1165                         else {
 1166                                 crypto_copydata(crp->crp_flags, crp->crp_buf,
 1167                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
 1168                         }
 1169                 }
 1170 
 1171                 ctx.pc_deskey[0] = ses->ses_deskey[0];
 1172                 ctx.pc_deskey[1] = ses->ses_deskey[1];
 1173                 ctx.pc_deskey[2] = ses->ses_deskey[2];
 1174                 ctx.pc_deskey[3] = ses->ses_deskey[3];
 1175                 ctx.pc_deskey[4] = ses->ses_deskey[4];
 1176                 ctx.pc_deskey[5] = ses->ses_deskey[5];
 1177                 SWAP32(ctx.pc_iv[0]);
 1178                 SWAP32(ctx.pc_iv[1]);
 1179         }
 1180 
 1181         if (maccrd) {
 1182                 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
 1183                         ubsec_setup_mackey(ses, maccrd->crd_alg,
 1184                             maccrd->crd_key, maccrd->crd_klen / 8);
 1185                 }
 1186 
 1187                 macoffset = maccrd->crd_skip;
 1188 
 1189                 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
 1190                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
 1191                 else
 1192                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
 1193 
 1194                 for (i = 0; i < 5; i++) {
 1195                         ctx.pc_hminner[i] = ses->ses_hminner[i];
 1196                         ctx.pc_hmouter[i] = ses->ses_hmouter[i];
 1197 
 1198                         HTOLE32(ctx.pc_hminner[i]);
 1199                         HTOLE32(ctx.pc_hmouter[i]);
 1200                 }
 1201         }
 1202 
 1203         if (enccrd && maccrd) {
 1204                 /*
 1205                  * ubsec cannot handle packets where the end of encryption
 1206                  * and authentication are not the same, or where the
 1207                  * encrypted part begins before the authenticated part.
 1208                  */
 1209                 if ((encoffset + enccrd->crd_len) !=
 1210                     (macoffset + maccrd->crd_len)) {
 1211                         ubsecstats.hst_lenmismatch++;
 1212                         err = EINVAL;
 1213                         goto errout;
 1214                 }
 1215                 if (enccrd->crd_skip < maccrd->crd_skip) {
 1216                         ubsecstats.hst_skipmismatch++;
 1217                         err = EINVAL;
 1218                         goto errout;
 1219                 }
 1220                 sskip = maccrd->crd_skip;
 1221                 cpskip = dskip = enccrd->crd_skip;
 1222                 stheend = maccrd->crd_len;
 1223                 dtheend = enccrd->crd_len;
 1224                 coffset = enccrd->crd_skip - maccrd->crd_skip;
 1225                 cpoffset = cpskip + dtheend;
 1226 #ifdef UBSEC_DEBUG
 1227                 if (ubsec_debug) {
 1228                         printf("mac: skip %d, len %d, inject %d\n",
 1229                             maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
 1230                         printf("enc: skip %d, len %d, inject %d\n",
 1231                             enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
 1232                         printf("src: skip %d, len %d\n", sskip, stheend);
 1233                         printf("dst: skip %d, len %d\n", dskip, dtheend);
 1234                         printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
 1235                             coffset, stheend, cpskip, cpoffset);
 1236                 }
 1237 #endif
 1238         } else {
 1239                 cpskip = dskip = sskip = macoffset + encoffset;
 1240                 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
 1241                 cpoffset = cpskip + dtheend;
 1242                 coffset = 0;
 1243         }
 1244         ctx.pc_offset = htole16(coffset >> 2);
 1245 
 1246         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
 1247                 ubsecstats.hst_nomap++;
 1248                 err = ENOMEM;
 1249                 goto errout;
 1250         }
 1251         if (crp->crp_flags & CRYPTO_F_IMBUF) {
 1252                 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
 1253                     q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
 1254                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
 1255                         q->q_src_map = NULL;
 1256                         ubsecstats.hst_noload++;
 1257                         err = ENOMEM;
 1258                         goto errout;
 1259                 }
 1260         } else if (crp->crp_flags & CRYPTO_F_IOV) {
 1261                 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
 1262                     q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
 1263                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
 1264                         q->q_src_map = NULL;
 1265                         ubsecstats.hst_noload++;
 1266                         err = ENOMEM;
 1267                         goto errout;
 1268                 }
 1269         }
 1270         nicealign = ubsec_dmamap_aligned(&q->q_src);
 1271 
 1272         dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
 1273 
 1274 #ifdef UBSEC_DEBUG
 1275         if (ubsec_debug)
 1276                 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
 1277 #endif
 1278         for (i = j = 0; i < q->q_src_nsegs; i++) {
 1279                 struct ubsec_pktbuf *pb;
 1280                 bus_size_t packl = q->q_src_segs[i].ds_len;
 1281                 bus_addr_t packp = q->q_src_segs[i].ds_addr;
 1282 
 1283                 if (sskip >= packl) {
 1284                         sskip -= packl;
 1285                         continue;
 1286                 }
 1287 
 1288                 packl -= sskip;
 1289                 packp += sskip;
 1290                 sskip = 0;
 1291 
 1292                 if (packl > 0xfffc) {
 1293                         err = EIO;
 1294                         goto errout;
 1295                 }
 1296 
 1297                 if (j == 0)
 1298                         pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
 1299                 else
 1300                         pb = &dmap->d_dma->d_sbuf[j - 1];
 1301 
 1302                 pb->pb_addr = htole32(packp);
 1303 
 1304                 if (stheend) {
 1305                         if (packl > stheend) {
 1306                                 pb->pb_len = htole32(stheend);
 1307                                 stheend = 0;
 1308                         } else {
 1309                                 pb->pb_len = htole32(packl);
 1310                                 stheend -= packl;
 1311                         }
 1312                 } else
 1313                         pb->pb_len = htole32(packl);
 1314 
 1315                 if ((i + 1) == q->q_src_nsegs)
 1316                         pb->pb_next = 0;
 1317                 else
 1318                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
 1319                             offsetof(struct ubsec_dmachunk, d_sbuf[j]));
 1320                 j++;
 1321         }
 1322 
 1323         if (enccrd == NULL && maccrd != NULL) {
 1324                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
 1325                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
 1326                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
 1327                     offsetof(struct ubsec_dmachunk, d_macbuf[0]));
 1328 #ifdef UBSEC_DEBUG
 1329                 if (ubsec_debug)
 1330                         printf("opkt: %x %x %x\n",
 1331                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
 1332                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
 1333                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
 1334 #endif
 1335         } else {
 1336                 if (crp->crp_flags & CRYPTO_F_IOV) {
 1337                         if (!nicealign) {
 1338                                 ubsecstats.hst_iovmisaligned++;
 1339                                 err = EINVAL;
 1340                                 goto errout;
 1341                         }
 1342                         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
 1343                              &q->q_dst_map)) {
 1344                                 ubsecstats.hst_nomap++;
 1345                                 err = ENOMEM;
 1346                                 goto errout;
 1347                         }
 1348                         if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
 1349                             q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
 1350                                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
 1351                                 q->q_dst_map = NULL;
 1352                                 ubsecstats.hst_noload++;
 1353                                 err = ENOMEM;
 1354                                 goto errout;
 1355                         }
 1356                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
 1357                         if (nicealign) {
 1358                                 q->q_dst = q->q_src;
 1359                         } else {
 1360                                 int totlen, len;
 1361                                 struct mbuf *m, *top, **mp;
 1362 
 1363                                 ubsecstats.hst_unaligned++;
 1364                                 totlen = q->q_src_mapsize;
 1365                                 if (totlen >= MINCLSIZE) {
 1366                                         m = m_getcl(M_NOWAIT, MT_DATA,
 1367                                             q->q_src_m->m_flags & M_PKTHDR);
 1368                                         len = MCLBYTES;
 1369                                 } else if (q->q_src_m->m_flags & M_PKTHDR) {
 1370                                         m = m_gethdr(M_NOWAIT, MT_DATA);
 1371                                         len = MHLEN;
 1372                                 } else {
 1373                                         m = m_get(M_NOWAIT, MT_DATA);
 1374                                         len = MLEN;
 1375                                 }
 1376                                 if (m && q->q_src_m->m_flags & M_PKTHDR &&
 1377                                     !m_dup_pkthdr(m, q->q_src_m, M_NOWAIT)) {
 1378                                         m_free(m);
 1379                                         m = NULL;
 1380                                 }
 1381                                 if (m == NULL) {
 1382                                         ubsecstats.hst_nombuf++;
 1383                                         err = sc->sc_nqueue ? ERESTART : ENOMEM;
 1384                                         goto errout;
 1385                                 }
 1386                                 m->m_len = len = min(totlen, len);
 1387                                 totlen -= len;
 1388                                 top = m;
 1389                                 mp = &top;
 1390 
 1391                                 while (totlen > 0) {
 1392                                         if (totlen >= MINCLSIZE) {
 1393                                                 m = m_getcl(M_NOWAIT,
 1394                                                     MT_DATA, 0);
 1395                                                 len = MCLBYTES;
 1396                                         } else {
 1397                                                 m = m_get(M_NOWAIT, MT_DATA);
 1398                                                 len = MLEN;
 1399                                         }
 1400                                         if (m == NULL) {
 1401                                                 m_freem(top);
 1402                                                 ubsecstats.hst_nombuf++;
 1403                                                 err = sc->sc_nqueue ? ERESTART : ENOMEM;
 1404                                                 goto errout;
 1405                                         }
 1406                                         m->m_len = len = min(totlen, len);
 1407                                         totlen -= len;
 1408                                         *mp = m;
 1409                                         mp = &m->m_next;
 1410                                 }
 1411                                 q->q_dst_m = top;
 1412                                 ubsec_mcopy(q->q_src_m, q->q_dst_m,
 1413                                     cpskip, cpoffset);
 1414                                 if (bus_dmamap_create(sc->sc_dmat,
 1415                                     BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
 1416                                         ubsecstats.hst_nomap++;
 1417                                         err = ENOMEM;
 1418                                         goto errout;
 1419                                 }
 1420                                 if (bus_dmamap_load_mbuf(sc->sc_dmat,
 1421                                     q->q_dst_map, q->q_dst_m,
 1422                                     ubsec_op_cb, &q->q_dst,
 1423                                     BUS_DMA_NOWAIT) != 0) {
 1424                                         bus_dmamap_destroy(sc->sc_dmat,
 1425                                         q->q_dst_map);
 1426                                         q->q_dst_map = NULL;
 1427                                         ubsecstats.hst_noload++;
 1428                                         err = ENOMEM;
 1429                                         goto errout;
 1430                                 }
 1431                         }
 1432                 } else {
 1433                         ubsecstats.hst_badflags++;
 1434                         err = EINVAL;
 1435                         goto errout;
 1436                 }
 1437 
 1438 #ifdef UBSEC_DEBUG
 1439                 if (ubsec_debug)
 1440                         printf("dst skip: %d\n", dskip);
 1441 #endif
 1442                 for (i = j = 0; i < q->q_dst_nsegs; i++) {
 1443                         struct ubsec_pktbuf *pb;
 1444                         bus_size_t packl = q->q_dst_segs[i].ds_len;
 1445                         bus_addr_t packp = q->q_dst_segs[i].ds_addr;
 1446 
 1447                         if (dskip >= packl) {
 1448                                 dskip -= packl;
 1449                                 continue;
 1450                         }
 1451 
 1452                         packl -= dskip;
 1453                         packp += dskip;
 1454                         dskip = 0;
 1455 
 1456                         if (packl > 0xfffc) {
 1457                                 err = EIO;
 1458                                 goto errout;
 1459                         }
 1460 
 1461                         if (j == 0)
 1462                                 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
 1463                         else
 1464                                 pb = &dmap->d_dma->d_dbuf[j - 1];
 1465 
 1466                         pb->pb_addr = htole32(packp);
 1467 
 1468                         if (dtheend) {
 1469                                 if (packl > dtheend) {
 1470                                         pb->pb_len = htole32(dtheend);
 1471                                         dtheend = 0;
 1472                                 } else {
 1473                                         pb->pb_len = htole32(packl);
 1474                                         dtheend -= packl;
 1475                                 }
 1476                         } else
 1477                                 pb->pb_len = htole32(packl);
 1478 
 1479                         if ((i + 1) == q->q_dst_nsegs) {
 1480                                 if (maccrd)
 1481                                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
 1482                                             offsetof(struct ubsec_dmachunk, d_macbuf[0]));
 1483                                 else
 1484                                         pb->pb_next = 0;
 1485                         } else
 1486                                 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
 1487                                     offsetof(struct ubsec_dmachunk, d_dbuf[j]));
 1488                         j++;
 1489                 }
 1490         }
 1491 
 1492         dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
 1493             offsetof(struct ubsec_dmachunk, d_ctx));
 1494 
 1495         if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
 1496                 struct ubsec_pktctx_long *ctxl;
 1497 
 1498                 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
 1499                     offsetof(struct ubsec_dmachunk, d_ctx));
 1500 
 1501                 /* transform small context into long context */
 1502                 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
 1503                 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
 1504                 ctxl->pc_flags = ctx.pc_flags;
 1505                 ctxl->pc_offset = ctx.pc_offset;
 1506                 for (i = 0; i < 6; i++)
 1507                         ctxl->pc_deskey[i] = ctx.pc_deskey[i];
 1508                 for (i = 0; i < 5; i++)
 1509                         ctxl->pc_hminner[i] = ctx.pc_hminner[i];
 1510                 for (i = 0; i < 5; i++)
 1511                         ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
 1512                 ctxl->pc_iv[0] = ctx.pc_iv[0];
 1513                 ctxl->pc_iv[1] = ctx.pc_iv[1];
 1514         } else
 1515                 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
 1516                     offsetof(struct ubsec_dmachunk, d_ctx),
 1517                     sizeof(struct ubsec_pktctx));
 1518 
 1519         mtx_lock(&sc->sc_mcr1lock);
 1520         SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
 1521         sc->sc_nqueue++;
 1522         ubsecstats.hst_ipackets++;
 1523         ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
 1524         if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
 1525                 ubsec_feed(sc);
 1526         mtx_unlock(&sc->sc_mcr1lock);
 1527         return (0);
 1528 
 1529 errout:
 1530         if (q != NULL) {
 1531                 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
 1532                         m_freem(q->q_dst_m);
 1533 
 1534                 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
 1535                         bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
 1536                         bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
 1537                 }
 1538                 if (q->q_src_map != NULL) {
 1539                         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
 1540                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
 1541                 }
 1542         }
 1543         if (q != NULL || err == ERESTART) {
 1544                 mtx_lock(&sc->sc_freeqlock);
 1545                 if (q != NULL)
 1546                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
 1547                 if (err == ERESTART)
 1548                         sc->sc_needwakeup |= CRYPTO_SYMQ;
 1549                 mtx_unlock(&sc->sc_freeqlock);
 1550         }
 1551         if (err != ERESTART) {
 1552                 crp->crp_etype = err;
 1553                 crypto_done(crp);
 1554         }
 1555         return (err);
 1556 }
 1557 
 1558 static void
 1559 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
 1560 {
 1561         struct cryptop *crp = (struct cryptop *)q->q_crp;
 1562         struct cryptodesc *crd;
 1563         struct ubsec_dma *dmap = q->q_dma;
 1564 
 1565         ubsecstats.hst_opackets++;
 1566         ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
 1567 
 1568         ubsec_dma_sync(&dmap->d_alloc,
 1569             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 1570         if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
 1571                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
 1572                     BUS_DMASYNC_POSTREAD);
 1573                 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
 1574                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
 1575         }
 1576         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
 1577         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
 1578         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
 1579 
 1580         if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
 1581                 m_freem(q->q_src_m);
 1582                 crp->crp_buf = (caddr_t)q->q_dst_m;
 1583         }
 1584 
 1585         /* copy out IV for future use */
 1586         if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
 1587                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
 1588                         if (crd->crd_alg != CRYPTO_DES_CBC &&
 1589                             crd->crd_alg != CRYPTO_3DES_CBC)
 1590                                 continue;
 1591                         crypto_copydata(crp->crp_flags, crp->crp_buf,
 1592                             crd->crd_skip + crd->crd_len - 8, 8,
 1593                             (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
 1594                         break;
 1595                 }
 1596         }
 1597 
 1598         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
 1599                 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
 1600                     crd->crd_alg != CRYPTO_SHA1_HMAC)
 1601                         continue;
 1602                 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
 1603                     sc->sc_sessions[q->q_sesn].ses_mlen,
 1604                     (caddr_t)dmap->d_dma->d_macbuf);
 1605                 break;
 1606         }
 1607         mtx_lock(&sc->sc_freeqlock);
 1608         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
 1609         mtx_unlock(&sc->sc_freeqlock);
 1610         crypto_done(crp);
 1611 }
 1612 
 1613 static void
 1614 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
 1615 {
 1616         int i, j, dlen, slen;
 1617         caddr_t dptr, sptr;
 1618 
 1619         j = 0;
 1620         sptr = srcm->m_data;
 1621         slen = srcm->m_len;
 1622         dptr = dstm->m_data;
 1623         dlen = dstm->m_len;
 1624 
 1625         while (1) {
 1626                 for (i = 0; i < min(slen, dlen); i++) {
 1627                         if (j < hoffset || j >= toffset)
 1628                                 *dptr++ = *sptr++;
 1629                         slen--;
 1630                         dlen--;
 1631                         j++;
 1632                 }
 1633                 if (slen == 0) {
 1634                         srcm = srcm->m_next;
 1635                         if (srcm == NULL)
 1636                                 return;
 1637                         sptr = srcm->m_data;
 1638                         slen = srcm->m_len;
 1639                 }
 1640                 if (dlen == 0) {
 1641                         dstm = dstm->m_next;
 1642                         if (dstm == NULL)
 1643                                 return;
 1644                         dptr = dstm->m_data;
 1645                         dlen = dstm->m_len;
 1646                 }
 1647         }
 1648 }
 1649 
 1650 /*
 1651  * feed the key generator, must be called at splimp() or higher.
 1652  */
 1653 static int
 1654 ubsec_feed2(struct ubsec_softc *sc)
 1655 {
 1656         struct ubsec_q2 *q;
 1657 
 1658         while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
 1659                 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
 1660                         break;
 1661                 q = SIMPLEQ_FIRST(&sc->sc_queue2);
 1662 
 1663                 ubsec_dma_sync(&q->q_mcr,
 1664                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1665                 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
 1666 
 1667                 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
 1668                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
 1669                 --sc->sc_nqueue2;
 1670                 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
 1671         }
 1672         return (0);
 1673 }
 1674 
 1675 /*
 1676  * Callback for handling random numbers
 1677  */
 1678 static void
 1679 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
 1680 {
 1681         struct cryptkop *krp;
 1682         struct ubsec_ctx_keyop *ctx;
 1683 
 1684         ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
 1685         ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
 1686 
 1687         switch (q->q_type) {
 1688 #ifndef UBSEC_NO_RNG
 1689         case UBS_CTXOP_RNGBYPASS: {
 1690                 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
 1691 
 1692                 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
 1693                 (*sc->sc_harvest)(sc->sc_rndtest,
 1694                         rng->rng_buf.dma_vaddr,
 1695                         UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
 1696                 rng->rng_used = 0;
 1697                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
 1698                 break;
 1699         }
 1700 #endif
 1701         case UBS_CTXOP_MODEXP: {
 1702                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
 1703                 u_int rlen, clen;
 1704 
 1705                 krp = me->me_krp;
 1706                 rlen = (me->me_modbits + 7) / 8;
 1707                 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
 1708 
 1709                 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
 1710                 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
 1711                 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
 1712                 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
 1713 
 1714                 if (clen < rlen)
 1715                         krp->krp_status = E2BIG;
 1716                 else {
 1717                         if (sc->sc_flags & UBS_FLAGS_HWNORM) {
 1718                                 bzero(krp->krp_param[krp->krp_iparams].crp_p,
 1719                                     (krp->krp_param[krp->krp_iparams].crp_nbits
 1720                                         + 7) / 8);
 1721                                 bcopy(me->me_C.dma_vaddr,
 1722                                     krp->krp_param[krp->krp_iparams].crp_p,
 1723                                     (me->me_modbits + 7) / 8);
 1724                         } else
 1725                                 ubsec_kshift_l(me->me_shiftbits,
 1726                                     me->me_C.dma_vaddr, me->me_normbits,
 1727                                     krp->krp_param[krp->krp_iparams].crp_p,
 1728                                     krp->krp_param[krp->krp_iparams].crp_nbits);
 1729                 }
 1730 
 1731                 crypto_kdone(krp);
 1732 
 1733                 /* bzero all potentially sensitive data */
 1734                 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
 1735                 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
 1736                 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
 1737                 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
 1738 
 1739                 /* Can't free here, so put us on the free list. */
 1740                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
 1741                 break;
 1742         }
 1743         case UBS_CTXOP_RSAPRIV: {
 1744                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
 1745                 u_int len;
 1746 
 1747                 krp = rp->rpr_krp;
 1748                 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
 1749                 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
 1750 
 1751                 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
 1752                 bcopy(rp->rpr_msgout.dma_vaddr,
 1753                     krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
 1754 
 1755                 crypto_kdone(krp);
 1756 
 1757                 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
 1758                 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
 1759                 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
 1760 
 1761                 /* Can't free here, so put us on the free list. */
 1762                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
 1763                 break;
 1764         }
 1765         default:
 1766                 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
 1767                     letoh16(ctx->ctx_op));
 1768                 break;
 1769         }
 1770 }
 1771 
 1772 #ifndef UBSEC_NO_RNG
 1773 static void
 1774 ubsec_rng(void *vsc)
 1775 {
 1776         struct ubsec_softc *sc = vsc;
 1777         struct ubsec_q2_rng *rng = &sc->sc_rng;
 1778         struct ubsec_mcr *mcr;
 1779         struct ubsec_ctx_rngbypass *ctx;
 1780 
 1781         mtx_lock(&sc->sc_mcr2lock);
 1782         if (rng->rng_used) {
 1783                 mtx_unlock(&sc->sc_mcr2lock);
 1784                 return;
 1785         }
 1786         sc->sc_nqueue2++;
 1787         if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
 1788                 goto out;
 1789 
 1790         mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
 1791         ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
 1792 
 1793         mcr->mcr_pkts = htole16(1);
 1794         mcr->mcr_flags = 0;
 1795         mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
 1796         mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
 1797         mcr->mcr_ipktbuf.pb_len = 0;
 1798         mcr->mcr_reserved = mcr->mcr_pktlen = 0;
 1799         mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
 1800         mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
 1801             UBS_PKTBUF_LEN);
 1802         mcr->mcr_opktbuf.pb_next = 0;
 1803 
 1804         ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
 1805         ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
 1806         rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
 1807 
 1808         ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
 1809 
 1810         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
 1811         rng->rng_used = 1;
 1812         ubsec_feed2(sc);
 1813         ubsecstats.hst_rng++;
 1814         mtx_unlock(&sc->sc_mcr2lock);
 1815 
 1816         return;
 1817 
 1818 out:
 1819         /*
 1820          * Something weird happened, generate our own call back.
 1821          */
 1822         sc->sc_nqueue2--;
 1823         mtx_unlock(&sc->sc_mcr2lock);
 1824         callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
 1825 }
 1826 #endif /* UBSEC_NO_RNG */
 1827 
 1828 static void
 1829 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 1830 {
 1831         bus_addr_t *paddr = (bus_addr_t*) arg;
 1832         *paddr = segs->ds_addr;
 1833 }
 1834 
 1835 static int
 1836 ubsec_dma_malloc(
 1837         struct ubsec_softc *sc,
 1838         bus_size_t size,
 1839         struct ubsec_dma_alloc *dma,
 1840         int mapflags
 1841 )
 1842 {
 1843         int r;
 1844 
 1845         /* XXX could specify sc_dmat as parent but that just adds overhead */
 1846         r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),     /* parent */
 1847                                1, 0,                    /* alignment, bounds */
 1848                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 1849                                BUS_SPACE_MAXADDR,       /* highaddr */
 1850                                NULL, NULL,              /* filter, filterarg */
 1851                                size,                    /* maxsize */
 1852                                1,                       /* nsegments */
 1853                                size,                    /* maxsegsize */
 1854                                BUS_DMA_ALLOCNOW,        /* flags */
 1855                                NULL, NULL,              /* lockfunc, lockarg */
 1856                                &dma->dma_tag);
 1857         if (r != 0) {
 1858                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
 1859                         "bus_dma_tag_create failed; error %u\n", r);
 1860                 goto fail_1;
 1861         }
 1862 
 1863         r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
 1864                              BUS_DMA_NOWAIT, &dma->dma_map);
 1865         if (r != 0) {
 1866                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
 1867                         "bus_dmammem_alloc failed; size %ju, error %u\n",
 1868                         (intmax_t)size, r);
 1869                 goto fail_2;
 1870         }
 1871 
 1872         r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
 1873                             size,
 1874                             ubsec_dmamap_cb,
 1875                             &dma->dma_paddr,
 1876                             mapflags | BUS_DMA_NOWAIT);
 1877         if (r != 0) {
 1878                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
 1879                         "bus_dmamap_load failed; error %u\n", r);
 1880                 goto fail_3;
 1881         }
 1882 
 1883         dma->dma_size = size;
 1884         return (0);
 1885 
 1886 fail_3:
 1887         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 1888 fail_2:
 1889         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 1890 fail_1:
 1891         bus_dma_tag_destroy(dma->dma_tag);
 1892         dma->dma_tag = NULL;
 1893         return (r);
 1894 }
 1895 
 1896 static void
 1897 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
 1898 {
 1899         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 1900         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 1901         bus_dma_tag_destroy(dma->dma_tag);
 1902 }
 1903 
 1904 /*
 1905  * Resets the board.  Values in the regesters are left as is
 1906  * from the reset (i.e. initial values are assigned elsewhere).
 1907  */
 1908 static void
 1909 ubsec_reset_board(struct ubsec_softc *sc)
 1910 {
 1911     volatile u_int32_t ctrl;
 1912 
 1913     ctrl = READ_REG(sc, BS_CTRL);
 1914     ctrl |= BS_CTRL_RESET;
 1915     WRITE_REG(sc, BS_CTRL, ctrl);
 1916 
 1917     /*
 1918      * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
 1919      */
 1920     DELAY(10);
 1921 }
 1922 
 1923 /*
 1924  * Init Broadcom registers
 1925  */
 1926 static void
 1927 ubsec_init_board(struct ubsec_softc *sc)
 1928 {
 1929         u_int32_t ctrl;
 1930 
 1931         ctrl = READ_REG(sc, BS_CTRL);
 1932         ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
 1933         ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
 1934 
 1935         if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
 1936                 ctrl |= BS_CTRL_MCR2INT;
 1937         else
 1938                 ctrl &= ~BS_CTRL_MCR2INT;
 1939 
 1940         if (sc->sc_flags & UBS_FLAGS_HWNORM)
 1941                 ctrl &= ~BS_CTRL_SWNORM;
 1942 
 1943         WRITE_REG(sc, BS_CTRL, ctrl);
 1944 }
 1945 
 1946 /*
 1947  * Init Broadcom PCI registers
 1948  */
 1949 static void
 1950 ubsec_init_pciregs(device_t dev)
 1951 {
 1952 #if 0
 1953         u_int32_t misc;
 1954 
 1955         misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
 1956         misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
 1957             | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
 1958         misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
 1959             | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
 1960         pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
 1961 #endif
 1962 
 1963         /*
 1964          * This will set the cache line size to 1, this will
 1965          * force the BCM58xx chip just to do burst read/writes.
 1966          * Cache line read/writes are to slow
 1967          */
 1968         pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
 1969 }
 1970 
 1971 /*
 1972  * Clean up after a chip crash.
 1973  * It is assumed that the caller in splimp()
 1974  */
 1975 static void
 1976 ubsec_cleanchip(struct ubsec_softc *sc)
 1977 {
 1978         struct ubsec_q *q;
 1979 
 1980         while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
 1981                 q = SIMPLEQ_FIRST(&sc->sc_qchip);
 1982                 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
 1983                 ubsec_free_q(sc, q);
 1984         }
 1985         sc->sc_nqchip = 0;
 1986 }
 1987 
 1988 /*
 1989  * free a ubsec_q
 1990  * It is assumed that the caller is within splimp().
 1991  */
 1992 static int
 1993 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
 1994 {
 1995         struct ubsec_q *q2;
 1996         struct cryptop *crp;
 1997         int npkts;
 1998         int i;
 1999 
 2000         npkts = q->q_nstacked_mcrs;
 2001 
 2002         for (i = 0; i < npkts; i++) {
 2003                 if(q->q_stacked_mcr[i]) {
 2004                         q2 = q->q_stacked_mcr[i];
 2005 
 2006                         if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
 2007                                 m_freem(q2->q_dst_m);
 2008 
 2009                         crp = (struct cryptop *)q2->q_crp;
 2010 
 2011                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
 2012 
 2013                         crp->crp_etype = EFAULT;
 2014                         crypto_done(crp);
 2015                 } else {
 2016                         break;
 2017                 }
 2018         }
 2019 
 2020         /*
 2021          * Free header MCR
 2022          */
 2023         if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
 2024                 m_freem(q->q_dst_m);
 2025 
 2026         crp = (struct cryptop *)q->q_crp;
 2027 
 2028         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
 2029 
 2030         crp->crp_etype = EFAULT;
 2031         crypto_done(crp);
 2032         return(0);
 2033 }
 2034 
 2035 /*
 2036  * Routine to reset the chip and clean up.
 2037  * It is assumed that the caller is in splimp()
 2038  */
 2039 static void
 2040 ubsec_totalreset(struct ubsec_softc *sc)
 2041 {
 2042         ubsec_reset_board(sc);
 2043         ubsec_init_board(sc);
 2044         ubsec_cleanchip(sc);
 2045 }
 2046 
 2047 static int
 2048 ubsec_dmamap_aligned(struct ubsec_operand *op)
 2049 {
 2050         int i;
 2051 
 2052         for (i = 0; i < op->nsegs; i++) {
 2053                 if (op->segs[i].ds_addr & 3)
 2054                         return (0);
 2055                 if ((i != (op->nsegs - 1)) &&
 2056                     (op->segs[i].ds_len & 3))
 2057                         return (0);
 2058         }
 2059         return (1);
 2060 }
 2061 
 2062 static void
 2063 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
 2064 {
 2065         switch (q->q_type) {
 2066         case UBS_CTXOP_MODEXP: {
 2067                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
 2068 
 2069                 ubsec_dma_free(sc, &me->me_q.q_mcr);
 2070                 ubsec_dma_free(sc, &me->me_q.q_ctx);
 2071                 ubsec_dma_free(sc, &me->me_M);
 2072                 ubsec_dma_free(sc, &me->me_E);
 2073                 ubsec_dma_free(sc, &me->me_C);
 2074                 ubsec_dma_free(sc, &me->me_epb);
 2075                 free(me, M_DEVBUF);
 2076                 break;
 2077         }
 2078         case UBS_CTXOP_RSAPRIV: {
 2079                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
 2080 
 2081                 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
 2082                 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
 2083                 ubsec_dma_free(sc, &rp->rpr_msgin);
 2084                 ubsec_dma_free(sc, &rp->rpr_msgout);
 2085                 free(rp, M_DEVBUF);
 2086                 break;
 2087         }
 2088         default:
 2089                 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
 2090                 break;
 2091         }
 2092 }
 2093 
 2094 static int
 2095 ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint)
 2096 {
 2097         struct ubsec_softc *sc = device_get_softc(dev);
 2098         int r;
 2099 
 2100         if (krp == NULL || krp->krp_callback == NULL)
 2101                 return (EINVAL);
 2102 
 2103         while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
 2104                 struct ubsec_q2 *q;
 2105 
 2106                 q = SIMPLEQ_FIRST(&sc->sc_q2free);
 2107                 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
 2108                 ubsec_kfree(sc, q);
 2109         }
 2110 
 2111         switch (krp->krp_op) {
 2112         case CRK_MOD_EXP:
 2113                 if (sc->sc_flags & UBS_FLAGS_HWNORM)
 2114                         r = ubsec_kprocess_modexp_hw(sc, krp, hint);
 2115                 else
 2116                         r = ubsec_kprocess_modexp_sw(sc, krp, hint);
 2117                 break;
 2118         case CRK_MOD_EXP_CRT:
 2119                 return (ubsec_kprocess_rsapriv(sc, krp, hint));
 2120         default:
 2121                 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
 2122                     krp->krp_op);
 2123                 krp->krp_status = EOPNOTSUPP;
 2124                 crypto_kdone(krp);
 2125                 return (0);
 2126         }
 2127         return (0);                     /* silence compiler */
 2128 }
 2129 
 2130 /*
 2131  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
 2132  */
 2133 static int
 2134 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
 2135 {
 2136         struct ubsec_q2_modexp *me;
 2137         struct ubsec_mcr *mcr;
 2138         struct ubsec_ctx_modexp *ctx;
 2139         struct ubsec_pktbuf *epb;
 2140         int err = 0;
 2141         u_int nbits, normbits, mbits, shiftbits, ebits;
 2142 
 2143         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
 2144         if (me == NULL) {
 2145                 err = ENOMEM;
 2146                 goto errout;
 2147         }
 2148         bzero(me, sizeof *me);
 2149         me->me_krp = krp;
 2150         me->me_q.q_type = UBS_CTXOP_MODEXP;
 2151 
 2152         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
 2153         if (nbits <= 512)
 2154                 normbits = 512;
 2155         else if (nbits <= 768)
 2156                 normbits = 768;
 2157         else if (nbits <= 1024)
 2158                 normbits = 1024;
 2159         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
 2160                 normbits = 1536;
 2161         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
 2162                 normbits = 2048;
 2163         else {
 2164                 err = E2BIG;
 2165                 goto errout;
 2166         }
 2167 
 2168         shiftbits = normbits - nbits;
 2169 
 2170         me->me_modbits = nbits;
 2171         me->me_shiftbits = shiftbits;
 2172         me->me_normbits = normbits;
 2173 
 2174         /* Sanity check: result bits must be >= true modulus bits. */
 2175         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
 2176                 err = ERANGE;
 2177                 goto errout;
 2178         }
 2179 
 2180         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
 2181             &me->me_q.q_mcr, 0)) {
 2182                 err = ENOMEM;
 2183                 goto errout;
 2184         }
 2185         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
 2186 
 2187         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
 2188             &me->me_q.q_ctx, 0)) {
 2189                 err = ENOMEM;
 2190                 goto errout;
 2191         }
 2192 
 2193         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
 2194         if (mbits > nbits) {
 2195                 err = E2BIG;
 2196                 goto errout;
 2197         }
 2198         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
 2199                 err = ENOMEM;
 2200                 goto errout;
 2201         }
 2202         ubsec_kshift_r(shiftbits,
 2203             krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
 2204             me->me_M.dma_vaddr, normbits);
 2205 
 2206         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
 2207                 err = ENOMEM;
 2208                 goto errout;
 2209         }
 2210         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
 2211 
 2212         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
 2213         if (ebits > nbits) {
 2214                 err = E2BIG;
 2215                 goto errout;
 2216         }
 2217         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
 2218                 err = ENOMEM;
 2219                 goto errout;
 2220         }
 2221         ubsec_kshift_r(shiftbits,
 2222             krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
 2223             me->me_E.dma_vaddr, normbits);
 2224 
 2225         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
 2226             &me->me_epb, 0)) {
 2227                 err = ENOMEM;
 2228                 goto errout;
 2229         }
 2230         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
 2231         epb->pb_addr = htole32(me->me_E.dma_paddr);
 2232         epb->pb_next = 0;
 2233         epb->pb_len = htole32(normbits / 8);
 2234 
 2235 #ifdef UBSEC_DEBUG
 2236         if (ubsec_debug) {
 2237                 printf("Epb ");
 2238                 ubsec_dump_pb(epb);
 2239         }
 2240 #endif
 2241 
 2242         mcr->mcr_pkts = htole16(1);
 2243         mcr->mcr_flags = 0;
 2244         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
 2245         mcr->mcr_reserved = 0;
 2246         mcr->mcr_pktlen = 0;
 2247 
 2248         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
 2249         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
 2250         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
 2251 
 2252         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
 2253         mcr->mcr_opktbuf.pb_next = 0;
 2254         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
 2255 
 2256 #ifdef DIAGNOSTIC
 2257         /* Misaligned output buffer will hang the chip. */
 2258         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
 2259                 panic("%s: modexp invalid addr 0x%x\n",
 2260                     device_get_nameunit(sc->sc_dev),
 2261                     letoh32(mcr->mcr_opktbuf.pb_addr));
 2262         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
 2263                 panic("%s: modexp invalid len 0x%x\n",
 2264                     device_get_nameunit(sc->sc_dev),
 2265                     letoh32(mcr->mcr_opktbuf.pb_len));
 2266 #endif
 2267 
 2268         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
 2269         bzero(ctx, sizeof(*ctx));
 2270         ubsec_kshift_r(shiftbits,
 2271             krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
 2272             ctx->me_N, normbits);
 2273         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
 2274         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
 2275         ctx->me_E_len = htole16(nbits);
 2276         ctx->me_N_len = htole16(nbits);
 2277 
 2278 #ifdef UBSEC_DEBUG
 2279         if (ubsec_debug) {
 2280                 ubsec_dump_mcr(mcr);
 2281                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
 2282         }
 2283 #endif
 2284 
 2285         /*
 2286          * ubsec_feed2 will sync mcr and ctx, we just need to sync
 2287          * everything else.
 2288          */
 2289         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
 2290         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
 2291         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
 2292         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
 2293 
 2294         /* Enqueue and we're done... */
 2295         mtx_lock(&sc->sc_mcr2lock);
 2296         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
 2297         ubsec_feed2(sc);
 2298         ubsecstats.hst_modexp++;
 2299         mtx_unlock(&sc->sc_mcr2lock);
 2300 
 2301         return (0);
 2302 
 2303 errout:
 2304         if (me != NULL) {
 2305                 if (me->me_q.q_mcr.dma_tag != NULL)
 2306                         ubsec_dma_free(sc, &me->me_q.q_mcr);
 2307                 if (me->me_q.q_ctx.dma_tag != NULL) {
 2308                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
 2309                         ubsec_dma_free(sc, &me->me_q.q_ctx);
 2310                 }
 2311                 if (me->me_M.dma_tag != NULL) {
 2312                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
 2313                         ubsec_dma_free(sc, &me->me_M);
 2314                 }
 2315                 if (me->me_E.dma_tag != NULL) {
 2316                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
 2317                         ubsec_dma_free(sc, &me->me_E);
 2318                 }
 2319                 if (me->me_C.dma_tag != NULL) {
 2320                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
 2321                         ubsec_dma_free(sc, &me->me_C);
 2322                 }
 2323                 if (me->me_epb.dma_tag != NULL)
 2324                         ubsec_dma_free(sc, &me->me_epb);
 2325                 free(me, M_DEVBUF);
 2326         }
 2327         krp->krp_status = err;
 2328         crypto_kdone(krp);
 2329         return (0);
 2330 }
 2331 
 2332 /*
 2333  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
 2334  */
 2335 static int
 2336 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
 2337 {
 2338         struct ubsec_q2_modexp *me;
 2339         struct ubsec_mcr *mcr;
 2340         struct ubsec_ctx_modexp *ctx;
 2341         struct ubsec_pktbuf *epb;
 2342         int err = 0;
 2343         u_int nbits, normbits, mbits, shiftbits, ebits;
 2344 
 2345         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
 2346         if (me == NULL) {
 2347                 err = ENOMEM;
 2348                 goto errout;
 2349         }
 2350         bzero(me, sizeof *me);
 2351         me->me_krp = krp;
 2352         me->me_q.q_type = UBS_CTXOP_MODEXP;
 2353 
 2354         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
 2355         if (nbits <= 512)
 2356                 normbits = 512;
 2357         else if (nbits <= 768)
 2358                 normbits = 768;
 2359         else if (nbits <= 1024)
 2360                 normbits = 1024;
 2361         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
 2362                 normbits = 1536;
 2363         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
 2364                 normbits = 2048;
 2365         else {
 2366                 err = E2BIG;
 2367                 goto errout;
 2368         }
 2369 
 2370         shiftbits = normbits - nbits;
 2371 
 2372         /* XXX ??? */
 2373         me->me_modbits = nbits;
 2374         me->me_shiftbits = shiftbits;
 2375         me->me_normbits = normbits;
 2376 
 2377         /* Sanity check: result bits must be >= true modulus bits. */
 2378         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
 2379                 err = ERANGE;
 2380                 goto errout;
 2381         }
 2382 
 2383         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
 2384             &me->me_q.q_mcr, 0)) {
 2385                 err = ENOMEM;
 2386                 goto errout;
 2387         }
 2388         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
 2389 
 2390         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
 2391             &me->me_q.q_ctx, 0)) {
 2392                 err = ENOMEM;
 2393                 goto errout;
 2394         }
 2395 
 2396         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
 2397         if (mbits > nbits) {
 2398                 err = E2BIG;
 2399                 goto errout;
 2400         }
 2401         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
 2402                 err = ENOMEM;
 2403                 goto errout;
 2404         }
 2405         bzero(me->me_M.dma_vaddr, normbits / 8);
 2406         bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
 2407             me->me_M.dma_vaddr, (mbits + 7) / 8);
 2408 
 2409         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
 2410                 err = ENOMEM;
 2411                 goto errout;
 2412         }
 2413         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
 2414 
 2415         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
 2416         if (ebits > nbits) {
 2417                 err = E2BIG;
 2418                 goto errout;
 2419         }
 2420         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
 2421                 err = ENOMEM;
 2422                 goto errout;
 2423         }
 2424         bzero(me->me_E.dma_vaddr, normbits / 8);
 2425         bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
 2426             me->me_E.dma_vaddr, (ebits + 7) / 8);
 2427 
 2428         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
 2429             &me->me_epb, 0)) {
 2430                 err = ENOMEM;
 2431                 goto errout;
 2432         }
 2433         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
 2434         epb->pb_addr = htole32(me->me_E.dma_paddr);
 2435         epb->pb_next = 0;
 2436         epb->pb_len = htole32((ebits + 7) / 8);
 2437 
 2438 #ifdef UBSEC_DEBUG
 2439         if (ubsec_debug) {
 2440                 printf("Epb ");
 2441                 ubsec_dump_pb(epb);
 2442         }
 2443 #endif
 2444 
 2445         mcr->mcr_pkts = htole16(1);
 2446         mcr->mcr_flags = 0;
 2447         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
 2448         mcr->mcr_reserved = 0;
 2449         mcr->mcr_pktlen = 0;
 2450 
 2451         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
 2452         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
 2453         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
 2454 
 2455         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
 2456         mcr->mcr_opktbuf.pb_next = 0;
 2457         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
 2458 
 2459 #ifdef DIAGNOSTIC
 2460         /* Misaligned output buffer will hang the chip. */
 2461         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
 2462                 panic("%s: modexp invalid addr 0x%x\n",
 2463                     device_get_nameunit(sc->sc_dev),
 2464                     letoh32(mcr->mcr_opktbuf.pb_addr));
 2465         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
 2466                 panic("%s: modexp invalid len 0x%x\n",
 2467                     device_get_nameunit(sc->sc_dev),
 2468                     letoh32(mcr->mcr_opktbuf.pb_len));
 2469 #endif
 2470 
 2471         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
 2472         bzero(ctx, sizeof(*ctx));
 2473         bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
 2474             (nbits + 7) / 8);
 2475         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
 2476         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
 2477         ctx->me_E_len = htole16(ebits);
 2478         ctx->me_N_len = htole16(nbits);
 2479 
 2480 #ifdef UBSEC_DEBUG
 2481         if (ubsec_debug) {
 2482                 ubsec_dump_mcr(mcr);
 2483                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
 2484         }
 2485 #endif
 2486 
 2487         /*
 2488          * ubsec_feed2 will sync mcr and ctx, we just need to sync
 2489          * everything else.
 2490          */
 2491         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
 2492         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
 2493         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
 2494         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
 2495 
 2496         /* Enqueue and we're done... */
 2497         mtx_lock(&sc->sc_mcr2lock);
 2498         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
 2499         ubsec_feed2(sc);
 2500         mtx_unlock(&sc->sc_mcr2lock);
 2501 
 2502         return (0);
 2503 
 2504 errout:
 2505         if (me != NULL) {
 2506                 if (me->me_q.q_mcr.dma_tag != NULL)
 2507                         ubsec_dma_free(sc, &me->me_q.q_mcr);
 2508                 if (me->me_q.q_ctx.dma_tag != NULL) {
 2509                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
 2510                         ubsec_dma_free(sc, &me->me_q.q_ctx);
 2511                 }
 2512                 if (me->me_M.dma_tag != NULL) {
 2513                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
 2514                         ubsec_dma_free(sc, &me->me_M);
 2515                 }
 2516                 if (me->me_E.dma_tag != NULL) {
 2517                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
 2518                         ubsec_dma_free(sc, &me->me_E);
 2519                 }
 2520                 if (me->me_C.dma_tag != NULL) {
 2521                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
 2522                         ubsec_dma_free(sc, &me->me_C);
 2523                 }
 2524                 if (me->me_epb.dma_tag != NULL)
 2525                         ubsec_dma_free(sc, &me->me_epb);
 2526                 free(me, M_DEVBUF);
 2527         }
 2528         krp->krp_status = err;
 2529         crypto_kdone(krp);
 2530         return (0);
 2531 }
 2532 
 2533 static int
 2534 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
 2535 {
 2536         struct ubsec_q2_rsapriv *rp = NULL;
 2537         struct ubsec_mcr *mcr;
 2538         struct ubsec_ctx_rsapriv *ctx;
 2539         int err = 0;
 2540         u_int padlen, msglen;
 2541 
 2542         msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
 2543         padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
 2544         if (msglen > padlen)
 2545                 padlen = msglen;
 2546 
 2547         if (padlen <= 256)
 2548                 padlen = 256;
 2549         else if (padlen <= 384)
 2550                 padlen = 384;
 2551         else if (padlen <= 512)
 2552                 padlen = 512;
 2553         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
 2554                 padlen = 768;
 2555         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
 2556                 padlen = 1024;
 2557         else {
 2558                 err = E2BIG;
 2559                 goto errout;
 2560         }
 2561 
 2562         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
 2563                 err = E2BIG;
 2564                 goto errout;
 2565         }
 2566 
 2567         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
 2568                 err = E2BIG;
 2569                 goto errout;
 2570         }
 2571 
 2572         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
 2573                 err = E2BIG;
 2574                 goto errout;
 2575         }
 2576 
 2577         rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
 2578         if (rp == NULL)
 2579                 return (ENOMEM);
 2580         bzero(rp, sizeof *rp);
 2581         rp->rpr_krp = krp;
 2582         rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
 2583 
 2584         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
 2585             &rp->rpr_q.q_mcr, 0)) {
 2586                 err = ENOMEM;
 2587                 goto errout;
 2588         }
 2589         mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
 2590 
 2591         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
 2592             &rp->rpr_q.q_ctx, 0)) {
 2593                 err = ENOMEM;
 2594                 goto errout;
 2595         }
 2596         ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
 2597         bzero(ctx, sizeof *ctx);
 2598 
 2599         /* Copy in p */
 2600         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
 2601             &ctx->rpr_buf[0 * (padlen / 8)],
 2602             (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
 2603 
 2604         /* Copy in q */
 2605         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
 2606             &ctx->rpr_buf[1 * (padlen / 8)],
 2607             (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
 2608 
 2609         /* Copy in dp */
 2610         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
 2611             &ctx->rpr_buf[2 * (padlen / 8)],
 2612             (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
 2613 
 2614         /* Copy in dq */
 2615         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
 2616             &ctx->rpr_buf[3 * (padlen / 8)],
 2617             (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
 2618 
 2619         /* Copy in pinv */
 2620         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
 2621             &ctx->rpr_buf[4 * (padlen / 8)],
 2622             (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
 2623 
 2624         msglen = padlen * 2;
 2625 
 2626         /* Copy in input message (aligned buffer/length). */
 2627         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
 2628                 /* Is this likely? */
 2629                 err = E2BIG;
 2630                 goto errout;
 2631         }
 2632         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
 2633                 err = ENOMEM;
 2634                 goto errout;
 2635         }
 2636         bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
 2637         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
 2638             rp->rpr_msgin.dma_vaddr,
 2639             (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
 2640 
 2641         /* Prepare space for output message (aligned buffer/length). */
 2642         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
 2643                 /* Is this likely? */
 2644                 err = E2BIG;
 2645                 goto errout;
 2646         }
 2647         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
 2648                 err = ENOMEM;
 2649                 goto errout;
 2650         }
 2651         bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
 2652 
 2653         mcr->mcr_pkts = htole16(1);
 2654         mcr->mcr_flags = 0;
 2655         mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
 2656         mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
 2657         mcr->mcr_ipktbuf.pb_next = 0;
 2658         mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
 2659         mcr->mcr_reserved = 0;
 2660         mcr->mcr_pktlen = htole16(msglen);
 2661         mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
 2662         mcr->mcr_opktbuf.pb_next = 0;
 2663         mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
 2664 
 2665 #ifdef DIAGNOSTIC
 2666         if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
 2667                 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
 2668                     device_get_nameunit(sc->sc_dev),
 2669                     rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
 2670         }
 2671         if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
 2672                 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
 2673                     device_get_nameunit(sc->sc_dev),
 2674                     rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
 2675         }
 2676 #endif
 2677 
 2678         ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
 2679         ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
 2680         ctx->rpr_q_len = htole16(padlen);
 2681         ctx->rpr_p_len = htole16(padlen);
 2682 
 2683         /*
 2684          * ubsec_feed2 will sync mcr and ctx, we just need to sync
 2685          * everything else.
 2686          */
 2687         ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
 2688         ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
 2689 
 2690         /* Enqueue and we're done... */
 2691         mtx_lock(&sc->sc_mcr2lock);
 2692         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
 2693         ubsec_feed2(sc);
 2694         ubsecstats.hst_modexpcrt++;
 2695         mtx_unlock(&sc->sc_mcr2lock);
 2696         return (0);
 2697 
 2698 errout:
 2699         if (rp != NULL) {
 2700                 if (rp->rpr_q.q_mcr.dma_tag != NULL)
 2701                         ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
 2702                 if (rp->rpr_msgin.dma_tag != NULL) {
 2703                         bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
 2704                         ubsec_dma_free(sc, &rp->rpr_msgin);
 2705                 }
 2706                 if (rp->rpr_msgout.dma_tag != NULL) {
 2707                         bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
 2708                         ubsec_dma_free(sc, &rp->rpr_msgout);
 2709                 }
 2710                 free(rp, M_DEVBUF);
 2711         }
 2712         krp->krp_status = err;
 2713         crypto_kdone(krp);
 2714         return (0);
 2715 }
 2716 
 2717 #ifdef UBSEC_DEBUG
 2718 static void
 2719 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
 2720 {
 2721         printf("addr 0x%x (0x%x) next 0x%x\n",
 2722             pb->pb_addr, pb->pb_len, pb->pb_next);
 2723 }
 2724 
 2725 static void
 2726 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
 2727 {
 2728         printf("CTX (0x%x):\n", c->ctx_len);
 2729         switch (letoh16(c->ctx_op)) {
 2730         case UBS_CTXOP_RNGBYPASS:
 2731         case UBS_CTXOP_RNGSHA1:
 2732                 break;
 2733         case UBS_CTXOP_MODEXP:
 2734         {
 2735                 struct ubsec_ctx_modexp *cx = (void *)c;
 2736                 int i, len;
 2737 
 2738                 printf(" Elen %u, Nlen %u\n",
 2739                     letoh16(cx->me_E_len), letoh16(cx->me_N_len));
 2740                 len = (cx->me_N_len + 7)/8;
 2741                 for (i = 0; i < len; i++)
 2742                         printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
 2743                 printf("\n");
 2744                 break;
 2745         }
 2746         default:
 2747                 printf("unknown context: %x\n", c->ctx_op);
 2748         }
 2749         printf("END CTX\n");
 2750 }
 2751 
 2752 static void
 2753 ubsec_dump_mcr(struct ubsec_mcr *mcr)
 2754 {
 2755         volatile struct ubsec_mcr_add *ma;
 2756         int i;
 2757 
 2758         printf("MCR:\n");
 2759         printf(" pkts: %u, flags 0x%x\n",
 2760             letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
 2761         ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
 2762         for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
 2763                 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
 2764                     letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
 2765                     letoh16(ma->mcr_reserved));
 2766                 printf(" %d: ipkt ", i);
 2767                 ubsec_dump_pb(&ma->mcr_ipktbuf);
 2768                 printf(" %d: opkt ", i);
 2769                 ubsec_dump_pb(&ma->mcr_opktbuf);
 2770                 ma++;
 2771         }
 2772         printf("END MCR\n");
 2773 }
 2774 #endif /* UBSEC_DEBUG */
 2775 
 2776 /*
 2777  * Return the number of significant bits of a big number.
 2778  */
 2779 static int
 2780 ubsec_ksigbits(struct crparam *cr)
 2781 {
 2782         u_int plen = (cr->crp_nbits + 7) / 8;
 2783         int i, sig = plen * 8;
 2784         u_int8_t c, *p = cr->crp_p;
 2785 
 2786         for (i = plen - 1; i >= 0; i--) {
 2787                 c = p[i];
 2788                 if (c != 0) {
 2789                         while ((c & 0x80) == 0) {
 2790                                 sig--;
 2791                                 c <<= 1;
 2792                         }
 2793                         break;
 2794                 }
 2795                 sig -= 8;
 2796         }
 2797         return (sig);
 2798 }
 2799 
 2800 static void
 2801 ubsec_kshift_r(
 2802         u_int shiftbits,
 2803         u_int8_t *src, u_int srcbits,
 2804         u_int8_t *dst, u_int dstbits)
 2805 {
 2806         u_int slen, dlen;
 2807         int i, si, di, n;
 2808 
 2809         slen = (srcbits + 7) / 8;
 2810         dlen = (dstbits + 7) / 8;
 2811 
 2812         for (i = 0; i < slen; i++)
 2813                 dst[i] = src[i];
 2814         for (i = 0; i < dlen - slen; i++)
 2815                 dst[slen + i] = 0;
 2816 
 2817         n = shiftbits / 8;
 2818         if (n != 0) {
 2819                 si = dlen - n - 1;
 2820                 di = dlen - 1;
 2821                 while (si >= 0)
 2822                         dst[di--] = dst[si--];
 2823                 while (di >= 0)
 2824                         dst[di--] = 0;
 2825         }
 2826 
 2827         n = shiftbits % 8;
 2828         if (n != 0) {
 2829                 for (i = dlen - 1; i > 0; i--)
 2830                         dst[i] = (dst[i] << n) |
 2831                             (dst[i - 1] >> (8 - n));
 2832                 dst[0] = dst[0] << n;
 2833         }
 2834 }
 2835 
 2836 static void
 2837 ubsec_kshift_l(
 2838         u_int shiftbits,
 2839         u_int8_t *src, u_int srcbits,
 2840         u_int8_t *dst, u_int dstbits)
 2841 {
 2842         int slen, dlen, i, n;
 2843 
 2844         slen = (srcbits + 7) / 8;
 2845         dlen = (dstbits + 7) / 8;
 2846 
 2847         n = shiftbits / 8;
 2848         for (i = 0; i < slen; i++)
 2849                 dst[i] = src[i + n];
 2850         for (i = 0; i < dlen - slen; i++)
 2851                 dst[slen + i] = 0;
 2852 
 2853         n = shiftbits % 8;
 2854         if (n != 0) {
 2855                 for (i = 0; i < (dlen - 1); i++)
 2856                         dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
 2857                 dst[dlen - 1] = dst[dlen - 1] >> n;
 2858         }
 2859 }

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